\chapter{Control and Status Registers}
\label{chap:csr}

\rvcore does not implement all control and status registers specified in the
\riscv privileged specifications, but is limited to the registers that were
needed for the PULP system.
The reason for this is that we wanted to keep the footprint of the core as low
as possible and avoid any overhead that we do not explicitely need.

\begin{landscape}
\begin{table}[H]
 \caption{Control and Status Register Map}
 \label{tab:csr_map}
 \centering\begin{tabularx}{\linewidth}{@{}|cccc|c|l|l|X|@{}} \toprule
   \multicolumn{4}{|c|}{\textbf{CSR Address}} & \textbf{Hex} & \textbf{Name} & \textbf{Access}  & \textbf{Description} \\ \hline
   \textbf{[11:10]} & \textbf{[9:8]} & \textbf{[7:6]} & \textbf{[5:0]} & & & & \\ \toprule
   00 & 11 & 00 & 000000  & 0x300         & MSTATUS  & R/W & Machine Status Register \\ \hline
   00 & 11 & 01 & 000001  & 0x341         & MEPC     & R/W & Machine exception program counter \\ \hline
   00 & 11 & 01 & 000010  & 0x342         & MCAUSE   & R/W & Machine trap cause \\ \hline
   01 & 11 & 00 & 0XXXXX  & 0x780 - 0x79F & PCCRs    & R/W & Performance Counter Counter Registers \\ \hline
   01 & 11 & 10 & 100000  & 0x7A0         & PCER     & R/W & Performance Counter Enable Register \\ \hline
   01 & 11 & 10 & 100001  & 0x7A1         & PCMR     & R/W & Performance Counter Mode Register \\ \hline
   01 & 11 & 10 & 110XXX  & 0x7B0 - 0x7B6 & HWLP     & R/W & Hardware Loop Registers \\ \hline
   01 & 11 & 10 & 111000  & 0x7C0         & MESTATUS & R/W & Machine exception Status Register \\ \hline
   11 & 11 & 00 & 000000  & 0xF00         & MCPUID   & R   & CPU description  \\ \hline
   11 & 11 & 00 & 000001  & 0xF01         & MIMPID   & R   & Vendor ID and version number \\ \hline
   11 & 11 & 00 & 010000  & 0xF10         & MHARTID  & R   & Hardware Thread ID \\ \bottomrule
  \end{tabularx}
\end{table}
\end{landscape}

\section{Register Description}

\subsection{MSTATUS}
\csrDesc{0x300}{0x0000\_0006}{MSTATUS}{
  \begin{bytefield}[endianness=big,bitheight=60pt]{32}
    \bitheader{31,2,1,0} \\
    \bitbox{29}{ Unused                            }
    \bitbox{2}{\rotatebox{90}{\tiny PRV[1:0]      }}
    \bitbox{1}{\rotatebox{90}{\tiny Interrupt Enable }}
  \end{bytefield}
}

Note that \signal{PRV[1:0]} is statically \signal{2'b11} and cannot be altered (read-only).
When en exception is encountered, \signal{Interrupt Enable} will be set to
\signal{1'b0}. When the \signal{eret} instruction is executed, the original
value of \signal{Interrupt Enable} will be restored, as \signal{MESTATUS} will
replace \signal{MSTATUS}.
If you want to enable interrupt handling in your exception hanlder, set the
\signal{Interrupt Enable} to \signal{1'b1} inside your handler code.

\subsection{MESTATUS}
\csrDesc{0x7C0}{0x0000\_0006}{MESTATUS}{
  \begin{bytefield}[endianness=big,bitheight=60pt]{32}
    \bitheader{31,2,1,0} \\
    \bitbox{29}{ Unused                            }
    \bitbox{2}{\rotatebox{90}{\tiny PRV[1:0]      }}
    \bitbox{1}{\rotatebox{90}{\tiny Interrupt Enable }}
  \end{bytefield}
}

Note that \signal{PRV[1:0]} is statically \signal{2'b11} and cannot be altered (read-only).

When an exception is encountered, the current value of \signal{MSTATUS} is saved
in \signal{MESTATUS}. When an \instr{eret} instruction is executed, the value
from \signal{MESTATUS} replaces the \signal{MSTATUS} register.


\subsection{MEPC}
\csrDesc{0x341}{0x0000\_0000}{MEPC}{
  \begin{bytefield}[endianness=big]{32}
    \bitheader{31,0} \\
    \bitbox{32}{ mepc                              }
  \end{bytefield}
}

When an exception is encountered, the current program counter is saved in
\signal{MEPC}, and the core jumps to the exception address. When an \instr{eret}
instruction is executed, the value from \signal{MEPC} replaces the current
program counter.

\subsection{MCAUSE}
\csrDesc{0x341}{0x0000\_0000}{MCAUSE}{
  \begin{bytefield}[endianness=big,bitheight=60pt]{32}
    \bitheader{31,30,4,0} \\
    \bitbox{1}{\rotatebox{90}{\tiny Interrupt      }}
    \bitbox{27}{ Unused                            }
    \bitbox{5}{\rotatebox{90}{\tiny Exception Code }}
  \end{bytefield}
}

\subsection{MCPUID}
\csrDesc{0xF00}{0x0000\_0100}{MCPUID}{
  \begin{bytefield}[endianness=big,bitheight=60pt]{32}
    \bitheader{31,29,26,25,0} \\
    \bitbox{2}{\rotatebox{90}{\tiny Base      }}
    \bitbox{4}{ 0                              }
    \bitbox{26}{ Extensions                    }
  \end{bytefield}
}

\subsection{MIMPID}
\csrDesc{0xF01}{0x0000\_8000}{MIMPID}{
  \begin{bytefield}[endianness=big]{32}
    \bitheader{31,16,15,0} \\
    \bitbox{16}{ Implementation  }
    \bitbox{16}{ Source          }
  \end{bytefield}
}

\subsection{MHARTID}
\csrDesc{0xF10}{Defined}{MHARTID}{
  \begin{bytefield}[endianness=big,bitheight=60pt]{32}
    \bitheader{31,9,5,4,0} \\
    \bitbox{22}{ Unused  }
    \bitbox{5}{\rotatebox{90}{\tiny Cluster ID }}
    \bitbox{5}{\rotatebox{90}{\tiny Core ID    }}
  \end{bytefield}
}

Both \signal{core id} and \signal{cluster id} are set on the top-level module
of the core and are read-only.
