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# Authors: Nathan Binkert
#          Andreas Hansson

from MemObject import MemObject
from m5.params import *
from m5.defines import buildEnv

from BaseTLB import BaseTLB

# TLB move to memory-side//
if buildEnv['TARGET_ISA'] == 'alpha':
    from AlphaTLB import AlphaDTB, AlphaITB
    from AlphaInterrupts import AlphaInterrupts

class BaseBus(MemObject):
    type = 'BaseBus'
    abstract = True
    slave = VectorSlavePort("vector port for connecting masters")
    master = VectorMasterPort("vector port for connecting slaves")
    # Override the default clock
    clock = '1GHz'
    header_cycles = Param.Cycles(1, "cycles of overhead per transaction")
    width = Param.Unsigned(8, "bus width (bytes)")
    block_size = Param.Unsigned(64, "The default block size if not set by " \
                                    "any connected module")

    # The default port can be left unconnected, or be used to connect
    # a default slave port
    default = MasterPort("Port for connecting an optional default slave")

    # The default port can be used unconditionally, or based on
    # address range, in which case it may overlap with other
    # ports. The default range is always checked first, thus creating
    # a two-level hierarchical lookup. This is useful e.g. for the PCI
    # bus configuration.
    use_default_range = Param.Bool(False, "Perform address mapping for " \
                                       "the default port")

    #TLB move to memory-side//
    if buildEnv['TARGET_ISA'] == 'alpha':
            dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
	    itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
            interrupts = Param.AlphaInterrupts(
	            NULL, "Interrupt Controller")

class NoncoherentBus(BaseBus):
    type = 'NoncoherentBus'

class CoherentBus(BaseBus):
    type = 'CoherentBus'
    CacheBus = Param.Bool(False, "This bus is used as cross-cache bar")
