question: How does a processor work with just electrical currents?
comment: So imagine you have a switch. You flip it, current goes through. Flip it again, no current. Thing is, you have to flip it. But there's another solution: the transistor. It's like a switch, but electronic - it has three pins, basically in, out and switch (base, emitter and collector are the actual terms, but we'll stick with simpler terms). Put a current on the switch, and the current will flow from in to out. No current on the switch means no current between in and out (some transistors work the other way around, ignore that for now). Now, the thing is, the transistor doesn't particularly care where that current on the switch pin comes from - it can come from another transistor too! So you can put a few of them together and do cool stuff. For instance, you can make what's called logic gates! They take two inputs, and have an output depending on whether there's a current in the inputs or not. An AND gate will only output a current with a current on both inputs, an XOR (exclusive or) gate will only output a current when one of the two inputs has a current on it but not the other, and there's a bunch of others. Like the NAND (not-and) gate, which requires only two transistors, and will always output a current *unless* both inputs have a current on them. See how we went from simple switches to more complicated logic? You can combine these into a lot more complex stuff! For instance you can build a simple one-bit memory out of two NAND (not-and) gates - when put together in just the right way you can have what's called an *RS latch*. It has two inputs, *set* and *reset*, and it keeps outputting either a current (1) or no current (0) depending on which input last had a current on it, even if both inputs now have no current on them. Add two more NAND gates to that system in the right configuration, and you have a third input to enable the whole system - no input on that third pin means you can send *any* signal to the set and reset pins, and nothing will happen - the latch will only change its output if that third pin has a current on it! Now, this is all a far cry from a processor, but with just 8 transistors we went from a simple yes/no circuit to a sort of simple memory that can be enabled and disabled as we please! It's not hard to imagine that with millions of transistors we can build *incredibly* complicated logic, and that's exactly how processors are structures. Yes, the individual components are just simple yes/no switches, but they're put together in *just* the right way (and they're insanely tiny!), so you get something that can do a lot of calculations really really fast.
passages: An additional form of power consumption became significant in the 1990s as wires on chip became narrower and the long wires became more resistive. CMOS gates at the end of those resistive wires see slow input transitions. During the middle of these transitions, both the NMOS and PMOS logic networks are partially conductive, and current flows directly from V to V. The power thus used is called "crowbar" power. Careful design which avoids weakly driven long skinny wires ameliorates this effect, but crowbar power can be a substantial part of dynamic CMOS power.
   By far, the most common digital integrated circuits built today use CMOS logic, which is fast, offers high circuit density and low-power per gate. This is used even in large, fast computers, such as the IBM System z.
  
  Section::::Recent developments.
  
  In 2009, researchers discovered that memristors can implement a boolean state storage (similar to a flip flop, implication and logical inversion), providing a complete logic family with very small amounts of space and power, using familiar CMOS semiconductor processes.
   The TTL "totem-pole" output structure often has a momentary overlap when both the upper and lower transistors are conducting, resulting in a substantial pulse of current drawn from the power supply. These pulses can couple in unexpected ways between multiple integrated circuit packages, resulting in reduced noise margin and lower performance. TTL systems usually have a decoupling capacitor for every one or two IC packages, so that a current pulse from one TTL chip does not momentarily reduce the supply voltage to another.
   There are many sophisticated current mirrors that have higher output resistances than the basic mirror (more closely approach an ideal mirror with current output independent of output voltage) and produce currents less sensitive to temperature and device parameter variations and to circuit voltage fluctuations. These multi-transistor mirror circuits are used both with bipolar and MOS transistors. These circuits include:
  
  BULLET::::- the Widlar current source
  
  BULLET::::- the Wilson current mirror used as a current source
  
  BULLET::::- Cascoded current sources
  
  Section::::See also.
  
  BULLET::::- Current source
  
  BULLET::::- Widlar current source
  
  BULLET::::- Wilson current mirror
  
  BULLET::::- Bipolar junction transistor
  
  BULLET::::- MOSFET
   BULLET::::- The "short-circuit power" component. During the transition of the output line (of a CMOS gate) from one voltage level to the other, there is a period of time when both the PMOS and the NMOS transistors are on, thus creating a path from V to ground.
   BULLET::::- More rarely, inductive structures can be built as tiny on-chip coils, or simulated by gyrators.
  
  Since a CMOS device only draws current on the "transition" between logic states, CMOS devices consume much less current than bipolar junction transistor devices.
   BULLET::::- Capacitive structures, in form very much like the parallel conducting plates of a traditional electrical capacitor, are formed according to the area of the "plates", with insulating material between the plates. Capacitors of a wide range of sizes are common on ICs.
  
  BULLET::::- Meandering stripes of varying lengths are sometimes used to form on-chip resistors, though most logic circuits do not need any resistors. The ratio of the length of the resistive structure to its width, combined with its sheet resistivity, determines the resistance.
   In short, the outputs of the PMOS and NMOS transistors are complementary such that when the input is low, the output is high, and when the input is high, the output is low. Because of this behavior of input and output, the CMOS circuit's output is the inverse of the input.
  
  Section::::Inversion.:Power supply pins.
   An advantage of CMOS over NMOS logic is that both low-to-high and high-to-low output transitions are fast since the (PMOS) pull-up transistors have low resistance when switched on, unlike the load resistors in NMOS logic. In addition, the output signal swings the full voltage between the low and high rails. This strong, more nearly symmetric response also makes CMOS more resistant to noise.
  
  See Logical effort for a method of calculating delay in a CMOS circuit.
  
  Section::::Inversion.:Example: NAND gate in physical layout.
   The 2015 ITRS 2.0 report included a detailed chapter on "Beyond CMOS", covering RAM and logic gates.
  
  Section::::Some areas of investigation.
  
  BULLET::::- tunnel junction devices, eg Tunnel field-effect transistor
  
  BULLET::::- indium antimonide transistors
  
  BULLET::::- carbon nanotube FET, eg CNT Tunnel field-effect transistor
  
  BULLET::::- graphene nanoribbons
  
  BULLET::::- molecular electronics
  
  BULLET::::- spintronics — many variants
  
  BULLET::::- , ultra-low dissipation conduction paths, including
  
  BULLET::::- topological materials
  
  BULLET::::- exciton superfluids
  
  BULLET::::- photonics and optical computing
  
  BULLET::::- superconducting computing
  
  BULLET::::- rapid single-flux quantum (RSFQ)
  
  Section::::Superconducting computing and RSFQ.
   Some devices exploit sub-threshold conduction to process data without fully turning on or off. Even in standard transistors a small amount of current leaks even when they are technically switched off. Some sub-threshold devices have been able to operate with between 1 and 0.1 percent of the power of standard chips.
  
  Such lower power operations allow some devices to function with the small amounts of power that can be scavenged without an attached power supply, such as a wearable EKG monitor that can run entirely on body heat.
  
  Section::::See also.
  
  BULLET::::- Integrated circuit
  
  BULLET::::- Moore's law
  
  BULLET::::- Subthreshold slope
   BULLET::::- A slot showing a high and low is an either or (such as on a data line)
  
  BULLET::::- A Z indicates high impedance
  
  BULLET::::- A greyed out slot is a don't-care or indeterminate.
  
  Section::::Example: SPI bus timing.
  
  The timing diagram example on the right describes the Serial Peripheral Interface (SPI) Bus.
  
  Most SPI master nodes have the ability to set the clock polarity (CPOL) and clock phase (CPHA) with respect to the data.
   Finally, there are several techniques for reducing the number of state changes associated with a given computation. For clocked- logic circuits, clock gating technique is used, to avoid changing the state of functional blocks that are not required for a given operation. As a more-extreme alternative, the asynchronous logic approach implements circuits in such a way that a specific externally supplied clock is not required. While both of these techniques are used to different extents in integrated circuit design, the limit of practical applicability for each appears to have been reached.
  
  Section::::Electronics.:Wireless communication elements.
   As of 2013, processors specifically designed for wristwatches are the lowest-power processors manufactured today—often 4-bit, 32 kHz processors.
  
  Section::::History.:Mobile computing.
   Ultra small (L = 20 nm, W = 20 nm) CMOS transistors achieve the single-electron limit when operated at cryogenic temperature over a range of –269 °C (4 K) to about –258 °C (15 K). The transistor displays Coulomb blockade due to progressive charging of electrons one by one. The number of electrons confined in the channel is driven by the gate voltage, starting from an occupation of zero electrons, and it can be set to one or many.
  
  Section::::See also.
  
  BULLET::::- Active pixel sensor
  
  BULLET::::- Beyond CMOS
  
  BULLET::::- Electric (software) – used to lay out CMOS circuits
   Devices, at the circuit level, use various techniques to measure current:
  
  BULLET::::- Shunt resistors
  
  BULLET::::- Hall effect current sensor transducers
  
  BULLET::::- Transformers (however DC cannot be measured)
  
  BULLET::::- Magnetoresistive field sensors
  
  BULLET::::- Rogowski coils
  
  BULLET::::- current clamps
  
  Section::::Resistive heating.
   The pass transistor is driven by a periodic clock signal and acts as an access switch to either charge up or charge down the parasitic capacitance C, depending on the input signal V. Thus, two possible operations when the clock signal is active (CK = 1) are the logic "1" transfer (charging up the capacitance C to a logic-high level) and the logic "0" transfer (charging down the capacitance C to a logic-low level). In either case, the output of the depletion load nMOS inverter obviously assumes a logic-low or a logic-high level, depending upon the voltage V.
   The MOSFET formula: formula_1 says that the current formula_2 supplied by the FET is proportional to the gate-source voltage reduced by a threshold voltage formula_3 which is dependent on the geometrical shape of the FET's channel and gate and their physical properties, especially capacitance. In order to reduce formula_3 (necessary both in order to reduce the supply voltage and to increase current) one must increase capacitance. But, the load being driven is in fact another FET gate. The current needed to drive it is proportional to capacitance, which thus requires the designer to keep it low. 
   Complementary metal–oxide–semiconductor (CMOS) is a non-volatile medium. It is used in microprocessors, microcontrollers, static RAM, and other digital logic circuits. Memory is read through the use of a combination of p-type and n-type metal–oxide–semiconductor field-effect transistors (MOSFETs). In CMOS logic, a collection of n-type MOSFETs are arranged in a pull-down network between the output node and the lower-voltage power supply rail, named V, which often has ground potential. By asserting or de-asserting the inputs to the CMOS circuit, individual transistors along the pull-up and pull-down networks become conductive and resistive to electric current, and results in the desired path connecting from the output node to one of the voltage rails.
   CMOS circuits use a combination of p-type and n-type metal–oxide–semiconductor field-effect transistor (MOSFETs) to implement logic gates and other digital circuits. Although CMOS logic can be implemented with discrete devices for demonstrations, commercial CMOS products are integrated circuits composed of up to billions of transistors of both types, on a rectangular piece of silicon of between 10 and 400 mm.
  
  CMOS always uses all enhancement-mode MOSFETs (in other words, a zero gate-to-source voltage turns the transistor off).
  
  Section::::History.
   This example shows a NAND logic device drawn as a physical representation as it would be manufactured. The physical layout perspective is a "bird's eye view" of a stack of layers. The circuit is constructed on a P-type substrate. The polysilicon, diffusion, and n-well are referred to as "base layers" and are actually inserted into trenches of the P-type substrate. (See steps 1 to 6 in the process diagram below right) The contacts penetrate an insulating layer between the base layers and the first layer of metal (metal1) making a connection.
   The required silicon area for implementing such digital CMOS functions has rapidly shrunk. VLSI technology incorporating millions of basic logic operations onto one chip, almost exclusively uses CMOS. The extremely small capacitance of the on-chip wiring caused an increase in performance by several orders of magnitude. On-chip clock rates as high as 4 GHz have become common, approximately 1000 times faster than the technology by 1970.
  
  Section::::CMOS.:Lowering the power supply voltage.
   CMOS logic dissipates less power than NMOS logic circuits because CMOS dissipates power only when switching ("dynamic power"). On a typical ASIC in a modern 90 nanometer process, switching the output might take 120 picoseconds, and happens once every ten nanoseconds. NMOS logic dissipates power whenever the transistor is on, because there is a current path from V to V through the load resistor and the n-type network.
   The inputs to the NAND (illustrated in green color) are in polysilicon. The CMOS transistors (devices) are formed by the intersection of the polysilicon and diffusion; N diffusion for the N device & P diffusion for the P device (illustrated in salmon and yellow coloring respectively). The output ("out") is connected together in metal (illustrated in cyan coloring). Connections between metal and polysilicon or diffusion are made through contacts (illustrated as black squares). The physical layout example matches the NAND logic circuit given in the previous example.
   Section::::Circuit realizations of current mirrors.:Basic MOSFET current mirror.
  
  The basic current mirror can also be implemented using MOSFET transistors, as shown in Figure 2. Transistor "M" is operating in the saturation or active mode, and so is "M". In this setup, the output current "I" is directly related to "I", as discussed next.
  