question: If we can't get under 7nm with silicon why are intel/AMD not building bigger dies with more transistor instead of always shrinking?
comment: > why aren't they building HUGE cpu that consume 3-400 watts? all we would have to do is having a bigger PSU and more efficient cooling. Because it will generate a metric ton of heat. Like, a lot. Which means a big ol' heatsink and a noisy, high RPM fan. Your power user might use liquid cooling to make this more efficient (which would also mean using larger fans which mean lower RPMs for the same airflow which means more quiet) but this isn't practical for Joe Consumer or Joe Business User. Furthermore - did I mention it will generate a ton of heat? Using a processor that was 125W stock and close to 200W overclocked in a ~10-14' bedroom that would normally be 68 degrees in winter, in a few hours it would heat the room up to about 78 degrees and I'd have to open my window in the dead of winter. Now try generating 2-3 times as much heat. Oof. Also, energy isn't free. An extra 305 watts for 8 hours a day is 890.6kWh in a year. The average price americans pay per kWh is 12 cents, which means you're spending an extra $106.87 a year on energy. Finally.... Why NOT continue to reduce die size until we've hit practical limits? More efficient means you can get the same performance for less heat/power... Which means you can get even MORE performance if you overclock it a bit.
passages: Section::::History.:Technology Commercialization.
  
  On July 7, 2019, AMD officially launches their Ryzen 3000 series of central processing units, based on the TSMC 7nm process and Zen 2 microarchitecture.
  
  Section::::7 nm patterning difficulties.
  
  The 7 nm foundry node is expected to utilize any of or a combination of the following patterning technologies: pitch splitting, self-aligned patterning, and EUV lithography. Each of these technologies carries significant challenges in critical dimension (CD) control as well as pattern placement, all involving neighboring features.
  
  Section::::7 nm patterning difficulties.:Pitch splitting.
   The 7 nm process offerings by Samsung and TSMC are similar to the 10 nm process offered by Intel, thus some argue that what really matters beyond 10 nm is transistor density (number of transistors per square milimeter).
  
  Section::::History.
  
  Section::::History.:Technology demos.
  
  In July 2015, IBM announced that they had built the first functional transistors with 7 nm technology, using a silicon-germanium process.
  
  In June 2016, TSMC had produced 256 Mbit SRAM memory cells at their 7 nm process, with a cell area of 0.027 mm (550 F) with reasonable risk production yields.
  
  Section::::History.:Expected commercialization and technologies.
   TSMC began production of 256 Mbit SRAM memory chips using a 7 nm process in 2017, before Samsung and TSMC began mass production of 7 nm devices in 2018. The first mainstream 7 nm mobile processor intended for mass market use, the Apple A12 Bionic, was released at their September 2018 event. Although Huawei announced its own 7 nm processor before the Apple A12 Bionic, the Kirin 980 on August 31, 2018, the Apple A12 Bionic was released for public, mass market use to consumers before the Kirin 980. Both chips are manufactured by TSMC. AMD is currently working on their "Rome" processors for servers and datacenters, which are based on the 7 nanometer node and feature up to 64 cores.
   Section::::7 nm process nodes and process offerings.
  
  The naming of process nodes by different major manufacturers (TSMC, Intel, Samsung, GlobalFoundries) is partially marketing-driven and not directly related to any measurable distance on a chip for example TSMC's 7 nm node is similar in some key dimensions to Intel's 10 nm node. Nevertheless, as of 2017, the technological race to the greatest density was still competitive between the main players, with TSMC, Samsung, and Intel all holding leading positions between the years 2016 and 2017 when measured by the smallest feature size on chip.
   Since EUV implementation at 7nm is still limited, multipatterning still plays an important part in cost and yield; EUV adds extra considerations. The resolution for most critical layers is still determined by multiple patterning. For example, for Samsung's 7nm, even with EUV single-patterned 36 nm pitch layers, 44 nm pitch layers would still be quadruple patterned.
  
  Section::::7 nm design rule management in volume production.
   The 10 nm process from Intel is similar to the 7 nm processes offered by Samsung and TSMC, thus some argue that what really matters beyond 10 nm is transistor density (number of transistors per square milimeter).
  
  Section::::Background.
  
  In 2002, a team of researchers consisting of TSMC researcher Chenming Hu and UC Berkeley researchers including B. Yu, Leland Chang, Shibly Ahmed, Cyrus Tabery, Tsu-Jae King Liu and Jeffrey Bokor described a 10nm FinFET process.
   For identical designs, these die shrinks would use less current (and power) at the same frequency (or voltage). As CPUs are usually power limited (typically up to ~125W, or ~45W for mobile), smaller transistors allow for either lower power at the same frequency, or higher frequency at the same power.
  
  Section::::Advantages over predecessors.:Performance.
   In June 2018, AMD announced 7 nm Radeon Instinct GPUs launching in the second half of 2018. In August 2018, the company has confirmed the release of the GPUs.
  
  In August 2018, GlobalFoundries announced it was stopping development of 7 nm chips citing cost.
  
  In August 21, 2018, Huawei announced their HiSilicon Kirin 980 SoC to be used in their Huawei Mate 20 and Mate 20 Pro built using TSMC's 7 nm (N7) process.
   In August 2014, Intel announced details of the 14 nm microarchitecture for its upcoming Core M processors, the first product to be manufactured on Intel's 14 nm manufacturing process. The first systems based on the Core M processor were to become available in Q4 2014 — according to the press release. "Intel's 14 nanometer technology uses second-generation tri-gate transistors to deliver industry-leading performance, power, density and cost per transistor," said Mark Bohr, Intel senior fellow, Technology and Manufacturing Group, and director, Process Architecture and Integration.
  
  In 2018 a shortage of 14 nm fab capacity was announced by Intel.
  
  Section::::History.:Shipping devices.
   IEDM papers from Intel in 2002, 2004, and 2005 illustrate the industry trend that the transistor sizes can no longer scale along with the rest of the feature dimensions (gate width only changed from 220 nm to 210 nm going from 90 nm to 65 nm technologies). However, the interconnects (metal and poly pitch) continue to shrink, thus reducing chip area and chip cost, as well as shortening the distance between transistors, leading to higher-performance devices of greater complexity when compared with earlier nodes.
  
  Section::::Example: Fujitsu 65 nm process.
  
  BULLET::::- Gate length: 30 nm (high-performance) to 50 nm (low-power)
  
  BULLET::::- Core voltage: 1.0 V
   In 2017, IBM revealed that they had created 5 nm silicon chips, using silicon nanosheets in a "gate-all-around" configuration (GAAFET), a break from the usual FinFET design.
  
  Section::::History.:Commercialization.
  
  In early 2018, TSMC announced production of a 5 nm node by 2020 on its new Fab 18. In October 2018, TSMC disclosed plans to start risk production of 5 nm devices by April 2019.
   Processors based on Zen use 14 nm FinFET silicon. These processors are reportedly produced at GlobalFoundries and TSMC. Prior to Zen, AMD's smallest process size was 28 nm, as utilized by their Steamroller and Excavator microarchitectures. The immediate competition, Intel's Skylake and Kaby Lake microarchitecture, are also fabricated on 14 nm FinFET; though Intel planned to begin the release of 10 nm parts later in 2017. In comparison to Intel's 14 nm FinFET, AMD claimed in February 2017 the Zen cores would be 10% smaller. Intel has later announced in July 2018 that 10nm mainstream processors should not be expected before the second half of 2019.
   However, as Moore's law has driven features to ever-smaller dimensions, new physical effects that could be effectively ignored in the past are now affecting the features that are formed on the silicon wafer. So even though the final layout may represent what is desired in silicon, the layout can still undergo dramatic alteration through several EDA tools before the masks are fabricated and shipped. These alterations are required not to make any change in the device as designed, but to simply allow the manufacturing equipment, often purchased and optimized for making ICs one or two generations behind, to deliver the new devices. These alterations can be classed as being of two types. 
   In September 2016, GlobalFoundries announced trial production in the second half of 2017 and risk production in early 2018, with test chips already running.
  
  In February 2017, Intel announced Fab 42 in Chandler, Arizona will produce microprocessors using 7 nm manufacturing process. The company has not published any expected values for feature lengths at this process node.
  
  In April 2018, TSMC announced volume production of 7 nm (CLN7FF, N7) chips. In June 2018, the company announced mass production ramp up.
  
  In May 2018, Samsung announced production of 7 nm chips this year. ASML Holding NV is their main supplier of EUV lithography machines.
   Section::::7 nm patterning difficulties.:Comparison with previous nodes.
  
  Due to these challenges, 7 nm poses unprecedented patterning difficulty in the BEOL. The previous high-volume, long-lived foundry node (Samsung 10 nm, TSMC 16 nm) used pitch splitting for the tighter pitch metal layers.
  
  Section::::7 nm patterning difficulties.:Cycle time: immersion vs. EUV.
  
  Due to the immersion tools being faster presently, multipatterning is still used on most layers. On the layers requiring immersion quad-patterning, the layer completion throughput by EUV is comparable. On the other layers, immersion would be more productive at completing the layer even with multipatterning.
   In April 2018, Intel announced a delay in volume production of 10 nm mainstream CPUs until sometime in 2019. In July the exact time was further pinned down to the holiday season. In the meantime, however, they did release a low-power 10 nm mobile chip, albeit exclusive to Chinese markets and with much of the chip disabled.
  
  In June 2018 at VLSI 2018, Samsung announced their 11LPP and 8LPP processes. 11LPP is a hybrid based on Samsung 14nm and 10nm technology. 11LPP is based on their 10nm BEOL, not their 20nm BEOL like their 14LPP. 8LPP is based on their 10LPP process.
   Die shrinks are beneficial to end-users as shrinking a die reduces the current used by each transistor switching on or off in semiconductor devices while maintaining the same clock frequency of a chip, making a product with less power consumption (and thus less heat production), increased clock rate headroom, and lower prices. Since the cost to fabricate a 200-mm or 300-mm silicon wafer is proportional to the number of fabrication steps, and not proportional to the number of chips on the wafer, die shrinks cram more chips onto each wafer, resulting in lowered manufacturing costs per chip.
  
  Section::::Half-shrink.
   As of 2019, 14 nanometer and 10 nanometer process chips are commonly in mass production, with 7 nanometer process chips in mass production by TSMC and Samsung, although their 7nanometer node definition is similar to Intel's 10 nanometer process. The 5 nanometer process began being produced by Samsung in 2018. As of 2019, the node with the highest transistor density is TSMC's 5nanometer node, with a density of 171.3million transistors per square millimeter. In 2019, Samsung and TSMC announced plans to produce 3 nanometer nodes.
  
  Section::::History.
   Section::::Major enabling factors.:Alternative materials research.
  
  The vast majority of current transistors on ICs are composed principally of doped silicon and its alloys. As silicon is fabricated into single nanometer transistors, short-channel effects adversely change desired material properties of silicon as a functional transistor. Below are several non-silicon substitutes in the fabrication of small nanometer transistors.
   BULLET::::- In 2018, Samsung Electronics began commercial production of a 5 nm process, using FinFET and EUV technology. In early 2019, TSMC began commercial production of their own 5 nm process.
  
  BULLET::::- Samsung and TSMC have presented plans to manufacture 3nm GAAFET nodes by 20212022.
  
  New technology advances may help sustain Moore's law through improved performance, with or without reduced feature size.
   In April 2013, Samsung announced that it had begun mass production of multi-level cell (MLC) flash memory chips using a 10nm process. On 17 October 2016, Samsung Electronics announced mass production of SoC chips at 10 nm. The technology's main announced challenge has been triple patterning for its metal layer.
  
  TSMC began commercial production of 10 nm chips in early 2016, before moving onto mass production in early 2017.
   A return to extended generations of single exposure patterning would be possible with higher numerical aperture (NA) tools. An NA of 0.45 could require retuning of a few percent. Increasing demagnification could avoid this retuning, but the reduced field size severely affects large patterns (one die per 26 mm × 33 mm field) such as the many-core multi-billion transistor 14 nm Xeon chips. by requiring field stitching.
   Section::::Metal gate contacts re-introduced.
  
  For the above reason as the devices go down on the scaling (32-28nm nodes) poly gates are being replaced by metal gates. The following technology is known as High-k Dielectric Metal Gate (HKMG) integration. Recently, Intel also released a press-kit regarding their fabrication procedures of different nodes, which showed the use of Metal gate technology.
   In September 2012, GlobalFoundries announced plans to offer a 14-nanometer process technology featuring FinFET three-dimensional transistors in 2014. The next month, the rival company TSMC announced start early or "risk" production of 16 nm FinFETS in November 2013.
  
  In March 2014, TSMC announced that it is nearing implementation of several 16 nm FinFETs die-on wafers manufacturing processes:
  
  BULLET::::- 16 nm FinFET (Q4 2014),
  
  BULLET::::- 16 nm FinFET+ ( Q4 2014),
  
  BULLET::::- 16 nm FinFET "Turbo" (estimated in 2015–2016).
   There has been a trend to produce ever larger wafers, so each process step is being performed on more and more chips at once. The goal is to spread production costs (chemicals, fab time) over a larger number of saleable chips. It is impossible (or at least impracticable) to retrofit machinery to handle larger wafers. This is not to say that foundries using smaller wafers are necessarily obsolete; older foundries can be cheaper to operate, have higher yields for simple chips and still be productive.
  