question: How come phone CPUs have octa-core processers when most laptop CPUs (even high end) are usually dual/quad core?
comment: If you look at the specs on these phones, they're actually *two joined quad core* processors. There's one set of fast cores for when you're actively using the phone and a set of slow processors that don't use nearly as much power for times it's not "active" (eg - sitting in your pocket). This is done to help them preserve battery power because the slower cores use far less power. ...and the standard for desktops has moved to quad core with all but the absolute cheapest new systems coming with at least 4 cores & high-end desktops can have 12 or more.
passages: BULLET::::- Haswell-EP models with ten and more cores support "cluster on die" (COD) operation mode, allowing CPU's multiple columns of cores and last level cache (LLC) slices to be logically divided into what is presented as two non-uniform memory access (NUMA) CPUs to the operating system. By keeping data and instructions local to the "partition" of CPU which is processing them, therefore decreasing the LLC access latency, COD brings performance improvements to NUMA-aware operating systems and applications.
  
  Section::::Technology.:Haswell Refresh.
   Core 2 Quad processors are multi-chip modules consisting of two dies similar to those used in Core 2 Duo, forming a quad-core processor. This allows twice the performance of a dual-core processors at the same clock frequency in ideal conditions.
  
  Initially, all Core 2 Quad models were versions of Core 2 Duo desktop processors, Kentsfield derived from Conroe and Yorkfield from Wolfdale, but later Penryn-QC was added as a high-end version of the mobile dual-core Penryn.
  
  The Xeon 32xx and 33xx processors are mostly identical versions of the desktop Core 2 Quad processors and can be used interchangeably.
   The desktop market has been in a transition towards quad-core CPUs since Intel's Core 2 Quad was released and are now common, although dual-core CPUs are still more prevalent. Older or mobile computers are less likely to have more than two cores than newer desktops. Not all software is optimised for multi-core CPUs, making fewer, more powerful cores preferable.
   Vendors may license some software "per processor". This can give rise to ambiguity, because a "processor" may consist either of a single core or of a combination of cores.
  
  BULLET::::- Initially, for some of its enterprise software, Microsoft continued to use a per-socket licensing system. However, for some software such as BizTalk Server 2013, SQL Server 2014, and Windows Server 2016, Microsoft has shifted to per-core licensing.
  
  BULLET::::- Oracle Corporation counts an AMD X2 or an Intel dual-core CPU as a single processor but uses other metrics for other types, especially for processors with more than two cores.
  
  Section::::Embedded applications.
   BULLET::::- Note: Interrupt latency cycle count assumes: 1) stack located in zero-wait state RAM, 2) another interrupt function not currently executing, 3) Security Extension option doesn't exist, because it adds additional cycles. The Cortex-M cores with a Harvard computer architecture have a shorter interrupt latency than Cortex-M cores with a Von Neumann computer architecture.
  
  BULLET::::- Note: The single-precision (SP) FPU instructions are valid in the Cortex-M4 / M7 / M33 / M35P only when the SP FPU option exists in the silicon.
   Modern desktop computers support systems with multiple CPUs, but few applications outside of the professional market can make good use of more than four cores. Both Intel and AMD currently offer fast quad, hex and octa-core desktop CPUs, making multi-CPU systems obsolete for many purposes.
   Westmere-EP is the first six-core dual-socket processor from Intel, following the quad-core Bloomfield and Gainestown (also known as Nehalem-EP) processors using the same LGA 1366 package, while the earlier Dunnington six-core processor is a Socket 604 based multi-socket processor. The CPUID extended model number is 44 (2Ch) and two product codes are used, 80613 for the UP desktop/server models and 80614 for the Xeon 5600-series DP server models. In some models, only four of the six cores are enabled.
   All instructions execute in two clock cycles, making performance of the core instruction set deterministic. Interrupt response is not more than five clock cycles. As a resource optimization, it is possible for two PicoBlaze cores to share the same 1k x 18 instruction PROM, taking advantage of the dual-ported implementation of this block on Xilinx FPGAs.
  
  Section::::Architectural notes.
   The Conroe-L and Merom-L processors are based around the same core as Conroe and Merom, but only contain a single core and 1 MB of L2 cache, significantly reducing production cost and power consumption of the processor at the expense of performance compared to the dual-core version. It is used only in ultra-low voltage Core 2 Solo U2xxx and in Celeron processors and is identified as CPUID family 6 model 22.
  
  Section::::Processor cores.:Penryn/Wolfdale (45 nm).
   Two companies have emerged that specialize in building multi-core devices using the MIPS architecture. Raza Microelectronics, Inc. purchased the product line from failing SandCraft and later produced devices that contained eight cores that were targeted at the telecommunications and networking markets. Cavium, originally a security processor vendor also produced devices with eight CPU cores, and later up to 32 cores, for the same markets. Both of these companies designed their cores in-house, just licensing the architecture instead of purchasing cores from MIPS.
  
  Section::::History.:The desktop.
   The processors of the Core microarchitecture can be categorized by number of cores, cache size, and socket; each combination of these has a unique code name and product code that is used across a number of brands. For instance, code name "Allendale" with product code 80557 has two cores, 2 MB L2 cache and uses the desktop socket 775, but has been marketed as Celeron, Pentium, Core 2 and Xeon, each with different sets of features enabled. Most of the mobile and desktop processors come in two variants that differ in the size of the L2 cache, but the specific amount of L2 cache in a product can also be reduced by disabling parts at production time.
   BULLET::::- Intel Takes Popular Laptops to 'Extreme' with First-Ever Extreme Edition Mobile Processor; Adds New Desktop Chip, 16 July 2007
  
  BULLET::::- CORE 2 DUO 1333 MHZ STEPPING, 18 July 2007
  
  Section::::External links.
  
  BULLET::::- Intel Core 2 Duo desktop processor product order code table
  
  BULLET::::- Intel Core 2 Quad desktop processor product order code table
  
  BULLET::::- Intel Core 2 Extreme desktop processor product order code table
  
  BULLET::::- Intel Core 2 Solo mobile processor product order code table
  
  BULLET::::- Intel Core 2 Duo mobile processor product order code table
  
  BULLET::::- Intel Core 2 Quad mobile processor product order code table
   On the Superdome you have four-cell slices called "Quadrants" which means that within this slice you will have better / faster intercommunication between the cells, and the guidelines on nPartitioning should be followed here, this does not apply to mid-range servers since they have a maximum of four cells.
  
  You are not allowed to mix PA-RISC and itanium cells in one nPar, nor are you allowed to mix CPU steppings
  
  Section::::Partitioning software.
  
  There are several ways to edit the nPartition configuration :
  
  BULLET::::- From HP-UX via the par-tools (parmodify, parcreate, etc.)
   BULLET::::- IBM POWER9 "SO" scale-out variant, optimized for dual socket computers with up to 120 GB/s bandwidth to directly attached DDR4 memory (targeted for release in 2017)
  
  BULLET::::- IBM POWER9 "SU" scale-up variant, optimized for four sockets or more, for large NUMA machines with up to 230 GB/s bandwidth to buffered memory
  
  Both POWER9 variants can ship in versions with some cores disabled due to yield reasons, as such Raptor Computing Systems first sold 4-core chips, and even IBM initially sold its AC922 systems with no more than 22-core chips, even though both types of chips have 24 cores on their dies.
   In heterogeneous computing, where a system uses more than one kind of processor or cores, multi-core solutions are becoming more common: Xilinx Zynq UltraScale+ MPSoC has Quad-core ARM Cortex-A53 and Dual-core ARM Cortex-R5. Software solutions such as OpenAMP are being used to help with inter processor communication.
  
  Mobile devices may use the ARM big.LITTLE architecture.
  
  Section::::Hardware examples.
  
  Section::::Hardware examples.:Commercial.
  
  BULLET::::- Adapteva Epiphany, a many-core processor architecture which allows up to 4096 processors on-chip, although only a 16 core version has been commercially produced.
  
  BULLET::::- Aeroflex Gaisler LEON3, a multi-core SPARC that also exists in a fault-tolerant version.
   Section::::Variants.
  
  Section::::Variants.:Merom.
  
  Merom, the first mobile version of the Core 2, was officially released on July 27, 2006 but quietly began shipping to PC manufacturers in mid-July alongside Conroe. Merom became Intel's premier line of mobile processors, with mostly the same features of Conroe, but with more emphasis on low power consumption to enhance notebook battery life. Merom-based Core 2 Duo provides a slight performance increase associated with 3D rendering and media encoding tasks , yet maintains the same battery life as the Yonah-based Core Duo. Merom is the first Intel mobile processor to feature Intel 64 architecture.
   BULLET::::- Dynamic Acceleration Technology for some mobile Core 2 Duo processors, and Dual Dynamic Acceleration Technology for mobile Core 2 Quad processors. Dynamic Acceleration Technology allows the CPU to overclock one processor core while turning off the one. In Dual Dynamic Acceleration Technology two cores are deactivated and two cores are overclocked. This feature is triggered when an application only uses a single core for Core 2 Duo or up to two cores for Core 2 Quad. The overclocking is performed by increasing the clock multiplier by 1.
   While the first processors in this category were single core (such as the SU3500), newer CULV processors are dual core (e.g., the SU9600). They are all based on the Intel Core 2 architecture, but the ultra-low voltage versions have a thermal rating of 5.5 W – more than the Intel Atom, but a fraction of the dual-core mainstream Intel mobile chips rated at 25 and 35 watts – and they come in a small 22 mm chip package.
  
  The newest CULV processors come from the Core i5 and Core i7 product lines, and are based on a 14 nm process.
   Regarding interprocessor communication in a multicore setup, there are similarities between the Cell's inter-localstore DMA and a shared L2 cache setup as in the Intel Core 2 Duo or the Xbox 360's custom powerPC: the L2 cache allows processors to share results without those results having to be committed to main memory. This can be an advantage where the working set for an algorithm encompasses the entirety of the L2 cache. 
   The LC1813/1913 were released in 2013 and support Android 4.3. Both chips have a 13M pixels ISP. The LC1913 tablet processor has USB-OTG support as an extra feature.
  
  The LC1860 and LC1960 with hexa-core CPU and LTE support were announced in 2014 and support Android 4.4. The LC1860 has a 20M pixels ISP. The LC1860C is a lower-end version of the LC1860 with quad-core CPU, lower GPU speed, single-channel memory interface and a 13M pixels ISP.
  
  The company also offers feature phone processors, including the LC1712, manufactured at 55 nm, and the 65 nm L1808B.
  
  Section::::See also.
  
  BULLET::::- Allwinner Technology
  
  BULLET::::- HiSilicon
   The Slate 7 runs mainly stock Android 4.1, with the exception of "HP ePrint", an application that will allow a user to print wirelessly from most Android applications.
  
  When asked if webOS, HP's mobile operating system would be installable, Omar Javaid, VP of Product Management stated that it is possible, however any such port would have to be undertaken by the webOS community.
  
  Section::::Reception.
   Intel's new 45 nm Penryn-based Core 2 Duo and Core 2 Extreme processors were released on January 6, 2008. The new processors launched exclusively with a TDP of 35 W. HP began to offer the first model, the T9500, from late January 2008. The T9500 offers a 2.6 GHz clock rate, higher than all but the Extreme Edition of the Merom range, and 6 MB (rather than 4 MB) of Level 2 Cache.
   On 19 January 2014, the Suzhou PowerCore Technology Company announced that they will join the OpenPOWER Foundation and license the POWER8 core to design custom-made processors for use in big data and cloud computing applications.
  
  Section::::Variants.
  
  BULLET::::- IBM " Murano" a 12-core processor with two six-core chips. Scale-out processor is available in configurations with disabled cores.
  
  BULLET::::- IBM "Turismo" a single-chip 12-core processor. Scale-up processor is commercially available for licensing and purchase in configurations with disabled cores.
   A large portion of the current mid-range Android handsets use the Cortex-A53 or Cortex-A55 in an octa-core arrangement and are not affected by either the Meltdown or Spectre vulnerability as they do not perform out-of-order execution. This includes devices with the Qualcomm Snapdragon 630, Snapdragon 626, Snapdragon 625, and all Snapdragon 4xx processors based on A53 or A55 cores. Also, no Raspberry Pi computers are vulnerable to either Meltdown or Spectre, except the newly-released Raspberry Pi 4, which uses the ARM Cortex-A72 CPU.
   There have been a wide range of CPUs designed for laptops available from both Intel, AMD, and other manufacturers. On non-x86 architectures, Motorola and IBM produced the chips for the former PowerPC-based Apple laptops (iBook and PowerBook). Many laptops have removable CPUs, although this has become less common in the past few years as the trend has been towards thinner and lighter models. In other laptops the CPU is soldered on the motherboard and is non-replaceable; this is nearly universal in ultrabooks.
  
presuppositions: Phones have octa-core processors. Phones have octa-core processors rather than dual cores.
corrections: Phones have two joined quad-core processors. Phones have two joined quad core processors rather than octa-processors.
raw_presuppositions: Phones have octa-core processors. Phones have octa-core processors rather than dual cores.
raw_corrections: Phones have two joined quad-core processors. Phones have two joined quad core processors rather than octa-processors.