code:
/*	$OpenBSD: cn30xxasx.c,v 1.6 2014/08/11 18:29:56 miod Exp $	*/

/*
 * Copyright (c) 2007 Internet Initiative Japan, Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */

#include <sys/param.h>
#include <sys/systm.h>
#include <sys/malloc.h>

#include <machine/octeonvar.h>

#include <octeon/dev/cn30xxasxreg.h>
#include <octeon/dev/cn30xxasxvar.h>

#ifdef OCTEON_ETH_DEBUG
void	cn30xxasx_intr_rml(void *);
struct cn30xxasx_softc *__cn30xxasx_softc;
#endif

/* XXX */
void
cn30xxasx_init(struct cn30xxasx_attach_args *aa,
    struct cn30xxasx_softc **rsc)
{
	struct cn30xxasx_softc *sc;
	int status;

	sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
	if (sc == NULL)
		panic("can't allocate memory: %s", __func__);

	sc->sc_port = aa->aa_port;
	sc->sc_regt = aa->aa_regt;

	status = bus_space_map(sc->sc_regt, ASX0_BASE, ASX0_SIZE, 0,
	    &sc->sc_regh);
	if (status != 0)
		panic("can't map %s space", "asx register");

	*rsc = sc;

#ifdef OCTEON_ETH_DEBUG
	if (__cn30xxasx_softc == NULL)
		__cn30xxasx_softc = sc;
#endif
}

#define	_ASX_RD8(sc, off) \
	bus_space_read_8((sc)->sc_regt, (sc)->sc_regh, (off))
#define	_ASX_WR8(sc, off, v) \
	bus_space_write_8((sc)->sc_regt, (sc)->sc_regh, (off), (v))

int	cn30xxasx_enable_tx(struct cn30xxasx_softc *, int);
int	cn30xxasx_enable_rx(struct cn30xxasx_softc *, int);
#ifdef OCTEON_ETH_DEBUG
int	cn30xxasx_enable_intr(struct cn30xxasx_softc *, int);
#endif

int
cn30xxasx_enable(struct cn30xxasx_softc *sc, int enable)
{

#ifdef OCTEON_ETH_DEBUG
	cn30xxasx_enable_intr(sc, enable);
#endif
	cn30xxasx_enable_tx(sc, enable);
	cn30xxasx_enable_rx(sc, enable);
	return 0;
}

int
cn30xxasx_enable_tx(struct cn30xxasx_softc *sc, int enable)
{
	uint64_t asx_tx_port;

	asx_tx_port = _ASX_RD8(sc, ASX0_TX_PRT_EN_OFFSET);
	if (enable)
		SET(asx_tx_port, 1 << sc->sc_port);
	else
		CLR(asx_tx_port, 1 << sc->sc_port);
	_ASX_WR8(sc, ASX0_TX_PRT_EN_OFFSET, asx_tx_port);
	return 0;
}

int
cn30xxasx_enable_rx(struct cn30xxasx_softc *sc, int enable)
{
	uint64_t asx_rx_port;

	asx_rx_port = _ASX_RD8(sc, ASX0_RX_PRT_EN_OFFSET);
	if (enable)
		SET(asx_rx_port, 1 << sc->sc_port);
	else
		CLR(asx_rx_port, 1 << sc->sc_port);
	_ASX_WR8(sc, ASX0_RX_PRT_EN_OFFSET, asx_rx_port);
	return 0;
}

#if defined(OCTEON_ETH_DEBUG)
int	cn30xxasx_intr_rml_verbose;

void
cn30xxasx_intr_rml(void *arg)
{
	struct cn30xxasx_softc *sc = __cn30xxasx_softc;
	uint64_t reg;

	reg = cn30xxasx_int_summary(sc);
	if (cn30xxasx_intr_rml_verbose)
		printf("%s: ASX_INT_REG=0x%016llx\n", __func__, reg);
}

int
cn30xxasx_enable_intr(struct cn30xxasx_softc *sc, int enable)
{
	uint64_t asx_int_xxx = 0;

	SET(asx_int_xxx,
	    ASX0_INT_REG_TXPSH |
	    ASX0_INT_REG_TXPOP |
	    ASX0_INT_REG_OVRFLW);
	_ASX_WR8(sc, ASX0_INT_REG_OFFSET, asx_int_xxx);
	_ASX_WR8(sc, ASX0_INT_EN_OFFSET, enable ? asx_int_xxx : 0);
	return 0;
}
#endif

int
cn30xxasx_clk_set(struct cn30xxasx_softc *sc, int tx_setting, int rx_setting)
{
	_ASX_WR8(sc, ASX0_TX_CLK_SET0_OFFSET + 8 * sc->sc_port, tx_setting);
	_ASX_WR8(sc, ASX0_RX_CLK_SET0_OFFSET + 8 * sc->sc_port, rx_setting);
	return 0;
}

#ifdef OCTEON_ETH_DEBUG
uint64_t
cn30xxasx_int_summary(struct cn30xxasx_softc *sc)
{
	uint64_t summary;

	summary = _ASX_RD8(sc, ASX0_INT_REG_OFFSET);
	_ASX_WR8(sc, ASX0_INT_REG_OFFSET, summary);
	return summary;
}

#define	_ENTRY(x)	{ #x, x##_OFFSET }

struct cn30xxasx_dump_reg_ {
	const char *name;
	size_t	offset;
};

void		cn30xxasx_dump(void);

const struct cn30xxasx_dump_reg_ cn30xxasx_dump_regs_[] = {
	_ENTRY(ASX0_RX_PRT_EN),
	_ENTRY(ASX0_TX_PRT_EN),
	_ENTRY(ASX0_INT_REG),
	_ENTRY(ASX0_INT_EN),
	_ENTRY(ASX0_RX_CLK_SET0),
	_ENTRY(ASX0_RX_CLK_SET1),
	_ENTRY(ASX0_RX_CLK_SET2),
	_ENTRY(ASX0_PRT_LOOP),
	_ENTRY(ASX0_TX_CLK_SET0),
	_ENTRY(ASX0_TX_CLK_SET1),
	_ENTRY(ASX0_TX_CLK_SET2),
	_ENTRY(ASX0_COMP_BYP),
	_ENTRY(ASX0_TX_HI_WATER000),
	_ENTRY(ASX0_TX_HI_WATER001),
	_ENTRY(ASX0_TX_HI_WATER002),
	_ENTRY(ASX0_GMII_RX_CLK_SET),
	_ENTRY(ASX0_GMII_RX_DAT_SET),
	_ENTRY(ASX0_MII_RX_DAT_SET),
};

void
cn30xxasx_dump(void)
{
	struct cn30xxasx_softc *sc = __cn30xxasx_softc;
	const struct cn30xxasx_dump_reg_ *reg;
	uint64_t tmp;
	int i;

	for (i = 0; i < (int)nitems(cn30xxasx_dump_regs_); i++) {
		reg = &cn30xxasx_dump_regs_[i];
		tmp = _ASX_RD8(sc, reg->offset);
		printf("\t%-24s: %016llx\n", reg->name, tmp);
	}
}
#endif


code:
/*
 * THIS FILE IS AUTOMATICALLY GENERATED
 * DONT EDIT THIS FILE
 */

/*	$OpenBSD: cn30xxasxreg.h,v 1.2 2014/08/11 18:29:56 miod Exp $	*/

/*
 * Copyright (c) 2007 Internet Initiative Japan, Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */

/*
 * Cavium Networks OCTEON CN30XX Hardware Reference Manual
 * CN30XX-HM-1.0
 * 13.9 ASX Registers
 */

#ifndef _CN30XXASXREG_H_
#define _CN30XXASXREG_H_

#define	ASX0_RX_PRT_EN				0x00011800b0000000ULL
#define	ASX0_TX_PRT_EN				0x00011800b0000008ULL
#define	ASX0_INT_REG				0x00011800b0000010ULL
#define	ASX0_INT_EN				0x00011800b0000018ULL
#define	ASX0_RX_CLK_SET0			0x00011800b0000020ULL
#define	ASX0_RX_CLK_SET1			0x00011800b0000028ULL
#define	ASX0_RX_CLK_SET2			0x00011800b0000030ULL
#define	ASX0_PRT_LOOP				0x00011800b0000040ULL
#define	ASX0_TX_CLK_SET0			0x00011800b0000048ULL
#define	ASX0_TX_CLK_SET1			0x00011800b0000050ULL
#define	ASX0_TX_CLK_SET2			0x00011800b0000058ULL
#define	ASX0_COMP_BYP				0x00011800b0000068ULL
#define	ASX0_TX_HI_WATER000			0x00011800b0000080ULL
#define	ASX0_TX_HI_WATER001			0x00011800b0000088ULL
#define	ASX0_TX_HI_WATER002			0x00011800b0000090ULL
#define	ASX0_GMII_RX_CLK_SET			0x00011800b0000180ULL
#define	ASX0_GMII_RX_DAT_SET			0x00011800b0000188ULL
#define	ASX0_MII_RX_DAT_SET			0x00011800b0000190ULL

#define ASX0_BASE				0x00011800b0000000ULL
#define ASX0_SIZE				0x0198ULL

#define	ASX0_RX_PRT_EN_OFFSET			0x0000
#define	ASX0_TX_PRT_EN_OFFSET			0x0008
#define	ASX0_INT_REG_OFFSET			0x0010
#define	ASX0_INT_EN_OFFSET			0x0018
#define	ASX0_RX_CLK_SET0_OFFSET			0x0020
#define	ASX0_RX_CLK_SET1_OFFSET			0x0028
#define	ASX0_RX_CLK_SET2_OFFSET			0x0030
#define	ASX0_PRT_LOOP_OFFSET			0x0040
#define	ASX0_TX_CLK_SET0_OFFSET			0x0048
#define	ASX0_TX_CLK_SET1_OFFSET			0x0050
#define	ASX0_TX_CLK_SET2_OFFSET			0x0058
#define	ASX0_COMP_BYP_OFFSET			0x0068
#define	ASX0_TX_HI_WATER000_OFFSET		0x0080
#define	ASX0_TX_HI_WATER001_OFFSET		0x0088
#define	ASX0_TX_HI_WATER002_OFFSET		0x0090
#define	ASX0_GMII_RX_CLK_SET_OFFSET		0x0180
#define	ASX0_GMII_RX_DAT_SET_OFFSET		0x0188
#define	ASX0_MII_RX_DAT_SET_OFFSET		0x0190

/* XXX */

/*
 * ASX_RX_PRT_EN
 */
#define ASX0_RX_PRT_EN_63_3			0xfffffff8
#define ASX0_RX_PRT_EN_PRT_EN			0x00000007

/*
 * ASX0_TX_PRT_EN
 */
#define ASX0_TX_PRT_EN_63_3			0xfffffff8
#define ASX0_TX_PRT_EN_PRT_EN			0x00000007

/*
 * ASX0_INT_REG
 */
#define ASX0_INT_REG_63_11			0xfffff800
#define ASX0_INT_REG_TXPSH			0x00000700
#define ASX0_INT_REG_7				0x00000080
#define ASX0_INT_REG_TXPOP			0x00000070
#define ASX0_INT_REG_3				0x00000008
#define ASX0_INT_REG_OVRFLW			0x00000007

/*
 * ASX0_INT_EN
 */
#define ASX0_INT_EN_63_11			0xfffff800
#define ASX0_INT_EN_TXPSH			0x00000700
#define ASX0_INT_EN_7				0x00000080
#define ASX0_INT_EN_TXPOP			0x00000070
#define ASX0_INT_EN_3				0x00000008
#define ASX0_INT_EN_OVRFLW			0x00000007

/*
 * ASX0_RX_CLK_SET
 */
#define ASX0_RX_CLK_SET_63_5			0xffffffe0
#define ASX0_RX_CLK_SET_SETTING			0x0000001f

/*
 * ASX0_RRT_LOOP
 */
#define ASX0_PRT_LOOP_63_7			0xffffff80
#define ASX0_PRT_LOOP_EXT_LOOP			0x00000070
#define ASX0_PRT_LOOP_3				0x00000008
#define ASX0_PRT_LOOP_PRT_LOOP			0x00000007

/*
 * ASX0_TX_CLK_SET
 */
#define ASX0_TX_CLK_SET_63_5			0xffffffe0
#define ASX0_TX_CLK_SET_SETTING			0x0000001f

/*
 * ASX0_TX_COMP_BYP
 */
#define ASX0_TX_COMP_BYP_63_9			0xfffffe00
#define ASX0_TX_COMP_BYP_BYPASS			0x00000100
#define ASX0_TX_COMP_BYP_PCTL			0x000000f0
#define ASX0_TX_COMP_BYP_NCTL			0x0000000f

/*
 * ASX0_TX_HI_WATER
 */
#define ASX0_TX_HI_WATER_63_3			0xfffffff8
#define ASX0_TX_HI_WATER_MARK			0x00000007

/*
 * ASX0_GMXII_RX_CLK_SET
 */
#define ASX0_GMII_RX_CLK_SET_63_5		0xffffffe0
#define ASX0_GMII_RX_CLK_SET_SETTING		0x0000001f

/*
 * ASX0_GMXII_RX_DAT_SET
 */
#define ASX0_GMII_RX_DAT_SET_63_5		0xffffffe0
#define ASX0_GMII_RX_DAT_SET_SETTING		0x0000001f

#endif /* _CN30XXASXREG_H_ */

license: unknown


code:
/*	$OpenBSD: cn30xxasxvar.h,v 1.3 2014/08/11 18:29:56 miod Exp $	*/

/*
 * Copyright (c) 2007 Internet Initiative Japan, Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */

#ifndef _CN30XXASXVAR_H_
#define _CN30XXASXVAR_H_

/* XXX */
struct cn30xxasx_softc {
	int			sc_port;
	bus_space_tag_t		sc_regt;
	bus_space_handle_t	sc_regh;
};

/* XXX */
struct cn30xxasx_attach_args {
	int			aa_port;
	bus_space_tag_t		aa_regt;
};

void			cn30xxasx_init(struct cn30xxasx_attach_args *,
			    struct cn30xxasx_softc **);
int			cn30xxasx_enable(struct cn30xxasx_softc *, int);
int			cn30xxasx_clk_set(struct cn30xxasx_softc *, int, int);
uint64_t		cn30xxasx_int_summary(struct cn30xxasx_softc *sc);

#endif


code:
/*
 * THIS FILE IS AUTOMATICALLY GENERATED
 * DONT EDIT THIS FILE
 */

/*	$OpenBSD: cn30xxbootbusreg.h,v 1.2 2014/08/11 18:29:56 miod Exp $	*/

/*
 * Copyright (c) 2007 Internet Initiative Japan, Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */

/*
 * Cavium Networks OCTEON CN30XX Hardware Reference Manual
 * CN30XX-HM-1.0
 * 12.8 Boot-Bus Registers
 */

#ifndef _CN30XXBOOTBUSREG_H_
#define _CN30XXBOOTBUSREG_H_

/* ---- register addresses */

#define	MIO_BOOT_REG_CFG0			0x0001180000000000ULL
#define	MIO_BOOT_REG_CFG1			0x0001180000000008ULL
#define	MIO_BOOT_REG_CFG2			0x0001180000000010ULL
#define	MIO_BOOT_REG_CFG3			0x0001180000000018ULL
#define	MIO_BOOT_REG_CFG4			0x0001180000000020ULL
#define	MIO_BOOT_REG_CFG5			0x0001180000000028ULL
#define	MIO_BOOT_REG_CFG6			0x0001180000000030ULL
#define	MIO_BOOT_REG_CFG7			0x0001180000000038ULL
#define	MIO_BOOT_REG_TIM0			0x0001180000000040ULL
#define	MIO_BOOT_REG_TIM1			0x0001180000000048ULL
#define	MIO_BOOT_REG_TIM2			0x0001180000000050ULL
#define	MIO_BOOT_REG_TIM3			0x0001180000000058ULL
#define	MIO_BOOT_REG_TIM4			0x0001180000000060ULL
#define	MIO_BOOT_REG_TIM5			0x0001180000000068ULL
#define	MIO_BOOT_REG_TIM6			0x0001180000000070ULL
#define	MIO_BOOT_REG_TIM7			0x0001180000000078ULL
#define	MIO_BOOT_LOC_CFG0			0x0001180000000080ULL
#define	MIO_BOOT_LOC_CFG1			0x0001180000000088ULL
#define	MIO_BOOT_LOC_ADR			0x0001180000000090ULL
#define	MIO_BOOT_LOC_DAT			0x0001180000000098ULL
#define	MIO_BOOT_ERR				0x00011800000000a0ULL
#define	MIO_BOOT_INT				0x00011800000000a8ULL
#define	MIO_BOOT_THR				0x00011800000000b0ULL
#define	MIO_BOOT_BIST_STAT			0x00011800000000f8ULL

/* ---- register bits */

#define	MIO_BOOT_REG_CFGN_XXX_63_37		0xffffffe000000000ULL
#define	MIO_BOOT_REG_CFGN_SAM			0x0000001000000000ULL
#define	MIO_BOOT_REG_CFGN_WE_EXT		0x0000000c00000000ULL
#define	MIO_BOOT_REG_CFGN_OE_EXT		0x0000000300000000ULL
#define	MIO_BOOT_REG_CFGN_EN			0x0000000080000000ULL
#define	MIO_BOOT_REG_CFGN_OR			0x0000000040000000ULL
#define	MIO_BOOT_REG_CFGN_ALE			0x0000000020000000ULL
#define	MIO_BOOT_REG_CFGN_WIDTH			0x0000000010000000ULL
#define	MIO_BOOT_REG_CFGN_SIZE			0x000000000fff0000ULL
#define	MIO_BOOT_REG_CFGN_BASE			0x000000000000ffffULL

#define	MIO_BOOT_REG_TIMN_PAGEM			0x8000000000000000ULL
#define	MIO_BOOT_REG_TIMN_WAITM			0x4000000000000000ULL
#define	MIO_BOOT_REG_TIMN_PAGES			0x3000000000000000ULL
#define	MIO_BOOT_REG_TIMN_ALE			0x0fc0000000000000ULL
#define	MIO_BOOT_REG_TIMN_PAGE			0x003f000000000000ULL
#define	MIO_BOOT_REG_TIMN_WAIT			0x0000fc0000000000ULL
#define	MIO_BOOT_REG_TIMN_PAUSE			0x000003f000000000ULL
#define	MIO_BOOT_REG_TIMN_WR_HLD		0x0000000fc0000000ULL
#define	MIO_BOOT_REG_TIMN_RD_HLD		0x000000003f000000ULL
#define	MIO_BOOT_REG_TIMN_WE			0x0000000000fc0000ULL
#define	MIO_BOOT_REG_TIMN_OE			0x000000000003f000ULL
#define	MIO_BOOT_REG_TIMN_CE			0x0000000000000fc0ULL
#define	MIO_BOOT_REG_TIMN_ADR			0x000000000000003fULL

#define	MIO_BOOT_LOC_CFGN_XXX_63_32		0xffffffff00000000ULL
#define	MIO_BOOT_LOC_CFGN_EN			0x0000000080000000ULL
#define	MIO_BOOT_LOC_CFGN_XXX_30_28		0x0000000070000000ULL
#define	MIO_BOOT_LOC_CFGN_BASE			0x000000000ffffff8ULL
#define	MIO_BOOT_LOC_CFGN_XXX_2_0		0x0000000000000007ULL

#define	MIO_BOOT_LOC_ADR_XXX_63_8		0xffffffffffffff00ULL
#define	MIO_BOOT_LOC_ADR_ADR			0x00000000000000f8ULL
#define	MIO_BOOT_LOC_ADR_XXX_2_0		0x0000000000000007ULL

#define	MIO_BOOT_ERR_XXX_63_2			0xfffffffffffffffcULL
#define	MIO_BOOT_ERR_WAIT_ERR			0x0000000000000002ULL
#define	MIO_BOOT_ERR_ADR_ERR			0x0000000000000001ULL

#define	MIO_BOOT_INT_XXX_63_2			0xfffffffffffffffcULL
#define	MIO_BOOT_INT_WAIT_INT			0x0000000000000002ULL
#define	MIO_BOOT_INT_ADR_INT			0x0000000000000001ULL

#define	MIO_BOOT_THR_XXX_63_14			0xffffffffffffc000ULL
#define	MIO_BOOT_THR_FIF_CNT			0x0000000000003f00ULL
#define	MIO_BOOT_THR_XXX_7_6			0x00000000000000c0ULL
#define	MIO_BOOT_THR_FIF_THR			0x000000000000003fULL

#define	MIO_BOOT_BIST_STAT_XXX_63_4		0xfffffffffffffff0ULL
#define	MIO_BOOT_BIST_STAT_NCBO_1		0x0000000000000008ULL
#define	MIO_BOOT_BIST_STAT_NCBO_0		0x0000000000000004ULL
#define	MIO_BOOT_BIST_STAT_LOC			0x0000000000000002ULL
#define	MIO_BOOT_BIST_STAT_NCBI			0x0000000000000001ULL

/* ---- bus_space */

#define	MIO_BOOT_REG_CFG0_OFFSET		0x0000
#define	MIO_BOOT_REG_CFG1_OFFSET		0x0008
#define	MIO_BOOT_REG_CFG2_OFFSET		0x0010
#define	MIO_BOOT_REG_CFG3_OFFSET		0x0018
#define	MIO_BOOT_REG_CFG4_OFFSET		0x0020
#define	MIO_BOOT_REG_CFG5_OFFSET		0x0028
#define	MIO_BOOT_REG_CFG6_OFFSET		0x0030
#define	MIO_BOOT_REG_CFG7_OFFSET		0x0038
#define	MIO_BOOT_REG_TIM0_OFFSET		0x0040
#define	MIO_BOOT_REG_TIM1_OFFSET		0x0048
#define	MIO_BOOT_REG_TIM2_OFFSET		0x0050
#define	MIO_BOOT_REG_TIM3_OFFSET		0x0058
#define	MIO_BOOT_REG_TIM4_OFFSET		0x0060
#define	MIO_BOOT_REG_TIM5_OFFSET		0x0068
#define	MIO_BOOT_REG_TIM6_OFFSET		0x0070
#define	MIO_BOOT_REG_TIM7_OFFSET		0x0078
#define	MIO_BOOT_LOC_CFG0_OFFSET		0x0080
#define	MIO_BOOT_LOC_CFG1_OFFSET		0x0088
#define	MIO_BOOT_LOC_ADR_OFFSET			0x0090
#define	MIO_BOOT_LOC_DAT_OFFSET			0x0098
#define	MIO_BOOT_ERR_OFFSET			0x00a0
#define	MIO_BOOT_INT_OFFSET			0x00a8
#define	MIO_BOOT_THR_OFFSET			0x00b0
#define	MIO_BOOT_BIST_STAT_OFFSET		0x00f8

#endif /* _CN30XXBOOTBUSREG_H_ */


code:
/*
 * THIS FILE IS AUTOMATICALLY GENERATED
 * DONT EDIT THIS FILE
 */

/*	$OpenBSD: cn30xxciureg.h,v 1.2 2014/08/11 18:29:56 miod Exp $	*/

/*
 * Copyright (c) 2007 Internet Initiative Japan, Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */

/*
 * Cavium Networks OCTEON CN30XX Hardware Reference Manual
 * CN30XX-HM-1.0
 * 11.10 CIU Registers
 */

#ifndef _CN30XXCIUREG_H_
#define _CN30XXCIUREG_H_

/* ---- register addresses */

#define	CIU_INT0_SUM0				0x0001070000000000ULL
#define	CIU_INT1_SUM0				0x0001070000000008ULL
#define	CIU_INT2_SUM0				0x0001070000000010ULL
#define	CIU_INT3_SUM0				0x0001070000000018ULL
#define	CIU_INT32_SUM0				0x0001070000000100ULL
#define	CIU_INT_SUM1				0x0001070000000008ULL
#define	CIU_INT0_EN0				0x0001070000000200ULL
#define	CIU_INT1_EN0				0x0001070000000210ULL
#define	CIU_INT2_EN0				0x0001070000000220ULL
#define	CIU_INT3_EN0				0x0001070000000230ULL
#define	CIU_INT32_EN0				0x0001070000000400ULL
#define	CIU_INT0_EN1				0x0001070000000208ULL
#define	CIU_INT1_EN1				0x0001070000000218ULL
#define	CIU_INT2_EN1				0x0001070000000228ULL
#define	CIU_INT3_EN1				0x0001070000000238ULL
#define	CIU_INT32_EN1				0x0001070000000408ULL
#define	CIU_TIM0				0x0001070000000480ULL
#define	CIU_TIM1				0x0001070000000488ULL
#define	CIU_TIM2				0x0001070000000490ULL
#define	CIU_TIM3				0x0001070000000498ULL
#define	CIU_WDOG0				0x0001070000000500ULL
#define	CIU_WDOG1				0x0001070000000508ULL
#define	CIU_PP_POKE0				0x0001070000000580ULL
#define	CIU_PP_POKE1				0x0001070000000588ULL
#define	CIU_MBOX_SET0				0x0001070000000600ULL
#define	CIU_MBOX_SET1				0x0001070000000600ULL
#define	CIU_MBOX_CLR0				0x0001070000000680ULL
#define	CIU_MBOX_CLR1				0x0001070000000680ULL
#define	CIU_PP_RST				0x0001070000000700ULL
#define	CIU_PP_DBG				0x0001070000000708ULL
#define	CIU_GSTOP				0x0001070000000710ULL
#define	CIU_NMI					0x0001070000000718ULL
#define	CIU_DINT				0x0001070000000720ULL
#define	CIU_FUSE				0x0001070000000728ULL
#define	CIU_BIST				0x0001070000000730ULL
#define	CIU_SOFT_BIST				0x0001070000000738ULL
#define	CIU_SOFT_RST				0x0001070000000740ULL
#define	CIU_SOFT_PRST				0x0001070000000748ULL
#define	CIU_PCI_INTA				0x0001070000000750ULL

#define	CIU_INT0_SUM0_OFFSET			0x0000
#define	CIU_INT1_SUM0_OFFSET			0x0008
#define	CIU_INT2_SUM0_OFFSET			0x0010
#define	CIU_INT3_SUM0_OFFSET			0x0018
#define	CIU_INT32_SUM0_OFFSET			0x0100
#define	CIU_INT_SUM1_OFFSET			0x0008
#define	CIU_INT0_EN0_OFFSET			0x0200
#define	CIU_INT1_EN0_OFFSET			0x0210
#define	CIU_INT2_EN0_OFFSET			0x0220
#define	CIU_INT3_EN0_OFFSET			0x0230
#define	CIU_INT32_EN0_OFFSET			0x0400
#define	CIU_INT0_EN1_OFFSET			0x0208
#define	CIU_INT1_EN1_OFFSET			0x0218
#define	CIU_INT2_EN1_OFFSET			0x0228
#define	CIU_INT3_EN1_OFFSET			0x0238
#define	CIU_INT32_EN1_OFFSET			0x0408
#define	CIU_TIM0_OFFSET				0x0480
#define	CIU_TIM1_OFFSET				0x0488
#define	CIU_TIM2_OFFSET				0x0490
#define	CIU_TIM3_OFFSET				0x0498
#define	CIU_WDOG0_OFFSET			0x0500
#define	CIU_WDOG1_OFFSET			0x0508
#define	CIU_PP_POKE0_OFFSET			0x0580
#define	CIU_PP_POKE1_OFFSET			0x0588
#define	CIU_MBOX_SET0_OFFSET			0x0600
#define	CIU_MBOX_SET1_OFFSET			0x0608
#define	CIU_MBOX_CLR0_OFFSET			0x0680
#define	CIU_MBOX_CLR1_OFFSET			0x0688
#define	CIU_PP_RST_OFFSET			0x0700
#define	CIU_PP_DBG_OFFSET			0x0708
#define	CIU_GSTOP_OFFSET			0x0710
#define	CIU_NMI_OFFSET				0x0718
#define	CIU_DINT_OFFSET				0x0720
#define	CIU_FUSE_OFFSET				0x0728
#define	CIU_BIST_OFFSET				0x0730
#define	CIU_SOFT_BIST_OFFSET			0x0738
#define	CIU_SOFT_RST_OFFSET			0x0740
#define	CIU_SOFT_PRST_OFFSET			0x0748
#define	CIU_PCI_INTA_OFFSET			0x0750

/* ---- register bits */

/* ``interrupt bits'' shift values */

#define	_CIU_INT_XXX_63_SHIFT			0x3f
#define	_CIU_INT_XXX_62_SHIFT			0x3e
#define	_CIU_INT_XXX_61_SHIFT			0x3d
#define	_CIU_INT_XXX_60_SHIFT			0x3c
#define	_CIU_INT_XXX_59_SHIFT			0x3b
#define	_CIU_INT_MPI_SHIFT			0x3a
#define	_CIU_INT_PCM_SHIFT			0x39
#define	_CIU_INT_USB_SHIFT			0x38
#define	_CIU_INT_TIMER_3_SHIFT			0x37
#define	_CIU_INT_TIMER_2_SHIFT			0x36
#define	_CIU_INT_TIMER_1_SHIFT			0x35
#define	_CIU_INT_TIMER_0_SHIFT			0x34
#define	_CIU_INT_XXX_51_SHIFT			0x33
#define	_CIU_INT_IPD_DRP_SHIFT			0x32
#define	_CIU_INT_GMX_DRP_SHIFT			0x30
#define	_CIU_INT_TRACE_SHIFT			0x2f
#define	_CIU_INT_RML_SHIFT			0x2e
#define	_CIU_INT_TWSI_SHIFT			0x2d
#define	_CIU_INT_WDOG_SUM_SHIFT			0x2c
#define	_CIU_INT_PCI_MSI_63_48_SHIFT		0x2b
#define	_CIU_INT_PCI_MSI_47_32_SHIFT		0x2a
#define	_CIU_INT_PCI_MSI_31_16_SHIFT		0x29
#define	_CIU_INT_PCI_MSI_15_0_SHIFT		0x28
#define	_CIU_INT_PCI_INT_D_SHIFT		0x27
#define	_CIU_INT_PCI_INT_C_SHIFT		0x26
#define	_CIU_INT_PCI_INT_B_SHIFT		0x25
#define	_CIU_INT_PCI_INT_A_SHIFT		0x24
#define	_CIU_INT_UART_1_SHIFT			0x23
#define	_CIU_INT_UART_0_SHIFT			0x22
#define	_CIU_INT_MBOX_31_16_SHIFT		0x21
#define	_CIU_INT_MBOX_15_0_SHIFT		0x20
#define	_CIU_INT_GPIO_15_SHIFT			0x1f
#define	_CIU_INT_GPIO_14_SHIFT			0x1e
#define	_CIU_INT_GPIO_13_SHIFT			0x1d
#define	_CIU_INT_GPIO_12_SHIFT			0x1c
#define	_CIU_INT_GPIO_11_SHIFT			0x1b
#define	_CIU_INT_GPIO_10_SHIFT			0x1a
#define	_CIU_INT_GPIO_9_SHIFT			0x19
#define	_CIU_INT_GPIO_8_SHIFT			0x18
#define	_CIU_INT_GPIO_7_SHIFT			0x17
#define	_CIU_INT_GPIO_6_SHIFT			0x16
#define	_CIU_INT_GPIO_5_SHIFT			0x15
#define	_CIU_INT_GPIO_4_SHIFT			0x14
#define	_CIU_INT_GPIO_3_SHIFT			0x13
#define	_CIU_INT_GPIO_2_SHIFT			0x12
#define	_CIU_INT_GPIO_1_SHIFT			0x11
#define	_CIU_INT_GPIO_0_SHIFT			0x10
#define	_CIU_INT_WORKQ_15_SHIFT			0x0f
#define	_CIU_INT_WORKQ_14_SHIFT			0x0e
#define	_CIU_INT_WORKQ_13_SHIFT			0x0d
#define	_CIU_INT_WORKQ_12_SHIFT			0x0c
#define	_CIU_INT_WORKQ_11_SHIFT			0x0b
#define	_CIU_INT_WORKQ_10_SHIFT			0x0a
#define	_CIU_INT_WORKQ_9_SHIFT			0x09
#define	_CIU_INT_WORKQ_8_SHIFT			0x08
#define	_CIU_INT_WORKQ_7_SHIFT			0x07
#define	_CIU_INT_WORKQ_6_SHIFT			0x06
#define	_CIU_INT_WORKQ_5_SHIFT			0x05
#define	_CIU_INT_WORKQ_4_SHIFT			0x04
#define	_CIU_INT_WORKQ_3_SHIFT			0x03
#define	_CIU_INT_WORKQ_2_SHIFT			0x02
#define	_CIU_INT_WORKQ_1_SHIFT			0x01

#define	CIU_INTX_SUM0_XXX_63_59			0xf800000000000000ULL
#define	CIU_INTX_SUM0_MPI			0x0400000000000000ULL
#define	CIU_INTX_SUM0_PCM			0x0200000000000000ULL
#define	CIU_INTX_SUM0_USB			0x0100000000000000ULL
#define	CIU_INTX_SUM0_TIMER			0x00f0000000000000ULL
#define	 CIU_INTX_SUM0_TIMER_3			0x0080000000000000ULL
#define	 CIU_INTX_SUM0_TIMER_2			0x0040000000000000ULL
#define	 CIU_INTX_SUM0_TIMER_1			0x0020000000000000ULL
#define	 CIU_INTX_SUM0_TIMER_0			0x0010000000000000ULL
#define	CIU_INTX_SUM0_XXX_51			0x0008000000000000ULL
#define	CIU_INTX_SUM0_IPD_DRP			0x0004000000000000ULL
#define	CIU_INTX_SUM0_XXX_49			0x0002000000000000ULL
#define	CIU_INTX_SUM0_GMX_DRP			0x0001000000000000ULL
#define	CIU_INTX_SUM0_TRACE			0x0000800000000000ULL
#define	CIU_INTX_SUM0_RML			0x0000400000000000ULL
#define	CIU_INTX_SUM0_TWSI			0x0000200000000000ULL
#define	CIU_INTX_SUM0_WDOG_SUM			0x0000100000000000ULL
#define	CIU_INTX_SUM0_PCI_MSI			0x00000f0000000000ULL
#define	 CIU_INTX_SUM0_PCI_MSI_63_48		0x0000080000000000ULL
#define	 CIU_INTX_SUM0_PCI_MSI_47_32		0x0000040000000000ULL
#define	 CIU_INTX_SUM0_PCI_MSI_31_16		0x0000020000000000ULL
#define	 CIU_INTX_SUM0_PCI_MSI_15_0		0x0000010000000000ULL
#define	CIU_INTX_SUM0_PCI_INT			0x000000f000000000ULL
#define	 CIU_INTX_SUM0_PCI_INT_D		0x0000008000000000ULL
#define	 CIU_INTX_SUM0_PCI_INT_C		0x0000004000000000ULL
#define	 CIU_INTX_SUM0_PCI_INT_B		0x0000002000000000ULL
#define	 CIU_INTX_SUM0_PCI_INT_A		0x0000001000000000ULL
#define	CIU_INTX_SUM0_UART			0x0000000c00000000ULL
#define	 CIU_INTX_SUM0_UART_1			0x0000000800000000ULL
#define	 CIU_INTX_SUM0_UART_0			0x0000000400000000ULL
#define	CIU_INTX_SUM0_MBOX			0x0000000300000000ULL
#define	 CIU_INTX_SUM0_MBOX_31_16		0x0000000200000000ULL
#define	 CIU_INTX_SUM0_MBOX_15_0		0x0000000100000000ULL
#define	CIU_INTX_SUM0_GPIO			0x00000000ffff0000ULL
#define	 CIU_INTX_SUM0_GPIO_15			0x0000000080000000ULL
#define	 CIU_INTX_SUM0_GPIO_14			0x0000000040000000ULL
#define	 CIU_INTX_SUM0_GPIO_13			0x0000000020000000ULL
#define	 CIU_INTX_SUM0_GPIO_12			0x0000000010000000ULL
#define	 CIU_INTX_SUM0_GPIO_11			0x0000000008000000ULL
#define	 CIU_INTX_SUM0_GPIO_10			0x0000000004000000ULL
#define	 CIU_INTX_SUM0_GPIO_9			0x0000000002000000ULL
#define	 CIU_INTX_SUM0_GPIO_8			0x0000000001000000ULL
#define	 CIU_INTX_SUM0_GPIO_7			0x0000000000800000ULL
#define	 CIU_INTX_SUM0_GPIO_6			0x0000000000400000ULL
#define	 CIU_INTX_SUM0_GPIO_5			0x0000000000200000ULL
#define	 CIU_INTX_SUM0_GPIO_4			0x0000000000100000ULL
#define	 CIU_INTX_SUM0_GPIO_3			0x0000000000080000ULL
#define	 CIU_INTX_SUM0_GPIO_2			0x0000000000040000ULL
#define	 CIU_INTX_SUM0_GPIO_1			0x0000000000020000ULL
#define	 CIU_INTX_SUM0_GPIO_0			0x0000000000010000ULL
#define	CIU_INTX_SUM0_WORKQ			0x000000000000ffffULL
#define	 CIU_INTX_SUM0_WORKQ_15			0x0000000000008000ULL
#define	 CIU_INTX_SUM0_WORKQ_14			0x0000000000004000ULL
#define	 CIU_INTX_SUM0_WORKQ_13			0x0000000000002000ULL
#define	 CIU_INTX_SUM0_WORKQ_12			0x0000000000001000ULL
#define	 CIU_INTX_SUM0_WORKQ_11			0x0000000000000800ULL
#define	 CIU_INTX_SUM0_WORKQ_10			0x0000000000000400ULL
#define	 CIU_INTX_SUM0_WORKQ_9			0x0000000000000200ULL
#define	 CIU_INTX_SUM0_WORKQ_8			0x0000000000000100ULL
#define	 CIU_INTX_SUM0_WORKQ_7			0x0000000000000080ULL
#define	 CIU_INTX_SUM0_WORKQ_6			0x0000000000000040ULL
#define	 CIU_INTX_SUM0_WORKQ_5			0x0000000000000020ULL
#define	 CIU_INTX_SUM0_WORKQ_4			0x0000000000000010ULL
#define	 CIU_INTX_SUM0_WORKQ_3			0x0000000000000008ULL
#define	 CIU_INTX_SUM0_WORKQ_2			0x0000000000000004ULL
#define	 CIU_INTX_SUM0_WORKQ_1			0x0000000000000002ULL
#define	 CIU_INTX_SUM0_WORKQ_0			0x0000000000000001ULL

#define	CIU_INT_SUM1_XXX_63_1			0xfffffffffffffffeULL
#define	CIU_INT_SUM1_WDOG			0x0000000000000001ULL

#define	CIU_INTX_EN0_XXX_63_59			0xf800000000000000ULL
#define	CIU_INTX_EN0_MPI			0x0400000000000000ULL
#define	CIU_INTX_EN0_PCM			0x0200000000000000ULL
#define	CIU_INTX_EN0_USB			0x0100000000000000ULL
#define	CIU_INTX_EN0_TIMER			0x00f0000000000000ULL
#define	 CIU_INTX_EN0_TIMER_3			0x0080000000000000ULL
#define	 CIU_INTX_EN0_TIMER_2			0x0040000000000000ULL
#define	 CIU_INTX_EN0_TIMER_1			0x0020000000000000ULL
#define	 CIU_INTX_EN0_TIMER_0			0x0010000000000000ULL
#define	CIU_INTX_EN0_XXX_51			0x0008000000000000ULL
#define	CIU_INTX_EN0_IPD_DRP			0x0004000000000000ULL
#define	CIU_INTX_EN0_XXX_49			0x0002000000000000ULL
#define	CIU_INTX_EN0_GMX_DRP			0x0001000000000000ULL
#define	CIU_INTX_EN0_TRACE			0x0000800000000000ULL
#define	CIU_INTX_EN0_RML			0x0000400000000000ULL
#define	CIU_INTX_EN0_TWSI			0x0000200000000000ULL
#define	CIU_INTX_EN0_WDOG_SUM			0x0000100000000000ULL
#define	CIU_INTX_EN0_PCI_MSI			0x00000f0000000000ULL
#define	 CIU_INTX_EN0_PCI_MSI_63_48		0x0000080000000000ULL
#define	 CIU_INTX_EN0_PCI_MSI_47_32		0x0000040000000000ULL
#define	 CIU_INTX_EN0_PCI_MSI_31_16		0x0000020000000000ULL
#define	 CIU_INTX_EN0_PCI_MSI_15_0		0x0000010000000000ULL
#define	CIU_INTX_EN0_PCI_INT			0x000000f000000000ULL
#define	 CIU_INTX_EN0_PCI_INT_D			0x0000008000000000ULL
#define	 CIU_INTX_EN0_PCI_INT_C			0x0000004000000000ULL
#define	 CIU_INTX_EN0_PCI_INT_B			0x0000002000000000ULL
#define	 CIU_INTX_EN0_PCI_INT_A			0x0000001000000000ULL
#define	CIU_INTX_EN0_UART			0x0000000c00000000ULL
#define	 CIU_INTX_EN0_UART_1			0x0000000800000000ULL
#define	 CIU_INTX_EN0_UART_0			0x0000000400000000ULL
#define	CIU_INTX_EN0_MBOX			0x0000000300000000ULL
#define	 CIU_INTX_EN0_MBOX_31_16		0x0000000200000000ULL
#define	 CIU_INTX_EN0_MBOX_15_0			0x0000000100000000ULL
#define	CIU_INTX_EN0_GPIO			0x00000000ffff0000ULL
#define	 CIU_INTX_EN0_GPIO_15			0x0000000080000000ULL
#define	 CIU_INTX_EN0_GPIO_14			0x0000000040000000ULL
#define	 CIU_INTX_EN0_GPIO_13			0x0000000020000000ULL
#define	 CIU_INTX_EN0_GPIO_12			0x0000000010000000ULL
#define	 CIU_INTX_EN0_GPIO_11			0x0000000008000000ULL
#define	 CIU_INTX_EN0_GPIO_10			0x0000000004000000ULL
#define	 CIU_INTX_EN0_GPIO_9			0x0000000002000000ULL
#define	 CIU_INTX_EN0_GPIO_8			0x0000000001000000ULL
#define	 CIU_INTX_EN0_GPIO_7			0x0000000000800000ULL
#define	 CIU_INTX_EN0_GPIO_6			0x0000000000400000ULL
#define	 CIU_INTX_EN0_GPIO_5			0x0000000000200000ULL
#define	 CIU_INTX_EN0_GPIO_4			0x0000000000100000ULL
#define	 CIU_INTX_EN0_GPIO_3			0x0000000000080000ULL
#define	 CIU_INTX_EN0_GPIO_2			0x0000000000040000ULL
#define	 CIU_INTX_EN0_GPIO_1			0x0000000000020000ULL
#define	 CIU_INTX_EN0_GPIO_0			0x0000000000010000ULL
#define	CIU_INTX_EN0_WORKQ			0x000000000000ffffULL
#define	 CIU_INTX_EN0_WORKQ_15			0x0000000000008000ULL
#define	 CIU_INTX_EN0_WORKQ_14			0x0000000000004000ULL
#define	 CIU_INTX_EN0_WORKQ_13			0x0000000000002000ULL
#define	 CIU_INTX_EN0_WORKQ_12			0x0000000000001000ULL
#define	 CIU_INTX_EN0_WORKQ_11			0x0000000000000800ULL
#define	 CIU_INTX_EN0_WORKQ_10			0x0000000000000400ULL
#define	 CIU_INTX_EN0_WORKQ_9			0x0000000000000200ULL
#define	 CIU_INTX_EN0_WORKQ_8			0x0000000000000100ULL
#define	 CIU_INTX_EN0_WORKQ_7			0x0000000000000080ULL
#define	 CIU_INTX_EN0_WORKQ_6			0x0000000000000040ULL
#define	 CIU_INTX_EN0_WORKQ_5			0x0000000000000020ULL
#define	 CIU_INTX_EN0_WORKQ_4			0x0000000000000010ULL
#define	 CIU_INTX_EN0_WORKQ_3			0x0000000000000008ULL
#define	 CIU_INTX_EN0_WORKQ_2			0x0000000000000004ULL
#define	 CIU_INTX_EN0_WORKQ_1			0x0000000000000002ULL
#define	 CIU_INTX_EN0_WORKQ_0			0x0000000000000001ULL

#define	CIU_INTX_EN1_XXX_63_1			0xfffffffffffffffeULL
#define	CIU_INTX_EN1_WDOG			0x0000000000000001ULL

#define	CIU_TIMX_XXX_63_37			0xffffffe000000000ULL
#define	CIU_TIMX_ONE_SHOT			0x0000001000000000ULL
#define	CIU_TIMX_LEN				0x0000000fffffffffULL

#define	CIU_WDOGX_XXX_63_46			0xffffc00000000000ULL
#define	CIU_WDOGX_GSTOPEN			0x0000200000000000ULL
#define	CIU_WDOGX_DSTOP				0x0000100000000000ULL
#define	CIU_WDOGX_CNT				0x00000ffffff00000ULL
#define	CIU_WDOGX_LEN				0x00000000000ffff0ULL
#define	CIU_WDOGX_STATE				0x000000000000000cULL
#define	CIU_WDOGX_MODE				0x0000000000000003ULL

#define	CIU_PP_POKEX_XXX_63_0			0xffffffffffffffffULL

#define	CIU_MBOX_SETX_XXX_63_32			0xffffffff00000000ULL
#define	CIU_MBOX_SETX_SET			0x00000000ffffffffULL

#define	CIU_MBOX_CLRX_XXX_63_32			0xffffffff00000000ULL
#define	CIU_MBOX_CLRX_CLR			0x00000000ffffffffULL

#define	CIU_PP_RST_XXX_63_1			0xfffffffffffffffeULL
#define	CIU_PP_RST_RST0				0x0000000000000001ULL

#define	CIU_PP_DBG_XXX_63_1			0xfffffffffffffffeULL
#define	CIU_PP_DBG_PPDBG			0x0000000000000001ULL

#define	CIU_GSTOP_XXX_63_1			0xfffffffffffffffeULL
#define	CIU_GSTOP_GSTOP				0x0000000000000001ULL

#define	CIU_NMI_XXX_63_1			0xfffffffffffffffeULL
#define	CIU_NMI_NMI				0x0000000000000001ULL

#define	CIU_DINT_XXX_63_1			0xfffffffffffffffeULL
#define	CIU_DINT_DINT				0x0000000000000001ULL

#define	CIU_FUSE_XXX_63_1			0xfffffffffffffffeULL
#define	CIU_FUSE_FUSE				0x0000000000000001ULL

#define	CIU_BIST_XXX_63_4			0xfffffffffffffff0ULL
#define	CIU_BIST_BIST				0x000000000000000fULL

#define	CIU_SOFT_BIST_XXX_63_1			0xfffffffffffffffeULL
#define	CIU_SOFT_BIST_SOFT_BIST			0x0000000000000001ULL

#define	CIU_SOFT_RST_XXX_63_1			0xfffffffffffffffeULL
#define	CIU_SOFT_RST_SOFT_RST			0x0000000000000001ULL

#define	CIU_SOFT_PRST_XXX_63_1			0xfffffffffffffff8ULL
#define	CIU_SOFT_PRST_HOST64			0x0000000000000004ULL
#define	CIU_SOFT_PRST_NPI			0x0000000000000002ULL
#define	CIU_SOFT_PRST_SOFT_PRST			0x0000000000000001ULL

#define	CIU_PCI_INTA_XXX_63_2			0xfffffffffffffffcULL
#define	CIU_PCI_INTA_INT			0x0000000000000003ULL

#endif /* _CN30XXCIUREG_H_ */


code:
/*	$OpenBSD: cn30xxcorereg.h,v 1.1 2014/03/13 02:17:13 yasuoka Exp $	*/

/*
 * Copyright (c) 2014 YASUOKA Masahiko <yasuoka@openbsd.org>
 *
 * Permission to use, copy, modify, and distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#ifndef _CN30XXCOREREG_H_
#define _CN30XXCOREREG_H_

/*
 * Cavium Networks OCTEON CN30XX Hardware Reference Manual CN30XX-HM-1.0
 * 4. cnMIPS Cores
 */

/* 4.11 Core Coprocessor 0 Privileged Registers */

/* CvmCtl Registers */
#define COP_0_CVMCTL_FUSE_START_BIT	0x80000000
#define COP_0_CVMCTL_NOFDA_CP2		0x10000000
#define COP_0_CVMCTL_NOMUL		0x08000000
#define COP_0_CVMCTL_NOCRYPTO		0x04000000
#define COP_0_CVMCTL_RST_SHT		0x02000000
#define COP_0_CVMCTL_BIST_DIS		0x01000000
#define COP_0_CVMCTL_DISSETPRED		0x00800000
#define COP_0_CVMCTL_DISJRPRED		0x00400000
#define COP_0_CVMCTL_DISICACHE		0x00200000
#define COP_0_CVMCTL_DISWAIT		0x00100000
#define COP_0_CVMCTL_DEFET		0x00080000
#define COP_0_CVMCTL_DISCO		0x00040000
#define COP_0_CVMCTL_DISCE		0x00020000
#define COP_0_CVMCTL_DDCLK		0x00010000
#define COP_0_CVMCTL_DCICLK		0x00008000
#define COP_0_CVMCTL_REPUN		0x00004000
#define COP_0_CVMCTL_IPREF		0x00002000
#define COP_0_CVMCTL_USEUN		0x00001000
#define COP_0_CVMCTL_DISIOCACHE		0x00000800
#define COP_0_CVMCTL_IRAND		0x00000400
#define COP_0_CVMCTL_IPPCI		0x00000380
#define COP_0_CVMCTL_IPTI		0x00000070
#define COP_0_CVMCTL_LE			0x00000002
#define COP_0_CVMCTL_USELY		0x00000001

#endif /* _CN30XXCOREREG_H_ */


code:
/*	$OpenBSD: cn30xxfau.c,v 1.5 2014/08/11 18:08:17 miod Exp $	*/

/*
 * Copyright (c) 2007 Internet Initiative Japan, Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */

#include <sys/param.h>
#include <sys/systm.h>

#include <machine/octeonvar.h>

#include <octeon/dev/cn30xxfaureg.h>
#include <octeon/dev/cn30xxfauvar.h>

int64_t	cn30xxfau_op_load(uint64_t);
void	cn30xxfau_op_iobdma(int, uint64_t);
void	cn30xxfau_op_store(uint64_t, int64_t);
int64_t	cn30xxfau_op_load_paddr(int, int, int) __unused;
void	cn30xxfau_op_iobdma_store_data(int, int, int, int, int);
void	cn30xxfau_op_store_paddr(int, int, int64_t);

/* ---- utilities */

int64_t
cn30xxfau_op_load(uint64_t args)
{
	paddr_t addr;

	addr =
	    ((uint64_t)1 << 48) |
	    ((uint64_t)(CN30XXFAU_MAJORDID & 0x1f) << 43) |
	    ((uint64_t)(CN30XXFAU_SUBDID & 0x7) << 40) |
	    ((uint64_t)(args & 0xfffffffffULL) << 0);
	return octeon_xkphys_read_8(addr);
}

void
cn30xxfau_op_store(uint64_t args, int64_t value)
{
	paddr_t addr;

	addr =
	    ((uint64_t)1 << 48) |
	    ((uint64_t)(CN30XXFAU_MAJORDID & 0x1f) << 43) |
	    ((uint64_t)(CN30XXFAU_SUBDID & 0x7) << 40) |
	    ((uint64_t)(args & 0xfffffffffULL) << 0);
	octeon_xkphys_write_8(addr, value);
}

/* ---- operation primitives */

/*
 * 3.4 Fetch-and-Add Operations
 */

/* 3.4.1 Load Operations */

/* Load Physical Address for FAU Operations */

int64_t
cn30xxfau_op_load_paddr(int incval, int tagwait, int reg)
{
	uint64_t args;

	args =
	    ((uint64_t)(incval & 0x3fffff) << 14) |
	    ((uint64_t)(tagwait & 0x1) << 13) |
	    ((uint64_t)(reg & 0x7ff) << 0);
	return cn30xxfau_op_load(args);
}

/* 3.4.3 Store Operations */

/* Store Physical Address for FAU Operations */

void
cn30xxfau_op_store_paddr(int noadd, int reg, int64_t value)
{
	uint64_t args;

	args =
	    ((uint64_t)(noadd & 0x1) << 13) |
	    ((uint64_t)(reg & 0x7ff) << 0);
	cn30xxfau_op_store(args, value);
}

/* ---- API */

void
cn30xxfau_op_init(struct cn30xxfau_desc *fd, size_t scroff, size_t regno)
{
	fd->fd_scroff = scroff;
	fd->fd_regno = regno;
}

uint64_t
cn30xxfau_op_save(struct cn30xxfau_desc *fd)
{
	mips_sync();
	return octeon_cvmseg_read_8(fd->fd_scroff);
}

void
cn30xxfau_op_restore(struct cn30xxfau_desc *fd, uint64_t backup)
{
	octeon_cvmseg_write_8(fd->fd_scroff, backup);
}

int64_t
cn30xxfau_op_inc_8(struct cn30xxfau_desc *fd, int64_t v)
{
	cn30xxfau_op_iobdma_store_data(fd->fd_scroff, v, 0, OCT_FAU_OP_SIZE_64/* XXX */,
	    fd->fd_regno);
	mips_sync();
	return octeon_cvmseg_read_8(fd->fd_scroff)/* XXX */;
}

int64_t
cn30xxfau_op_incwait_8(struct cn30xxfau_desc *fd, int v)
{
	cn30xxfau_op_iobdma_store_data(fd->fd_scroff, v, 1, OCT_FAU_OP_SIZE_64/* XXX */,
	    fd->fd_regno);
	/* XXX */
	mips_sync();
	/* XXX */
	return octeon_cvmseg_read_8(fd->fd_scroff)/* XXX */;
}

void
cn30xxfau_op_add_8(struct cn30xxfau_desc *fd, int64_t v)
{
	cn30xxfau_op_store_paddr(0, fd->fd_regno, v);
}

void
cn30xxfau_op_set_8(struct cn30xxfau_desc *fd, int64_t v)
{
	cn30xxfau_op_store_paddr(1, fd->fd_regno, v);
}


code:
/*
 * THIS FILE IS AUTOMATICALLY GENERATED
 * DONT EDIT THIS FILE
 */

/*	$OpenBSD: cn30xxfaureg.h,v 1.1 2011/06/16 11:22:30 syuu Exp $	*/

/*
 * Copyright (c) 2007 Internet Initiative Japan, Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */

/*
 * Cavium Networks OCTEON CN30XX Hardware Reference Manual
 * CN30XX-HM-1.0
 * 3.4 Fetch-and-Add Operations
 */

#ifndef _CN30XXFAUREG_H_
#define _CN30XXFAUREG_H_

/* ---- operations */

#define	CN30XXFAU_MAJORDID	0x1e
#define	CN30XXFAU_SUBDID	0

#endif /* _CN30XXFAUREG_H_ */


code:
/*	$OpenBSD: cn30xxfauvar.h,v 1.2 2013/06/01 22:20:35 jasper Exp $	*/

/*
 * Copyright (c) 2007 Internet Initiative Japan, Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */

#ifndef _CN30XXFAUVAR_H_
#define _CN30XXFAUVAR_H_

/* ---- API */

struct cn30xxfau_desc {
	/* offset in scratch buffer */
	size_t		fd_scroff;	/* XXX offset_t */
	/* FAU register number */
	size_t		fd_regno;	/* XXX offset_t */
};

void		cn30xxfau_op_init(struct cn30xxfau_desc *, size_t, size_t);
uint64_t	cn30xxfau_op_save(struct cn30xxfau_desc *);
void		cn30xxfau_op_restore(struct cn30xxfau_desc *, uint64_t);
int64_t		cn30xxfau_op_inc_8(struct cn30xxfau_desc *, int64_t);
int32_t		cn30xxfau_op_inc_4(struct cn30xxfau_desc *, int32_t);
int16_t		cn30xxfau_op_inc_2(struct cn30xxfau_desc *, int16_t);
int8_t		cn30xxfau_op_inc_1(struct cn30xxfau_desc *, int8_t);
int64_t		cn30xxfau_op_incwait_8(struct cn30xxfau_desc *, int);
int32_t		cn30xxfau_op_incwait_4(struct cn30xxfau_desc *, int);
int16_t		cn30xxfau_op_incwait_2(struct cn30xxfau_desc *, int);
int8_t		cn30xxfau_op_incwait_1(struct cn30xxfau_desc *, int);
int64_t		cn30xxfau_op_get_8(struct cn30xxfau_desc *);
int32_t		cn30xxfau_op_get_4(struct cn30xxfau_desc *);
int16_t		cn30xxfau_op_get_2(struct cn30xxfau_desc *);
int8_t		cn30xxfau_op_get_1(struct cn30xxfau_desc *);
int64_t		cn30xxfau_op_getwait_8(struct cn30xxfau_desc *);
int32_t		cn30xxfau_op_getwait_4(struct cn30xxfau_desc *);
int16_t		cn30xxfau_op_getwait_2(struct cn30xxfau_desc *);
int8_t		cn30xxfau_op_getwait_1(struct cn30xxfau_desc *);
void		cn30xxfau_op_add_8(struct cn30xxfau_desc *, int64_t);
void		cn30xxfau_op_add_4(struct cn30xxfau_desc *, int32_t);
void		cn30xxfau_op_add_2(struct cn30xxfau_desc *, int16_t);
void		cn30xxfau_op_add_1(struct cn30xxfau_desc *, int8_t);
void		cn30xxfau_op_set_8(struct cn30xxfau_desc *, int64_t);
void		cn30xxfau_op_set_4(struct cn30xxfau_desc *, int32_t);
void		cn30xxfau_op_set_2(struct cn30xxfau_desc *, int16_t);
void		cn30xxfau_op_set_1(struct cn30xxfau_desc *, int8_t);

/* ---- old API */

/* XXX */
#define OCT_FAU_REG_OQ_ADDR_INDEX (0)
#define OCT_FAU_REG_ADDR_END (256)
/* XXX */

/* XXX */
typedef enum {
	OCT_FAU_OP_SIZE_8  = 0,
	OCT_FAU_OP_SIZE_16 = 1,
	OCT_FAU_OP_SIZE_32 = 2,
	OCT_FAU_OP_SIZE_64 = 3
} fau_op_size_t;
/* XXX */

static inline void
cn30xxfau_op_iobdma(int index, uint64_t args)
{
	uint64_t value;

	value =
	    ((uint64_t)(index & 0xff) << 56) |
	    ((uint64_t)1 << 48) |
	    ((uint64_t)(CN30XXFAU_MAJORDID & 0x1f) << 43) |
	    ((uint64_t)(CN30XXFAU_SUBDID & 0x7) << 40) |
	    ((uint64_t)args & 0xfffffffffULL);
	octeon_iobdma_write_8(value);
}

/* 3.4.2 IOBDMA Operations */

/* IOBDMA Store Data for FAU Operations */

static inline void
cn30xxfau_op_iobdma_store_data(int scraddr, int incval, int tagwait,
    int size, int reg)
{
	uint64_t args;

	args =
	    ((uint64_t)(incval & 0x3fffff) << 14) |
	    ((uint64_t)(tagwait & 0x1) << 13) |
	    ((uint64_t)(size & 0x3) << 11) |
	    ((uint64_t)(reg & 0x7ff) << 0);
	/* use `srcaddr` as `index' */
	cn30xxfau_op_iobdma((int)((uint32_t)scraddr >> 3) /* XXX */, args);
}

static inline void
cn30xxfau_op_inc_fetch_8(struct cn30xxfau_desc *fd, int64_t v)
{
	cn30xxfau_op_iobdma_store_data(fd->fd_scroff, v, 0, OCT_FAU_OP_SIZE_64/* XXX */,
	    fd->fd_regno);
}

static inline int64_t
cn30xxfau_op_inc_read_8(struct cn30xxfau_desc *fd)
{
	mips_sync();
	return octeon_cvmseg_read_8(fd->fd_scroff);
}

#endif /* _CN30XXFAUVAR_H_ */


code:
/*	$OpenBSD: cn30xxfpa.c,v 1.5 2015/07/19 00:12:54 jasper Exp $	*/

/*
 * Copyright (c) 2007 Internet Initiative Japan, Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */

#undef	FPADEBUG

#include <sys/param.h>
#include <sys/systm.h>
#include <sys/types.h>
#include <sys/malloc.h>

#include <machine/bus.h>
#include <machine/vmparam.h>
#include <machine/octeonvar.h>

#include <octeon/dev/cn30xxfpavar.h>
#include <octeon/dev/cn30xxfpareg.h>

#ifdef FPADEBUG
#define	DPRINTF(x)	printf x
#else
#define	DPRINTF(x)
#endif

#define	_DMA_NSEGS	1
#define	_DMA_BUFLEN	0x01000000

/* pool descriptor */
struct cn30xxfpa_desc {
};

struct cn30xxfpa_softc {
	int			sc_initialized;

	bus_space_tag_t		sc_regt;
	bus_space_handle_t	sc_regh;

	bus_space_tag_t		sc_opst;
	bus_space_handle_t	sc_opsh;

	bus_dma_tag_t		sc_dmat;

	struct cn30xxfpa_desc	sc_descs[8];
};

void		cn30xxfpa_bootstrap(struct octeon_config *);
void		cn30xxfpa_reset(void);
void		cn30xxfpa_int_enable(struct cn30xxfpa_softc *, int);
void		cn30xxfpa_buf_dma_alloc(struct cn30xxfpa_buf *);

void		cn30xxfpa_init(struct cn30xxfpa_softc *);
#ifdef notyet
uint64_t	cn30xxfpa_iobdma(struct cn30xxfpa_softc *, int, int);
#endif

#ifdef OCTEON_ETH_DEBUG
void		cn30xxfpa_intr_rml(void *);
#endif

static struct cn30xxfpa_softc	cn30xxfpa_softc;

/* ---- global functions */

void
cn30xxfpa_bootstrap(struct octeon_config *mcp)
{
	struct cn30xxfpa_softc *sc = &cn30xxfpa_softc;

	sc->sc_regt = mcp->mc_iobus_bust;
	sc->sc_opst = mcp->mc_iobus_bust;
	sc->sc_dmat = mcp->mc_iobus_dmat;

	cn30xxfpa_init(sc);
}

void
cn30xxfpa_reset(void)
{
	/* XXX */
}

#ifdef OCTEON_ETH_DEBUG
int	cn30xxfpa_intr_rml_verbose;

void
cn30xxfpa_intr_rml(void *arg)
{
	struct cn30xxfpa_softc *sc;
	uint64_t reg;

	sc = &cn30xxfpa_softc;
	KASSERT(sc != NULL);
	reg = cn30xxfpa_int_summary();
	if (cn30xxfpa_intr_rml_verbose)
		printf("%s: FPA_INT_SUM=0x%016llx\n", __func__, reg);
}

void
cn30xxfpa_int_enable(struct cn30xxfpa_softc *sc, int enable)
{
	const uint64_t int_xxx =
	    FPA_INT_ENB_Q7_PERR | FPA_INT_ENB_Q7_COFF | FPA_INT_ENB_Q7_UND |
	    FPA_INT_ENB_Q6_PERR | FPA_INT_ENB_Q6_COFF | FPA_INT_ENB_Q6_UND |
	    FPA_INT_ENB_Q5_PERR | FPA_INT_ENB_Q5_COFF | FPA_INT_ENB_Q5_UND |
	    FPA_INT_ENB_Q4_PERR | FPA_INT_ENB_Q4_COFF | FPA_INT_ENB_Q4_UND |
	    FPA_INT_ENB_Q3_PERR | FPA_INT_ENB_Q3_COFF | FPA_INT_ENB_Q3_UND |
	    FPA_INT_ENB_Q2_PERR | FPA_INT_ENB_Q2_COFF | FPA_INT_ENB_Q2_UND |
	    FPA_INT_ENB_Q1_PERR | FPA_INT_ENB_Q1_COFF | FPA_INT_ENB_Q1_UND |
	    FPA_INT_ENB_Q0_PERR | FPA_INT_ENB_Q0_COFF | FPA_INT_ENB_Q0_UND |
	    FPA_INT_ENB_FED1_DBE | FPA_INT_ENB_FED1_SBE |
	    FPA_INT_ENB_FED0_DBE | FPA_INT_ENB_FED0_SBE;

	bus_space_write_8(sc->sc_regt, sc->sc_regh, FPA_INT_SUM_OFFSET,
	    int_xxx);
	if (enable)
		bus_space_write_8(sc->sc_regt, sc->sc_regh, FPA_INT_ENB_OFFSET,
		    int_xxx);
}

uint64_t
cn30xxfpa_int_summary(void)
{
	struct cn30xxfpa_softc *sc = &cn30xxfpa_softc;
	uint64_t summary;

	summary = bus_space_read_8(sc->sc_regt, sc->sc_regh, FPA_INT_SUM_OFFSET);
	bus_space_write_8(sc->sc_regt, sc->sc_regh, FPA_INT_SUM_OFFSET, summary);
	return summary;
}
#endif

int
cn30xxfpa_buf_init(int poolno, size_t size, size_t nelems,
    struct cn30xxfpa_buf **rfb)
{
	struct cn30xxfpa_softc *sc = &cn30xxfpa_softc;
	struct cn30xxfpa_buf *fb;
	int nsegs;
	paddr_t paddr;

	nsegs = 1/* XXX */;
	fb = malloc(sizeof(*fb) + sizeof(*fb->fb_dma_segs) * nsegs, M_DEVBUF,
	    M_WAITOK | M_ZERO);
	if (fb == NULL)
		return 1;
	fb->fb_poolno = poolno;
	fb->fb_size = size;
	fb->fb_nelems = nelems;
	fb->fb_len = size * nelems;
	fb->fb_dmat = sc->sc_dmat;
	fb->fb_dma_segs = (void *)(fb + 1);
	fb->fb_dma_nsegs = nsegs;

	cn30xxfpa_buf_dma_alloc(fb);

	for (paddr = fb->fb_paddr; paddr < fb->fb_paddr + fb->fb_len;
	    paddr += fb->fb_size)
		cn30xxfpa_buf_put_paddr(fb, paddr);

	*rfb = fb;

	return 0;
}

void *
cn30xxfpa_buf_get(struct cn30xxfpa_buf *fb)
{
	paddr_t paddr;
	vaddr_t addr;

	paddr = cn30xxfpa_buf_get_paddr(fb);
	if (paddr == 0)
		addr = 0;
	else
		addr = fb->fb_addr + (vaddr_t/* XXX */)(paddr - fb->fb_paddr);
	return (void *)addr;
}

void
cn30xxfpa_buf_dma_alloc(struct cn30xxfpa_buf *fb)
{
	int status;
	int nsegs;
	caddr_t va;

	status = bus_dmamap_create(fb->fb_dmat, fb->fb_len,
	    fb->fb_len / PAGE_SIZE,	/* # of segments */
	    fb->fb_len,			/* we don't use s/g for FPA buf */
	    PAGE_SIZE,			/* OCTEON hates >PAGE_SIZE boundary */
	    0, &fb->fb_dmah);
	if (status != 0)
		panic("%s failed", "bus_dmamap_create");

	status = bus_dmamem_alloc(fb->fb_dmat, fb->fb_len, 128, 0,
	    fb->fb_dma_segs, fb->fb_dma_nsegs, &nsegs, 0);
	if (status != 0 || fb->fb_dma_nsegs != nsegs)
		panic("%s failed", "bus_dmamem_alloc");

	status = bus_dmamem_map(fb->fb_dmat, fb->fb_dma_segs, fb->fb_dma_nsegs,
	    fb->fb_len, &va, 0);
	if (status != 0)
		panic("%s failed", "bus_dmamem_map");

	status = bus_dmamap_load(fb->fb_dmat, fb->fb_dmah, va, fb->fb_len,
	    NULL,		/* kernel */
	    0);
	if (status != 0)
		panic("%s failed", "bus_dmamap_load");

	fb->fb_addr = (vaddr_t)va;
	fb->fb_paddr = fb->fb_dma_segs[0].ds_addr;
}

uint64_t
cn30xxfpa_query(int poolno)
{
	struct cn30xxfpa_softc *sc = &cn30xxfpa_softc;

	return bus_space_read_8(sc->sc_regt, sc->sc_regh,
	    FPA_QUE0_AVAILABLE_OFFSET + sizeof(uint64_t) * poolno);
}

/* ---- local functions */

void	cn30xxfpa_init_bus(struct cn30xxfpa_softc *);
void	cn30xxfpa_init_bus_space(struct cn30xxfpa_softc *);
void	cn30xxfpa_init_regs(struct cn30xxfpa_softc *);

void
cn30xxfpa_init(struct cn30xxfpa_softc *sc)
{
	if (sc->sc_initialized != 0)
		panic("%s: already initialized", __func__);
	sc->sc_initialized = 1;

	cn30xxfpa_init_bus(sc);
	cn30xxfpa_init_regs(sc);
#ifdef OCTEON_ETH_DEBUG
	cn30xxfpa_int_enable(sc, 1);
#endif
}

void
cn30xxfpa_init_bus(struct cn30xxfpa_softc *sc)
{
	cn30xxfpa_init_bus_space(sc);
}

void
cn30xxfpa_init_bus_space(struct cn30xxfpa_softc *sc)
{
	int status;

	status = bus_space_map(sc->sc_regt, FPA_BASE, FPA_SIZE, 0, &sc->sc_regh);
	if (status != 0)
		panic("can't map %s space", "register");

	/* CN30XX-HM-1.0 Table 4-25 */
	status = bus_space_map(sc->sc_opst,
	    0x0001180028000000ULL/* XXX */, 0x0200/* XXX */, 0, &sc->sc_opsh);
	if (status != 0)
		panic("can't map %s space", "operations");
}

void
cn30xxfpa_init_regs(struct cn30xxfpa_softc *sc)
{

	bus_space_write_8(sc->sc_regt, sc->sc_regh, FPA_CTL_STATUS_OFFSET,
	    FPA_CTL_STATUS_ENB);

/* XXX */
#ifdef OCTEON_ETH_DEBUG
	bus_space_write_8(sc->sc_regt, sc->sc_regh, FPA_INT_ENB_OFFSET,
	    FPA_INT_ENB_Q7_PERR | FPA_INT_ENB_Q7_COFF | FPA_INT_ENB_Q7_UND |
	    FPA_INT_ENB_Q6_PERR | FPA_INT_ENB_Q6_COFF | FPA_INT_ENB_Q6_UND |
	    FPA_INT_ENB_Q5_PERR | FPA_INT_ENB_Q5_COFF | FPA_INT_ENB_Q5_UND |
	    FPA_INT_ENB_Q4_PERR | FPA_INT_ENB_Q4_COFF | FPA_INT_ENB_Q4_UND |
	    FPA_INT_ENB_Q3_PERR | FPA_INT_ENB_Q3_COFF | FPA_INT_ENB_Q3_UND |
	    FPA_INT_ENB_Q2_PERR | FPA_INT_ENB_Q2_COFF | FPA_INT_ENB_Q2_UND |
	    FPA_INT_ENB_Q1_PERR | FPA_INT_ENB_Q1_COFF | FPA_INT_ENB_Q1_UND |
	    FPA_INT_ENB_Q0_PERR | FPA_INT_ENB_Q0_COFF | FPA_INT_ENB_Q0_UND |
	    FPA_INT_ENB_FED1_DBE | FPA_INT_ENB_FED1_SBE |
	    FPA_INT_ENB_FED0_DBE | FPA_INT_ENB_FED0_SBE);
#endif
}

#ifdef OCTEON_ETH_DEBUG
void	cn30xxfpa_dump_regs(void);
void	cn30xxfpa_dump_bufs(void);
void	cn30xxfpa_dump_buf(int);

#define	_ENTRY(x)	{ #x, x##_OFFSET }

struct cn30xxfpa_dump_reg_ {
	const char *name;
	size_t	offset;
};

const struct cn30xxfpa_dump_reg_ cn30xxfpa_dump_regs_[] = {
	_ENTRY(FPA_INT_SUM),
	_ENTRY(FPA_INT_ENB),
	_ENTRY(FPA_CTL_STATUS),
	_ENTRY(FPA_QUE0_AVAILABLE),
	_ENTRY(FPA_QUE1_AVAILABLE),
	_ENTRY(FPA_QUE2_AVAILABLE),
	_ENTRY(FPA_QUE3_AVAILABLE),
	_ENTRY(FPA_QUE4_AVAILABLE),
	_ENTRY(FPA_QUE5_AVAILABLE),
	_ENTRY(FPA_QUE6_AVAILABLE),
	_ENTRY(FPA_QUE7_AVAILABLE),
	_ENTRY(FPA_WART_CTL),
	_ENTRY(FPA_WART_STATUS),
	_ENTRY(FPA_BIST_STATUS),
	_ENTRY(FPA_QUE0_PAGE_INDEX),
	_ENTRY(FPA_QUE1_PAGE_INDEX),
	_ENTRY(FPA_QUE2_PAGE_INDEX),
	_ENTRY(FPA_QUE3_PAGE_INDEX),
	_ENTRY(FPA_QUE4_PAGE_INDEX),
	_ENTRY(FPA_QUE5_PAGE_INDEX),
	_ENTRY(FPA_QUE6_PAGE_INDEX),
	_ENTRY(FPA_QUE7_PAGE_INDEX),
	_ENTRY(FPA_QUE_EXP),
	_ENTRY(FPA_QUE_ACT),
};

const char *cn30xxfpa_dump_bufs_[8] = {
	[0] = "recv",
	[1] = "wq",
	[2] = "cmdbuf",
	[3] = "gbuf",
};

void
cn30xxfpa_dump(void)
{
	cn30xxfpa_dump_regs();
	cn30xxfpa_dump_bufs();
}

void
cn30xxfpa_dump_regs(void)
{
	struct cn30xxfpa_softc *sc = &cn30xxfpa_softc;
	const struct cn30xxfpa_dump_reg_ *reg;
	uint64_t tmp;
	int i;

	for (i = 0; i < nitems(cn30xxfpa_dump_regs_); i++) {
		reg = &cn30xxfpa_dump_regs_[i];
		tmp = bus_space_read_8(sc->sc_regt, sc->sc_regh, reg->offset);
		printf("\t%-24s: %16llx\n", reg->name, tmp);
	}
}

/*
 * XXX assume pool 7 is unused!
 */
void
cn30xxfpa_dump_bufs(void)
{
	int i;

	for (i = 0; i < 8; i++)
		cn30xxfpa_dump_buf(i);
}

void
cn30xxfpa_dump_buf(int pool)
{
	int i;
	uint64_t ptr;
	const char *name;

	name = cn30xxfpa_dump_bufs_[pool];
	if (name == NULL)
		return;
	printf("%s pool:\n", name);
	for (i = 0; (ptr = cn30xxfpa_load(pool)) != 0; i++) {
		printf("\t%016llx%s", ptr, ((i % 4) == 3) ? "\n" : "");
		cn30xxfpa_store(ptr, OCTEON_POOL_NO_DUMP, 0);
	}
	if (i % 4 != 3)
		printf("\n");
	printf("total = %d buffers\n", i);
	while ((ptr = cn30xxfpa_load(OCTEON_POOL_NO_DUMP)) != 0)
		cn30xxfpa_store(ptr, pool, 0);
}
#endif


code:
/*
 * THIS FILE IS AUTOMATICALLY GENERATED
 * DONT EDIT THIS FILE
 */

/*	$OpenBSD: cn30xxfpareg.h,v 1.2 2014/08/11 18:29:56 miod Exp $	*/

/*
 * Copyright (c) 2007 Internet Initiative Japan, Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */

/*
 * Cavium Networks OCTEON CN30XX Hardware Reference Manual
 * CN30XX-HM-1.0
 * 6.2 FPA Registers
 */

#ifndef _CN30XXFPAREG_H_
#define _CN30XXFPAREG_H_

/* ---- register offsets */

#define	FPA_INT_SUM				0x0001180028000040ULL
#define	FPA_INT_ENB				0x0001180028000048ULL
#define	FPA_CTL_STATUS				0x0001180028000050ULL
#define	FPA_QUE0_AVAILABLE			0x0001180028000098ULL
#define	FPA_QUE1_AVAILABLE			0x00011800280000a0ULL
#define	FPA_QUE2_AVAILABLE			0x00011800280000a8ULL
#define	FPA_QUE3_AVAILABLE			0x00011800280000b0ULL
#define	FPA_QUE4_AVAILABLE			0x00011800280000b8ULL
#define	FPA_QUE5_AVAILABLE			0x00011800280000c0ULL
#define	FPA_QUE6_AVAILABLE			0x00011800280000c8ULL
#define	FPA_QUE7_AVAILABLE			0x00011800280000d0ULL
#define	FPA_WART_CTL				0x00011800280000d8ULL
#define	FPA_WART_STATUS				0x00011800280000e0ULL
#define	FPA_BIST_STATUS				0x00011800280000e8ULL
#define	FPA_QUE0_PAGE_INDEX			0x00011800280000f0ULL
#define	FPA_QUE1_PAGE_INDEX			0x00011800280000f8ULL
#define	FPA_QUE2_PAGE_INDEX			0x0001180028000100ULL
#define	FPA_QUE3_PAGE_INDEX			0x0001180028000108ULL
#define	FPA_QUE4_PAGE_INDEX			0x0001180028000110ULL
#define	FPA_QUE5_PAGE_INDEX			0x0001180028000118ULL
#define	FPA_QUE6_PAGE_INDEX			0x0001180028000120ULL
#define	FPA_QUE7_PAGE_INDEX			0x0001180028000128ULL
#define	FPA_QUE_EXP				0x0001180028000130ULL
#define	FPA_QUE_ACT				0x0001180028000138ULL

/* ---- register bit definitions */

#define	FPA_INT_SUM_XXX_63_28			0xfffffffff0000000ULL
#define	FPA_INT_SUM_Q7_PERR			0x0000000008000000ULL
#define	FPA_INT_SUM_Q7_COFF			0x0000000004000000ULL
#define	FPA_INT_SUM_Q7_UND			0x0000000002000000ULL
#define	FPA_INT_SUM_Q6_PERR			0x0000000001000000ULL
#define	FPA_INT_SUM_Q6_COFF			0x0000000000800000ULL
#define	FPA_INT_SUM_Q6_UND			0x0000000000400000ULL
#define	FPA_INT_SUM_Q5_PERR			0x0000000000200000ULL
#define	FPA_INT_SUM_Q5_COFF			0x0000000000100000ULL
#define	FPA_INT_SUM_Q5_UND			0x0000000000080000ULL
#define	FPA_INT_SUM_Q4_PERR			0x0000000000040000ULL
#define	FPA_INT_SUM_Q4_COFF			0x0000000000020000ULL
#define	FPA_INT_SUM_Q4_UND			0x0000000000010000ULL
#define	FPA_INT_SUM_Q3_PERR			0x0000000000008000ULL
#define	FPA_INT_SUM_Q3_COFF			0x0000000000004000ULL
#define	FPA_INT_SUM_Q3_UND			0x0000000000002000ULL
#define	FPA_INT_SUM_Q2_PERR			0x0000000000001000ULL
#define	FPA_INT_SUM_Q2_COFF			0x0000000000000800ULL
#define	FPA_INT_SUM_Q2_UND			0x0000000000000400ULL
#define	FPA_INT_SUM_Q1_PERR			0x0000000000000200ULL
#define	FPA_INT_SUM_Q1_COFF			0x0000000000000100ULL
#define	FPA_INT_SUM_Q1_UND			0x0000000000000080ULL
#define	FPA_INT_SUM_Q0_PERR			0x0000000000000040ULL
#define	FPA_INT_SUM_Q0_COFF			0x0000000000000020ULL
#define	FPA_INT_SUM_Q0_UND			0x0000000000000010ULL
#define	FPA_INT_SUM_FED1_DBE			0x0000000000000008ULL
#define	FPA_INT_SUM_FED1_SBE			0x0000000000000004ULL
#define	FPA_INT_SUM_FED0_DBE			0x0000000000000002ULL
#define	FPA_INT_SUM_FED0_SBE			0x0000000000000001ULL

#define	FPA_INT_ENB_XXX_63_28			0xfffffffff0000000ULL
#define	FPA_INT_ENB_Q7_PERR			0x0000000008000000ULL
#define	FPA_INT_ENB_Q7_COFF			0x0000000004000000ULL
#define	FPA_INT_ENB_Q7_UND			0x0000000002000000ULL
#define	FPA_INT_ENB_Q6_PERR			0x0000000001000000ULL
#define	FPA_INT_ENB_Q6_COFF			0x0000000000800000ULL
#define	FPA_INT_ENB_Q6_UND			0x0000000000400000ULL
#define	FPA_INT_ENB_Q5_PERR			0x0000000000200000ULL
#define	FPA_INT_ENB_Q5_COFF			0x0000000000100000ULL
#define	FPA_INT_ENB_Q5_UND			0x0000000000080000ULL
#define	FPA_INT_ENB_Q4_PERR			0x0000000000040000ULL
#define	FPA_INT_ENB_Q4_COFF			0x0000000000020000ULL
#define	FPA_INT_ENB_Q4_UND			0x0000000000010000ULL
#define	FPA_INT_ENB_Q3_PERR			0x0000000000008000ULL
#define	FPA_INT_ENB_Q3_COFF			0x0000000000004000ULL
#define	FPA_INT_ENB_Q3_UND			0x0000000000002000ULL
#define	FPA_INT_ENB_Q2_PERR			0x0000000000001000ULL
#define	FPA_INT_ENB_Q2_COFF			0x0000000000000800ULL
#define	FPA_INT_ENB_Q2_UND			0x0000000000000400ULL
#define	FPA_INT_ENB_Q1_PERR			0x0000000000000200ULL
#define	FPA_INT_ENB_Q1_COFF			0x0000000000000100ULL
#define	FPA_INT_ENB_Q1_UND			0x0000000000000080ULL
#define	FPA_INT_ENB_Q0_PERR			0x0000000000000040ULL
#define	FPA_INT_ENB_Q0_COFF			0x0000000000000020ULL
#define	FPA_INT_ENB_Q0_UND			0x0000000000000010ULL
#define	FPA_INT_ENB_FED1_DBE			0x0000000000000008ULL
#define	FPA_INT_ENB_FED1_SBE			0x0000000000000004ULL
#define	FPA_INT_ENB_FED0_DBE			0x0000000000000002ULL
#define	FPA_INT_ENB_FED0_SBE			0x0000000000000001ULL

#define	FPA_CTL_STATUS_XXX_63_18		0xfffffffffffc0000ULL
#define	FPA_CTL_STATUS_RESET			0x0000000000020000ULL
#define	FPA_CTL_STATUS_USE_LDT			0x0000000000010000ULL
#define	FPA_CTL_STATUS_USE_STT			0x0000000000008000ULL
#define	FPA_CTL_STATUS_ENB			0x0000000000004000ULL
#define	FPA_CTL_STATUS_MEM1_ERR			0x0000000000003f80ULL
#define	FPA_CTL_STATUS_MEM0_ERR			0x000000000000007fULL

#define	FPA_QUEX_AVAILABLE_XXX_63_29		0xffffffffe0000000ULL
#define	FPA_QUEX_AVAILABLE_QUE_SIZ		0x000000001fffffffULL

#define	FPA_WART_CTL_XXX_63_16			0xffffffffffff0000ULL
#define	FPA_WART_CTL_CTL			0x000000000000ffffULL

#define	FPA_WART_STATUS_XXX_63_32		0xffffffff00000000ULL
#define	FPA_WART_STATUS_STATUS			0x00000000ffffffffULL

#define	FPA_BIST_STATUS_XXX_63_5		0xffffffffffffffe0ULL
#define	FPA_BIST_STATUS_FRD			0x0000000000000010ULL
#define	FPA_BIST_STATUS_FPF0			0x0000000000000008ULL
#define	FPA_BIST_STATUS_FPF1			0x0000000000000004ULL
#define	FPA_BIST_STATUS_FFR			0x0000000000000002ULL
#define	FPA_BIST_STATUS_FDR			0x0000000000000001ULL

#define	FPA_QUEX_PAGE_INDEX_XXX_63_25		0xfffffffffe000000ULL
#define	FPA_QUEX_PAGE_INDEX_PG_NUM		0x0000000001ffffffULL

#define	FPA_QUE_EXP_XXX_63_32			0xffffffff00000000ULL
#define	FPA_QUE_EXP_XXX_31_29			0x00000000e0000000ULL
#define	FPA_QUE_EXP_EXP_QUE			0x000000001c000000ULL
#define	FPA_QUE_EXP_EXP_INDX			0x0000000003ffffffULL

#define	FPA_QUE_ACT_XXX_63_32			0xffffffff00000000ULL
#define	FPA_QUE_ACT_XXX_31_29			0x00000000e0000000ULL
#define	FPA_QUE_ACT_ACT_QUE			0x000000001c000000ULL
#define	FPA_QUE_ACT_ACT_INDX			0x0000000003ffffffULL

/* ---- operations */

/*
 * 6.1 Free Pool Unit Operations
 */

#define	FPA_MAJORDID				0x5			/* 0b00101 */

#define	FPA_OPS_MAJORDID			0x0000f80000000000ULL
#define	 FPA_OPS_MAJORDID_SHIFT			43
#define	FPA_OPS_SUBDID				0x0000070000000000ULL
#define	 FPA_OPS_SUBDID_SHIFT			40
#define	FPA_OPS_XXX_39_0			0x000000ffffffffffULL

/* 6.1.1 Load Operations */

#define	FPA_OPS_LOAD_1				0x0001000000000000ULL
#define	FPA_OPS_LOAD_MAJORDID			0x0000f80000000000ULL
#define	FPA_OPS_LOAD_SUBDID			0x0000070000000000ULL
#define	FPA_OPS_LOAD_XXX_39_0			0x000000ffffffffffULL

/* 6.1.2 IOBDMA Operations */

#define	FPA_OPS_IOBDMA_SRCADDR			0xff00000000000000ULL
#define	FPA_OPS_IOBDMA_LEN			0x00ff000000000000ULL
#define	 FPA_OPS_IOBDMA_LEN_SHIFT		48
#define	FPA_OPS_IOBDMA_MAJORDID			0x0000f80000000000ULL
#define	FPA_OPS_IOBDMA_SUBDIR			0x0000070000000000ULL
#define	FPA_OPS_IOBDMA_XXX_39_0			0x000000ffffffffffULL

/* 6.1.3 Store Operations */

#define	FPA_OPS_STORE_1				0x0001000000000000ULL
#define	FPA_OPS_STORE_MAJORDID			0x0000f80000000000ULL
#define	FPA_OPS_STORE_SUBDID			0x0000070000000000ULL
#define	FPA_OPS_STORE_XXX_39_0			0x000000ffffffffffULL

#define	FPA_OPS_STORE_DATA_XXX_63_9		0xfffffffffffffe00ULL
#define	FPA_OPS_STORE_DATA_DWBCOUNT		0x00000000000001ffULL

/* ---- bus_space(9) */

#define	FPA_BASE				0x0001180028000000ULL
#define	FPA_SIZE				0x0200

#define	FPA_INT_SUM_OFFSET			0x0040
#define	FPA_INT_ENB_OFFSET			0x0048
#define	FPA_CTL_STATUS_OFFSET			0x0050
#define	FPA_QUE0_AVAILABLE_OFFSET		0x0098
#define	FPA_QUE1_AVAILABLE_OFFSET		0x00a0
#define	FPA_QUE2_AVAILABLE_OFFSET		0x00a8
#define	FPA_QUE3_AVAILABLE_OFFSET		0x00b0
#define	FPA_QUE4_AVAILABLE_OFFSET		0x00b8
#define	FPA_QUE5_AVAILABLE_OFFSET		0x00c0
#define	FPA_QUE6_AVAILABLE_OFFSET		0x00c8
#define	FPA_QUE7_AVAILABLE_OFFSET		0x00d0
#define	FPA_WART_CTL_OFFSET			0x00d8
#define	FPA_WART_STATUS_OFFSET			0x00e0
#define	FPA_BIST_STATUS_OFFSET			0x00e8
#define	FPA_QUE0_PAGE_INDEX_OFFSET		0x00f0
#define	FPA_QUE1_PAGE_INDEX_OFFSET		0x00f8
#define	FPA_QUE2_PAGE_INDEX_OFFSET		0x0100
#define	FPA_QUE3_PAGE_INDEX_OFFSET		0x0108
#define	FPA_QUE4_PAGE_INDEX_OFFSET		0x0110
#define	FPA_QUE5_PAGE_INDEX_OFFSET		0x0118
#define	FPA_QUE6_PAGE_INDEX_OFFSET		0x0120
#define	FPA_QUE7_PAGE_INDEX_OFFSET		0x0128
#define	FPA_QUE_EXP_OFFSET			0x0130
#define	FPA_QUE_ACT_OFFSET			0x0138

/* XXXX not use bit field */
/**
 * cvmx_fpa_ctl_status
 *
 * FPA_CTL_STATUS = FPA's Control/Status Register
 *
 * The FPA's interrupt enable register.
 */

#if 0

#ifndef MIPS_SPACE
#define MIPS_SPACE
typedef enum {
   MIPS_SPACE_XKSEG = 3LL,
   MIPS_SPACE_XKPHYS = 2LL,
   MIPS_SPACE_XSSEG = 1LL,
   MIPS_SPACE_XUSEG = 0LL
} mips_space_t;
#endif

typedef enum {
   MIPS_XKSEG_SPACE_KSEG0 = 0LL,
   MIPS_XKSEG_SPACE_KSEG1 = 1LL,
   MIPS_XKSEG_SPACE_SSEG = 2LL,
   MIPS_XKSEG_SPACE_KSEG3 = 3LL
} mips_xkseg_space_t;

// decodes <14:13> of a kseg3 window address
typedef enum {
   OCTEON_ADD_WIN_SCR = 0L,
   OCTEON_ADD_WIN_DMA = 1L,   // see cvmx_add_win_dma_dec_t for further decode
   OCTEON_ADD_WIN_UNUSED = 2L,
   OCTEON_ADD_WIN_UNUSED2 = 3L
} octeon_add_win_dec_t;

// decode within DMA space
typedef enum {
   OCTEON_ADD_WIN_DMA_ADD = 0L,     // add store data to the write buffer entry, allocating it if necessary
   OCTEON_ADD_WIN_DMA_SENDMEM = 1L, // send out the write buffer entry to DRAM
                                     // store data must be normal DRAM memory space address in this case
   OCTEON_ADD_WIN_DMA_SENDDMA = 2L, // send out the write buffer entry as an IOBDMA command
                                     // see CVMX_ADD_WIN_DMA_SEND_DEC for data contents
   OCTEON_ADD_WIN_DMA_SENDIO = 3L,  // send out the write buffer entry as an IO write
                                     // store data must be normal IO space address in this case
   OCTEON_ADD_WIN_DMA_SENDSINGLE = 4L, // send out a single-tick command on the NCB bus
                                        // no write buffer data needed/used
} octeon_add_win_dma_dec_t;

typedef union {

   uint64_t         u64;

   struct {
      mips_space_t          R   : 2;
      uint64_t               offset :62;
   } sva; // mapped or unmapped virtual address

   struct {
      uint64_t               zeroes :33;
      uint64_t               offset :31;
   } suseg; // mapped USEG virtual addresses (typically)

   struct {
      uint64_t                ones  :33;
      mips_xkseg_space_t   sp   : 2;
      uint64_t               offset :29;
   } sxkseg; // mapped or unmapped virtual address

   struct {
      mips_space_t          R   : 2; // CVMX_MIPS_SPACE_XKPHYS in this case
      uint64_t                 cca  : 3; // ignored by octeon
      uint64_t                 mbz  :10;
      uint64_t                  pa  :49; // physical address
   } sxkphys; // physical address accessed through xkphys unmapped virtual address

   struct {
      uint64_t                 mbz  :15;
      uint64_t                is_io : 1; // if set, the address is uncached and resides on MCB bus
      uint64_t                 did  : 8; // the hardware ignores this field when is_io==0, else device ID
      uint64_t                unaddr: 4; // the hardware ignores <39:36> in Octeon I
      uint64_t               offset :36;
   } sphys; // physical address

   struct {
      uint64_t               zeroes :24; // techically, <47:40> are dont-cares
      uint64_t                unaddr: 4; // the hardware ignores <39:36> in Octeon I
      uint64_t               offset :36;
   } smem; // physical mem address

   struct {
      uint64_t                 mem_region  :2;
      uint64_t                 mbz  :13;
      uint64_t                is_io : 1; // 1 in this case
      uint64_t                 did  : 8; // the hardware ignores this field when is_io==0, else device ID
      uint64_t                unaddr: 4; // the hardware ignores <39:36> in Octeon I
      uint64_t               offset :36;
   } sio; // physical IO address

   struct {
      uint64_t                ones   : 49;
      octeon_add_win_dec_t   csrdec : 2;    // CVMX_ADD_WIN_SCR (0) in this case
      uint64_t                addr   : 13;
   } sscr; // scratchpad virtual address - accessed through a window at the end of kseg3
   // there should only be stores to IOBDMA space, no loads
   struct {
      uint64_t                ones   : 49;
      octeon_add_win_dec_t   csrdec : 2;    // CVMX_ADD_WIN_DMA (1) in this case
      uint64_t                unused2: 3;
      octeon_add_win_dma_dec_t type : 3;
      uint64_t                addr   : 7;
   } sdma; // IOBDMA virtual address - accessed through a window at the end of kseg3

   struct {
      uint64_t                didspace : 24;
      uint64_t                unused   : 40;
   } sfilldidspace;

} cn30xxfpa_addr_t;

#endif

#endif /* _CN30XXFPAREG_H_ */


code:
/*	$OpenBSD: cn30xxfpavar.h,v 1.3 2013/06/01 22:20:35 jasper Exp $	*/
/*
 * Copyright (c) 2007 Internet Initiative Japan, Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */

#ifndef _CN30XXFPAVAR_H_
#define _CN30XXFPAVAR_H_

struct cn30xxfpa_buf {
	int		fb_poolno;	/* pool # */

	size_t		fb_size;	/* element size */
	size_t		fb_nelems;	/* # of elements */

	paddr_t		fb_paddr;	/* physical address */
	vaddr_t		fb_addr;	/* virtual address */
	size_t		fb_len;		/* total length */

	bus_dma_tag_t	fb_dmat;
	bus_dmamap_t	fb_dmah;
	bus_dma_segment_t
			*fb_dma_segs;
	int		fb_dma_nsegs;
};

uint64_t	cn30xxfpa_int_summary(void);
int		cn30xxfpa_buf_init(int, size_t, size_t, struct cn30xxfpa_buf **);
void		*cn30xxfpa_buf_get(struct cn30xxfpa_buf *);
uint64_t	cn30xxfpa_query(int);

#ifdef OCTEON_ETH_DEBUG
void	cn30xxfpa_dump(void);
#endif

#define CACHE_LINE_SIZE (128)

/* Pool sizes in bytes, must be multiple of a cache line */
#define FPA_POOL_0_SIZE (16 * CACHE_LINE_SIZE)
#define FPA_POOL_1_SIZE (1 * CACHE_LINE_SIZE)
#define FPA_POOL_2_SIZE (8 * CACHE_LINE_SIZE)
#define FPA_POOL_3_SIZE (4 * CACHE_LINE_SIZE)

#define FPA_POOL_4_SIZE (16 * CACHE_LINE_SIZE)
#define FPA_POOL_5_SIZE (16 * CACHE_LINE_SIZE)
#define FPA_POOL_6_SIZE (16 * CACHE_LINE_SIZE)
#define FPA_POOL_7_SIZE (16 * CACHE_LINE_SIZE)

/* Pools in use */
#define FPA_RECV_PKT_POOL		(0)	/* Recieve Packet buffers */
#define FPA_RECV_PKT_POOL_SIZE		FPA_POOL_0_SIZE
#define FPA_RECV_PKT_POOL_LINE		16
#define FPA_WQE_POOL			(1)	/* Work queue entrys */
#define FPA_WQE_POOL_SIZE		FPA_POOL_1_SIZE
#define FPA_WQE_POOL_LINE		1
#define FPA_COMMAND_BUFFER_POOL		(2)	/* PKO queue command buffers */
#define FPA_COMMAND_BUFFER_POOL_SIZE	FPA_POOL_2_SIZE
#define FPA_COMMAND_BUFFER_POOL_LINE	8
#define FPA_GATHER_BUFFER_POOL		(3)	/* PKO gather list buffers */
#define FPA_GATHER_BUFFER_POOL_SIZE	FPA_POOL_3_SIZE
#define FPA_GATHER_BUFFER_POOL_LINE	4

#ifndef FPA_OUTPUT_BUFFER_POOL
#define FPA_OUTPUT_BUFFER_POOL		FPA_COMMAND_BUFFER_POOL
#define FPA_OUTPUT_BUFFER_POOL_SIZE	FPA_COMMAND_BUFFER_POOL_SIZE
#endif

/*
 * operations
 */

static inline uint64_t
cn30xxfpa_load(uint64_t fpapool)
{
	uint64_t addr;

	addr =
	    (0x1ULL << 48) |
	    (0x5ULL << 43) |
	    (fpapool & 0x07ULL) << 40;

	return octeon_xkphys_read_8(addr);
}

#ifdef notyet
static inline uint64_t
cn30xxfpa_iobdma(struct cn30xxfpa_softc *sc, int srcaddr, int len)
{
	/* XXX */
	return 0ULL;
}
#endif

static inline void
cn30xxfpa_store(uint64_t addr, uint64_t fpapool, uint64_t dwbcount)
{
	uint64_t ptr;

	ptr =
	    (0x1ULL << 48) |
	    (0x5ULL << 43) |
	    (fpapool & 0x07ULL) << 40 |
	    (addr & 0xffffffffffULL);

	mips_sync();
	octeon_xkphys_write_8(ptr, (dwbcount & 0x0ffULL));
}

static inline paddr_t
cn30xxfpa_buf_get_paddr(struct cn30xxfpa_buf *fb)
{
	return cn30xxfpa_load(fb->fb_poolno);
}

static inline void
cn30xxfpa_buf_put_paddr(struct cn30xxfpa_buf *fb, paddr_t paddr)
{
	KASSERT(paddr >= fb->fb_paddr);
	KASSERT(paddr < fb->fb_paddr + fb->fb_len);
	cn30xxfpa_store(paddr, fb->fb_poolno, fb->fb_size / 128);
}

static inline void
cn30xxfpa_buf_put(struct cn30xxfpa_buf *fb, void *addr)
{
	paddr_t paddr;

	KASSERT((vaddr_t)addr >= fb->fb_addr);
	KASSERT((vaddr_t)addr < fb->fb_addr + fb->fb_len);
	paddr = fb->fb_paddr + (paddr_t/* XXX */)((vaddr_t)addr - fb->fb_addr);
	cn30xxfpa_buf_put_paddr(fb, paddr);
}

#endif