code:
/*	$OpenBSD: bha.c,v 1.30 2014/09/14 14:17:24 jsg Exp $	*/
/*	$NetBSD: bha.c,v 1.27 1998/11/19 21:53:00 thorpej Exp $	*/

#undef BHADEBUG
#ifdef DDB
#define	integrate
#else
#define	integrate	static inline
#endif

/*-
 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
 * All rights reserved.
 *
 * This code is derived from software contributed to The NetBSD Foundation
 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace
 * Simulation Facility, NASA Ames Research Center.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

/*
 * Originally written by Julian Elischer (julian@tfs.com)
 * for TRW Financial Systems for use under the MACH(2.5) operating system.
 *
 * TRW Financial Systems, in accordance with their agreement with Carnegie
 * Mellon University, makes this software available to CMU to distribute
 * or use in any manner that they see fit as long as this message is kept with
 * the software. For this reason TFS also grants any other persons or
 * organisations permission to use or modify this software.
 *
 * TFS supplies this software to be publicly redistributed
 * on the understanding that TFS is not responsible for the correct
 * functioning of this software in any circumstances.
 */

#include <sys/types.h>
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/errno.h>
#include <sys/ioctl.h>
#include <sys/device.h>
#include <sys/malloc.h>
#include <sys/buf.h>

#include <machine/bus.h>
#include <machine/intr.h>

#include <scsi/scsi_all.h>
#include <scsi/scsiconf.h>

#include <dev/ic/bhareg.h>
#include <dev/ic/bhavar.h>

#define	BHA_MAXXFER	((BHA_NSEG - 1) << PGSHIFT)
#define	ISWIDE(sc)	((sc)->sc_iswide)

#ifdef BHADEBUG
int     bha_debug = 1;
#endif /* BHADEBUG */

integrate void bha_finish_ccbs(struct bha_softc *);
integrate void bha_reset_ccb(struct bha_softc *, struct bha_ccb *);
void bha_ccb_free(void *, void *);
integrate int bha_init_ccb(struct bha_softc *, struct bha_ccb *);
void *bha_ccb_alloc(void *);
struct bha_ccb *bha_ccb_phys_kv(struct bha_softc *, u_long);
void bha_queue_ccb(struct bha_softc *, struct bha_ccb *);
void bha_collect_mbo(struct bha_softc *);
void bha_start_ccbs(struct bha_softc *);
void bha_done(struct bha_softc *, struct bha_ccb *);
int bha_init(struct bha_softc *);
void bhaminphys(struct buf *, struct scsi_link *);
void bha_scsi_cmd(struct scsi_xfer *);
int bha_poll(struct bha_softc *, struct scsi_xfer *, int);
void bha_timeout(void *arg);
int bha_create_ccbs(struct bha_softc *, struct bha_ccb *, int);

struct cfdriver bha_cd = {
	NULL, "bha", DV_DULL
};

#define BHA_RESET_TIMEOUT	2000	/* time to wait for reset (mSec) */
#define	BHA_ABORT_TIMEOUT	2000	/* time to wait for abort (mSec) */

/*
 * bha_cmd(iot, ioh, sc, icnt, ibuf, ocnt, obuf)
 *
 * Activate Adapter command
 *    icnt:   number of args (outbound bytes including opcode)
 *    ibuf:   argument buffer
 *    ocnt:   number of expected returned bytes
 *    obuf:   result buffer
 *    wait:   number of seconds to wait for response
 *
 * Performs an adapter command through the ports.  Not to be confused with a
 * scsi command, which is read in via the dma; one of the adapter commands
 * tells it to read in a scsi command.
 */
int
bha_cmd(iot, ioh, sc, icnt, ibuf, ocnt, obuf)
	bus_space_tag_t iot;
	bus_space_handle_t ioh;
	struct bha_softc *sc;
	int icnt, ocnt;
	u_char *ibuf, *obuf;
{
	const char *name;
	register int i;
	int wait;
	u_char sts;
	u_char opcode = ibuf[0];

	if (sc != NULL)
		name = sc->sc_dev.dv_xname;
	else
		name = "(bha probe)";

	/*
	 * Calculate a reasonable timeout for the command.
	 */
	switch (opcode) {
	case BHA_INQUIRE_DEVICES:
	case BHA_INQUIRE_DEVICES_2:
		wait = 90 * 20000;
		break;
	default:
		wait = 1 * 20000;
		break;
	}

	/*
	 * Wait for the adapter to go idle, unless it's one of
	 * the commands which don't need this
	 */
	if (opcode != BHA_MBO_INTR_EN) {
		for (i = 20000; i; i--) {	/* 1 sec? */
			sts = bus_space_read_1(iot, ioh, BHA_STAT_PORT);
			if (sts & BHA_STAT_IDLE)
				break;
			delay(50);
		}
		if (!i) {
			printf("%s: bha_cmd, host not idle(0x%x)\n",
			    name, sts);
			return (1);
		}
	}
	/*
	 * Now that it is idle, if we expect output, preflush the
	 * queue feeding to us.
	 */
	if (ocnt) {
		while ((bus_space_read_1(iot, ioh, BHA_STAT_PORT)) &
		    BHA_STAT_DF)
			bus_space_read_1(iot, ioh, BHA_DATA_PORT);
	}
	/*
	 * Output the command and the number of arguments given
	 * for each byte, first check the port is empty.
	 */
	while (icnt--) {
		for (i = wait; i; i--) {
			sts = bus_space_read_1(iot, ioh, BHA_STAT_PORT);
			if (!(sts & BHA_STAT_CDF))
				break;
			delay(50);
		}
		if (!i) {
			if (opcode != BHA_INQUIRE_REVISION)
				printf("%s: bha_cmd, cmd/data port full\n",
				    name);
			goto bad;
		}
		bus_space_write_1(iot, ioh, BHA_CMD_PORT, *ibuf++);
	}
	/*
	 * If we expect input, loop that many times, each time,
	 * looking for the data register to have valid data
	 */
	while (ocnt--) {
		for (i = wait; i; i--) {
			sts = bus_space_read_1(iot, ioh, BHA_STAT_PORT);
			if (sts & BHA_STAT_DF)
				break;
			delay(50);
		}
		if (!i) {
			if (opcode != BHA_INQUIRE_REVISION)
				printf("%s: bha_cmd, cmd/data port empty %d\n",
				    name, ocnt);
			goto bad;
		}
		*obuf++ = bus_space_read_1(iot, ioh, BHA_DATA_PORT);
	}
	/*
	 * Wait for the board to report a finished instruction.
	 * We may get an extra interrupt for the HACC signal, but this is
	 * unimportant.
	 */
	if (opcode != BHA_MBO_INTR_EN && opcode != BHA_MODIFY_IOPORT) {
		for (i = 20000; i; i--) {	/* 1 sec? */
			sts = bus_space_read_1(iot, ioh, BHA_INTR_PORT);
			/* XXX Need to save this in the interrupt handler? */
			if (sts & BHA_INTR_HACC)
				break;
			delay(50);
		}
		if (!i) {
			printf("%s: bha_cmd, host not finished(0x%x)\n",
			    name, sts);
			return (1);
		}
	}
	bus_space_write_1(iot, ioh, BHA_CTRL_PORT, BHA_CTRL_IRST);
	return (0);

bad:
	bus_space_write_1(iot, ioh, BHA_CTRL_PORT, BHA_CTRL_SRST);
	return (1);
}

/*
 * Attach all the sub-devices we can find
 */
void
bha_attach(sc, bpd)
	struct bha_softc *sc;
	struct bha_probe_data *bpd;
{
	struct scsibus_attach_args saa;
	int s;

	TAILQ_INIT(&sc->sc_free_ccb);
	TAILQ_INIT(&sc->sc_waiting_ccb);

	mtx_init(&sc->sc_ccb_mtx, IPL_BIO);
	scsi_iopool_init(&sc->sc_iopool, sc, bha_ccb_alloc, bha_ccb_free);

	/*
	 * Fill in the adapter.
	 */
	sc->sc_adapter.scsi_cmd = bha_scsi_cmd;
	sc->sc_adapter.scsi_minphys = bhaminphys;

	/*
	 * fill in the prototype scsi_link.
	 */
	sc->sc_link.adapter_softc = sc;
	sc->sc_link.adapter_target = bpd->sc_scsi_dev;
	sc->sc_link.adapter = &sc->sc_adapter;
	sc->sc_link.openings = 4;
	sc->sc_link.pool = &sc->sc_iopool;

	s = splbio();
	bha_inquire_setup_information(sc);

	printf("%s: model BT-%s, firmware %s\n", sc->sc_dev.dv_xname,
	    sc->sc_model, sc->sc_firmware);

	if (bha_init(sc) != 0) {
		/* Error during initialization! */
		splx(s);
		return;
	}

	splx(s);

	bzero(&saa, sizeof(saa));
	saa.saa_sc_link = &sc->sc_link;

	/*
	 * ask the adapter what subunits are present
	 */
	config_found(&sc->sc_dev, &saa, scsiprint);
}

integrate void
bha_finish_ccbs(sc)
	struct bha_softc *sc;
{
	struct bha_mbx_in *wmbi;
	struct bha_ccb *ccb;
	int i;

	wmbi = wmbx->tmbi;

	bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_control,
	    0, sc->sc_dmamap_control->dm_mapsize,
	    BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);

	if (wmbi->comp_stat == BHA_MBI_FREE) {
		for (i = 0; i < BHA_MBX_SIZE; i++) {
			if (wmbi->comp_stat != BHA_MBI_FREE) {
				printf("%s: mbi not in round-robin order\n",
				    sc->sc_dev.dv_xname);
				goto AGAIN;
			}
			bha_nextmbx(wmbi, wmbx, mbi);
			bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_control,
			    0, sc->sc_dmamap_control->dm_mapsize,
			    BUS_DMASYNC_POSTREAD);
		}
#ifdef BHADIAGnot
		printf("%s: mbi interrupt with no full mailboxes\n",
		    sc->sc_dev.dv_xname);
#endif
		return;
	}

AGAIN:
	do {
		ccb = bha_ccb_phys_kv(sc, phystol(wmbi->ccb_addr));
		if (!ccb) {
			printf("%s: bad mbi ccb pointer; skipping\n",
			    sc->sc_dev.dv_xname);
			goto next;
		}

		bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_control,
		    0, sc->sc_dmamap_control->dm_mapsize,
		    BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);

#ifdef BHADEBUG
		if (bha_debug) {
			u_int8_t *cp = ccb->scsi_cmd.bytes;
			printf("op=%x %x %x %x %x %x\n",
				ccb->scsi_cmd.opcode,
				cp[0], cp[1], cp[2], cp[3], cp[4]);
			printf("stat %x for mbi addr = 0x%08x, ",
				wmbi->comp_stat, wmbi);
			printf("ccb addr = 0x%x\n", ccb);
		}
#endif /* BHADEBUG */

		switch (wmbi->comp_stat) {
		case BHA_MBI_OK:
		case BHA_MBI_ERROR:
			if ((ccb->flags & CCB_ABORT) != 0) {
				/*
				 * If we already started an abort, wait for it
				 * to complete before clearing the CCB.  We
				 * could instead just clear CCB_SENDING, but
				 * what if the mailbox was already received?
				 * The worst that happens here is that we clear
				 * the CCB a bit later than we need to.  BFD.
				 */
				goto next;
			}
			break;

		case BHA_MBI_ABORT:
		case BHA_MBI_UNKNOWN:
			/*
			 * Even if the CCB wasn't found, we clear it anyway.
			 * See preceding comment.
			 */
			break;

		default:
			printf("%s: bad mbi status %02x; skipping\n",
			    sc->sc_dev.dv_xname, wmbi->comp_stat);
			goto next;
		}

		timeout_del(&ccb->xs->stimeout);
		bha_done(sc, ccb);

	next:
		wmbi->comp_stat = BHA_MBI_FREE;
		bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_control,
		    0, sc->sc_dmamap_control->dm_mapsize,
		    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
		bha_nextmbx(wmbi, wmbx, mbi);
		bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_control,
		    0, sc->sc_dmamap_control->dm_mapsize,
		    BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
	} while (wmbi->comp_stat != BHA_MBI_FREE);

	wmbx->tmbi = wmbi;
}

/*
 * Catch an interrupt from the adaptor
 */
int
bha_intr(arg)
	void *arg;
{
	struct bha_softc *sc = arg;
	bus_space_tag_t iot = sc->sc_iot;
	bus_space_handle_t ioh = sc->sc_ioh;
	u_char sts;

#ifdef BHADEBUG
	printf("%s: bha_intr ", sc->sc_dev.dv_xname);
#endif /* BHADEBUG */

	/*
	 * First acknowledge the interrupt, Then if it's not telling about
	 * a completed operation just return.
	 */
	sts = bus_space_read_1(iot, ioh, BHA_INTR_PORT);
	if ((sts & BHA_INTR_ANYINTR) == 0)
		return (0);
	bus_space_write_1(iot, ioh, BHA_CTRL_PORT, BHA_CTRL_IRST);

#ifdef BHADIAG
	/* Make sure we clear CCB_SENDING before finishing a CCB. */
	bha_collect_mbo(sc);
#endif

	/* Mail box out empty? */
	if (sts & BHA_INTR_MBOA) {
		struct bha_toggle toggle;

		toggle.cmd.opcode = BHA_MBO_INTR_EN;
		toggle.cmd.enable = 0;
		bha_cmd(iot, ioh, sc,
		    sizeof(toggle.cmd), (u_char *)&toggle.cmd,
		    0, (u_char *)0);
		bha_start_ccbs(sc);
	}

	/* Mail box in full? */
	if (sts & BHA_INTR_MBIF)
		bha_finish_ccbs(sc);

	return (1);
}

integrate void
bha_reset_ccb(sc, ccb)
	struct bha_softc *sc;
	struct bha_ccb *ccb;
{

	ccb->flags = 0;
}

/*
 * A ccb is put onto the free list.
 */
void
bha_ccb_free(xsc, xccb)
	void *xsc, *xccb;
{
	struct bha_softc *sc = xsc;
	struct bha_ccb *ccb = xccb;

	bha_reset_ccb(sc, ccb);

	mtx_enter(&sc->sc_ccb_mtx);
	TAILQ_INSERT_HEAD(&sc->sc_free_ccb, ccb, chain);
	mtx_leave(&sc->sc_ccb_mtx);
}

integrate int
bha_init_ccb(sc, ccb)
	struct bha_softc *sc;
	struct bha_ccb *ccb;
{
	bus_dma_tag_t dmat = sc->sc_dmat;
	int hashnum, error;

	/*
	 * Create the DMA map for this CCB.
	 */
	error = bus_dmamap_create(dmat, BHA_MAXXFER, BHA_NSEG, BHA_MAXXFER,
	    0, BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW | sc->sc_dmaflags,
	    &ccb->dmamap_xfer);
	if (error) {
		printf("%s: unable to create ccb DMA map, error = %d\n",
		    sc->sc_dev.dv_xname, error);
		return (error);
	}

	/*
	 * put in the phystokv hash table
	 * Never gets taken out.
	 */
	ccb->hashkey = sc->sc_dmamap_control->dm_segs[0].ds_addr +
	    BHA_CCB_OFF(ccb);
	hashnum = CCB_HASH(ccb->hashkey);
	ccb->nexthash = sc->sc_ccbhash[hashnum];
	sc->sc_ccbhash[hashnum] = ccb;
	bha_reset_ccb(sc, ccb);
	return (0);
}

/*
 * Create a set of ccbs and add them to the free list.  Called once
 * by bha_init().  We return the number of CCBs successfully created.
 */
int
bha_create_ccbs(sc, ccbstore, count)
	struct bha_softc *sc;
	struct bha_ccb *ccbstore;
	int count;
{
	struct bha_ccb *ccb;
	int i, error;

	for (i = 0; i < count; i++) {
		ccb = &ccbstore[i];
		if ((error = bha_init_ccb(sc, ccb)) != 0) {
			printf("%s: unable to initialize ccb, error = %d\n",
			    sc->sc_dev.dv_xname, error);
			goto out;
		}
		TAILQ_INSERT_TAIL(&sc->sc_free_ccb, ccb, chain);
	}
 out:
	return (i);
}

/*
 * Get a free ccb
 */
void *
bha_ccb_alloc(xsc)
	void *xsc;
{
	struct bha_softc *sc = xsc;
	struct bha_ccb *ccb;

	mtx_enter(&sc->sc_ccb_mtx);
	ccb = TAILQ_FIRST(&sc->sc_free_ccb);
	if (ccb) {
		TAILQ_REMOVE(&sc->sc_free_ccb, ccb, chain);
		ccb->flags |= CCB_ALLOC;
	}
	mtx_leave(&sc->sc_ccb_mtx);

	return (ccb);
}

/*
 * Given a physical address, find the ccb that it corresponds to.
 */
struct bha_ccb *
bha_ccb_phys_kv(sc, ccb_phys)
	struct bha_softc *sc;
	u_long ccb_phys;
{
	int hashnum = CCB_HASH(ccb_phys);
	struct bha_ccb *ccb = sc->sc_ccbhash[hashnum];

	while (ccb) {
		if (ccb->hashkey == ccb_phys)
			break;
		ccb = ccb->nexthash;
	}
	return (ccb);
}

/*
 * Queue a CCB to be sent to the controller, and send it if possible.
 */
void
bha_queue_ccb(sc, ccb)
	struct bha_softc *sc;
	struct bha_ccb *ccb;
{

	timeout_set(&ccb->xs->stimeout, bha_timeout, ccb);
	TAILQ_INSERT_TAIL(&sc->sc_waiting_ccb, ccb, chain);
	bha_start_ccbs(sc);
}

/*
 * Garbage collect mailboxes that are no longer in use.
 */
void
bha_collect_mbo(sc)
	struct bha_softc *sc;
{
	struct bha_mbx_out *wmbo;	/* Mail Box Out pointer */
#ifdef BHADIAG
	struct bha_ccb *ccb;
#endif

	wmbo = wmbx->cmbo;

	while (sc->sc_mbofull > 0) {
		bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_control,
		    0, sc->sc_dmamap_control->dm_mapsize,
		    BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
		if (wmbo->cmd != BHA_MBO_FREE)
			break;

#ifdef BHADIAG
		ccb = bha_ccb_phys_kv(sc, phystol(wmbo->ccb_addr));
		ccb->flags &= ~CCB_SENDING;
#endif

		--sc->sc_mbofull;
		bha_nextmbx(wmbo, wmbx, mbo);
	}

	wmbx->cmbo = wmbo;
}

/*
 * Send as many CCBs as we have empty mailboxes for.
 */
void
bha_start_ccbs(sc)
	struct bha_softc *sc;
{
	bus_space_tag_t iot = sc->sc_iot;
	bus_space_handle_t ioh = sc->sc_ioh;
	struct bha_mbx_out *wmbo;	/* Mail Box Out pointer */
	struct bha_ccb *ccb;
	struct scsi_xfer *xs;

	wmbo = wmbx->tmbo;

	while ((ccb = TAILQ_FIRST(&sc->sc_waiting_ccb)) != NULL) {

		xs = ccb->xs;
		if (sc->sc_mbofull >= BHA_MBX_SIZE) {
			bha_collect_mbo(sc);
			if (sc->sc_mbofull >= BHA_MBX_SIZE) {
				struct bha_toggle toggle;

				toggle.cmd.opcode = BHA_MBO_INTR_EN;
				toggle.cmd.enable = 1;
				bha_cmd(iot, ioh, sc,
				    sizeof(toggle.cmd), (u_char *)&toggle.cmd,
				    0, (u_char *)0);
				break;
			}
		}

		TAILQ_REMOVE(&sc->sc_waiting_ccb, ccb, chain);
#ifdef BHADIAG
		ccb->flags |= CCB_SENDING;
#endif

		/* Link ccb to mbo. */
		ltophys(sc->sc_dmamap_control->dm_segs[0].ds_addr +
		    BHA_CCB_OFF(ccb), wmbo->ccb_addr);
		if (ccb->flags & CCB_ABORT)
			wmbo->cmd = BHA_MBO_ABORT;
		else
			wmbo->cmd = BHA_MBO_START;

		bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_control,
		    0, sc->sc_dmamap_control->dm_mapsize,
		    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);

		/* Tell the card to poll immediately. */
		bus_space_write_1(iot, ioh, BHA_CMD_PORT, BHA_START_SCSI);

		if ((xs->flags & SCSI_POLL) == 0)
			timeout_add_msec(&xs->stimeout, ccb->timeout);

		++sc->sc_mbofull;
		bha_nextmbx(wmbo, wmbx, mbo);
	}

	wmbx->tmbo = wmbo;
}

/*
 * We have a ccb which has been processed by the
 * adaptor, now we look to see how the operation
 * went. Wake up the owner if waiting
 */
void
bha_done(sc, ccb)
	struct bha_softc *sc;
	struct bha_ccb *ccb;
{
	bus_dma_tag_t dmat = sc->sc_dmat;
	struct scsi_sense_data *s1, *s2;
	struct scsi_xfer *xs = ccb->xs;

	SC_DEBUG(xs->sc_link, SDEV_DB2, ("bha_done\n"));

	/*
	 * If we were a data transfer, unload the map that described
	 * the data buffer.
	 */
	if (xs->datalen) {
		bus_dmamap_sync(dmat, ccb->dmamap_xfer,
		    0, ccb->dmamap_xfer->dm_mapsize,
		    (xs->flags & SCSI_DATA_IN) ? BUS_DMASYNC_POSTREAD :
		    BUS_DMASYNC_POSTWRITE);
		bus_dmamap_unload(dmat, ccb->dmamap_xfer);
	}

	/*
	 * Otherwise, put the results of the operation
	 * into the xfer and call whoever started it
	 */
#ifdef BHADIAG
	if (ccb->flags & CCB_SENDING) {
		panic("%s: exiting ccb still in transit!",
		    sc->sc_dev.dv_xname);
		return;
	}
#endif
	if ((ccb->flags & CCB_ALLOC) == 0) {
		panic("%s: exiting ccb not allocated!",
		    sc->sc_dev.dv_xname);
		return;
	}
	if (xs->error == XS_NOERROR) {
		if (ccb->host_stat != BHA_OK) {
			switch (ccb->host_stat) {
			case BHA_SEL_TIMEOUT:	/* No response */
				xs->error = XS_SELTIMEOUT;
				break;
			default:	/* Other scsi protocol messes */
				printf("%s: host_stat %x\n",
				    sc->sc_dev.dv_xname, ccb->host_stat);
				xs->error = XS_DRIVER_STUFFUP;
				break;
			}
		} else if (ccb->target_stat != SCSI_OK) {
			switch (ccb->target_stat) {
			case SCSI_CHECK:
				s1 = &ccb->scsi_sense;
				s2 = &xs->sense;
				*s2 = *s1;
				xs->error = XS_SENSE;
				break;
			case SCSI_BUSY:
				xs->error = XS_BUSY;
				break;
			default:
				printf("%s: target_stat %x\n",
				    sc->sc_dev.dv_xname, ccb->target_stat);
				xs->error = XS_DRIVER_STUFFUP;
				break;
			}
		} else
			xs->resid = 0;
	}
	scsi_done(xs);
}

/*
 * Find the board and find its irq/drq
 */
int
bha_find(iot, ioh, sc)
	bus_space_tag_t iot;
	bus_space_handle_t ioh;
	struct bha_probe_data *sc;
{
	int i, iswide;
	u_char sts;
	struct bha_extended_inquire inquire;
	struct bha_config config;
	int irq, drq;

	/* Check something is at the ports we need to access */
	sts = bus_space_read_1(iot, ioh, BHA_STAT_PORT);
	if (sts == 0xFF) {
#ifdef BHADEBUG
		if (bha_debug)
			printf("bha_find: Not present\n");
#endif /* BHADEBUG */
		return (0);
	}

	/*
	 * Reset board, If it doesn't respond, assume
	 * that it's not there.. good for the probe
	 */

	bus_space_write_1(iot, ioh, BHA_CTRL_PORT,
	    BHA_CTRL_HRST | BHA_CTRL_SRST);

	for (i = BHA_RESET_TIMEOUT; i--;) {
		delay(100);
		sts = bus_space_read_1(iot, ioh, BHA_STAT_PORT);
		if (sts == (BHA_STAT_IDLE | BHA_STAT_INIT))
			break;
	}
	if (i < 0) {
#ifdef BHADEBUG
		if (bha_debug)
			printf("bha_find: No answer from board a=%x sts=%b\n",
			    ioh, sts, BHA_STAT_BITS);
#endif /* BHADEBUG */
		return (0);
	}

	/*
	 * The BusLogic cards implement an Adaptec 1542 (aha)-compatible
	 * interface. The native bha interface is not compatible with
	 * an aha. 1542. We need to ensure that we never match an
	 * Adaptec 1542. We must also avoid sending Adaptec-compatible
	 * commands to a real bha, lest it go into 1542 emulation mode.
	 * (On an indirect bus like ISA, we should always probe for BusLogic
	 * interfaces  before Adaptec interfaces).
	 */

	/*
	 * Make sure we don't match an AHA-1542A or AHA-1542B, by checking
	 * for an extended-geometry register.  The 1542[AB] don't have one.
	 */
	sts = bus_space_read_1(iot, ioh, BHA_EXTGEOM_PORT);
	if (sts == 0xFF)
		return (0);

	/*
	 * Check that we actually know how to use this board.
	 */
	delay(1000);
	inquire.cmd.opcode = BHA_INQUIRE_EXTENDED;
	inquire.cmd.len = sizeof(inquire.reply);
	i = bha_cmd(iot, ioh, NULL,
	    sizeof(inquire.cmd), (u_char *)&inquire.cmd,
	    sizeof(inquire.reply), (u_char *)&inquire.reply);

	/*
	 * Some 1542Cs (CP, perhaps not CF, may depend on firmware rev)
	 * have the extended-geometry register and also respond to
	 * BHA_INQUIRE_EXTENDED.  Make sure we never  match such cards,
	 * by checking the size of the reply is what a BusLogic card returns.
	 */
	if (i) {
#ifdef BHADEBUG
		printf("bha_find: board returned %d instead of %d to %s\n",
		       i, sizeof(inquire.reply), "INQUIRE_EXTENDED");
#endif
		return (0);
	}

	/* OK, we know we've found a buslogic adaptor. */

	switch (inquire.reply.bus_type) {
	case BHA_BUS_TYPE_24BIT:
	case BHA_BUS_TYPE_32BIT:
		break;
	case BHA_BUS_TYPE_MCA:
		/* We don't grok MicroChannel (yet). */
		return (0);
	default:
		printf("bha_find: illegal bus type %c\n",
		    inquire.reply.bus_type);
		return (0);
	}

	/* Note if we have a wide bus. */
	iswide = inquire.reply.scsi_flags & BHA_SCSI_WIDE;

	/*
	 * Assume we have a board at this stage setup dma channel from
	 * jumpers and save int level
	 */
	delay(1000);
	config.cmd.opcode = BHA_INQUIRE_CONFIG;
	bha_cmd(iot, ioh, NULL,
	    sizeof(config.cmd), (u_char *)&config.cmd,
	    sizeof(config.reply), (u_char *)&config.reply);
	switch (config.reply.chan) {
	case EISADMA:
		drq = -1;
		break;
	case CHAN0:
		drq = 0;
		break;
	case CHAN5:
		drq = 5;
		break;
	case CHAN6:
		drq = 6;
		break;
	case CHAN7:
		drq = 7;
		break;
	default:
		printf("bha_find: illegal drq setting %x\n",
		    config.reply.chan);
		return (0);
	}

	switch (config.reply.intr) {
	case INT9:
		irq = 9;
		break;
	case INT10:
		irq = 10;
		break;
	case INT11:
		irq = 11;
		break;
	case INT12:
		irq = 12;
		break;
	case INT14:
		irq = 14;
		break;
	case INT15:
		irq = 15;
		break;
	default:
		printf("bha_find: illegal irq setting %x\n",
		    config.reply.intr);
		return (0);
	}

	/* if we want to fill in softc, do so now */
	if (sc != NULL) {
		sc->sc_irq = irq;
		sc->sc_drq = drq;
		sc->sc_scsi_dev = config.reply.scsi_dev;
		sc->sc_iswide = iswide;
	}

	return (1);
}

/*
 * Disable the ISA-compatibility ioports on PCI bha devices,
 * to ensure they're not autoconfigured a second time as an ISA bha.
 */
int
bha_disable_isacompat(sc)
	struct bha_softc *sc;
{
	struct bha_isadisable isa_disable;

	isa_disable.cmd.opcode = BHA_MODIFY_IOPORT;
	isa_disable.cmd.modifier = BHA_IOMODIFY_DISABLE1;
	bha_cmd(sc->sc_iot, sc->sc_ioh, sc,
	    sizeof(isa_disable.cmd), (u_char *)&isa_disable.cmd,
	    0, (u_char *)0);
	return (0);
}

/*
 * Start the board, ready for normal operation
 */
int
bha_init(sc)
	struct bha_softc *sc;
{
	bus_space_tag_t iot = sc->sc_iot;
	bus_space_handle_t ioh = sc->sc_ioh;
	bus_dma_segment_t seg;
	struct bha_devices devices;
	struct bha_setup setup;
	struct bha_mailbox mailbox;
	struct bha_period period;
	int error, i, j, initial_ccbs, rlen, rseg;

	/* Enable round-robin scheme - appeared at firmware rev. 3.31. */
	if (strcmp(sc->sc_firmware, "3.31") >= 0) {
		struct bha_toggle toggle;

		toggle.cmd.opcode = BHA_ROUND_ROBIN;
		toggle.cmd.enable = 1;
		bha_cmd(iot, ioh, sc,
		    sizeof(toggle.cmd), (u_char *)&toggle.cmd,
		    0, (u_char *)0);
	}

	/*
	 * Inquire installed devices (to force synchronous negotiation).
	 */

	/*
	 * Poll targets 0 - 7.
	 */
	devices.cmd.opcode = BHA_INQUIRE_DEVICES;
	bha_cmd(iot, ioh, sc,
	    sizeof(devices.cmd), (u_char *)&devices.cmd,
	    sizeof(devices.reply), (u_char *)&devices.reply);

	/* Count installed units. */
	initial_ccbs = 0;
	for (i = 0; i < 8; i++) {
		for (j = 0; j < 8; j++) {
			if (((devices.reply.lun_map[i] >> j) & 1) == 1)
				initial_ccbs++;
		}
	}

	/*
	 * Poll targets 8 - 15 if we have a wide bus.
         */
	if (ISWIDE(sc)) {
		devices.cmd.opcode = BHA_INQUIRE_DEVICES_2;
		bha_cmd(iot, ioh, sc,
		    sizeof(devices.cmd), (u_char *)&devices.cmd,
		    sizeof(devices.reply), (u_char *)&devices.reply);

		for (i = 0; i < 8; i++) {
			for (j = 0; j < 8; j++) {
				if (((devices.reply.lun_map[i] >> j) & 1) == 1)
					initial_ccbs++;
			}
		}
	}

	initial_ccbs *= sc->sc_link.openings;
	if (initial_ccbs > BHA_CCB_MAX)
		initial_ccbs = BHA_CCB_MAX;
	if (initial_ccbs == 0)	/* yes, this can happen */
		initial_ccbs = sc->sc_link.openings;

	/* Obtain setup information from. */
	rlen = sizeof(setup.reply) +
	    (ISWIDE(sc) ? sizeof(setup.reply_w) : 0);
	setup.cmd.opcode = BHA_INQUIRE_SETUP;
	setup.cmd.len = rlen;
	bha_cmd(iot, ioh, sc,
	    sizeof(setup.cmd), (u_char *)&setup.cmd,
	    rlen, (u_char *)&setup.reply);

	printf("%s: %s, %s\n", sc->sc_dev.dv_xname,
	    setup.reply.sync_neg ? "sync" : "async",
	    setup.reply.parity ? "parity" : "no parity");

	for (i = 0; i < 8; i++)
		period.reply.period[i] = setup.reply.sync[i].period * 5 + 20;
	if (ISWIDE(sc)) {
		for (i = 0; i < 8; i++)
			period.reply_w.period[i] =
			    setup.reply_w.sync_high[i].period * 5 + 20;
	}

	if (sc->sc_firmware[0] >= '3') {
		rlen = sizeof(period.reply) +
		    (ISWIDE(sc) ? sizeof(period.reply_w) : 0);
		period.cmd.opcode = BHA_INQUIRE_PERIOD;
		period.cmd.len = sizeof(period.reply);
		bha_cmd(iot, ioh, sc,
		    sizeof(period.cmd), (u_char *)&period.cmd,
		    rlen, (u_char *)&period.reply);
	}

	for (i = 0; i < 8; i++) {
		if (!setup.reply.sync[i].valid ||
		    (!setup.reply.sync[i].offset &&
		     !setup.reply.sync[i].period))
			continue;
		printf("%s targ %d: sync, offset %d, period %dnsec\n",
		    sc->sc_dev.dv_xname, i,
		    setup.reply.sync[i].offset, period.reply.period[i] * 10);
	}
	if (ISWIDE(sc)) {
		for (i = 0; i < 8; i++) {
			if (!setup.reply_w.sync_high[i].valid ||
			    (!setup.reply_w.sync_high[i].offset &&
			     !setup.reply_w.sync_high[i].period))
				continue;
			printf("%s targ %d: sync, offset %d, period %dnsec\n",
			    sc->sc_dev.dv_xname, i + 8,
			    setup.reply_w.sync_high[i].offset,
			    period.reply_w.period[i] * 10);
		}
	}

	/*
	 * Allocate the mailbox and control blocks.
	 */
	if ((error = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct bha_control),
	    NBPG, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT | BUS_DMA_ZERO)) != 0) {
		printf("%s: unable to allocate control structures, "
		    "error = %d\n", sc->sc_dev.dv_xname, error);
		return (error);
	}
	if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg,
	    sizeof(struct bha_control), (caddr_t *)&sc->sc_control,
	    BUS_DMA_NOWAIT)) != 0) {
		printf("%s: unable to map control structures, error = %d\n",
		    sc->sc_dev.dv_xname, error);
		return (error);
	}

	/*
	 * Create and load the DMA map used for the mailbox and
	 * control blocks.
	 */
	if ((error = bus_dmamap_create(sc->sc_dmat, sizeof(struct bha_control),
	    1, sizeof(struct bha_control), 0, BUS_DMA_NOWAIT | sc->sc_dmaflags,
	    &sc->sc_dmamap_control)) != 0) {
		printf("%s: unable to create control DMA map, error = %d\n",
		    sc->sc_dev.dv_xname, error);
		return (error);
	}
	if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_control,
	    sc->sc_control, sizeof(struct bha_control), NULL,
	    BUS_DMA_NOWAIT)) != 0) {
		printf("%s: unable to load control DMA map, error = %d\n",
		    sc->sc_dev.dv_xname, error);
		return (error);
	}

	/*
	 * Initialize the control blocks.
	 */
	i = bha_create_ccbs(sc, sc->sc_control->bc_ccbs, initial_ccbs);
	if (i == 0) {
		printf("%s: unable to create control blocks\n",
		    sc->sc_dev.dv_xname);
		return (ENOMEM);
	} else if (i != initial_ccbs) {
		printf("%s: WARNING: only %d of %d control blocks created\n",
		    sc->sc_dev.dv_xname, i, initial_ccbs);
	}

	/*
	 * Set up initial mail box for round-robin operation.
	 */
	for (i = 0; i < BHA_MBX_SIZE; i++) {
		wmbx->mbo[i].cmd = BHA_MBO_FREE;
		bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_control,
		    0, sc->sc_dmamap_control->dm_mapsize,
		    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
		wmbx->mbi[i].comp_stat = BHA_MBI_FREE;
		bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_control,
		    0, sc->sc_dmamap_control->dm_mapsize,
		    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
	}
	wmbx->cmbo = wmbx->tmbo = &wmbx->mbo[0];
	wmbx->tmbi = &wmbx->mbi[0];
	sc->sc_mbofull = 0;

	/* Initialize mail box. */
	mailbox.cmd.opcode = BHA_MBX_INIT_EXTENDED;
	mailbox.cmd.nmbx = BHA_MBX_SIZE;
	ltophys(sc->sc_dmamap_control->dm_segs[0].ds_addr +
	    offsetof(struct bha_control, bc_mbx), mailbox.cmd.addr);
	bha_cmd(iot, ioh, sc,
	    sizeof(mailbox.cmd), (u_char *)&mailbox.cmd,
	    0, (u_char *)0);
	return (0);
}

void
bha_inquire_setup_information(sc)
	struct bha_softc *sc;
{
	bus_space_tag_t iot = sc->sc_iot;
	bus_space_handle_t ioh = sc->sc_ioh;
	struct bha_model model;
	struct bha_revision revision;
	struct bha_digit digit;
	char *p;

	/*
	 * Get the firmware revision.
	 */
	p = sc->sc_firmware;
	revision.cmd.opcode = BHA_INQUIRE_REVISION;
	bha_cmd(iot, ioh, sc,
	    sizeof(revision.cmd), (u_char *)&revision.cmd,
	    sizeof(revision.reply), (u_char *)&revision.reply);
	*p++ = revision.reply.firm_revision;
	*p++ = '.';
	*p++ = revision.reply.firm_version;
	digit.cmd.opcode = BHA_INQUIRE_REVISION_3;
	bha_cmd(iot, ioh, sc,
	    sizeof(digit.cmd), (u_char *)&digit.cmd,
	    sizeof(digit.reply), (u_char *)&digit.reply);
	*p++ = digit.reply.digit;
	if (revision.reply.firm_revision >= '3' ||
	    (revision.reply.firm_revision == '3' &&
	     revision.reply.firm_version >= '3')) {
		digit.cmd.opcode = BHA_INQUIRE_REVISION_4;
		bha_cmd(iot, ioh, sc,
		    sizeof(digit.cmd), (u_char *)&digit.cmd,
		    sizeof(digit.reply), (u_char *)&digit.reply);
		*p++ = digit.reply.digit;
	}
	while (p > sc->sc_firmware && (p[-1] == ' ' || p[-1] == '\0'))
		p--;
	*p = '\0';

	/*
	 * Get the model number.
	 */
	if (revision.reply.firm_revision >= '3') {
		p = sc->sc_model;
		model.cmd.opcode = BHA_INQUIRE_MODEL;
		model.cmd.len = sizeof(model.reply);
		bha_cmd(iot, ioh, sc,
		    sizeof(model.cmd), (u_char *)&model.cmd,
		    sizeof(model.reply), (u_char *)&model.reply);
		*p++ = model.reply.id[0];
		*p++ = model.reply.id[1];
		*p++ = model.reply.id[2];
		*p++ = model.reply.id[3];
		while (p > sc->sc_model && (p[-1] == ' ' || p[-1] == '\0'))
			p--;
		*p++ = model.reply.version[0];
		*p++ = model.reply.version[1];
		while (p > sc->sc_model && (p[-1] == ' ' || p[-1] == '\0'))
			p--;
		*p = '\0';
	} else
		strlcpy(sc->sc_model, "542B", sizeof sc->sc_model);
}

void
bhaminphys(struct buf *bp, struct scsi_link *sl)
{
	if (bp->b_bcount > BHA_MAXXFER)
		bp->b_bcount = BHA_MAXXFER;
	minphys(bp);
}

/*
 * start a scsi operation given the command and the data address.  Also needs
 * the unit, target and lu.
 */
void
bha_scsi_cmd(xs)
	struct scsi_xfer *xs;
{
	struct scsi_link *sc_link = xs->sc_link;
	struct bha_softc *sc = sc_link->adapter_softc;
	bus_dma_tag_t dmat = sc->sc_dmat;
	struct bha_ccb *ccb;
	int error, seg, flags, s;

	SC_DEBUG(sc_link, SDEV_DB2, ("bha_scsi_cmd\n"));

	/*
	 * get a ccb to use. If the transfer
	 * is from a buf (possibly from interrupt time)
	 * then we can't allow it to sleep
	 */
	flags = xs->flags;
	ccb = xs->io;

	ccb->xs = xs;
	ccb->timeout = xs->timeout;

	/*
	 * Put all the arguments for the xfer in the ccb
	 */
	if (flags & SCSI_RESET) {
		ccb->opcode = BHA_RESET_CCB;
		ccb->scsi_cmd_length = 0;
	} else {
		/* can't use S/G if zero length */
		ccb->opcode = (xs->datalen ? BHA_INIT_SCAT_GATH_CCB
					   : BHA_INITIATOR_CCB);
		bcopy(xs->cmd, &ccb->scsi_cmd,
		    ccb->scsi_cmd_length = xs->cmdlen);
	}

	if (xs->datalen) {
		/*
		 * Map the DMA transfer.
		 */
		error = bus_dmamap_load(dmat,
		    ccb->dmamap_xfer, xs->data, xs->datalen, NULL,
		    (flags & SCSI_NOSLEEP) ? BUS_DMA_NOWAIT :
		    BUS_DMA_WAITOK);

		if (error) {
			if (error == EFBIG) {
				printf("%s: bha_scsi_cmd, more than %d"
				    " dma segments\n",
				    sc->sc_dev.dv_xname, BHA_NSEG);
			} else {
				printf("%s: bha_scsi_cmd, error %d loading"
				    " dma map\n",
				    sc->sc_dev.dv_xname, error);
			}
			goto bad;
		}

		bus_dmamap_sync(dmat, ccb->dmamap_xfer,
		    0, ccb->dmamap_xfer->dm_mapsize,
		    (flags & SCSI_DATA_IN) ? BUS_DMASYNC_PREREAD :
		    BUS_DMASYNC_PREWRITE);

		/*
		 * Load the hardware scatter/gather map with the
		 * contents of the DMA map.
		 */
		for (seg = 0; seg < ccb->dmamap_xfer->dm_nsegs; seg++) {
			ltophys(ccb->dmamap_xfer->dm_segs[seg].ds_addr,
			    ccb->scat_gath[seg].seg_addr);
			ltophys(ccb->dmamap_xfer->dm_segs[seg].ds_len,
			    ccb->scat_gath[seg].seg_len);
		}

		ltophys(sc->sc_dmamap_control->dm_segs[0].ds_addr +
		    BHA_CCB_OFF(ccb) + offsetof(struct bha_ccb, scat_gath),
		    ccb->data_addr);
		ltophys(ccb->dmamap_xfer->dm_nsegs *
		    sizeof(struct bha_scat_gath), ccb->data_length);
	} else {
		/*
		 * No data xfer, use non S/G values.
		 */
		ltophys(0, ccb->data_addr);
		ltophys(0, ccb->data_length);
	}

	ccb->data_out = 0;
	ccb->data_in = 0;
	ccb->target = sc_link->target;
	ccb->lun = sc_link->lun;
	ltophys(sc->sc_dmamap_control->dm_segs[0].ds_addr +
	    BHA_CCB_OFF(ccb) + offsetof(struct bha_ccb, scsi_sense),
	    ccb->sense_ptr);
	ccb->req_sense_length = sizeof(ccb->scsi_sense);
	ccb->host_stat = 0x00;
	ccb->target_stat = 0x00;
	ccb->link_id = 0;
	ltophys(0, ccb->link_addr);

	bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_control,
	    0, sc->sc_dmamap_control->dm_mapsize,
	    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);

	s = splbio();
	bha_queue_ccb(sc, ccb);
	splx(s);

	/*
	 * Usually return SUCCESSFULLY QUEUED
	 */
	SC_DEBUG(sc_link, SDEV_DB3, ("cmd_sent\n"));
	if ((flags & SCSI_POLL) == 0)
		return;

	/*
	 * If we can't use interrupts, poll on completion
	 */
	if (bha_poll(sc, xs, ccb->timeout)) {
		bha_timeout(ccb);
		if (bha_poll(sc, xs, ccb->timeout))
			bha_timeout(ccb);
	}
	return;

bad:
	xs->error = XS_DRIVER_STUFFUP;
	scsi_done(xs);
}

/*
 * Poll a particular unit, looking for a particular xs
 */
int
bha_poll(sc, xs, count)
	struct bha_softc *sc;
	struct scsi_xfer *xs;
	int count;
{
	bus_space_tag_t iot = sc->sc_iot;
	bus_space_handle_t ioh = sc->sc_ioh;
	int s;

	/* timeouts are in msec, so we loop in 1000 usec cycles */
	while (count) {
		/*
		 * If we had interrupts enabled, would we
		 * have got an interrupt?
		 */
		if (bus_space_read_1(iot, ioh, BHA_INTR_PORT) &
		    BHA_INTR_ANYINTR) {
			s = splbio();
			bha_intr(sc);
			splx(s);
		}
		if (xs->flags & ITSDONE)
			return (0);
		delay(1000);	/* only happens in boot so ok */
		count--;
	}
	return (1);
}

void
bha_timeout(arg)
	void *arg;
{
	struct bha_ccb *ccb = arg;
	struct scsi_xfer *xs = ccb->xs;
	struct scsi_link *sc_link = xs->sc_link;
	struct bha_softc *sc = sc_link->adapter_softc;
	int s;

	sc_print_addr(sc_link);
	printf("timed out");

	s = splbio();

#ifdef BHADIAG
	/*
	 * If the ccb's mbx is not free, then the board has gone Far East?
	 */
	bha_collect_mbo(sc);
	if (ccb->flags & CCB_SENDING)
		panic("%s: not taking commands!", sc->sc_dev.dv_xname);
#endif

	/*
	 * If it has been through before, then
	 * a previous abort has failed, don't
	 * try abort again
	 */
	if (ccb->flags & CCB_ABORT) {
		/* abort timed out */
		printf(" AGAIN\n");
		/* XXX Must reset! */
	} else {
		/* abort the operation that has timed out */
		printf("\n");
		ccb->xs->error = XS_TIMEOUT;
		ccb->timeout = BHA_ABORT_TIMEOUT;
		ccb->flags |= CCB_ABORT;
		bha_queue_ccb(sc, ccb);
	}

	splx(s);
}


code:
/*	$OpenBSD: bhareg.h,v 1.5 2012/07/01 01:41:13 krw Exp $	*/
/*	$NetBSD: bhareg.h,v 1.12 1998/08/17 00:26:33 mycroft Exp $	*/

/*-
 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
 * All rights reserved.
 *
 * This code is derived from software contributed to The NetBSD Foundation
 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace
 * Simulation Facility, NASA Ames Research Center.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

/*
 * Originally written by Julian Elischer (julian@tfs.com)
 * for TRW Financial Systems for use under the MACH(2.5) operating system.
 *
 * TRW Financial Systems, in accordance with their agreement with Carnegie
 * Mellon University, makes this software available to CMU to distribute
 * or use in any manner that they see fit as long as this message is kept with
 * the software. For this reason TFS also grants any other persons or
 * organisations permission to use or modify this software.
 *
 * TFS supplies this software to be publicly redistributed
 * on the understanding that TFS is not responsible for the correct
 * functioning of this software in any circumstances.
 */

typedef u_int8_t physaddr[4];
typedef u_int8_t physlen[4];

static __inline void ltophys(u_int32_t val, u_int8_t *bytes);
static __inline u_int32_t phystol(u_int8_t *bytes);

static __inline void
ltophys(u_int32_t val, u_int8_t *bytes)
{
	bytes[0] = val & 0xff;
	bytes[1] = (val >> 8) & 0xff;
	bytes[2] = (val >> 16) & 0xff;
	bytes[3] = (val >> 24) & 0xff;
}

static __inline u_int32_t
phystol(u_int8_t *bytes)
{
	u_int32_t rv;

	rv = bytes[0] | (bytes[1] << 8) |
	    (bytes[2] << 16) | (bytes[3] << 24);
 	return (rv);
 }

/*
 * I/O port offsets
 */
#define	BHA_CTRL_PORT		0	/* control (wo) */
#define	BHA_STAT_PORT		0	/* status (ro) */
#define	BHA_CMD_PORT		1	/* command (wo) */
#define	BHA_DATA_PORT		1	/* data (ro) */
#define	BHA_INTR_PORT		2	/* interrupt status (ro) */
#define	BHA_EXTGEOM_PORT	3	/* extended geometry (ro) */

/*
 * BHA_CTRL bits
 */
#define BHA_CTRL_HRST		0x80	/* Hardware reset */
#define BHA_CTRL_SRST		0x40	/* Software reset */
#define BHA_CTRL_IRST		0x20	/* Interrupt reset */
#define BHA_CTRL_SCRST		0x10	/* SCSI bus reset */

/*
 * BHA_STAT bits
 */
#define BHA_STAT_STST		0x80	/* Self test in Progress */
#define BHA_STAT_DIAGF		0x40	/* Diagnostic Failure */
#define BHA_STAT_INIT		0x20	/* Mbx Init required */
#define BHA_STAT_IDLE		0x10	/* Host Adapter Idle */
#define BHA_STAT_CDF		0x08	/* cmd/data out port full */
#define BHA_STAT_DF		0x04	/* Data in port full */
#define BHA_STAT_INVDCMD	0x01	/* Invalid command */
#define	BHA_STAT_BITS	"\020\1invcmd\3df\4cdf\5idle\6init\7diagf\10stst"

/*
 * BHA_CMD opcodes
 */
#define	BHA_NOP			0x00	/* No operation */
#define BHA_MBX_INIT		0x01	/* Mbx initialization */
#define BHA_START_SCSI		0x02	/* start scsi command */
#define	BHA_EXECUTE_BIOS_CMD	0x03	/* execute BIOS command */
#define BHA_INQUIRE_REVISION	0x04	/* Adapter Inquiry */
#define BHA_MBO_INTR_EN		0x05	/* Enable MBO available interrupt */
#define BHA_SEL_TIMEOUT_SET	0x06	/* set selection time-out */
#define BHA_BUS_ON_TIME_SET	0x07	/* set bus-on time */
#define BHA_BUS_OFF_TIME_SET	0x08	/* set bus-off time */
#define BHA_BUS_SPEED_SET	0x09	/* set bus transfer speed */
#define BHA_INQUIRE_DEVICES	0x0a	/* return installed devices 0-7 */
#define BHA_INQUIRE_CONFIG	0x0b	/* return configuration data */
#define BHA_TARGET_EN		0x0c	/* enable target mode */
#define BHA_INQUIRE_SETUP	0x0d	/* return setup data */
#define	BHA_WRITE_LRAM		0x1a	/* write adapter local RAM */
#define	BHA_READ_LRAM		0x1b	/* read adapter local RAM */
#define	BHA_WRITE_CHIP_FIFO	0x1c	/* write bus master chip FIFO */
#define	BHA_READ_CHIP_FIFO	0x1d	/* read bus master chip FIFO */
#define BHA_ECHO		0x1f	/* Echo command byte */
#define	BHA_ADAPTER_DIAGNOSTICS	0x20	/* host adapter diagnostics */
#define	BHA_SET_ADAPTER_OPTIONS	0x21	/* set adapter options */
#define BHA_INQUIRE_DEVICES_2	0x23	/* return installed devices 8-15 */
#define	BHA_INQUIRE_TARG_DEVS	0x24	/* inquire target devices */
#define	BHA_DISABLE_HAC_INTR	0x25	/* disable host adapter interrupt */
#define BHA_MBX_INIT_EXTENDED	0x81	/* Mbx initialization */
#define	BHA_EXECUTE_SCSI_CMD	0x83	/* execute SCSI command */
#define BHA_INQUIRE_REVISION_3	0x84	/* Get 3rd firmware version byte */
#define BHA_INQUIRE_REVISION_4	0x85	/* Get 4th firmware version byte */
#define	BHA_INQUIRE_PCI_INFO	0x86	/* get PCI host adapter information */
#define BHA_INQUIRE_MODEL	0x8b	/* Get hardware ID and revision */
#define	BHA_INQUIRE_PERIOD	0x8c	/* Get synchronous period */
#define BHA_INQUIRE_EXTENDED	0x8d	/* Adapter Setup Inquiry */
#define	BHA_ROUND_ROBIN		0x8f	/* Enable/Disable(default)
					   round robin */
#define	BHA_STORE_LRAM		0x90	/* store host adapter local RAM */
#define	BHA_FETCH_LRAM		0x91	/* fetch host adapter local RAM */
#define	BHA_SAVE_TO_EEPROM	0x92	/* store local RAM data in EEPROM */
#define	BHA_UPLOAD_AUTOSCSI	0x94	/* upload AutoSCSI code */
#define BHA_MODIFY_IOPORT	0x95	/* change or disable I/O port */
#define	BHA_SET_CCB_FORMAT	0x96	/* set CCB format (legacy/wide lun) */
#define	BHA_WRITE_INQUIRY_BUF	0x9a	/* write inquiry buffer */
#define	BHA_READ_INQUIRY_BUF	0x9b	/* read inquiry buffer */
#define	BHA_FLASH_UP_DOWNLOAD	0xa7	/* flash upload/downlod */
#define	BHA_READ_SCAM_DATA	0xa8	/* read SCAM data */
#define	BHA_WRITE_SCAM_DATA	0xa9	/* write SCAM data */

/*
 * BHA_INTR bits
 */
#define BHA_INTR_ANYINTR	0x80	/* Any interrupt */
#define BHA_INTR_SCRD		0x08	/* SCSI reset detected */
#define BHA_INTR_HACC		0x04	/* Command complete */
#define BHA_INTR_MBOA		0x02	/* MBX out empty */
#define BHA_INTR_MBIF		0x01	/* MBX in full */

struct bha_mbx_out {
	physaddr ccb_addr;
	u_int8_t reserved[3];
	u_int8_t cmd;
} __packed;

struct bha_mbx_in {
	physaddr ccb_addr;
	u_int8_t host_stat;
	u_int8_t target_stat;
	u_int8_t reserved;
	u_int8_t comp_stat;
} __packed;

/*
 * mbo.cmd values
 */
#define BHA_MBO_FREE	0x0	/* MBO entry is free */
#define BHA_MBO_START	0x1	/* MBO activate entry */
#define BHA_MBO_ABORT	0x2	/* MBO abort entry */

/*
 * mbi.comp_stat values
 */
#define BHA_MBI_FREE	0x0	/* MBI entry is free */
#define BHA_MBI_OK	0x1	/* completed without error */
#define BHA_MBI_ABORT	0x2	/* aborted ccb */
#define BHA_MBI_UNKNOWN	0x3	/* Tried to abort invalid CCB */
#define BHA_MBI_ERROR	0x4	/* Completed with error */

#if	defined(BIG_DMA)
WARNING...THIS WON'T WORK(won't fit on 1 page)
#if 0
#define      BHA_NSEG 2048    /* Number of scatter gather segments - to much vm */
#endif
#define	BHA_NSEG	128
#else
#define	BHA_NSEG	33
#endif /* BIG_DMA */

struct bha_scat_gath {
	physlen seg_len;
	physaddr seg_addr;
} __packed;

struct bha_ccb {
	u_int8_t	opcode;
#if BYTE_ORDER == LITTLE_ENDIAN
	u_int8_t				:3,
			data_in			:1,
			data_out		:1,
			wide_tag_enable		:1, /* Wide Lun CCB format */
			wide_tag_type		:2; /* Wide Lun CCB format */
#else
	u_int8_t	wide_tag_type		:2, /* Wide Lun CCB format */
			wide_tag_enable		:1, /* Wide Lun CCB format */
			data_out		:1,
			data_in			:1,
						:3;
#endif
	u_int8_t	scsi_cmd_length;
	u_int8_t	req_sense_length;
	/*------------------------------------longword boundary */
	physlen data_length;
	/*------------------------------------longword boundary */
	physaddr data_addr;
	/*------------------------------------longword boundary */
	u_int8_t	reserved1[2];
	u_int8_t	host_stat;
	u_int8_t	target_stat;
	/*------------------------------------longword boundary */
	u_int8_t	target;
#if BYTE_ORDER == LITTLE_ENDIAN
	u_int8_t	lun			:5,
			tag_enable		:1,
			tag_type		:2;
#else
	u_int8_t	tag_type		:2,
			tag_enable		:1,
			lun			:5;
#endif
	struct scsi_generic scsi_cmd;
	u_int8_t	reserved2[1];
	u_int8_t	link_id;
	/*------------------------------------longword boundary */
	physaddr link_addr;
	/*------------------------------------longword boundary */
	physaddr sense_ptr;
/*-----end of HW fields-----------------------longword boundary */
	struct scsi_sense_data scsi_sense;
	/*------------------------------------longword boundary */
	struct bha_scat_gath scat_gath[BHA_NSEG];
	/*------------------------------------longword boundary */
	TAILQ_ENTRY(bha_ccb) chain;
	struct bha_ccb *nexthash;
	bus_addr_t	hashkey;

	struct scsi_xfer *xs;		/* the scsipi_xfer for this cmd */

	int flags;
#define	CCB_ALLOC	0x01
#define	CCB_ABORT	0x02
#ifdef BHADIAG
#define	CCB_SENDING	0x04
#endif
	int timeout;

	/*
	 * This DMA map maps the buffer involved in the transfer.
	 * Its contents are loaded into "scat_gath" above.
	 */
	bus_dmamap_t	dmamap_xfer;
} __packed;

/*
 * opcode fields
 */
#define BHA_INITIATOR_CCB	0x00	/* SCSI Initiator CCB */
#define BHA_TARGET_CCB		0x01	/* SCSI Target CCB */
#define BHA_INIT_SCAT_GATH_CCB	0x02	/* SCSI Initiator with S/G */
#define	BHA_INIT_RESID_CCB	0x03	/* SCSI Initiator w/ residual */
#define	BHA_INIT_RESID_SG_CCB	0x04	/* SCSI Initiator w/ residual and S/G */
#define BHA_RESET_CCB		0x81	/* SCSI Bus reset */

/*
 * bha_ccb.host_stat values
 */
#define BHA_OK		0x00	/* cmd ok */
#define BHA_LINK_OK	0x0a	/* Link cmd ok */
#define BHA_LINK_IT	0x0b	/* Link cmd ok + int */
#define	BHA_DATA_UNDRN		0x0c	/* data underrun error */
#define BHA_SEL_TIMEOUT	0x11	/* Selection time out */
#define BHA_OVER_UNDER	0x12	/* Data over/under run */
#define BHA_BUS_FREE	0x13	/* Bus dropped at unexpected time */
#define BHA_INV_BUS	0x14	/* Invalid bus phase/sequence */
#define BHA_BAD_MBO	0x15	/* Incorrect MBO cmd */
#define BHA_BAD_CCB	0x16	/* Incorrect ccb opcode */
#define BHA_BAD_LINK	0x17	/* Not same values of LUN for links */
#define BHA_INV_TARGET	0x18	/* Invalid target direction */
#define BHA_CCB_DUP	0x19	/* Duplicate CCB received */
#define BHA_INV_CCB	0x1a	/* Invalid CCB or segment list */
#define	BHA_AUTOSENSE_FAILED	0x1b	/* auto REQUEST SENSE failed */
#define	BHA_TAGGED_MSG_REJ	0x1c	/* tagged queueing message rejected */
#define	BHA_UNSUP_MSG_RECVD	0x1d	/* unsupported message received */
#define	BHA_HARDWARE_FAILURE	0x20	/* host adapter hardware failure */
#define	BHA_TARG_IGNORED_ATN	0x21	/* target ignored ATN signal */
#define	BHA_HA_SCSI_BUS_RESET	0x22	/* host adapter asserted RST */
#define	BHA_OTHER_SCSI_BUS_RESET 0x23	/* other device asserted RST */
#define	BHA_BAD_RECONNECT	0x24	/* target reconnected improperly */
#define	BHA_HA_BUS_DEVICE_RESET	0x25	/* host adapter performed BDR */
#define	BHA_ABORT_QUEUE		0x26	/* abort queue generated */
#define	BHA_SOFTWARE_FAILURE	0x27	/* host adapter software failure */
#define	BHA_HARDWARE_WATCHDOG	0x30	/* host adapter watchdog timer fired */
#define	BHA_SCSI_PARITY_ERROR	0x34	/* SCSI parity error detected */

struct bha_extended_inquire {
	struct {
		u_char	opcode;
		u_char	len;
	} __packed cmd;
	struct {
		u_char	bus_type;	/* Type of bus connected to */
#define	BHA_BUS_TYPE_24BIT	'A'	/* ISA bus */
#define	BHA_BUS_TYPE_32BIT	'E'	/* EISA/VLB/PCI bus */
#define	BHA_BUS_TYPE_MCA	'M'	/* MicroChannel bus */
		u_char	bios_address;	/* Address of adapter BIOS */
		u_short sg_limit;
		u_char	mbox_count;
		u_char	mbox_baseaddr[4]; /* packed/unaligned u_int32_t */
		u_char	intrflags;
#define	BHA_INTR_FASTEISA	0x04
#define BHA_INTR_LEVEL	0x40		/* bit 6: level-sensitive interrupt */
		u_char	firmware_level[3]; /* last 3 digits of firmware rev */
		u_char	scsi_flags;	/* supported SCSI  features */
#define BHA_SCSI_WIDE		0x01	/* host adapter is wide */
#define BHA_SCSI_DIFFERENTIAL	0x02	/* host adapter is differential */
#define BHA_SCSI_SCAM		0x04	/* host adapter supports SCAM */
#define BHA_SCSI_ULTRA		0x08	/* host adapter supports Ultra */
#define BHA_SCSI_TERMINATION	0x10	/* host adapter supports smart
					   termination */
	} __packed reply;
} __packed;

struct bha_config {
	struct {
		u_char	opcode;
	} __packed cmd;
	struct {
		u_char  chan;
		u_char  intr;
#if BYTE_ORDER == LITTLE_ENDIAN
		u_char  scsi_dev :3,
				 :5;
#else
		u_char		 :5,
			scsi_dev :3;
#endif
	} __packed reply;
} __packed;

struct bha_toggle {
	struct {
		u_char	opcode;
		u_char	enable;
	} __packed cmd;
} __packed;

struct bha_mailbox {
	struct {
		u_char	opcode;
		u_char	nmbx;
		physaddr addr;
	} __packed cmd;
} __packed;

struct bha_model {
	struct {
		u_char	opcode;
		u_char	len;
	} __packed cmd;
	struct {
		u_char	id[4];		/* i.e bt742a -> '7','4','2','A' */
		u_char	version[2];	/* i.e Board Revision 'H' -> 'H', 0x00 */
	} __packed reply;
} __packed;

struct bha_revision {
	struct {
		u_char	opcode;
	} __packed cmd;
	struct {
		u_char  board_type;
		u_char  custom_feature;
		char    firm_revision;
		u_char  firm_version;
	} __packed reply;
} __packed;

struct bha_digit {
	struct {
		u_char	opcode;
	} __packed cmd;
	struct {
		u_char  digit;
	} __packed reply;
} __packed;

struct bha_devices {
	struct {
		u_char	opcode;
	} __packed cmd;
	struct {
		u_char	lun_map[8];
	} __packed reply;
} __packed;

struct bha_sync {
#if BYTE_ORDER == LITTLE_ENDIAN
	u_char	offset	:4,
		period	:3,
		valid	:1;
#else
	u_char	valid	:1,
		period	:3,
		offset	:4;
#endif
} __packed;

struct bha_setup_reply {
#if BYTE_ORDER == LITTLE_ENDIAN
	u_int8_t	sync_neg	:1,
			parity		:1,
					:6;
#else
	u_int8_t			:6,
			parity		:1,
			sync_neg	:1;
#endif
	u_int8_t	speed;
	u_int8_t	bus_on;
	u_int8_t	bus_off;
	u_int8_t	num_mbx;
	u_int8_t	mbx[3];		/*XXX */
	/* doesn't make sense with 32bit addresses */
	struct bha_sync	sync[8];
	u_int8_t	disc_sts;
} __packed;

/* additional reply data supplied by wide controllers */
struct bha_setup_reply_wide {
	u_int8_t	signature;
	u_int8_t	letter_d;
	u_int8_t	ha_type;
	u_int8_t	low_wide_allowed;
	u_int8_t	low_wide_active;
	struct bha_sync	sync_high[8];
	u_int8_t	high_disc_info;
	u_int8_t	reserved;
	u_int8_t	high_wide_allowed;
	u_int8_t	high_wide_active;
} __packed;

struct bha_setup {
	struct {
		u_char	opcode;
		u_char	len;
	} __packed cmd;
	struct bha_setup_reply reply;
	struct bha_setup_reply_wide reply_w;	/* for wide controllers */
} __packed;

struct bha_period_reply {
	u_char	period[8];
} __packed;

struct bha_period {
	struct {
		u_char	opcode;
		u_char	len;
	} __packed cmd;
	struct bha_period_reply reply;
	struct bha_period_reply reply_w;	/* for wide controllers */
} __packed;

struct bha_isadisable {
	struct {
		u_char	opcode;
		u_char	modifier;
	} __packed cmd;
} __packed;

/*
 * bha_isadisable.modifier parameters
 */
#define BHA_IOMODIFY_330	0x00
#define BHA_IOMODIFY_334	0x01
#define BHA_IOMODIFY_DISABLE1	0x06
#define BHA_IOMODIFY_DISABLE2	0x07

#define INT9	0x01
#define INT10	0x02
#define INT11	0x04
#define INT12	0x08
#define INT14	0x20
#define INT15	0x40

#define EISADMA	0x00
#define CHAN0	0x01
#define CHAN5	0x20
#define CHAN6	0x40
#define CHAN7	0x80

license: unknown


code:
/*	$OpenBSD: bhavar.h,v 1.5 2011/04/03 12:42:36 krw Exp $	*/
/*	$NetBSD: bhavar.h,v 1.12 1998/11/19 21:53:00 thorpej Exp $	*/

/*-
 * Copyright (c) 1998 The NetBSD Foundation, Inc.
 * All rights reserved.
 *
 * This code is derived from software contributed to The NetBSD Foundation
 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace
 * Simulation Facility, NASA Ames Research Center.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

#include <sys/queue.h>

/*
 * Mail box defs  etc.
 * these could be bigger but we need the bha_softc to fit on a single page..
 */
#define BHA_MBX_SIZE	32	/* mail box size  (MAX 255 MBxs) */
				/* don't need that many really */
#define BHA_CCB_MAX	32	/* store up to 32 CCBs at one time */
#define	CCB_HASH_SIZE	32	/* hash table size for phystokv */
#define	CCB_HASH_SHIFT	9
#define CCB_HASH(x)	((((long)(x))>>CCB_HASH_SHIFT) & (CCB_HASH_SIZE - 1))

#define bha_nextmbx(wmb, mbx, mbio) \
	if ((wmb) == &(mbx)->mbio[BHA_MBX_SIZE - 1])	\
		(wmb) = &(mbx)->mbio[0];		\
	else						\
		(wmb)++;

struct bha_mbx {
	struct bha_mbx_out mbo[BHA_MBX_SIZE];
	struct bha_mbx_in mbi[BHA_MBX_SIZE];
	struct bha_mbx_out *cmbo;	/* Collection Mail Box out */
	struct bha_mbx_out *tmbo;	/* Target Mail Box out */
	struct bha_mbx_in *tmbi;	/* Target Mail Box in */
};

struct bha_control {
	struct bha_mbx bc_mbx;		/* all our mailboxes */
	struct bha_ccb bc_ccbs[BHA_CCB_MAX]; /* all our control blocks */
};

struct bha_softc {
	struct device sc_dev;

	bus_space_tag_t sc_iot;
	bus_space_handle_t sc_ioh;
	bus_dma_tag_t sc_dmat;
	bus_dmamap_t sc_dmamap_control;	/* maps the control structures */
	int sc_dmaflags;		/* bus-specific dma map flags */
	void *sc_ih;

	struct bha_control *sc_control;	/* control structures */
	int sc_iswide;

#define	wmbx	(&sc->sc_control->bc_mbx)

	struct bha_ccb *sc_ccbhash[CCB_HASH_SIZE];
	TAILQ_HEAD(, bha_ccb) sc_free_ccb, sc_waiting_ccb;
	int sc_mbofull;
	struct scsi_link sc_link;	/* prototype for devs */
	struct scsi_adapter sc_adapter;

	struct mutex		sc_ccb_mtx;
	struct scsi_iopool	sc_iopool;

	char sc_model[7];
	char sc_firmware[6];
};

/*
 * Offset of a Mail Box In from the beginning of the control DMA mapping.
 */
#define	BHA_MBI_OFF(m)	(offsetof(struct bha_control, bc_mbx.mbi[0]) +	\
			    (((u_long)(m)) - ((u_long)&wmbx->mbi[0])))

/*
 * Offset of a Mail Box Out from the beginning of the control DMA mapping.
 */
#define	BHA_MBO_OFF(m)	(offsetof(struct bha_control, bc_mbx.mbo[0]) +	\
			    (((u_long)(m)) - ((u_long)&wmbx->mbo[0])))

/*
 * Offset of a CCB from the beginning of the control DMA mapping.
 */
#define	BHA_CCB_OFF(c)	(offsetof(struct bha_control, bc_ccbs[0]) +	\
		    (((u_long)(c)) - ((u_long)&sc->sc_control->bc_ccbs[0])))

struct bha_probe_data {
	int sc_irq, sc_drq;
	int sc_scsi_dev;		/* adapters scsi id */
	int sc_iswide;			/* adapter is wide */
};

/*#define	ISWIDE(sc)	(sc->sc_link.max_target >= 8)*/

int	bha_cmd(bus_space_tag_t, bus_space_handle_t, struct bha_softc *,
	    int, u_char *, int, u_char *);
int	bha_find(bus_space_tag_t, bus_space_handle_t,
	    struct bha_probe_data *);
void	bha_attach(struct bha_softc *, struct bha_probe_data *);
int	bha_intr(void *);

int	bha_disable_isacompat(struct bha_softc *);
void	bha_inquire_setup_information(struct bha_softc *);


code:
/*	$OpenBSD: bt458reg.h,v 1.2 2003/06/02 18:53:18 jason Exp $	*/

/*
 * Copyright (c) 2003 Jason L. Wright (jason@thought.net)
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

/*
 * Brooktree Bt451, Bt457, Bt458 register definitions
 */
#define	BT_OV0	0x00		/* overlay 0 */
#define	BT_OV1	0x01		/* overlay 1 */
#define	BT_OV2	0x02		/* overlay 2 */
#define	BT_OV3	0x03		/* overlay 3 */
#define	BT_RMR	0x04		/* read mask */
#define	BT_BMR	0x05		/* blink mask */
#define	BT_CR	0x06		/* control */
#define	BT_CTR	0x07		/* control/test */

#define	BTCR_MPLX_5		0x80	/* multiplex select, 5:1 */
#define	BTCR_MPLX_4		0x00	/* multiplex select, 4:1 */
#define	BTCR_RAMENA		0x40	/* use color palette RAM */
#define	BTCR_BLINK_M		0x30	/* blink mask */
#define	BTCR_BLINK_1648		0x00	/*  16 on, 48 off */
#define	BTCR_BLINK_1616		0x10	/*  16 on, 16 off */
#define	BTCR_BLINK_3232		0x20	/*  32 on, 32 off */
#define	BTCR_BLINK_6464		0x30	/*  64 on, 64 off */
#define	BTCR_BLINKENA_OV1	0x08	/* OV1 blink enable */
#define	BTCR_BLINKENA_OV0	0x04	/* OV0 blink enable */
#define	BTCR_DISPENA_OV1	0x02	/* OV1 display enable */
#define	BTCR_DISPENA_OV0	0x01	/* OV0 display enable */

#define	BTCTR_R_ENA		0x01	/* red channel enable */
#define	BTCTR_G_ENA		0x02	/* green channel enable */
#define	BTCTR_B_ENA		0x04	/* blue channel enable */
#define	BTCTR_NIB_M		0x08	/* nibble mask: */
#define	BTCTR_NIB_LOW		0x08	/*  low */
#define	BTCTR_NIB_HIGH		0x00	/*  high */


code:
/* $OpenBSD: bt463.c,v 1.13 2014/07/08 17:19:25 deraadt Exp $ */
/* $NetBSD: bt463.c,v 1.2 2000/06/13 17:21:06 nathanw Exp $ */

/*-
 * Copyright (c) 1998 The NetBSD Foundation, Inc.
 * All rights reserved.
 *
 * This code is derived from software contributed to The NetBSD Foundation
 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
 * NASA Ames Research Center.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

/*
 * Copyright (c) 1995, 1996 Carnegie-Mellon University.
 * All rights reserved.
 *
 * Author: Chris G. Demetriou
 *
 * Permission to use, copy, modify and distribute this software and
 * its documentation is hereby granted, provided that both the copyright
 * notice and this permission notice appear in all copies of the
 * software, derivative works or modified versions, and any portions
 * thereof, and that both notices appear in supporting documentation.
 *
 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
 * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
 *
 * Carnegie Mellon requests users of this software to return to
 *
 *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
 *  School of Computer Science
 *  Carnegie Mellon University
 *  Pittsburgh PA 15213-3890
 *
 * any improvements or extensions that they make and grant Carnegie the
 * rights to redistribute these changes.
 */

 /* This code was derived from and originally located in sys/dev/pci/
  *	 NetBSD: tga_bt463.c,v 1.5 2000/03/04 10:27:59 elric Exp
  */

#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <sys/buf.h>
#include <sys/kernel.h>
#include <sys/malloc.h>

#include <dev/pci/pcivar.h>
#include <dev/pci/tgareg.h>
#include <dev/pci/tgavar.h>
#include <dev/ic/bt463reg.h>
#include <dev/ic/bt463var.h>

#include <dev/wscons/wsconsio.h>

/*
 * Functions exported via the RAMDAC configuration table.
 */
void	bt463_init(struct ramdac_cookie *);
int	bt463_set_cmap(struct ramdac_cookie *,
	    struct wsdisplay_cmap *);
int	bt463_get_cmap(struct ramdac_cookie *,
	    struct wsdisplay_cmap *);
int	bt463_set_cursor(struct ramdac_cookie *,
	    struct wsdisplay_cursor *);
int	bt463_get_cursor(struct ramdac_cookie *,
	    struct wsdisplay_cursor *);
int	bt463_set_curpos(struct ramdac_cookie *,
	    struct wsdisplay_curpos *);
int	bt463_get_curpos(struct ramdac_cookie *,
	    struct wsdisplay_curpos *);
int	bt463_get_curmax(struct ramdac_cookie *,
	    struct wsdisplay_curpos *);
int	bt463_check_curcmap(struct ramdac_cookie *,
	    struct wsdisplay_cursor *cursorp);
void	bt463_set_curcmap(struct ramdac_cookie *,
	    struct wsdisplay_cursor *cursorp);
int	bt463_get_curcmap(struct ramdac_cookie *,
	    struct wsdisplay_cursor *cursorp);

#ifdef BT463_DEBUG
int bt463_store(void *);
int bt463_debug(void *);
int bt463_readback(void *);
void	bt463_copyback(void *);
#endif

struct ramdac_funcs bt463_funcsstruct = {
	"Bt463",
	bt463_register,
	bt463_init,
	bt463_set_cmap,
	bt463_get_cmap,
	bt463_set_cursor,
	bt463_get_cursor,
	bt463_set_curpos,
	bt463_get_curpos,
	bt463_get_curmax,
	bt463_check_curcmap,
	bt463_set_curcmap,
	bt463_get_curcmap,
	NULL,
};

/*
 * Private data.
 */
struct bt463data {
	void            *cookie;        /* This is what is passed
					 * around, and is probably
					 * struct tga_devconfig *
					 */

	int             (*ramdac_sched_update)(void *, void (*)(void *));
	void            (*ramdac_wr)(void *, u_int, u_int8_t);
	u_int8_t        (*ramdac_rd)(void *, u_int);

	int	changed;			/* what changed; see below */
	char curcmap_r[2];			/* cursor colormap */
	char curcmap_g[2];
	char curcmap_b[2];
	char cmap_r[BT463_NCMAP_ENTRIES];	/* colormap */
	char cmap_g[BT463_NCMAP_ENTRIES];
	char cmap_b[BT463_NCMAP_ENTRIES];
	int window_type[16]; /* 16 24-bit window type table entries */
};

/* When we're doing console initialization, there's no
 * way to get our cookie back to the video card's softc
 * before we call sched_update. So we stash it here,
 * and bt463_update will look for it here first.
 */
static struct bt463data *console_data;

#define BTWREG(data, addr, val) do { bt463_wraddr((data), (addr)); \
	(data)->ramdac_wr((data)->cookie, BT463_REG_IREG_DATA, (val)); } while (0)
#define BTWNREG(data, val) (data)->ramdac_wr((data)->cookie, \
	BT463_REG_IREG_DATA, (val))
#define BTRREG(data, addr) (bt463_wraddr((data), (addr)), \
	(data)->ramdac_rd((data)->cookie, BT463_REG_IREG_DATA))
#define BTRNREG(data) ((data)->ramdac_rd((data)->cookie, BT463_REG_IREG_DATA))

#define	DATA_CURCMAP_CHANGED	0x01	/* cursor colormap changed */
#define	DATA_CMAP_CHANGED	0x02	/* colormap changed */
#define	DATA_WTYPE_CHANGED	0x04	/* window type table changed */
#define	DATA_ALL_CHANGED	0x07

/*
 * Internal functions.
 */
inline void bt463_wraddr(struct bt463data *, u_int16_t);

void	bt463_update(void *);

/*****************************************************************************/

/*
 * Functions exported via the RAMDAC configuration table.
 */

struct ramdac_funcs *
bt463_funcs(void)
{
	return &bt463_funcsstruct;
}

struct ramdac_cookie *
bt463_register(v, sched_update, wr, rd)
	void *v;
	int (*sched_update)(void *, void (*)(void *));
	void (*wr)(void *, u_int, u_int8_t);
	u_int8_t (*rd)(void *, u_int);
{
	struct bt463data *data;
	/*
	 * XXX -- comment out of date.  rcd.
	 * If we should allocate a new private info struct, do so.
	 * Otherwise, use the one we have (if it's there), or
	 * use the temporary one on the stack.
	 */
	data = malloc(sizeof *data, M_DEVBUF, M_WAITOK);
	/* XXX -- if !data */
	data->cookie = v;
	data->ramdac_sched_update = sched_update;
	data->ramdac_wr = wr;
	data->ramdac_rd = rd;
	return (struct ramdac_cookie *)data;
}

/*
 * This function exists solely to provide a means to init
 * the RAMDAC without first registering.  It is useful for
 * initializing the console early on.
 */
void
bt463_cninit(v, sched_update, wr, rd)
	void *v;
	int (*sched_update)(void *, void (*)(void *));
	void (*wr)(void *, u_int, u_int8_t);
	u_int8_t (*rd)(void *, u_int);
{
	struct bt463data tmp, *data = &tmp;
	data->cookie = v;
	data->ramdac_sched_update = sched_update;
	data->ramdac_wr = wr;
	data->ramdac_rd = rd;
	/* Set up console_data so that when bt463_update is called back,
	 * it can use the right information.
	 */
	console_data = data;
	bt463_init((struct ramdac_cookie *)data);
	console_data = NULL;
}

void
bt463_init(rc)
	struct ramdac_cookie *rc;
{
	struct bt463data *data = (struct bt463data *)rc;

	int i;

	/*
	 * Init the BT463 for normal operation.
	 */

	/*
	 * Setup:
	 * reg 0: 4:1 multiplexing, 25/75 blink.
	 * reg 1: Overlay mapping: mapped to common palette,
	 *        14 window type entries, 24-plane configuration mode,
	 *        4 overlay planes, underlays disabled, no cursor.
	 * reg 2: sync-on-green enabled, pedestal enabled.
	 */

	BTWREG(data, BT463_IREG_COMMAND_0, 0x40);
	BTWREG(data, BT463_IREG_COMMAND_1, 0x48);
	BTWREG(data, BT463_IREG_COMMAND_2, 0xC0);

	/*
	 * Initialize the read mask.
	 */
	bt463_wraddr(data, BT463_IREG_READ_MASK_P0_P7);
	for (i = 0; i < 4; i++)
		BTWNREG(data, 0xff);

	/*
	 * Initialize the blink mask.
	 */
	bt463_wraddr(data, BT463_IREG_BLINK_MASK_P0_P7);
	for (i = 0; i < 4; i++)
		BTWNREG(data, 0);

	/*
	 * Clear test register
	 */
	BTWREG(data, BT463_IREG_TEST, 0);

	/*
	 * Initialize the RAMDAC info struct to hold all of our
	 * data, and fill it in.
	 */
	data->changed = DATA_ALL_CHANGED;

	/* initial cursor colormap: 0 is black, 1 is white */
	data->curcmap_r[0] = data->curcmap_g[0] = data->curcmap_b[0] = 0;
	data->curcmap_r[1] = data->curcmap_g[1] = data->curcmap_b[1] = 0xff;

	/* Initial colormap: 0 is black, everything else is white */
	data->cmap_r[0] = data->cmap_g[0] = data->cmap_b[0] = 0;
	for (i = 1; i < 256; i++) {
		data->cmap_r[i] = rasops_cmap[3*i + 0];
		data->cmap_g[i] = rasops_cmap[3*i + 1];
		data->cmap_b[i] = rasops_cmap[3*i + 2];
	}

	/* Initialize the window type table:
	 *
	 * Entry 0: 24-plane truecolor, overlays enabled, bypassed.
	 *
	 *  Lookup table bypass:      yes (    1 << 23 & 0x800000)  800000
	 *  Colormap address:       0x000 (0x000 << 17 & 0x7e0000)       0
	 *  Overlay mask:             0xf (  0xf << 13 & 0x01e000)   1e000
	 *  Overlay location:    P<27:24> (    0 << 12 & 0x001000)       0
	 *  Display mode:       Truecolor (    0 <<  9 & 0x000e00)     000
	 *  Number of planes:           8 (    8 <<  5 & 0x0001e0)     100
	 *  Plane shift:                0 (    0 <<  0 & 0x00001f)       0
	 *                                                        --------
	 *                                                        0x81e100
	 */
	data->window_type[0] = 0x81e100;

	/* Entry 1: 8-plane pseudocolor in the bottom 8 bits,
	 *          overlays enabled, colormap starting at 0.
	 *
	 *  Lookup table bypass:       no (    0 << 23 & 0x800000)       0
	 *  Colormap address:       0x000 (0x000 << 17 & 0x7e0000)       0
	 *  Overlay mask:             0xf (  0xf << 13 & 0x01e000) 0x1e000
	 *  Overlay location:    P<27:24> (    0 << 12 & 0x001000)       0
	 *  Display mode:     Pseudocolor (    1 <<  9 & 0x000e00)   0x200
	 *  Number of planes:           8 (    8 <<  5 & 0x0001e0)   0x100
	 *  Plane shift:               16 ( 0x10 <<  0 & 0x00001f)      10
	 *                                                        --------
	 *                                                        0x01e310
	 */
	data->window_type[1] = 0x01e310;

	/* The colormap interface to the world only supports one colormap,
	 * so having an entry for the 'alternate' colormap in the bt463
	 * probably isn't useful.
	 */

	/* Fill the remaining table entries with clones of entry 0 until we
	 * figure out a better use for them.
	 */

	for (i = 2; i < BT463_NWTYPE_ENTRIES; i++) {
		data->window_type[i] = 0x81e100;
	}

	data->ramdac_sched_update(data->cookie, bt463_update);

}

int
bt463_set_cmap(rc, cmapp)
	struct ramdac_cookie *rc;
	struct wsdisplay_cmap *cmapp;
{
	struct bt463data *data = (struct bt463data *)rc;
	u_int count, index;
	int s, error;

	index = cmapp->index;
	count = cmapp->count;

	if (index >= BT463_NCMAP_ENTRIES || count > BT463_NCMAP_ENTRIES - index)
		return (EINVAL);

	s = spltty();

	if ((error = copyin(cmapp->red, &data->cmap_r[index], count)) != 0) {
		splx(s);
		return (error);
	}
	if ((error = copyin(cmapp->green, &data->cmap_g[index], count)) != 0) {
		splx(s);
		return (error);
	}
	if ((error = copyin(cmapp->blue, &data->cmap_b[index], count)) != 0) {
		splx(s);
		return (error);
	}

	data->changed |= DATA_CMAP_CHANGED;

	data->ramdac_sched_update(data->cookie, bt463_update);
	splx(s);

	return (0);
}

int
bt463_get_cmap(rc, cmapp)
	struct ramdac_cookie *rc;
	struct wsdisplay_cmap *cmapp;
{
	struct bt463data *data = (struct bt463data *)rc;
	u_int count, index;
	int error;

	count = cmapp->count;
	index = cmapp->index;

	if (index >= BT463_NCMAP_ENTRIES || count > BT463_NCMAP_ENTRIES - index)
		return (EINVAL);

	error = copyout(&data->cmap_r[index], cmapp->red, count);
	if (error)
		return (error);
	error = copyout(&data->cmap_g[index], cmapp->green, count);
	if (error)
		return (error);
	error = copyout(&data->cmap_b[index], cmapp->blue, count);
	return (error);
}

int
bt463_check_curcmap(rc, cursorp)
	struct ramdac_cookie *rc;
	struct wsdisplay_cursor *cursorp;
{
	u_int index, count;
	u_int8_t spare[2];
	int error;

	index = cursorp->cmap.index;
	count = cursorp->cmap.count;

	if (index >= 2 || count > 2 - index)
		return (EINVAL);

	if ((error = copyin(&cursorp->cmap.red, &spare, count)) != 0)
		return (error);
	if ((error = copyin(&cursorp->cmap.green, &spare, count)) != 0)
		return (error);
	if ((error = copyin(&cursorp->cmap.blue, &spare, count)) != 0)
		return (error);

	return (0);
}

void
bt463_set_curcmap(rc, cursorp)
	struct ramdac_cookie *rc;
	struct wsdisplay_cursor *cursorp;
{
	struct bt463data *data = (struct bt463data *)rc;
	int count, index;

	/* can't fail; parameters have already been checked. */
	count = cursorp->cmap.count;
	index = cursorp->cmap.index;
	copyin(cursorp->cmap.red, &data->curcmap_r[index], count);
	copyin(cursorp->cmap.green, &data->curcmap_g[index], count);
	copyin(cursorp->cmap.blue, &data->curcmap_b[index], count);
	data->changed |= DATA_CURCMAP_CHANGED;
	data->ramdac_sched_update(data->cookie, bt463_update);
}

int
bt463_get_curcmap(rc, cursorp)
	struct ramdac_cookie *rc;
	struct wsdisplay_cursor *cursorp;
{
	struct bt463data *data = (struct bt463data *)rc;
	int error;

	cursorp->cmap.index = 0;	/* DOCMAP */
	cursorp->cmap.count = 2;
	if (cursorp->cmap.red != NULL) {
		error = copyout(data->curcmap_r, cursorp->cmap.red, 2);
		if (error)
			return (error);
	}
	if (cursorp->cmap.green != NULL) {
		error = copyout(data->curcmap_g, cursorp->cmap.green, 2);
		if (error)
			return (error);
	}
	if (cursorp->cmap.blue != NULL) {
		error = copyout(data->curcmap_b, cursorp->cmap.blue, 2);
		if (error)
			return (error);
	}
	return (0);
}

/*****************************************************************************/

/*
 * Internal functions.
 */

#ifdef BT463_DEBUG
int bt463_store(void *v)
{
	struct bt463data *data = (struct bt463data *)v;

	data->changed = DATA_ALL_CHANGED;
	data->ramdac_sched_update(data->cookie, bt463_update);
	printf("Scheduled bt463 store\n");

	return 0;
}

int bt463_readback(void *v)
{
	struct bt463data *data = (struct bt463data *)v;

	data->ramdac_sched_update(data->cookie, bt463_copyback);
	printf("Scheduled bt463 copyback\n");
	return 0;
}

int
bt463_debug(v)
	void *v;
{
	struct bt463data *data = (struct bt463data *)v;
	int i;
	u_int8_t val;

	printf("BT463 main regs:\n");
	for (i = 0x200; i < 0x20F; i ++) {
	  val = BTRREG(data, i);
	  printf("  $%04x %02x\n", i, val);
	}

	printf("BT463 revision register:\n");
	  val = BTRREG(data, 0x220);
	  printf("  $%04x %02x\n", 0x220, val);

	printf("BT463 window type table (from softc):\n");

	for (i = 0; i < BT463_NWTYPE_ENTRIES; i++) {
	  printf("%02x %06x\n", i, data->window_type[i]);
	}

	return 0;
}

void
bt463_copyback(p)
	 void *p;
{
	struct bt463data *data = (struct bt463data *)p;
	int i;

		for (i = 0; i < BT463_NWTYPE_ENTRIES; i++) {
			bt463_wraddr(data, BT463_IREG_WINDOW_TYPE_TABLE + i);
			data->window_type[i] = (BTRNREG(data) & 0xff);        /* B0-7   */
			data->window_type[i] |= (BTRNREG(data) & 0xff) << 8;  /* B8-15  */
			data->window_type[i] |= (BTRNREG(data) & 0xff) << 16; /* B16-23 */
		}
}
#endif

inline void
bt463_wraddr(data, ireg)
	struct bt463data *data;
	u_int16_t ireg;
{
	data->ramdac_wr(data->cookie, BT463_REG_ADDR_LOW, ireg & 0xff);
	data->ramdac_wr(data->cookie, BT463_REG_ADDR_HIGH, (ireg >> 8) & 0xff);
}

void
bt463_update(p)
	void *p;
{
	struct bt463data *data = (struct bt463data *)p;
	int i, v;

	if (console_data != NULL) {
		/* The cookie passed in from sched_update is incorrect. Use the
		 * right one.
		 */
		data = console_data;
	}

	v = data->changed;

	/* The Bt463 won't accept window type data except during a blanking
	 * interval, so we do this early in the interrupt.
	 * Blanking the screen might also be a good idea, but it can cause
	 * unpleasant flashing and is hard to do from this side of the
	 * ramdac interface.
	 */
	if (v & DATA_WTYPE_CHANGED) {
		/* spit out the window type data */
		for (i = 0; i < BT463_NWTYPE_ENTRIES; i++) {
			bt463_wraddr(data, BT463_IREG_WINDOW_TYPE_TABLE + i);
			BTWNREG(data, (data->window_type[i]) & 0xff);       /* B0-7   */
			BTWNREG(data, (data->window_type[i] >> 8) & 0xff);  /* B8-15   */
			BTWNREG(data, (data->window_type[i] >> 16) & 0xff); /* B16-23  */
		}
	}

	if (v & DATA_CURCMAP_CHANGED) {
		bt463_wraddr(data, BT463_IREG_CURSOR_COLOR_0);
		/* spit out the cursor data */
		for (i = 0; i < 2; i++) {
			BTWNREG(data, data->curcmap_r[i]);
			BTWNREG(data, data->curcmap_g[i]);
			BTWNREG(data, data->curcmap_b[i]);
		}
	}

	if (v & DATA_CMAP_CHANGED) {
		bt463_wraddr(data, BT463_IREG_CPALETTE_RAM);
		/* spit out the colormap data */
		for (i = 0; i < BT463_NCMAP_ENTRIES; i++) {
			data->ramdac_wr(data->cookie, BT463_REG_CMAP_DATA,
				data->cmap_r[i]);
			data->ramdac_wr(data->cookie, BT463_REG_CMAP_DATA,
				data->cmap_g[i]);
			data->ramdac_wr(data->cookie, BT463_REG_CMAP_DATA,
				data->cmap_b[i]);
		}
	}

	data->changed = 0;
}

int	bt463_set_cursor (rc, cur)
	struct ramdac_cookie *rc;
	struct wsdisplay_cursor *cur;
{
	struct bt463data *data = (struct bt463data *)rc;
	return tga_builtin_set_cursor(data->cookie, cur);
}

int	bt463_get_cursor (rc, cur)
	struct ramdac_cookie *rc;
	struct wsdisplay_cursor *cur;
{
	struct bt463data *data = (struct bt463data *)rc;
	return tga_builtin_get_cursor(data->cookie, cur);
}

int	bt463_set_curpos (rc, cur)
	struct ramdac_cookie *rc;
	struct wsdisplay_curpos *cur;
{
	struct bt463data *data = (struct bt463data *)rc;
	return tga_builtin_set_curpos(data->cookie, cur);
}

int	bt463_get_curpos (rc, cur)
	struct ramdac_cookie *rc;
	struct wsdisplay_curpos *cur;
{
	struct bt463data *data = (struct bt463data *)rc;
	return tga_builtin_get_curpos(data->cookie, cur);
}

int	bt463_get_curmax (rc, cur)
	struct ramdac_cookie *rc;
	struct wsdisplay_curpos *cur;
{
	struct bt463data *data = (struct bt463data *)rc;
	return tga_builtin_get_curmax(data->cookie, cur);
}


code:
/*	$OpenBSD: bt463reg.h,v 1.3 2008/06/26 05:42:15 ray Exp $ */
/*	$NetBSD: bt463reg.h,v 1.1 1998/08/18 07:43:09 thorpej Exp $	*/

/*-
 * Copyright (c) 1998 The NetBSD Foundation, Inc.
 * All rights reserved.
 *
 * This code is derived from software contributed to The NetBSD Foundation
 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
 * NASA Ames Research Center.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

/*
 * Register definitions for the Brooktree Bt463 135MHz Monolithic
 * CMOS TrueVu RAMDAC.
 */

/*
 * Directly-accessible registers.  Note the address register is
 * auto-incrementing.
 */
#define	BT463_REG_ADDR_LOW		0x00	/* C1,C0 == 0,0 */
#define	BT463_REG_ADDR_HIGH		0x01	/* C1,C0 == 0,1 */
#define	BT463_REG_IREG_DATA		0x02	/* C1,C0 == 1,0 */
#define	BT463_REG_CMAP_DATA		0x03	/* C1,C0 == 1,1 */

#define	BT463_REG_MAX			BT463_REG_CMAP_DATA

/*
 * All internal register access to the Bt463 is done indirectly via the
 * Address Register (mapped into the host bus in a device-specific
 * fashion).  The following register definitions are in terms of
 * their address register address values.
 */

/* C1,C0 must be 1,0 */
#define	BT463_IREG_CURSOR_COLOR_0	0x0100	/* 3 r/w cycles */
#define	BT463_IREG_CURSOR_COLOR_1	0x0101	/* 3 r/w cycles */
#define	BT463_IREG_ID			0x0200
#define	BT463_IREG_COMMAND_0		0x0201
#define	BT463_IREG_COMMAND_1		0x0202
#define	BT463_IREG_COMMAND_2		0x0203
#define	BT463_IREG_READ_MASK_P0_P7	0x0205
#define	BT463_IREG_READ_MASK_P8_P15	0x0206
#define	BT463_IREG_READ_MASK_P16_P23	0x0207
#define	BT463_IREG_READ_MASK_P24_P27	0x0208
#define	BT463_IREG_BLINK_MASK_P0_P7	0x0209
#define	BT463_IREG_BLINK_MASK_P8_P15	0x020a
#define	BT463_IREG_BLINK_MASK_P16_P23	0x020b
#define	BT463_IREG_BLINK_MASK_P24_P27	0x020c
#define	BT463_IREG_TEST			0x020d
#define	BT463_IREG_INPUT_SIG		0x020e	/* 2 of 3 r/w cycles */
#define	BT463_IREG_OUTPUT_SIG		0x020f	/* 3 r/w cycles */
#define	BT463_IREG_REVISION		0x0220
#define	BT463_IREG_WINDOW_TYPE_TABLE	0x0300	/* 3 r/w cycles */

#define	BT463_NWTYPE_ENTRIES		0x10	/* 16 window type entries */

/* C1,C0 must be 1,1 */
#define	BT463_IREG_CPALETTE_RAM		0x0000	/* 3 r/w cycles */

#define	BT463_NCMAP_ENTRIES		0x210	/* 528 CMAP entries */


code:
/* $OpenBSD: bt463var.h,v 1.4 2008/06/26 05:42:15 ray Exp $ */
/* $NetBSD: bt485var.h,v 1.1 2000/03/04 10:25:57 elric Exp $ */

/*-
 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
 * All rights reserved.
 *
 * This code is derived from software contributed to The NetBSD Foundation
 * by Roland C. Dowdeswell.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

struct ramdac_funcs *bt463_funcs(void);
struct ramdac_cookie *bt463_register(void *,
	int (*)(void *, void (*)(void *)),
	void (*)(void *, u_int, u_int8_t),
	u_int8_t (*)(void *, u_int));
void bt463_cninit(void *,
	int (*)(void *, void (*)(void *)),
	void (*)(void *, u_int, u_int8_t),
	u_int8_t (*)(void *, u_int));


code:
/* $OpenBSD: bt485.c,v 1.14 2014/07/08 17:19:25 deraadt Exp $ */
/* $NetBSD: bt485.c,v 1.2 2000/04/02 18:55:01 nathanw Exp $ */

/*
 * Copyright (c) 1995, 1996 Carnegie-Mellon University.
 * All rights reserved.
 *
 * Author: Chris G. Demetriou
 *
 * Permission to use, copy, modify and distribute this software and
 * its documentation is hereby granted, provided that both the copyright
 * notice and this permission notice appear in all copies of the
 * software, derivative works or modified versions, and any portions
 * thereof, and that both notices appear in supporting documentation.
 *
 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
 * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
 *
 * Carnegie Mellon requests users of this software to return to
 *
 *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
 *  School of Computer Science
 *  Carnegie Mellon University
 *  Pittsburgh PA 15213-3890
 *
 * any improvements or extensions that they make and grant Carnegie the
 * rights to redistribute these changes.
 */

 /* This code was derived from and originally located in sys/dev/pci/
  *	 NetBSD: tga_bt485.c,v 1.4 1999/03/24 05:51:21 mrg Exp
  */

#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <sys/buf.h>
#include <sys/kernel.h>
#include <sys/malloc.h>

#include <dev/pci/pcivar.h>
#include <dev/ic/bt485reg.h>
#include <dev/ic/bt485var.h>
#include <dev/ic/ramdac.h>

#include <dev/wscons/wsconsio.h>
#include <dev/wscons/wsdisplayvar.h>
#include <dev/rasops/rasops.h>

/*
 * Functions exported via the RAMDAC configuration table.
 */
void	bt485_init(struct ramdac_cookie *);
int	bt485_set_cmap(struct ramdac_cookie *,
	    struct wsdisplay_cmap *);
int	bt485_get_cmap(struct ramdac_cookie *,
	    struct wsdisplay_cmap *);
int	bt485_set_cursor(struct ramdac_cookie *,
	    struct wsdisplay_cursor *);
int	bt485_get_cursor(struct ramdac_cookie *,
	    struct wsdisplay_cursor *);
int	bt485_set_curpos(struct ramdac_cookie *,
	    struct wsdisplay_curpos *);
int	bt485_get_curpos(struct ramdac_cookie *,
	    struct wsdisplay_curpos *);
int	bt485_get_curmax(struct ramdac_cookie *,
	    struct wsdisplay_curpos *);

/* XXX const */
struct ramdac_funcs bt485_funcsstruct = {
	"Bt485",
	bt485_register,
	bt485_init,
	bt485_set_cmap,
	bt485_get_cmap,
	bt485_set_cursor,
	bt485_get_cursor,
	bt485_set_curpos,
	bt485_get_curpos,
	bt485_get_curmax,
	NULL,			/* check_curcmap; not needed */
	NULL,			/* set_curcmap; not needed */
	NULL,			/* get_curcmap; not needed */
	NULL,			/* no dot clock to set */
};

/*
 * Private data.
 */
struct bt485data {
	void            *cookie;        /* This is what is passed
					 * around, and is probably
					 * struct tga_devconfig *
					 */

	int             (*ramdac_sched_update)(void *, void (*)(void *));
	void            (*ramdac_wr)(void *, u_int, u_int8_t);
	u_int8_t        (*ramdac_rd)(void *, u_int);

	int	changed;			/* what changed; see below */
	int	curenb;				/* cursor enabled */
	struct wsdisplay_curpos curpos;		/* current cursor position */
	struct wsdisplay_curpos curhot;		/* cursor hotspot */
	char curcmap_r[2];			/* cursor colormap */
	char curcmap_g[2];
	char curcmap_b[2];
	struct wsdisplay_curpos cursize;	/* current cursor size */
	char curimage[512];			/* cursor image data */
	char curmask[512];			/* cursor mask data */
	char cmap_r[256];				/* colormap */
	char cmap_g[256];
	char cmap_b[256];
};

#define	DATA_ENB_CHANGED	0x01	/* cursor enable changed */
#define	DATA_CURCMAP_CHANGED	0x02	/* cursor colormap changed */
#define	DATA_CURSHAPE_CHANGED	0x04	/* cursor size, image, mask changed */
#define	DATA_CMAP_CHANGED	0x08	/* colormap changed */
#define	DATA_ALL_CHANGED	0x0f

#define	CURSOR_MAX_SIZE		64

/*
 * Internal functions.
 */
inline void	bt485_wr_i(struct bt485data *, u_int8_t, u_int8_t);
inline u_int8_t bt485_rd_i(struct bt485data *, u_int8_t);
void	bt485_update(void *);
void	bt485_update_curpos(struct bt485data *);

/*****************************************************************************/

/*
 * Functions exported via the RAMDAC configuration table.
 */

struct ramdac_funcs *
bt485_funcs(void)
{
	return &bt485_funcsstruct;
}

struct ramdac_cookie *
bt485_register(v, sched_update, wr, rd)
	void *v;
	int (*sched_update)(void *, void (*)(void *));
	void (*wr)(void *, u_int, u_int8_t);
	u_int8_t (*rd)(void *, u_int);
{
	struct bt485data *data;
	/*
	 * XXX -- comment out of date.  rcd.
	 * If we should allocate a new private info struct, do so.
	 * Otherwise, use the one we have (if it's there), or
	 * use the temporary one on the stack.
	 */
	data = malloc(sizeof *data, M_DEVBUF, M_WAITOK);
	/* XXX -- if !data */
	data->cookie = v;
	data->ramdac_sched_update = sched_update;
	data->ramdac_wr = wr;
	data->ramdac_rd = rd;
	return (struct ramdac_cookie *)data;
}

/*
 * This function exists solely to provide a means to init
 * the RAMDAC without first registering.  It is useful for
 * initializing the console early on.
 */
void
bt485_cninit(v, sched_update, wr, rd)
	void *v;
	int (*sched_update)(void *, void (*)(void *));
	void (*wr)(void *, u_int, u_int8_t);
	u_int8_t (*rd)(void *, u_int);
{
	struct bt485data tmp, *data = &tmp;
	data->cookie = v;
	data->ramdac_sched_update = sched_update;
	data->ramdac_wr = wr;
	data->ramdac_rd = rd;
	bt485_init((struct ramdac_cookie *)data);
}

void
bt485_init(rc)
	struct ramdac_cookie *rc;
{
	u_int8_t regval;
	struct bt485data *data = (struct bt485data *)rc;
	int i;

	/*
	 * Init the BT485 for normal operation.
	 */

	/*
	 * Allow indirect register access.  (Actually, this is
	 * already enabled.  In fact, if it is _disabled_, for
	 * some reason the monitor appears to lose sync!!! (?!?!)
	 */
	regval = data->ramdac_rd(data->cookie, BT485_REG_COMMAND_0);
	regval |= 0x80;
	/*
	 * Set the RAMDAC to 8 bit resolution, rather than 6 bit
	 * resolution.
	 */
	regval |= 0x02;
	data->ramdac_wr(data->cookie, BT485_REG_COMMAND_0, regval);

	/* Set the RAMDAC to 8BPP (no interestion options). */
	data->ramdac_wr(data->cookie, BT485_REG_COMMAND_1, 0x40);

	/* Disable the cursor (for now) */
	regval = data->ramdac_rd(data->cookie, BT485_REG_COMMAND_2);
	regval &= ~0x03;
	regval |= 0x24;
	data->ramdac_wr(data->cookie, BT485_REG_COMMAND_2, regval);

	/* Use a 64x64x2 cursor */
	regval = bt485_rd_i(data, BT485_IREG_COMMAND_3);
	regval |= 0x04;
	regval |= 0x08;
	bt485_wr_i(data, BT485_IREG_COMMAND_3, regval);

	/* Set the Pixel Mask to something useful */
	data->ramdac_wr(data->cookie, BT485_REG_PIXMASK, 0xff);

	/*
	 * Initialize the RAMDAC info struct to hold all of our
	 * data, and fill it in.
	 */
	data->changed = DATA_ALL_CHANGED;

	data->curenb = 0;				/* cursor disabled */
	data->curpos.x = data->curpos.y = 0;		/* right now at 0,0 */
	data->curhot.x = data->curhot.y = 0;		/* hot spot at 0,0 */

	/* initial cursor colormap: 0 is black, 1 is white */
	data->curcmap_r[0] = data->curcmap_g[0] = data->curcmap_b[0] = 0;
	data->curcmap_r[1] = data->curcmap_g[1] = data->curcmap_b[1] = 0xff;

	/* initial cursor data: 64x64 block of white. */
	data->cursize.x = data->cursize.y = 64;
	for (i = 0; i < 512; i++)
		data->curimage[i] = data->curmask[i] = 0xff;

	/* Initial colormap: 0 is black, everything else is white */
	data->cmap_r[0] = data->cmap_g[0] = data->cmap_b[0] = 0;
	for (i = 0; i < 256; i++) {
		data->cmap_r[i] = rasops_cmap[3*i + 0];
		data->cmap_g[i] = rasops_cmap[3*i + 1];
		data->cmap_b[i] = rasops_cmap[3*i + 2];
	}

	bt485_update((void *)data);
}

int
bt485_set_cmap(rc, cmapp)
	struct ramdac_cookie *rc;
	struct wsdisplay_cmap *cmapp;
{
	struct bt485data *data = (struct bt485data *)rc;
	u_int count, index;
	int s, error;

#ifdef DIAGNOSTIC
	if (rc == NULL)
		panic("bt485_set_cmap: rc");
	if (cmapp == NULL)
		panic("bt485_set_cmap: cmapp");
#endif
	index = cmapp->index;
	count = cmapp->count;

	if (index >= 256 || count > 256 - index)
		return (EINVAL);

	s = spltty();

	if ((error = copyin(cmapp->red, &data->cmap_r[index], count)) != 0) {
		splx(s);
		return (error);
	}
	if ((error = copyin(cmapp->green, &data->cmap_g[index], count)) != 0) {
		splx(s);
		return (error);
	}
	if ((error = copyin(cmapp->blue, &data->cmap_b[index], count)) != 0) {
		splx(s);
		return (error);
	}

	data->changed |= DATA_CMAP_CHANGED;

	data->ramdac_sched_update(data->cookie, bt485_update);
#ifdef __alpha__
	alpha_mb();
#endif
	splx(s);

	return (0);
}

int
bt485_get_cmap(rc, cmapp)
	struct ramdac_cookie *rc;
	struct wsdisplay_cmap *cmapp;
{
	struct bt485data *data = (struct bt485data *)rc;
	u_int count, index;
	int error;

	if (cmapp->index >= 256 || cmapp->count > 256 - cmapp->index)
		return (EINVAL);

	count = cmapp->count;
	index = cmapp->index;

	error = copyout(&data->cmap_r[index], cmapp->red, count);
	if (error)
		return (error);
	error = copyout(&data->cmap_g[index], cmapp->green, count);
	if (error)
		return (error);
	error = copyout(&data->cmap_b[index], cmapp->blue, count);
	return (error);
}

int
bt485_set_cursor(rc, cursorp)
	struct ramdac_cookie *rc;
	struct wsdisplay_cursor *cursorp;
{
	struct bt485data *data = (struct bt485data *)rc;
	u_int count, index;
	int error;
	int v, s;

	v = cursorp->which;

	/*
	 * For DOCMAP and DOSHAPE, verify that parameters are OK
	 * before we do anything that we can't recover from.
	 */
	if (v & WSDISPLAY_CURSOR_DOCMAP) {
		index = cursorp->cmap.index;
		count = cursorp->cmap.count;
		if (index >= 2 || count > 2 - index)
			return (EINVAL);
	}
	if (v & WSDISPLAY_CURSOR_DOSHAPE) {
		if ((u_int)cursorp->size.x > CURSOR_MAX_SIZE ||
		    (u_int)cursorp->size.y > CURSOR_MAX_SIZE)
			return (EINVAL);
	}

	if (v & (WSDISPLAY_CURSOR_DOPOS | WSDISPLAY_CURSOR_DOCUR)) {
		if (v & WSDISPLAY_CURSOR_DOPOS)
			data->curpos = cursorp->pos;
		if (v & WSDISPLAY_CURSOR_DOCUR)
			data->curhot = cursorp->hot;
		bt485_update_curpos(data);
	}

	s = spltty();

	/* Parameters are OK; perform the requested operations. */
	if (v & WSDISPLAY_CURSOR_DOCUR) {
		data->curenb = cursorp->enable;
		data->changed |= DATA_ENB_CHANGED;
	}
	if (v & WSDISPLAY_CURSOR_DOCMAP) {
		index = cursorp->cmap.index;
		count = cursorp->cmap.count;
		if ((error = copyin(cursorp->cmap.red,
		    &data->curcmap_r[index], count)) != 0) {
			splx(s);
			return (error);
		}
		if ((error = copyin(cursorp->cmap.green,
		    &data->curcmap_g[index], count)) != 0) {
			splx(s);
			return (error);
		}
		if ((error = copyin(cursorp->cmap.blue,
		    &data->curcmap_b[index], count)) != 0) {
			splx(s);
			return (error);
		}
		data->changed |= DATA_CURCMAP_CHANGED;
	}
	if (v & WSDISPLAY_CURSOR_DOSHAPE) {
		data->cursize = cursorp->size;
		count = (CURSOR_MAX_SIZE / NBBY) * data->cursize.y;
		bzero(data->curimage, sizeof data->curimage);
		bzero(data->curmask, sizeof data->curmask);
		if ((error = copyin(cursorp->image, data->curimage,
		    count)) != 0) {
			splx(s);
			return (error);
		}
		if ((error = copyin(cursorp->mask, data->curmask,
		    count)) != 0) {
			splx(s);
			return (error);
		}
		data->changed |= DATA_CURSHAPE_CHANGED;
	}

	if (data->changed)
		data->ramdac_sched_update(data->cookie, bt485_update);
	splx(s);

	return (0);
}

int
bt485_get_cursor(rc, cursorp)
	struct ramdac_cookie *rc;
	struct wsdisplay_cursor *cursorp;
{
	struct bt485data *data = (struct bt485data *)rc;
	int error, count;

	/* we return everything they want */
	cursorp->which = WSDISPLAY_CURSOR_DOALL;

	cursorp->enable = data->curenb;	/* DOCUR */
	cursorp->pos = data->curpos;	/* DOPOS */
	cursorp->hot = data->curhot;	/* DOHOT */

	cursorp->cmap.index = 0;	/* DOCMAP */
	cursorp->cmap.count = 2;
	if (cursorp->cmap.red != NULL) {
		error = copyout(data->curcmap_r, cursorp->cmap.red, 2);
		if (error)
			return (error);
	}
	if (cursorp->cmap.green != NULL) {
		error = copyout(data->curcmap_g, cursorp->cmap.green, 2);
		if (error)
			return (error);
	}
	if (cursorp->cmap.blue != NULL) {
		error = copyout(data->curcmap_b, cursorp->cmap.blue, 2);
		if (error)
			return (error);
	}

	cursorp->size = data->cursize;	/* DOSHAPE */
	if (cursorp->image != NULL) {
		count = (CURSOR_MAX_SIZE / NBBY) * data->cursize.y;
		error = copyout(data->curimage, cursorp->image, count);
		if (error)
			return (error);
		error = copyout(data->curmask, cursorp->mask, count);
		if (error)
			return (error);
	}

	return (0);
}

int
bt485_set_curpos(rc, curposp)
	struct ramdac_cookie *rc;
	struct wsdisplay_curpos *curposp;
{
	struct bt485data *data = (struct bt485data *)rc;

	data->curpos = *curposp;
	bt485_update_curpos(data);

	return (0);
}

int
bt485_get_curpos(rc, curposp)
	struct ramdac_cookie *rc;
	struct wsdisplay_curpos *curposp;
{
	struct bt485data *data = (struct bt485data *)rc;

	*curposp = data->curpos;
	return (0);
}

int
bt485_get_curmax(rc, curposp)
	struct ramdac_cookie *rc;
	struct wsdisplay_curpos *curposp;
{

	curposp->x = curposp->y = CURSOR_MAX_SIZE;
	return (0);
}

/*****************************************************************************/

/*
 * Internal functions.
 */

inline void
bt485_wr_i(data, ireg, val)
	struct bt485data *data;
	u_int8_t ireg;
	u_int8_t val;
{
	data->ramdac_wr(data->cookie, BT485_REG_PCRAM_WRADDR, ireg);
	data->ramdac_wr(data->cookie, BT485_REG_EXTENDED, val);
}

inline u_int8_t
bt485_rd_i(data, ireg)
	struct bt485data *data;
	u_int8_t ireg;
{
	data->ramdac_wr(data->cookie, BT485_REG_PCRAM_WRADDR, ireg);
	return (data->ramdac_rd(data->cookie, BT485_REG_EXTENDED));
}

void
bt485_update(vp)
	void *vp;
{
	struct bt485data *data = vp;
	u_int8_t regval;
	int count, i, v;

	v = data->changed;
	data->changed = 0;

	if (v & DATA_ENB_CHANGED) {
		regval = data->ramdac_rd(data->cookie, BT485_REG_COMMAND_2);
		if (data->curenb)
			regval |= 0x01;
		else
			regval &= ~0x03;
                data->ramdac_wr(data->cookie, BT485_REG_COMMAND_2, regval);
	}

	if (v & DATA_CURCMAP_CHANGED) {
		/* addr[9:0] assumed to be 0 */
		/* set addr[7:0] to 1 */
                data->ramdac_wr(data->cookie, BT485_REG_COC_WRADDR, 0x01);

		/* spit out the cursor data */
		for (i = 0; i < 2; i++) {
                	data->ramdac_wr(data->cookie, BT485_REG_COCDATA,
			    data->curcmap_r[i]);
                	data->ramdac_wr(data->cookie, BT485_REG_COCDATA,
			    data->curcmap_g[i]);
                	data->ramdac_wr(data->cookie, BT485_REG_COCDATA,
			    data->curcmap_b[i]);
		}
	}

	if (v & DATA_CURSHAPE_CHANGED) {
		count = (CURSOR_MAX_SIZE / NBBY) * data->cursize.y;

		/*
		 * Write the cursor image data:
		 *	set addr[9:8] to 0,
		 *	set addr[7:0] to 0,
		 *	spit it all out.
		 */
		regval = bt485_rd_i(data, BT485_IREG_COMMAND_3);
		regval &= ~0x03;
		bt485_wr_i(data, BT485_IREG_COMMAND_3, regval);
                data->ramdac_wr(data->cookie, BT485_REG_PCRAM_WRADDR, 0);
		for (i = 0; i < count; i++)
			data->ramdac_wr(data->cookie, BT485_REG_CURSOR_RAM,
			    data->curimage[i]);

		/*
		 * Write the cursor mask data:
		 *	set addr[9:8] to 2,
		 *	set addr[7:0] to 0,
		 *	spit it all out.
		 */
		regval = bt485_rd_i(data, BT485_IREG_COMMAND_3);
		regval &= ~0x03; regval |= 0x02;
		bt485_wr_i(data, BT485_IREG_COMMAND_3, regval);
                data->ramdac_wr(data->cookie, BT485_REG_PCRAM_WRADDR, 0);
		for (i = 0; i < count; i++)
			data->ramdac_wr(data->cookie, BT485_REG_CURSOR_RAM,
			    data->curmask[i]);

		/* set addr[9:0] back to 0 */
		regval = bt485_rd_i(data, BT485_IREG_COMMAND_3);
		regval &= ~0x03;
		bt485_wr_i(data, BT485_IREG_COMMAND_3, regval);
	}

	if (v & DATA_CMAP_CHANGED) {
		/* addr[9:0] assumed to be 0 */
		/* set addr[7:0] to 0 */
                data->ramdac_wr(data->cookie, BT485_REG_PCRAM_WRADDR, 0x00);

		/* spit out the cursor data */
		for (i = 0; i < 256; i++) {
                	data->ramdac_wr(data->cookie, BT485_REG_PALETTE,
			    data->cmap_r[i]);
                	data->ramdac_wr(data->cookie, BT485_REG_PALETTE,
			    data->cmap_g[i]);
                	data->ramdac_wr(data->cookie, BT485_REG_PALETTE,
			    data->cmap_b[i]);
		}
	}
}

void
bt485_update_curpos(data)
	struct bt485data *data;
{
	void *cookie = data->cookie;
	int s, x, y;

	s = spltty();

	x = data->curpos.x + CURSOR_MAX_SIZE - data->curhot.x;
	y = data->curpos.y + CURSOR_MAX_SIZE - data->curhot.y;
	data->ramdac_wr(cookie, BT485_REG_CURSOR_X_LOW, x & 0xff);
	data->ramdac_wr(cookie, BT485_REG_CURSOR_X_HIGH, (x >> 8) & 0x0f);
	data->ramdac_wr(cookie, BT485_REG_CURSOR_Y_LOW, y & 0xff);
	data->ramdac_wr(cookie, BT485_REG_CURSOR_Y_HIGH, (y >> 8) & 0x0f);

	splx(s);
}