code:
/*	$OpenBSD: xbridgereg.h,v 1.15 2015/06/16 18:24:38 miod Exp $	*/

/*
 * Copyright (c) 2008, 2009 Miodrag Vallat.
 *
 * Permission to use, copy, modify, and distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

/*
 * IP27/IP30/IP35 Bridge and XBridge Registers
 * IP35 PIC Registers
 */

#define	BRIDGE_REGISTERS_SIZE		0x00030000
#define	BRIDGE_BUS_OFFSET		0x00800000

#define	BRIDGE_NBUSES				1
#define	PIC_NBUSES				2

#define	BRIDGE_NSLOTS				8
#define	PIC_NSLOTS				4
#define	MAX_SLOTS				BRIDGE_NSLOTS

#define	BRIDGE_NINTRS				8

#define	PIC_WIDGET_STATUS_PCIX_SPEED_MASK	0x0000000c00000000UL
#define	PIC_WIDGET_STATUS_PCIX_SPEED_SHIFT	34
#define	PIC_WIDGET_STATUS_PCIX_MODE		0x0000000200000000UL

#define	PIC_WIDGET_CONTROL_NO_SNOOP		0x4000000000000000UL
#define	PIC_WIDGET_CONTROL_RELAX_ORDER		0x2000000000000000UL
#define	BRIDGE_WIDGET_CONTROL_IO_SWAP		0x00800000
#define	BRIDGE_WIDGET_CONTROL_MEM_SWAP		0x00400000
#define	BRIDGE_WIDGET_CONTROL_LARGE_PAGES	0x00200000
#define	BRIDGE_WIDGET_CONTROL_SPEED_MASK	0x00000030
#define	BRIDGE_WIDGET_CONTROL_SPEED_SHIFT	4

/* Response Buffer Address */
#define	BRIDGE_WIDGET_RESP_UPPER	0x00000060
#define	BRIDGE_WIDGET_RESP_LOWER	0x00000068

/*
 * DMA Direct Window
 *
 * The direct map register allows the 2GB direct window to map to
 * a given widget address space. The upper bits of the XIO address,
 * identifying the node to access, are provided in the low-order
 * bits of the register.
 */

#define	BRIDGE_DIR_MAP			0x00000080

#define	BRIDGE_DIRMAP_WIDGET_SHIFT		20
#define	BRIDGE_DIRMAP_ADD_512MB			0x00020000	/* add 512MB */
#define	BRIDGE_DIRMAP_BASE_MASK			0x0001ffff
#define	BRIDGE_DIRMAP_BASE_SHIFT		31

#define	BRIDGE_PCI0_MEM_SPACE_BASE		0x0000000040000000ULL
#define	BRIDGE_PCI_MEM_SPACE_LENGTH		0x0000000040000000ULL
#define	BRIDGE_PCI1_MEM_SPACE_BASE		0x00000000c0000000ULL
#define	BRIDGE_PCI_IO_SPACE_BASE		0x0000000100000000ULL
#define	BRIDGE_PCI_IO_SPACE_LENGTH		0x0000000100000000ULL

#define	BRIDGE_NIC			0x000000b0

#define	BRIDGE_BUS_TIMEOUT		0x000000c0
#define	BRIDGE_BUS_PCI_RETRY_CNT_SHIFT			0
#define	BRIDGE_BUS_PCI_RETRY_CNT_MASK		0x000003ff
#define	BRIDGE_BUS_GIO_TIMEOUT			0x00001000
#define	BRIDGE_BUS_PCI_RETRY_HOLD_SHIFT			16
#define	BRIDGE_BUS_PCI_RETRY_HOLD_MASK		0x001f0000

#define	BRIDGE_PCI_CFG			0x000000c8
#define	BRIDGE_PCI_ERR_UPPER		0x000000d0
#define	BRIDGE_PCI_ERR_LOWER		0x000000d8

/*
 * Interrupt handling
 */

#define	BRIDGE_ISR			0x00000100
#define	BRIDGE_IER			0x00000108
#define	BRIDGE_ICR			0x00000110
#define	BRIDGE_INT_MODE			0x00000118
#define	BRIDGE_INT_DEV			0x00000120
#define	BRIDGE_INT_HOST_ERR		0x00000128
#define	BRIDGE_INT_ADDR(d)		(0x00000130 + 8 * (d))
/* the following two are XBridge-only */
#define	BRIDGE_INT_FORCE_ALWAYS(d)	(0x00000180 + 8 * (d))
#define	BRIDGE_INT_FORCE_PIN(d)		(0x000001c0 + 8 * (d))

/*
 * BRIDGE_ISR bits (bits 32 and beyond are PIC only)
 */

/* PCI-X split completion message parity error */
#define	BRIDGE_ISR_PCIX_SPLIT_MSG_PARITY	0x0000200000000000ULL
/* PCI-X split completion error message */
#define	BRIDGE_ISR_PCIX_SPLIT_EMSG		0x0000100000000000ULL
/* PCI-X split completion timeout */
#define	BRIDGE_ISR_PCIX_SPLIT_TO		0x0000080000000000ULL
/* PCI-X unexpected completion cycle */
#define	BRIDGE_ISR_PCIX_UNEX_COMP		0x0000040000000000ULL
/* internal RAM parity error */
#define	BRIDGE_ISR_INT_RAM_PERR			0x0000020000000000ULL
/* PCI/PCI-X arbitration error */
#define	BRIDGE_ISR_PCIX_ARB_ERR			0x0000010000000000ULL
/* PCI-X read request timeout */
#define	BRIDGE_ISR_PCIX_REQ_TMO			0x0000008000000000ULL
/* PCI-X target abort */
#define	BRIDGE_ISR_PCIX_TABORT			0x0000004000000000ULL
/* PCI-X PERR */
#define	BRIDGE_ISR_PCIX_PERR			0x0000002000000000ULL
/* PCI-X SERR */
#define	BRIDGE_ISR_PCIX_SERR			0x0000001000000000ULL
/* PCI-X PIO retry counter exceeded */
#define	BRIDGE_ISR_PCIX_MRETRY			0x0000000800000000ULL
/* PCI-X master timeout */
#define	BRIDGE_ISR_PCIX_MTMO			0x0000000400000000ULL
/* PCI-X data cycle parity error */
#define	BRIDGE_ISR_PCIX_D_PARITY		0x0000000200000000ULL
/* PCI-X address or attribute cycle parity error */
#define	BRIDGE_ISR_PCIX_A_PARITY		0x0000000100000000ULL
/* multiple errors occured - bridge only */
#define	BRIDGE_ISR_MULTIPLE_ERR			0x0000000080000000ULL
/* PMU access fault */
#define	BRIDGE_ISR_PMU_ESIZE_FAULT		0x0000000040000000ULL
/* unexpected xtalk incoming response */
#define	BRIDGE_ISR_UNEXPECTED_RESP		0x0000000020000000ULL
/* xtalk incoming response framing error */
#define	BRIDGE_ISR_BAD_XRESP_PACKET		0x0000000010000000ULL
/* xtalk incoming request framing error */
#define	BRIDGE_ISR_BAD_XREQ_PACKET		0x0000000008000000ULL
/* xtalk incoming response command word error bit set */
#define	BRIDGE_ISR_RESP_XTALK_ERR		0x0000000004000000ULL
/* xtalk incoming request command word error bit set */
#define	BRIDGE_ISR_REQ_XTALK_ERR		0x0000000002000000ULL
/* request packet has invalid address for this widget */
#define	BRIDGE_ISR_INVALID_ADDRESS		0x0000000001000000ULL
/* request operation not supported by the bridge */
#define	BRIDGE_ISR_UNSUPPORTED_XOP		0x0000000000800000ULL
/* request packet overflow */
#define	BRIDGE_ISR_XREQ_FIFO_OFLOW		0x0000000000400000ULL
/* LLP receiver sequence number error */
#define	BRIDGE_ISR_LLP_REC_SNERR		0x0000000000200000ULL
/* LLP receiver check bit error */
#define	BRIDGE_ISR_LLP_REC_CBERR		0x0000000000100000ULL
/* LLP receiver retry count exceeded */
#define	BRIDGE_ISR_LLP_RCTY			0x0000000000080000ULL
/* LLP transmitter side required retry */
#define	BRIDGE_ISR_LLP_TX_RETRY			0x0000000000040000ULL
/* LLP transmitter retry count exceeded */
#define	BRIDGE_ISR_LLP_TCTY			0x0000000000020000ULL
/* (ATE) SSRAM parity error - bridge only */
#define	BRIDGE_ISR_SSRAM_PERR			0x0000000000010000ULL
/* PCI abort condition */
#define	BRIDGE_ISR_PCI_ABORT			0x0000000000008000ULL
/* PCI bridge detected parity error */
#define	BRIDGE_ISR_PCI_PARITY			0x0000000000004000ULL
/* PCI address or command parity error */
#define	BRIDGE_ISR_PCI_SERR			0x0000000000002000ULL
/* PCI device parity error */
#define	BRIDGE_ISR_PCI_PERR			0x0000000000001000ULL
/* PCI device selection timeout */
#define	BRIDGE_ISR_PCI_MASTER_TMO		0x0000000000000800ULL
/* PCI retry count exceeded */
#define	BRIDGE_ISR_PCI_RETRY_CNT		0x0000000000000400ULL
/* PCI to xtalk read request timeout */
#define	BRIDGE_ISR_XREAD_REQ_TMO		0x0000000000000200ULL
/* GIO non-contiguous byte enable in xtalk packet - bridge only */
#define	BRIDGE_ISR_GIO_BENABLE_ERR		0x0000000000000100ULL
#define	BRIDGE_ISR_HWINTR_MASK			0x00000000000000ffULL

#define	BRIDGE_ISR_ERRMASK			0x00000000fffffe00ULL
#define	PIC_ISR_ERRMASK				0x00003fff7ffffe00ULL

/*
 * BRIDGE_ICR bits, for Bridge and XBridge chips only (error interrupts
 * being cleared in groups)
 */

#define	BRIDGE_ICR_MULTIPLE			0x00000040
#define	BRIDGE_ICR_CRP				0x00000020
#define	BRIDGE_ICR_RESP_BUF			0x00000010
#define	BRIDGE_ICR_REQ_DSP			0x00000008
#define	BRIDGE_ICR_LLP				0x00000004
#define	BRIDGE_ICR_SSRAM			0x00000002
#define	BRIDGE_ICR_PCI				0x00000001
#define	BRIDGE_ICR_ALL				0x0000007f

/*
 * PCI Resource Mapping control
 *
 * There are three ways to map a given device:
 * - memory mapping in the long window, at BRIDGE_PCI_MEM_SPACE_BASE,
 *   shared by all devices.
 * - I/O mapping in the long window, at BRIDGE_PCI_IO_SPACE_BASE,
 *   shared by all devices, but only on widget revision 4 or later.
 * - programmable memory or I/O mapping at a selectable place in the
 *   short window, with an 1MB granularity. The size of this
 *   window is 2MB for the windows at 2MB and 4MB, and 1MB onwards.
 *
 * ARCBios will setup mappings in the short window for us, and
 * the selected address will match BAR0.
 */

#define	BRIDGE_DEVICE(d)		(0x00000200 + 8 * (d))
/* flags applying to the device itself */
/* enable write gathering through ATE */
#define	BRIDGE_DEVICE_WGATHER_PMU		0x01000000
/* enable write gathering through the direct window */
#define	BRIDGE_DEVICE_WGATHER_DIR		0x00800000
/* byteswap DMA done through ATE */
#define	BRIDGE_DEVICE_SWAP_PMU			0x00100000
/* byteswap DMA done through the direct window */
#define	BRIDGE_DEVICE_SWAP_DIR			0x00080000
/* flags applying to the mapping in this devio register */
#define	BRIDGE_DEVICE_PREFETCH			0x00040000
#define	BRIDGE_DEVICE_PRECISE			0x00020000
#define	BRIDGE_DEVICE_COHERENT			0x00010000
#define	BRIDGE_DEVICE_BARRIER			0x00008000
/* byteswap PIO */
#define	BRIDGE_DEVICE_SWAP			0x00002000
/* set if memory space, clear if I/O space */
#define	BRIDGE_DEVICE_IO_MEM			0x00001000
#define	BRIDGE_DEVICE_BASE_MASK			0x00000fff
#define	BRIDGE_DEVICE_BASE_SHIFT		20

#define	BRIDGE_DEVIO_BASE			0x00200000
#define	BRIDGE_DEVIO_LARGE			0x00200000
#define	BRIDGE_DEVIO_SHORT			0x00100000

#define	BRIDGE_DEVIO_OFFS(d) \
	(BRIDGE_DEVIO_BASE + \
	 BRIDGE_DEVIO_LARGE * ((d) < 2 ? (d) : 2) + \
	 BRIDGE_DEVIO_SHORT * ((d) < 2 ? 0 : (d) - 2))
#define	BRIDGE_DEVIO_SIZE(d) \
	((d) < 2 ? BRIDGE_DEVIO_LARGE : BRIDGE_DEVIO_SHORT)
#define	PIC_DEVIO_OFFS(bus,d) \
	(BRIDGE_DEVIO_OFFS(d) + ((bus) != 0 ? BRIDGE_BUS_OFFSET : 0))

#define	BRIDGE_DEVICE_WBFLUSH(d)	(0x00000240 + 8 * (d))

/*
 * Read Response Buffer configuration registers
 *
 * There are 16 RRB, which are shared among the PCI devices.
 * The following registers provide four bits per RRB, describing
 * their RRB assignment.
 *
 * Since these four bits only assign two bits to map to a PCI slot,
 * the low-order bit is implied by the RRB register: one controls the
 * even-numbered PCI slots, while the other controls the odd-numbered
 * PCI slots.
 */

#define	BRIDGE_RRB_EVEN			0x00000280
#define	BRIDGE_RRB_ODD			0x00000288

#define	RRB_VALID				0x8
#define	RRB_VCHAN				0x4
#define	RRB_DEVICE_MASK				0x3
#define	RRB_SHIFT				4

/*
 * Address Translation Entries
 */

#define	BRIDGE_INTERNAL_ATE			128
#define	XBRIDGE_INTERNAL_ATE			1024

#define	BRIDGE_ATE_SSHIFT			12	/* 4KB */
#define	BRIDGE_ATE_LSHIFT			14	/* 16KB */
#define	BRIDGE_ATE_SSIZE			(1ULL << BRIDGE_ATE_SSHIFT)
#define	BRIDGE_ATE_LSIZE			(1ULL << BRIDGE_ATE_LSHIFT)
#define	BRIDGE_ATE_SMASK			(BRIDGE_ATE_SSIZE - 1)
#define	BRIDGE_ATE_LMASK			(BRIDGE_ATE_LSIZE - 1)

#define	BRIDGE_ATE(a)			(0x00010000 + (a) * 8)

#define	ATE_NV					0x0000000000000000ULL
#define	ATE_V					0x0000000000000001ULL
#define	ATE_COH					0x0000000000000002ULL
#define	ATE_PRECISE				0x0000000000000004ULL
#define	ATE_PREFETCH				0x0000000000000008ULL
#define	ATE_BARRIER				0x0000000000000010ULL
#define	ATE_BSWAP				0x0000000000000020ULL	/* XB */
#define	ATE_WIDGET_MASK				0x0000000000000f00ULL
#define	ATE_WIDGET_SHIFT			8
#define	ATE_ADDRESS_MASK			0x0000fffffffff000ULL
#define	ATE_RMF_MASK				0x00ff000000000000ULL	/* BR */

/*
 * PIC Write Request memory
 */

#define	PIC_WR_REQ_LOWER(a)		(0x00018000 + (a) * 8)
#define	PIC_WR_REQ_UPPER(a)		(0x00018800 + (a) * 8)
#define	PIC_WR_REQ_PARITY(a)		(0x00019000 + (a) * 8)

#define	PIC_WR_REQ_ENTRIES				0x100

/*
 * Configuration space
 *
 * Access to the first bus is done in the first area, sorted by
 * device number and function number.
 * Access to other buses is done in the second area, after programming
 * BRIDGE_PCI_CFG to the appropriate bus and slot number.
 */

#define	BRIDGE_PCI_CFG_SPACE		0x00020000
#define	BRIDGE_PCI_CFG1_SPACE		0x00028000

/*
 * DMA addresses
 * The Bridge can do DMA either through a direct 2GB window, or through
 * a 1GB translated window, using its ATE memory.
 */

#define	BRIDGE_DMA_TRANSLATED_BASE	0x40000000ULL
#define	XBRIDGE_DMA_TRANSLATED_SWAP	0x20000000ULL
#define	ATE_ADDRESS(a,s) \
		(BRIDGE_DMA_TRANSLATED_BASE + ((a) << (s)))
#define	ATE_INDEX(a,s) \
		(((a) - BRIDGE_DMA_TRANSLATED_BASE) >> (s))

#define	BRIDGE_DMA_DIRECT_BASE		0x80000000ULL
#define	BRIDGE_DMA_DIRECT_LENGTH	0x80000000ULL

license: unknown


code:
/*	$OpenBSD: xheart.c,v 1.27 2014/09/30 06:51:58 jmatthew Exp $	*/

/*
 * Copyright (c) 2008 Miodrag Vallat.
 *
 * Permission to use, copy, modify, and distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

/*
 * IP30 Heart Widget
 */

#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/device.h>
#include <sys/evcount.h>
#include <sys/malloc.h>
#include <sys/timetc.h>
#include <sys/atomic.h>

#include <machine/autoconf.h>
#include <machine/cpu.h>
#include <mips64/mips_cpu.h>
#include <machine/intr.h>

#include <sgi/xbow/xbow.h>
#include <sgi/xbow/xbowdevs.h>
#include <sgi/xbow/xheartreg.h>

#include <dev/onewire/onewirereg.h>
#include <dev/onewire/onewirevar.h>

struct xheart_softc {
	struct device		sc_dev;
	struct onewire_bus	sc_bus;
};

int	xheart_match(struct device *, void *, void *);
void	xheart_attach(struct device *, struct device *, void *);

const struct cfattach xheart_ca = {
	sizeof(struct xheart_softc), xheart_match, xheart_attach,
};

struct cfdriver xheart_cd = {
	NULL, "xheart", DV_DULL,
};

int	xheart_ow_reset(void *);
int	xheart_ow_read_bit(struct xheart_softc *);
int	xheart_ow_send_bit(void *, int);
int	xheart_ow_read_byte(void *);
int	xheart_ow_triplet(void *, int);
int	xheart_ow_pulse(struct xheart_softc *, int, int);

int	xheart_intr_register(int, int, int *);
int	xheart_intr_establish(int (*)(void *), void *, int, int, const char *,
	    struct intrhand *);
void	xheart_intr_disestablish(int);
void	xheart_intr_clear(int);
void	xheart_intr_set(int);
uint32_t xheart_intr_handler(uint32_t, struct trap_frame *);
void	xheart_intr_makemasks(void);
void	xheart_setintrmask(int);
void	xheart_splx(int);

u_int	xheart_get_timecount(struct timecounter *);

struct timecounter xheart_timecounter = {
	.tc_get_timecount = xheart_get_timecount,
	.tc_poll_pps = NULL,
	.tc_counter_mask = 0xffffffff,	/* truncate 52-bit counter to 32-bit */
	.tc_frequency = 12500000,
	.tc_name = "heart",
	.tc_quality = 100
};

extern uint32_t ip30_lights_frob(uint32_t, struct trap_frame *);

/*
 * HEART interrupt handling declarations: 64 sources; 5 levels.
 */

struct intrhand *xheart_intrhand[HEART_NINTS];

#ifdef notyet
#define	INTPRI_HEART_4	(INTPRI_CLOCK + 1)
#define	INTPRI_HEART_3	(INTPRI_HEART_4 + 1)
#define	INTPRI_HEART_2	(INTPRI_HEART_3 + 1)
#define	INTPRI_HEART_1	(INTPRI_HEART_2 + 1)
#define	INTPRI_HEART_0	(INTPRI_HEART_1 + 1)
#else
#define	INTPRI_HEART_2	(INTPRI_IPI)
#define	INTPRI_HEART_0	(INTPRI_CLOCK + 1)
#endif
#define	INTPRI_HEART_LEDS	(INTPRI_HEART_0 + 1)

uint64_t xheart_intem[MAXCPUS];
uint64_t xheart_imask[MAXCPUS][NIPLS];

int
xheart_match(struct device *parent, void *match, void *aux)
{
	struct xbow_attach_args *xaa = aux;

	if (xaa->xaa_vendor == XBOW_VENDOR_SGI4 &&
	    xaa->xaa_product == XBOW_PRODUCT_SGI4_HEART)
		return 1;

	return 0;
}

void
xheart_attach(struct device *parent, struct device *self, void *aux)
{
	struct xbow_attach_args *xaa = aux;
	struct xheart_softc *sc = (void *)self;
	struct onewirebus_attach_args oba;
	paddr_t heart;

	printf(" revision %d\n", xaa->xaa_revision);

	sc->sc_bus.bus_cookie = sc;
	sc->sc_bus.bus_reset = xheart_ow_reset;
	sc->sc_bus.bus_bit = xheart_ow_send_bit;
	sc->sc_bus.bus_read_byte = xheart_ow_read_byte;
	sc->sc_bus.bus_write_byte = NULL;	/* use default routine */
	sc->sc_bus.bus_read_block = NULL;	/* use default routine */
	sc->sc_bus.bus_write_block = NULL;	/* use default routine */
	sc->sc_bus.bus_triplet = xheart_ow_triplet;
	sc->sc_bus.bus_matchrom = NULL;		/* use default routine */
	sc->sc_bus.bus_search = NULL;		/* use default routine */

	oba.oba_bus = &sc->sc_bus;
	oba.oba_flags = ONEWIRE_SCAN_NOW | ONEWIRE_NO_PERIODIC_SCAN;
	config_found(self, &oba, onewirebus_print);

	xbow_intr_address = 0x80;
	xbow_intr_widget_intr_register = xheart_intr_register;
	xbow_intr_widget_intr_establish = xheart_intr_establish;
	xbow_intr_widget_intr_disestablish = xheart_intr_disestablish;
	xbow_intr_widget_intr_clear = xheart_intr_clear;
	xbow_intr_widget_intr_set = xheart_intr_set;

	/*
	 * Acknowledge and disable all interrupts.
	 */
	heart = PHYS_TO_XKPHYS(HEART_PIU_BASE, CCA_NC);
	*(volatile uint64_t*)(heart + HEART_ISR_CLR) = 0xffffffffffffffffUL;
	*(volatile uint64_t*)(heart + HEART_IMR(0)) = 0UL;
	*(volatile uint64_t*)(heart + HEART_IMR(1)) = 0UL;
	*(volatile uint64_t*)(heart + HEART_IMR(2)) = 0UL;
	*(volatile uint64_t*)(heart + HEART_IMR(3)) = 0UL;

#ifdef notyet
	set_intr(INTPRI_HEART_4, CR_INT_4, xheart_intr_handler);
	set_intr(INTPRI_HEART_3, CR_INT_3, xheart_intr_handler);
#endif
	set_intr(INTPRI_HEART_2, CR_INT_2, xheart_intr_handler);
#ifdef notyet
	set_intr(INTPRI_HEART_1, CR_INT_1, xheart_intr_handler);
#endif
	set_intr(INTPRI_HEART_0, CR_INT_0, xheart_intr_handler);

	set_intr(INTPRI_HEART_LEDS, CR_INT_5, ip30_lights_frob);

	register_splx_handler(xheart_splx);

	tc_init(&xheart_timecounter);
}

/*
 * Number-In-a-Can (1-Wire) interface
 */

int
xheart_ow_reset(void *v)
{
	struct xheart_softc *sc = v;
	return xheart_ow_pulse(sc, 500, 65);
}

int
xheart_ow_read_bit(struct xheart_softc *sc)
{
	return xheart_ow_pulse(sc, 6, 13);
}

int
xheart_ow_send_bit(void *v, int bit)
{
	struct xheart_softc *sc = v;
	int rc;

	if (bit != 0)
		rc = xheart_ow_pulse(sc, 6, 110);
	else
		rc = xheart_ow_pulse(sc, 80, 30);
	return rc;
}

int
xheart_ow_read_byte(void *v)
{
	struct xheart_softc *sc = v;
	unsigned int byte = 0;
	int i;

	for (i = 0; i < 8; i++)
		byte |= xheart_ow_read_bit(sc) << i;

	return byte;
}

int
xheart_ow_triplet(void *v, int dir)
{
	struct xheart_softc *sc = v;
	int rc;

	rc = xheart_ow_read_bit(sc);
	rc <<= 1;
	rc |= xheart_ow_read_bit(sc);

	switch (rc) {
	case 0x0:
		xheart_ow_send_bit(v, dir);
		break;
	case 0x1:
		xheart_ow_send_bit(v, 0);
		break;
	default:
		xheart_ow_send_bit(v, 1);
		break;
	}

	return (rc);
}

int
xheart_ow_pulse(struct xheart_softc *sc, int pulse, int data)
{
	uint64_t mcr_value;
	paddr_t heart;

	heart = PHYS_TO_XKPHYS(HEART_PIU_BASE + HEART_MICROLAN, CCA_NC);
	mcr_value = (pulse << 10) | (data << 2);
	*(volatile uint64_t *)heart = mcr_value;
	do {
		mcr_value = *(volatile uint64_t *)heart;
	} while ((mcr_value & 0x00000002) == 0);

	delay(500);

	return (mcr_value & 1);
}

/*
 * HEART interrupt handling routines
 */

/*
 * Find a suitable interrupt bit for the given interrupt.
 */
int
xheart_intr_register(int widget, int level, int *intrbit)
{
	int bit;
	u_long cpuid = cpu_number();

	/*
	 * All interrupts will be serviced at hardware level 0,
	 * so the `level' argument can be ignored.
	 */
	for (bit = HEART_INTR_WIDGET_MAX; bit >= HEART_INTR_WIDGET_MIN; bit--)
		if ((xheart_intem[cpuid] & (1UL << bit)) == 0)
			goto found;

	return EINVAL;

found:
	*intrbit = bit;
	return 0;
}

/*
 * Register an interrupt handler for a given source, and enable it.
 */
int
xheart_intr_establish(int (*func)(void *), void *arg, int intrbit,
    int level, const char *name, struct intrhand *ihstore)
{
	struct intrhand *ih;
	int s;
	u_long cpuid = cpu_number();

#ifdef DIAGNOSTIC
	if (intrbit < 0 || intrbit >= HEART_NINTS)
		return EINVAL;
#endif

	/*
	 * HEART interrupts are not supposed to be shared - the interrupt
	 * mask is large enough for all widgets.
	 */
	if (xheart_intrhand[intrbit] != NULL)
		return EEXIST;

	if (ihstore == NULL) {
		ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT);
		if (ih == NULL)
			return ENOMEM;
		ih->ih_flags = IH_ALLOCATED;
	} else {
		ih = ihstore;
		ih->ih_flags = 0;
	}

	ih->ih_next = NULL;
	ih->ih_fun = func;
	ih->ih_arg = arg;
	ih->ih_level = level;
	ih->ih_irq = intrbit;
	if (name != NULL)
		evcount_attach(&ih->ih_count, name, &ih->ih_level);

	s = splhigh();

	xheart_intrhand[intrbit] = ih;

	xheart_intem[cpuid] |= 1UL << intrbit;
	xheart_intr_makemasks();

	splx(s);	/* causes hw mask update */

	return 0;
}

void
xheart_intr_disestablish(int intrbit)
{
	struct intrhand *ih;
	int s;
	u_long cpuid = cpu_number();

#ifdef DIAGNOSTIC
	if (intrbit < 0 || intrbit >= HEART_NINTS)
		return;
#endif

	s = splhigh();

	if ((ih = xheart_intrhand[intrbit]) == NULL) {
		splx(s);
		return;
	}

	xheart_intrhand[intrbit] = NULL;

	xheart_intem[cpuid] &= ~(1UL << intrbit);
	xheart_intr_makemasks();

	splx(s);

	if (ISSET(ih->ih_flags, IH_ALLOCATED))
		free(ih, M_DEVBUF, 0);
}

void
xheart_intr_clear(int intrbit)
{
	*(volatile uint64_t *)PHYS_TO_XKPHYS(HEART_PIU_BASE + HEART_ISR_CLR,
	    CCA_NC) = 1UL << intrbit;
}

void
xheart_intr_set(int intrbit)
{
	*(volatile uint64_t *)PHYS_TO_XKPHYS(HEART_PIU_BASE + HEART_ISR_SET,
	    CCA_NC) = 1UL << intrbit;
}

void
xheart_splx(int newipl)
{
	struct cpu_info *ci = curcpu();

	/* Update masks to new ipl. Order highly important! */
	__asm__ (".set noreorder\n");
	ci->ci_ipl = newipl;
	mips_sync();
	__asm__ (".set reorder\n");

	if (CPU_IS_PRIMARY(ci))
		xheart_setintrmask(newipl);

	/* If we still have softints pending trigger processing. */
	if (ci->ci_softpending != 0 && newipl < IPL_SOFTINT)
		setsoftintr0();
}

/*
 * Heart interrupt handler. Can be registered at any hardware interrupt level.
 */

#define	INTR_FUNCTIONNAME	xheart_intr_handler
#define	MASK_FUNCTIONNAME	xheart_intr_makemasks
#define	INTR_LOCAL_DECLS \
	paddr_t heart = PHYS_TO_XKPHYS(HEART_PIU_BASE, CCA_NC); \
	u_long cpuid = cpu_number();
#define	MASK_LOCAL_DECLS \
	u_long cpuid = cpu_number();
#define	INTR_GETMASKS \
do { \
	isr = *(volatile uint64_t *)(heart + HEART_ISR); \
	imr = *(volatile uint64_t *)(heart + HEART_IMR(cpuid));	\
	switch (hwpend) { \
	case CR_INT_0: \
		isr &= HEART_ISR_LVL0_MASK; \
		bit = HEART_ISR_LVL0_MAX; \
		break; \
	case CR_INT_1: \
		isr &= HEART_ISR_LVL1_MASK; \
		bit = HEART_ISR_LVL1_MAX; \
		break; \
	case CR_INT_2: \
		isr &= HEART_ISR_LVL2_MASK; \
		bit = HEART_ISR_LVL2_MAX; \
		break; \
	case CR_INT_3: \
		isr &= HEART_ISR_LVL3_MASK; \
		bit = HEART_ISR_LVL3_MAX; \
		break; \
	case CR_INT_4: \
		isr &= HEART_ISR_LVL4_MASK; \
		bit = HEART_ISR_LVL4_MAX; \
		break; \
	default: \
		return 0;	/* can't happen */ \
	} \
} while (0)
#define	INTR_MASKPENDING \
	*(volatile uint64_t *)(heart + HEART_IMR(cpuid)) &= ~isr
#define	INTR_IMASK(ipl)		xheart_imask[cpuid][ipl]
#define	INTR_HANDLER(bit)	xheart_intrhand[bit]
#define	INTR_SPURIOUS(bit) \
do { \
	printf("spurious xheart interrupt %d\n", bit); \
} while (0)
#define	INTR_MASKRESTORE \
	*(volatile uint64_t *)(heart + HEART_IMR(cpuid)) = imr
#define	INTR_MASKSIZE	HEART_NINTS

#include <sgi/sgi/intr_template.c>

void
xheart_setintrmask(int level)
{
	paddr_t heart = PHYS_TO_XKPHYS(HEART_PIU_BASE, CCA_NC);
	u_long cpuid = cpu_number();

	*(volatile uint64_t *)(heart + HEART_IMR(cpuid)) =
		xheart_intem[cpuid] & ~xheart_imask[cpuid][level];
}

/*
 * Timecounter interface.
 */

uint
xheart_get_timecount(struct timecounter *tc)
{
	paddr_t heart = PHYS_TO_XKPHYS(HEART_PIU_BASE, CCA_NC);

	return (u_int)*(volatile uint64_t *)(heart + HEART_CTR_VALUE);
}


code:
/*	$OpenBSD: xheartreg.h,v 1.5 2012/06/17 12:34:19 miod Exp $	*/

/*
 * Copyright (c) 2008, 2011 Miodrag Vallat.
 *
 * Permission to use, copy, modify, and distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

/*
 * IP30 HEART registers
 */

/* physical address in PIU mode */
#define	HEART_PIU_BASE	0x000000000ff00000

#define	HEART_MODE		0x0000
#define	HEART_MEMORY_STATUS	0x0020	/* 8 32 bit registers */
#define	HEART_MEMORY_VALID		0x80000000
#define	HEART_MEMORY_SIZE_MASK		0x003f0000
#define	HEART_MEMORY_SIZE_SHIFT		16
#define	HEART_MEMORY_ADDR_MASK		0x000001ff
#define	HEART_MEMORY_ADDR_SHIFT		0
#define	HEART_MEMORY_UNIT_SHIFT		25	/* 32MB */

#define	HEART_MICROLAN		0x00b8

/*
 * Interrupt handling registers.
 * The Heart supports four different interrupt targets, although only
 * the two cpus are used in practice.
 */

#define	HEART_IMR(s)		(0x00010000 + (s) * 8)
#define	HEART_ISR_SET		0x00010020
#define	HEART_ISR_CLR		0x00010028
#define	HEART_ISR		0x00010030

/*
 * ISR bit assignments.
 */

/** Level 4 interrupt: hardware error */
#define	HEART_ISR_LVL4_MASK		0xfff8000000000000UL
#define	HEART_ISR_LVL4_MAX		63
/* Heart (widget 8) error */
#define	HEART_ISR_WID08_ERROR		63
/* CPU bus error */
#define	HEART_ISR_CPU_BUSERR(c)		(59 + (c))
/* Crossbow (widget 0) error */
#define	HEART_ISR_WID00_ERROR		58
/* Widget error */
#define	HEART_ISR_WID0F_ERROR		57
#define	HEART_ISR_WID0E_ERROR		56
#define	HEART_ISR_WID0D_ERROR		55
#define	HEART_ISR_WID0C_ERROR		54
#define	HEART_ISR_WID0B_ERROR		53
#define	HEART_ISR_WID0A_ERROR		52
#define	HEART_ISR_WID09_ERROR		51

#define	HEART_ISR_WID_ERROR(w)	\
	((w) == 0 ? HEART_ISR_WID00_ERROR : \
	 (w) == 8 ? HEART_ISR_WID08_ERROR : HEART_ISR_WID09_ERROR + (w) - 9)

/** Level 3 interrupt: heart counter/timer */
#define	HEART_ISR_LVL3_MASK		0x0004000000000000UL
#define	HEART_ISR_LVL3_MAX		50
/* Crossbow clock */
#define	HEART_ISR_HEARTCLOCK		50

/** Level 2 interrupt */
#define	HEART_ISR_LVL2_MASK		0x0003ffff00000000UL
#define	HEART_ISR_LVL2_MAX		49
/* IPI */
#define	HEART_ISR_IPI(c)		(46 + (c))
/* Debugger interrupts */
#define	HEART_ISR_DBG(c)		(42 + (c))
/* Power switch */
#define	HEART_ISR_POWER			41
/* 40-32 freely available */

/** Level 1 interrupt */
#define	HEART_ISR_LVL1_MASK		0x00000000ffff0000UL
#define	HEART_ISR_LVL1_MAX		31
/* 31-16 freely available */

/** Level 0 interrupt */
#define	HEART_ISR_LVL0_MASK		0x000000000000ffffUL
#define	HEART_ISR_LVL0_MAX		15
/* 15-3 freely available */

#define	HEART_INTR_WIDGET_MAX		15
#define	HEART_INTR_WIDGET_MIN		3

#define	HEART_NINTS			64

/*
 * Crossbow clock, as a free-running counter.
 * The clock rate is 400 MHz, with the counter running at 1/32 of the clock,
 * i.e. 12.5 MHz (80 nS period)
 */

#define	HEART_CTR_VALUE		0x00020000	/* 52-bit counter value, r/o */
#define	HEART_CTR_LIMIT		0x00030000	/* 24-bit limit value */
#define	HEART_CTR_TRIGGER	0x00040000

/*
 * Per-processor ID register.
 */

#define	HEART_PRID		0x00050000


code:
D/conf////
D/dev////
D/include////
D/sh////

path: sys/arch/sh/CVS/Entries


code: src/sys/arch/sh

path: sys/arch/sh/CVS/Repository


code: src/sys/arch/sh/conf

path: sys/arch/sh/conf/CVS/Repository


code:
#	$OpenBSD: files.sh,v 1.5 2015/07/17 22:52:29 tedu Exp $
#	$NetBSD: files.sh3,v 1.32 2005/12/11 12:18:58 christos Exp $

file	arch/sh/sh/cache.c
file	arch/sh/sh/cache_sh3.c		sh3
file	arch/sh/sh/cache_sh4.c		sh4
file	arch/sh/sh/clock.c
file	arch/sh/sh/db_disasm.c		ddb
file	arch/sh/sh/db_interface.c	ddb
file	arch/sh/sh/db_memrw.c		ddb
file	arch/sh/sh/db_trace.c		ddb
file	arch/sh/sh/devreg.c		sh3 & sh4
file	arch/sh/sh/interrupt.c
file	arch/sh/sh/locore_c.c
file	arch/sh/sh/locore_subr.S
file	arch/sh/sh/mem.c
file	arch/sh/sh/mmu.c
file	arch/sh/sh/mmu_sh3.c		sh3
file	arch/sh/sh/mmu_sh4.c		sh4
file	arch/sh/sh/mutex.c
file	arch/sh/sh/pmap.c
file	arch/sh/sh/process_machdep.c
file	arch/sh/sh/sh_machdep.c
file	arch/sh/sh/sys_machdep.c
file	arch/sh/sh/trap.c
file	arch/sh/sh/vectors.S
file	arch/sh/sh/vm_machdep.c

file	arch/sh/sh/in_cksum.S
file	netinet/in4_cksum.c

file	dev/cninit.c

# quad support is necessary for 32 bit architectures
file	lib/libkern/adddi3.c
file	lib/libkern/anddi3.c
file	lib/libkern/ashldi3.c
file	lib/libkern/ashrdi3.c
file	lib/libkern/cmpdi2.c
file	lib/libkern/divdi3.c
file	lib/libkern/iordi3.c
file	lib/libkern/lshldi3.c
file	lib/libkern/lshrdi3.c
file	lib/libkern/moddi3.c
file	lib/libkern/muldi3.c
file	lib/libkern/negdi2.c
file	lib/libkern/notdi2.c
file	lib/libkern/qdivrem.c
file	lib/libkern/subdi3.c
file	lib/libkern/ucmpdi2.c
file	lib/libkern/udivdi3.c
file	lib/libkern/umoddi3.c
file	lib/libkern/xordi3.c

file	lib/libkern/arch/sh/movstr_i4.S
file	lib/libkern/arch/sh/sdivsi3.S
file	lib/libkern/arch/sh/udivsi3.S


code:
#	$OpenBSD: files.shb,v 1.1.1.1 2006/10/06 21:02:55 miod Exp $
#	$NetBSD: files.shb,v 1.4 2005/12/11 12:18:58 christos Exp $
#
# SuperH internal devices.
#
device	shb { }
attach	shb at mainbus

file	arch/sh/dev/shb.c		shb

device	scif: tty
attach	scif at shb
file	arch/sh/dev/scif.c		scif	needs-flag


code:
#	$OpenBSD: files.shpcic,v 1.4 2009/04/25 16:25:12 kettenis Exp $
#	$NetBSD: files.shpcic,v 1.2 2005/12/11 12:18:58 christos Exp $

#
# SH7751{,R} integrated PCI controller
#
device  shpcic: pcibus
attach  shpcic at mainbus

file    arch/sh/dev/shpcic.c		sh4 & shpcic
file    arch/sh/dev/pciide_machdep.c	pciide


code: src/sys/arch/sh/dev

path: sys/arch/sh/dev/CVS/Repository


code:
/*	$OpenBSD: pcicreg.h,v 1.1.1.1 2006/10/06 21:02:55 miod Exp $	*/
/*	$NetBSD: pcicreg.h,v 1.2 2005/12/11 12:18:58 christos Exp $	*/

/*-
 * Copyright (c) 2005 NONAKA Kimihiro
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */

#include <sh/devreg.h>

/*
 * PCI Controller
 */

#define	SH4_PCIC		0xfe200000

#define	SH4_PCIC_IO		0xfe240000
#define	SH4_PCIC_IO_SIZE	0x00040000
#define	SH4_PCIC_IO_MASK	(SH4_PCIC_IO_SIZE-1)
#define	SH4_PCIC_MEM		0xfd000000
#define	SH4_PCIC_MEM_SIZE	0x01000000
#define	SH4_PCIC_MEM_MASK	(SH4_PCIC_MEM_SIZE-1)

#define	SH4_PCICONF	(SH4_PCIC+0x000)	/* 32bit */
#define	SH4_PCICONF0	(SH4_PCICONF+0x00)	/* 32bit */
#define	SH4_PCICONF1	(SH4_PCICONF+0x04)	/* 32bit */
#define	SH4_PCICONF2	(SH4_PCICONF+0x08)	/* 32bit */
#define	SH4_PCICONF3	(SH4_PCICONF+0x0c)	/* 32bit */
#define	SH4_PCICONF4	(SH4_PCICONF+0x10)	/* 32bit */
#define	SH4_PCICONF5	(SH4_PCICONF+0x14)	/* 32bit */
#define	SH4_PCICONF6	(SH4_PCICONF+0x18)	/* 32bit */
#define	SH4_PCICONF7	(SH4_PCICONF+0x1c)	/* 32bit */
#define	SH4_PCICONF8	(SH4_PCICONF+0x20)	/* 32bit */
#define	SH4_PCICONF9	(SH4_PCICONF+0x24)	/* 32bit */
#define	SH4_PCICONF10	(SH4_PCICONF+0x28)	/* 32bit */
#define	SH4_PCICONF11	(SH4_PCICONF+0x2c)	/* 32bit */
#define	SH4_PCICONF12	(SH4_PCICONF+0x30)	/* 32bit */
#define	SH4_PCICONF13	(SH4_PCICONF+0x34)	/* 32bit */
#define	SH4_PCICONF14	(SH4_PCICONF+0x38)	/* 32bit */
#define	SH4_PCICONF15	(SH4_PCICONF+0x3c)	/* 32bit */
#define	SH4_PCICONF16	(SH4_PCICONF+0x40)	/* 32bit */
#define	SH4_PCICONF17	(SH4_PCICONF+0x44)	/* 32bit */
#define	SH4_PCICR	(SH4_PCIC+0x100)	/* 32bit */
#define	SH4_PCILSR0	(SH4_PCIC+0x104)	/* 32bit */
#define	SH4_PCILSR1	(SH4_PCIC+0x108)	/* 32bit */
#define	SH4_PCILAR0	(SH4_PCIC+0x10c)	/* 32bit */
#define	SH4_PCILAR1	(SH4_PCIC+0x110)	/* 32bit */
#define	SH4_PCIINT	(SH4_PCIC+0x114)	/* 32bit */
#define	SH4_PCIINTM	(SH4_PCIC+0x118)	/* 32bit */
#define	SH4_PCIALR	(SH4_PCIC+0x11c)	/* 32bit */
#define	SH4_PCICLR	(SH4_PCIC+0x120)	/* 32bit */
#define	SH4_PCIAINT	(SH4_PCIC+0x130)	/* 32bit */
#define	SH4_PCIAINTM	(SH4_PCIC+0x134)	/* 32bit */
#define	SH4_PCIDMABT	(SH4_PCIC+0x140)	/* 32bit */
#define	SH4_PCIDPA0	(SH4_PCIC+0x180)	/* 32bit */
#define	SH4_PCIDLA0	(SH4_PCIC+0x184)	/* 32bit */
#define	SH4_PCIDTC0	(SH4_PCIC+0x188)	/* 32bit */
#define	SH4_PCIDCR0	(SH4_PCIC+0x18c)	/* 32bit */
#define	SH4_PCIDPA1	(SH4_PCIC+0x190)	/* 32bit */
#define	SH4_PCIDLA1	(SH4_PCIC+0x194)	/* 32bit */
#define	SH4_PCIDTC1	(SH4_PCIC+0x198)	/* 32bit */
#define	SH4_PCIDCR1	(SH4_PCIC+0x19c)	/* 32bit */
#define	SH4_PCIDPA2	(SH4_PCIC+0x1a0)	/* 32bit */
#define	SH4_PCIDLA2	(SH4_PCIC+0x1a4)	/* 32bit */
#define	SH4_PCIDTC2	(SH4_PCIC+0x1a8)	/* 32bit */
#define	SH4_PCIDCR2	(SH4_PCIC+0x1ac)	/* 32bit */
#define	SH4_PCIDPA3	(SH4_PCIC+0x1b0)	/* 32bit */
#define	SH4_PCIDLA3	(SH4_PCIC+0x1b4)	/* 32bit */
#define	SH4_PCIDTC3	(SH4_PCIC+0x1b8)	/* 32bit */
#define	SH4_PCIDCR3	(SH4_PCIC+0x1bc)	/* 32bit */
#define	SH4_PCIPAR	(SH4_PCIC+0x1c0)	/* 32bit */
#define	SH4_PCIMBR	(SH4_PCIC+0x1c4)	/* 32bit */
#define	SH4_PCIIOBR	(SH4_PCIC+0x1c8)	/* 32bit */
#define	SH4_PCIPINT	(SH4_PCIC+0x1cc)	/* 32bit */
#define	SH4_PCIPINTM	(SH4_PCIC+0x1d0)	/* 32bit */
#define	SH4_PCICLKR	(SH4_PCIC+0x1d4)	/* 32bit */
#define	SH4_PCIBCR1	(SH4_PCIC+0x1e0)	/* 32bit */
#define	SH4_PCIBCR2	(SH4_PCIC+0x1e4)	/* 32bit */
#define	SH4_PCIWCR1	(SH4_PCIC+0x1e8)	/* 32bit */
#define	SH4_PCIWCR2	(SH4_PCIC+0x1ec)	/* 32bit */
#define	SH4_PCIWCR3	(SH4_PCIC+0x1f0)	/* 32bit */
#define	SH4_PCIMCR	(SH4_PCIC+0x1f4)	/* 32bit */
#define	SH4_PCIBCR3	(SH4_PCIC+0x1f8)	/* 32bit: SH7751R */
#define	SH4_PCIPCTR	(SH4_PCIC+0x200)	/* 32bit */
#define	SH4_PCIPDTR	(SH4_PCIC+0x204)	/* 32bit */
#define	SH4_PCIPDR	(SH4_PCIC+0x220)	/* 32bit */

#define	PCICR_BASE		0xa5000000
#define	PCICR_TRDSGL		0x00000200
#define	PCICR_BYTESWAP		0x00000100
#define	PCICR_PCIPUP		0x00000080
#define	PCICR_BMABT		0x00000040
#define	PCICR_MD10		0x00000020
#define	PCICR_MD9		0x00000010
#define	PCICR_SERR		0x00000008
#define	PCICR_INTA		0x00000004
#define	PCICR_RSTCTL		0x00000002
#define	PCICR_CFINIT		0x00000001

#define	PCIINT_M_LOCKON		0x00008000
#define	PCIINT_T_TGT_ABORT	0x00004000
#define	PCIINT_TGT_RETRY	0x00000200
#define	PCIINT_MST_DIS		0x00000100
#define	PCIINT_ADRPERR		0x00000080
#define	PCIINT_SERR_DET		0x00000040
#define	PCIINT_T_DPERR_WT	0x00000020
#define	PCIINT_T_PERR_DET	0x00000010
#define	PCIINT_M_TGT_ABORT	0x00000008
#define	PCIINT_M_MST_ABORT	0x00000004
#define	PCIINT_M_DPERR_WT	0x00000002
#define	PCIINT_M_DPERR_RD	0x00000001
#define	PCIINT_ALL		0x0000c3ff
#define	PCIINT_CLEAR_ALL	PCIINT_ALL

#define	PCIINTM_MASK_ALL	0x00000000
#define	PCIINTM_UNMASK_ALL	PCIINT_ALL

#define	PCIMBR_MASK		0xff000000

#define	PCIIOBR_MASK		0xffc00000


code:
/*	$OpenBSD: pciide_machdep.c,v 1.2 2010/08/07 03:50:01 krw Exp $	*/

/*
 * Copyright (c) 1998 Christopher G. Demetriou.  All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *      This product includes software developed by Christopher G. Demetriou
 *	for the NetBSD Project.
 * 4. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/*
 * PCI IDE controller driver (i386 machine-dependent portion).
 *
 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD
 * sys/dev/pci/ppb.c, revision 1.16).
 *
 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" from the
 * PCI SIG.
 */

#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>

#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
#include <dev/pci/pciidereg.h>
#include <dev/pci/pciidevar.h>

void *
pciide_machdep_compat_intr_establish(struct device *dev,
    struct pci_attach_args *pa, int chan, int (*func)(void *), void *arg)
{
	panic("pciide_machdep_compat_intr_establish called");
	return (NULL);
}

void
pciide_machdep_compat_intr_disestablish(pci_chipset_tag_t pc, void *cookie)
{
	panic("pciide_machdep_compat_intr_disestablish called");
}


code:
/*	$OpenBSD: scif.c,v 1.15 2011/04/30 16:08:44 miod Exp $	*/
/*	$NetBSD: scif.c,v 1.47 2006/07/23 22:06:06 ad Exp $ */

/*-
 * Copyright (C) 1999 T.Horiuchi and SAITOH Masanobu.  All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/*-
 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
 * All rights reserved.
 *
 * This code is derived from software contributed to The NetBSD Foundation
 * by Charles M. Hannum.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

/*
 * Copyright (c) 1991 The Regents of the University of California.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of the University nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 *	@(#)com.c	7.5 (Berkeley) 5/16/91
 */

/*
 * SH internal serial driver
 *
 * This code is derived from both z8530tty.c and com.c
 */

#include <sys/param.h>
#include <sys/systm.h>
#include <sys/tty.h>
#include <sys/proc.h>
#include <sys/conf.h>
#include <sys/file.h>
#include <sys/syslog.h>
#include <sys/kernel.h>
#include <sys/device.h>
#include <sys/malloc.h>
#include <sys/timeout.h>

#include <dev/cons.h>

#include <sh/clock.h>
#include <sh/trap.h>
#include <machine/intr.h>
#include <machine/conf.h>

#include <sh/dev/scifreg.h>

#ifdef DDB
#include <ddb/db_var.h>
#endif

void	scifstart(struct tty *);
int	scifparam(struct tty *, struct termios *);

cons_decl(scif);
void scif_intr_init(void);
int scifintr(void *);

struct scif_softc {
	struct device sc_dev;		/* boilerplate */
	struct tty *sc_tty;
	void *sc_si;

	struct timeout sc_diag_tmo;

#if 0
	bus_space_tag_t sc_iot;		/* ISA i/o space identifier */
	bus_space_handle_t   sc_ioh;	/* ISA io handle */

	int sc_drq;

	int sc_frequency;
#endif

	u_int sc_overflows,
	      sc_floods,
	      sc_errors;		/* number of retries so far */
	u_char sc_status[7];		/* copy of registers */

	int sc_hwflags;
	int sc_swflags;
	u_int sc_fifolen;

	u_int sc_r_hiwat,
	      sc_r_lowat;
	u_char *volatile sc_rbget,
	       *volatile sc_rbput;
 	volatile u_int sc_rbavail;
	u_char *sc_rbuf,
	       *sc_ebuf;

 	u_char *sc_tba;			/* transmit buffer address */
 	u_int sc_tbc,			/* transmit byte count */
	      sc_heldtbc;

	volatile u_char sc_rx_flags,
#define	RX_TTY_BLOCKED		0x01
#define	RX_TTY_OVERFLOWED	0x02
#define	RX_IBUF_BLOCKED		0x04
#define	RX_IBUF_OVERFLOWED	0x08
#define	RX_ANY_BLOCK		0x0f
			sc_tx_busy,	/* working on an output chunk */
			sc_tx_done,	/* done with one output chunk */
			sc_tx_stopped,	/* H/W level stop (lost CTS) */
			sc_st_check,	/* got a status interrupt */
			sc_rx_ready;

	volatile u_char sc_heldchange;
};

/* controller driver configuration */
int scif_match(struct device *, void *, void *);
void scif_attach(struct device *, struct device *, void *);

void	scif_break(struct scif_softc *, int);
void	scif_iflush(struct scif_softc *);

void 	scifsoft(void *);
void scif_rxsoft(struct scif_softc *, struct tty *);
void scif_txsoft(struct scif_softc *, struct tty *);
void scif_stsoft(struct scif_softc *, struct tty *);
void scif_schedrx(struct scif_softc *);
void	scifdiag(void *);

#define	SCIFUNIT_MASK		0x7ffff
#define	SCIFDIALOUT_MASK	0x80000

#define	SCIFUNIT(x)	(minor(x) & SCIFUNIT_MASK)
#define	SCIFDIALOUT(x)	(minor(x) & SCIFDIALOUT_MASK)

/* Hardware flag masks */
#define	SCIF_HW_NOIEN	0x01
#define	SCIF_HW_FIFO	0x02
#define	SCIF_HW_FLOW	0x08
#define	SCIF_HW_DEV_OK	0x20
#define	SCIF_HW_CONSOLE	0x40

/* Buffer size for character buffer */
#define	SCIF_RING_SIZE	2048

/* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */
u_int scif_rbuf_hiwat = (SCIF_RING_SIZE * 1) / 4;
u_int scif_rbuf_lowat = (SCIF_RING_SIZE * 3) / 4;

#define	CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */
int scifconscflag = CONMODE;
int scifisconsole = 0;

#ifdef SCIFCN_SPEED
unsigned int scifcn_speed = SCIFCN_SPEED;
#else
unsigned int scifcn_speed = 9600;
#endif

#define	divrnd(n, q)	(((n)*2/(q)+1)/2)	/* divide and round off */

u_int scif_rbuf_size = SCIF_RING_SIZE;

struct cfattach scif_ca = {
	sizeof(struct scif_softc), scif_match, scif_attach
};

struct cfdriver scif_cd = {
	0, "scif", DV_DULL
};

static int scif_attached;

void InitializeScif(unsigned int);

/*
 * following functions are debugging prupose only
 */
#define	CR      0x0D
#define	USART_ON (unsigned int)~0x08

void scif_putc(unsigned char);
unsigned char scif_getc(void);
int ScifErrCheck(void);

/* XXX: uwe
 * Prepare for bus_spacification.  The difference in access widths is
 * still handled by the magic definitions in scifreg.h
 */
#define scif_smr_read()		SHREG_SCSMR2
#define scif_smr_write(v)	(SHREG_SCSMR2 = (v))

#define scif_brr_read()		SHREG_SCBRR2
#define scif_brr_write(v)	(SHREG_SCBRR2 = (v))

#define scif_scr_read()		SHREG_SCSCR2
#define scif_scr_write(v)	(SHREG_SCSCR2 = (v))

#define scif_ftdr_write(v)	(SHREG_SCFTDR2 = (v))

#define scif_ssr_read()		SHREG_SCSSR2
#define scif_ssr_write(v)	(SHREG_SCSSR2 = (v))

#define scif_frdr_read()	SHREG_SCFRDR2

#define scif_fcr_read()		SHREG_SCFCR2
#define scif_fcr_write(v)	(SHREG_SCFCR2 = (v))

#define scif_fdr_read()		SHREG_SCFDR2

#ifdef SH4 /* additional registers in sh4 */

#define scif_sptr_read()	SHREG_SCSPTR2
#define scif_sptr_write(v)	(SHREG_SCSPTR2 = (v))

#define scif_lsr_read()		SHREG_SCLSR2
#define scif_lsr_write(v)	(SHREG_SCLSR2 = (v))

#endif /* SH4 */

/*
 * InitializeScif
 * : unsigned int bps;
 * : SCIF(Serial Communication Interface)
 */

void
InitializeScif(unsigned int bps)
{
	/* Initialize SCR */
	scif_scr_write(0x00);

#if 0
	scif_fcr_write(SCFCR2_TFRST | SCFCR2_RFRST | SCFCR2_MCE);
#else
	scif_fcr_write(SCFCR2_TFRST | SCFCR2_RFRST);
#endif
	/* Serial Mode Register */
	scif_smr_write(0x00);	/* 8bit,NonParity,Even,1Stop */

	/* Bit Rate Register */
	scif_brr_write(divrnd(sh_clock_get_pclock(), 32 * bps) - 1);

	/*
	 * wait 2m Sec, because Send/Recv must begin 1 bit period after
	 * BRR is set.
	 */
	delay(2000);

#if 0
	scif_fcr_write(FIFO_RCV_TRIGGER_14 | FIFO_XMT_TRIGGER_1 | SCFCR2_MCE);
#else
	scif_fcr_write(FIFO_RCV_TRIGGER_14 | FIFO_XMT_TRIGGER_1);
#endif

	/* Send permission, Receive permission ON */
	scif_scr_write(SCSCR2_TE | SCSCR2_RE);

	/* Serial Status Register */
	scif_ssr_write(scif_ssr_read() & SCSSR2_TDFE); /* Clear Status */
}

/*
 * scif_putc
 *  : unsigned char c;
 */

void
scif_putc(unsigned char c)
{
	/* wait for ready */
	while ((scif_fdr_read() & SCFDR2_TXCNT) == SCFDR2_TXF_FULL)
		continue;

	/* write send data to send register */
	scif_ftdr_write(c);

	/* clear ready flag */
	scif_ssr_write(scif_ssr_read() & ~(SCSSR2_TDFE | SCSSR2_TEND));
}

/*
 * : ScifErrCheck
 *	0x80 = error
 *	0x08 = frame error
 *	0x04 = parity error
 */
int
ScifErrCheck(void)
{
	return (scif_ssr_read() & (SCSSR2_ER | SCSSR2_FER | SCSSR2_PER));
}

/*
 * scif_getc
 */
unsigned char
scif_getc(void)
{
	unsigned char c, err_c;
#ifdef SH4
	unsigned short err_c2 = 0; /* XXXGCC: -Wuninitialized */
#endif

	for (;;) {
		/* wait for ready */
		while ((scif_fdr_read() & SCFDR2_RECVCNT) == 0)
			continue;

		c = scif_frdr_read();
		err_c = scif_ssr_read();
		scif_ssr_write(scif_ssr_read()
			& ~(SCSSR2_ER | SCSSR2_BRK | SCSSR2_RDF | SCSSR2_DR));
#ifdef SH4
		if (CPU_IS_SH4) {
			err_c2 = scif_lsr_read();
			scif_lsr_write(scif_lsr_read() & ~SCLSR2_ORER);
		}
#endif
		if ((err_c & (SCSSR2_ER | SCSSR2_BRK | SCSSR2_FER
		    | SCSSR2_PER)) == 0) {
#ifdef SH4
			if (CPU_IS_SH4 && ((err_c2 & SCLSR2_ORER) == 0))
#endif
			return(c);
		}
	}

}

int
scif_match(struct device *parent, void *vcf, void *aux)
{
	if (scif_attached != 0)
		return 0;

	return 1;
}

void
scif_attach(struct device *parent, struct device *self, void *aux)
{
	struct scif_softc *sc = (struct scif_softc *)self;
	struct tty *tp;

	scif_attached = 1;

	sc->sc_hwflags = 0;	/* XXX */
	sc->sc_swflags = 0;	/* XXX */
	sc->sc_fifolen = 16;

	if (scifisconsole) {
		/* InitializeScif(scifcn_speed); */
		SET(sc->sc_hwflags, SCIF_HW_CONSOLE);
		SET(sc->sc_swflags, TIOCFLAG_SOFTCAR);
		printf("\n%s: console\n", sc->sc_dev.dv_xname);
	} else {
		InitializeScif(9600);
		printf("\n");
	}

	timeout_set(&sc->sc_diag_tmo, scifdiag, sc);
#ifdef SH4
	intc_intr_establish(SH4_INTEVT_SCIF_ERI, IST_LEVEL, IPL_TTY,
	    scifintr, sc, self->dv_xname);
	intc_intr_establish(SH4_INTEVT_SCIF_RXI, IST_LEVEL, IPL_TTY,
	    scifintr, sc, self->dv_xname);
	intc_intr_establish(SH4_INTEVT_SCIF_BRI, IST_LEVEL, IPL_TTY,
	    scifintr, sc, self->dv_xname);
	intc_intr_establish(SH4_INTEVT_SCIF_TXI, IST_LEVEL, IPL_TTY,
	    scifintr, sc, self->dv_xname);
#else
	intc_intr_establish(SH7709_INTEVT2_SCIF_ERI, IST_LEVEL, IPL_TTY,
	    scifintr, sc, self->dv_xname);
	intc_intr_establish(SH7709_INTEVT2_SCIF_RXI, IST_LEVEL, IPL_TTY,
	    scifintr, sc, self->dv_xname);
	intc_intr_establish(SH7709_INTEVT2_SCIF_BRI, IST_LEVEL, IPL_TTY,
	    scifintr, sc, self->dv_xname);
	intc_intr_establish(SH7709_INTEVT2_SCIF_TXI, IST_LEVEL, IPL_TTY,
	    scifintr, sc, self->dv_xname);
#endif

	sc->sc_si = softintr_establish(IPL_SOFTSERIAL, scifsoft, sc);
	SET(sc->sc_hwflags, SCIF_HW_DEV_OK);

	tp = ttymalloc(0);
	tp->t_oproc = scifstart;
	tp->t_param = scifparam;
	tp->t_hwiflow = NULL;

	sc->sc_tty = tp;
	sc->sc_rbuf = malloc(scif_rbuf_size << 1, M_DEVBUF, M_NOWAIT);
	if (sc->sc_rbuf == NULL) {
		printf("%s: unable to allocate ring buffer\n",
		    sc->sc_dev.dv_xname);
		return;
	}
	sc->sc_ebuf = sc->sc_rbuf + (scif_rbuf_size << 1);
}

/*
 * Start or restart transmission.
 */
void
scifstart(struct tty *tp)
{
	struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(tp->t_dev)];
	int s;

	s = spltty();
	if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP))
		goto out;
	if (sc->sc_tx_stopped)
		goto out;

	ttwakeupwr(tp);
	if (tp->t_outq.c_cc == 0)
		goto out;

	/* Grab the first contiguous region of buffer space. */
	{
		u_char *tba;
		int tbc;

		tba = tp->t_outq.c_cf;
		tbc = ndqb(&tp->t_outq, 0);

		sc->sc_tba = tba;
		sc->sc_tbc = tbc;
	}

	SET(tp->t_state, TS_BUSY);
	sc->sc_tx_busy = 1;

	/* Enable transmit completion interrupts if necessary. */
	scif_scr_write(scif_scr_read() | SCSCR2_TIE | SCSCR2_RIE);

	/* Output the first chunk of the contiguous buffer. */
	{
		int n;
		int maxchars;
		int i;

		n = sc->sc_tbc;
		maxchars = sc->sc_fifolen
			- ((scif_fdr_read() & SCFDR2_TXCNT) >> 8);
		if (n > maxchars)
			n = maxchars;

		for (i = 0; i < n; i++) {
			scif_putc(*(sc->sc_tba));
			sc->sc_tba++;
		}
		sc->sc_tbc -= n;
	}
out:
	splx(s);
	return;
}

/*
 * Set SCIF tty parameters from termios.
 * XXX - Should just copy the whole termios after
 * making sure all the changes could be done.
 */
int
scifparam(struct tty *tp, struct termios *t)
{
	struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(tp->t_dev)];
	int ospeed = t->c_ospeed;
	int s;

	/* Check requested parameters. */
	if (ospeed < 0)
		return (EINVAL);
	if (t->c_ispeed && t->c_ispeed != t->c_ospeed)
		return (EINVAL);

	/*
	 * For the console, always force CLOCAL and !HUPCL, so that the port
	 * is always active.
	 */
	if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) ||
	    ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) {
		SET(t->c_cflag, CLOCAL);
		CLR(t->c_cflag, HUPCL);
	}

	/*
	 * If there were no changes, don't do anything.  This avoids dropping
	 * input and improves performance when all we did was frob things like
	 * VMIN and VTIME.
	 */
	if (tp->t_ospeed == t->c_ospeed &&
	    tp->t_cflag == t->c_cflag)
		return (0);

#if 0
/* XXX (msaitoh) */
	lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag);
#endif

	s = spltty();

	/*
	 * Set the flow control pins depending on the current flow control
	 * mode.
	 */
	if (ISSET(t->c_cflag, CRTSCTS)) {
		scif_fcr_write(scif_fcr_read() | SCFCR2_MCE);
	} else {
		scif_fcr_write(scif_fcr_read() & ~SCFCR2_MCE);
	}

	scif_brr_write(divrnd(sh_clock_get_pclock(), 32 * ospeed) -1);

	/*
	 * Set the FIFO threshold based on the receive speed.
	 *
	 *  * If it's a low speed, it's probably a mouse or some other
	 *    interactive device, so set the threshold low.
	 *  * If it's a high speed, trim the trigger level down to prevent
	 *    overflows.
	 *  * Otherwise set it a bit higher.
	 */
#if 0
/* XXX (msaitoh) */
	if (ISSET(sc->sc_hwflags, SCIF_HW_HAYESP))
		sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8;
	else if (ISSET(sc->sc_hwflags, SCIF_HW_FIFO))
		sc->sc_fifo = FIFO_ENABLE |
		    (t->c_ospeed <= 1200 ? FIFO_TRIGGER_1 :
		     t->c_ospeed <= 38400 ? FIFO_TRIGGER_8 : FIFO_TRIGGER_4);
	else
		sc->sc_fifo = 0;
#endif

	/* And copy to tty. */
	tp->t_ispeed = 0;
	tp->t_ospeed = t->c_ospeed;
	tp->t_cflag = t->c_cflag;

	if (!sc->sc_heldchange) {
		if (sc->sc_tx_busy) {
			sc->sc_heldtbc = sc->sc_tbc;
			sc->sc_tbc = 0;
			sc->sc_heldchange = 1;
		}
#if 0
/* XXX (msaitoh) */
		else
			scif_loadchannelregs(sc);
#endif
	}

	if (!ISSET(t->c_cflag, CHWFLOW)) {
		/* Disable the high water mark. */
		sc->sc_r_hiwat = 0;
		sc->sc_r_lowat = 0;
		if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) {
			CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED);
			scif_schedrx(sc);
		}
	} else {
		sc->sc_r_hiwat = scif_rbuf_hiwat;
		sc->sc_r_lowat = scif_rbuf_lowat;
	}

	splx(s);

#ifdef SCIF_DEBUG
	if (scif_debug)
		scifstatus(sc, "scifparam ");
#endif

	if (!ISSET(t->c_cflag, CHWFLOW)) {
		if (sc->sc_tx_stopped) {
			sc->sc_tx_stopped = 0;
			scifstart(tp);
		}
	}

	return (0);
}

void
scif_iflush(struct scif_softc *sc)
{
	int i;
	unsigned char c;

	i = scif_fdr_read() & SCFDR2_RECVCNT;

	while (i > 0) {
		c = scif_frdr_read();
		scif_ssr_write(scif_ssr_read() & ~(SCSSR2_RDF | SCSSR2_DR));
		i--;
	}
}

int
scifopen(dev_t dev, int flag, int mode, struct proc *p)
{
	int unit = SCIFUNIT(dev);
	struct scif_softc *sc;
	struct tty *tp;
	int s;
	int error;

	if (unit >= scif_cd.cd_ndevs)
		return (ENXIO);
	sc = scif_cd.cd_devs[unit];
	if (sc == 0 || !ISSET(sc->sc_hwflags, SCIF_HW_DEV_OK) ||
	    sc->sc_rbuf == NULL)
		return (ENXIO);

	tp = sc->sc_tty;

	if (ISSET(tp->t_state, TS_ISOPEN) &&
	    ISSET(tp->t_state, TS_XCLUDE) &&
	    suser(p, 0) != 0)
		return (EBUSY);

	s = spltty();

	/*
	 * Do the following iff this is a first open.
	 */
	if (!ISSET(tp->t_state, TS_ISOPEN)) {
		struct termios t;

		tp->t_dev = dev;

		/* Turn on interrupts. */
		scif_scr_write(scif_scr_read() | SCSCR2_TIE | SCSCR2_RIE);

		/*
		 * Initialize the termios status to the defaults.  Add in the
		 * sticky bits from TIOCSFLAGS.
		 */
		t.c_ispeed = 0;
		if (ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) {
			t.c_ospeed = scifcn_speed;	/* XXX (msaitoh) */
			t.c_cflag = scifconscflag;
		} else {
			t.c_ospeed = TTYDEF_SPEED;
			t.c_cflag = TTYDEF_CFLAG;
		}
		if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL))
			SET(t.c_cflag, CLOCAL);
		if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS))
			SET(t.c_cflag, CRTSCTS);
		if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF))
			SET(t.c_cflag, MDMBUF);
		/* Make sure scifparam() will do something. */
		tp->t_ospeed = 0;
		(void) scifparam(tp, &t);

		/*
		 * XXX landisk has no hardware flow control!
		 * When porting to another platform, fix this somehow
		 */
		SET(tp->t_state, TS_CARR_ON);

		tp->t_iflag = TTYDEF_IFLAG;
		tp->t_oflag = TTYDEF_OFLAG;
		tp->t_lflag = TTYDEF_LFLAG;
		ttychars(tp);
		ttsetwater(tp);

		/* Clear the input ring, and unblock. */
		sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf;
		sc->sc_rbavail = scif_rbuf_size;
		scif_iflush(sc);
		CLR(sc->sc_rx_flags, RX_ANY_BLOCK);
#if 0
/* XXX (msaitoh) */
		scif_hwiflow(sc);
#endif

#ifdef SCIF_DEBUG
		if (scif_debug)
			scifstatus(sc, "scifopen  ");
#endif

	}

	splx(s);

	error = ttyopen(dev, tp, p);
	if (error)
		goto bad;

	error = (*linesw[tp->t_line].l_open)(dev, tp, p);
	if (error)
		goto bad;

	return (0);

bad:

	return (error);
}

int
scifclose(dev_t dev, int flag, int mode, struct proc *p)
{
	struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)];
	struct tty *tp = sc->sc_tty;

	/* XXX This is for cons.c. */
	if (!ISSET(tp->t_state, TS_ISOPEN))
		return (0);

	(*linesw[tp->t_line].l_close)(tp, flag, p);
	ttyclose(tp);

	return (0);
}

int
scifread(dev_t dev, struct uio *uio, int flag)
{
	struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)];
	struct tty *tp = sc->sc_tty;

	return ((*linesw[tp->t_line].l_read)(tp, uio, flag));
}

int
scifwrite(dev_t dev, struct uio *uio, int flag)
{
	struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)];
	struct tty *tp = sc->sc_tty;

	return ((*linesw[tp->t_line].l_write)(tp, uio, flag));
}

#if 0
int
scifpoll(dev_t dev, int events, struct proc *p)
{
	struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)];
	struct tty *tp = sc->sc_tty;

	return ((*linesw[tp->t_line].l_poll)(tp, events, p));
}
#endif

struct tty *
sciftty(dev_t dev)
{
	struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)];
	struct tty *tp = sc->sc_tty;

	return (tp);
}

int
scifioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p)
{
	struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)];
	struct tty *tp = sc->sc_tty;
	int error;
	int s;

	error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p);
	if (error != -1)
		return (error);

	error = ttioctl(tp, cmd, data, flag, p);
	if (error != -1)
		return (error);

	error = 0;

	s = spltty();

	switch (cmd) {
	case TIOCSBRK:
		scif_break(sc, 1);
		break;

	case TIOCCBRK:
		scif_break(sc, 0);
		break;

	case TIOCGFLAGS:
		*(int *)data = sc->sc_swflags;
		break;

	case TIOCSFLAGS:
		error = suser(p, 0);
		if (error)
			break;
		sc->sc_swflags = *(int *)data;
		break;

	default:
		error = -1;
		break;
	}

	splx(s);

	return (error);
}

void
scif_schedrx(struct scif_softc *sc)
{
	sc->sc_rx_ready = 1;

	/* Wake up the poller. */
	softintr_schedule(sc->sc_si);
}

void
scif_break(struct scif_softc *sc, int onoff)
{
	if (onoff)
		scif_ssr_write(scif_ssr_read() & ~SCSSR2_TDFE);
	else
		scif_ssr_write(scif_ssr_read() | SCSSR2_TDFE);

#if 0	/* XXX */
	if (!sc->sc_heldchange) {
		if (sc->sc_tx_busy) {
			sc->sc_heldtbc = sc->sc_tbc;
			sc->sc_tbc = 0;
			sc->sc_heldchange = 1;
		} else
			scif_loadchannelregs(sc);
	}
#endif
}

/*
 * Stop output, e.g., for ^S or output flush.
 */
int
scifstop(struct tty *tp, int flag)
{
	struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(tp->t_dev)];
	int s;

	s = spltty();
	if (ISSET(tp->t_state, TS_BUSY)) {
		/* Stop transmitting at the next chunk. */
		sc->sc_tbc = 0;
		sc->sc_heldtbc = 0;
		if (!ISSET(tp->t_state, TS_TTSTOP))
			SET(tp->t_state, TS_FLUSH);
	}
	splx(s);
	return (0);
}

void
scif_intr_init()
{
	/* XXX */
}

void
scifdiag(void *arg)
{
	struct scif_softc *sc = arg;
	int overflows, floods;
	int s;

	s = spltty();
	overflows = sc->sc_overflows;
	sc->sc_overflows = 0;
	floods = sc->sc_floods;
	sc->sc_floods = 0;
	sc->sc_errors = 0;
	splx(s);

	log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n",
	    sc->sc_dev.dv_xname,
	    overflows, overflows == 1 ? "" : "s",
	    floods, floods == 1 ? "" : "s");
}

void
scif_rxsoft(struct scif_softc *sc, struct tty *tp)
{
	int (*rint)(int, struct tty *) = *linesw[tp->t_line].l_rint;
	u_char *get, *end;
	u_int cc, scc;
	u_char ssr2;
	int code;
	int s;

	end = sc->sc_ebuf;
	get = sc->sc_rbget;
	scc = cc = scif_rbuf_size - sc->sc_rbavail;

	if (cc == scif_rbuf_size) {
		sc->sc_floods++;
		if (sc->sc_errors++ == 0)
			timeout_add_sec(&sc->sc_diag_tmo, 60);
	}

	while (cc) {
		code = get[0];
		ssr2 = get[1];
		if (ISSET(ssr2, SCSSR2_BRK | SCSSR2_FER | SCSSR2_PER)) {
			if (ISSET(ssr2, SCSSR2_BRK | SCSSR2_FER))
				SET(code, TTY_FE);
			if (ISSET(ssr2, SCSSR2_PER))
				SET(code, TTY_PE);
		}
		if ((*rint)(code, tp) == -1) {
			/*
			 * The line discipline's buffer is out of space.
			 */
			if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) {
				/*
				 * We're either not using flow control, or the
				 * line discipline didn't tell us to block for
				 * some reason.  Either way, we have no way to
				 * know when there's more space available, so
				 * just drop the rest of the data.
				 */
				get += cc << 1;
				if (get >= end)
					get -= scif_rbuf_size << 1;
				cc = 0;
			} else {
				/*
				 * Don't schedule any more receive processing
				 * until the line discipline tells us there's
				 * space available (through scifhwiflow()).
				 * Leave the rest of the data in the input
				 * buffer.
				 */
				SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED);
			}
			break;
		}
		get += 2;
		if (get >= end)
			get = sc->sc_rbuf;
		cc--;
	}

	if (cc != scc) {
		sc->sc_rbget = get;
		s = spltty();
		cc = sc->sc_rbavail += scc - cc;
		/* Buffers should be ok again, release possible block. */
		if (cc >= sc->sc_r_lowat) {
			if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) {
				CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED);
				scif_scr_write(scif_scr_read() | SCSCR2_RIE);
			}
#if 0
			if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) {
				CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED);
				scif_hwiflow(sc);
			}
#endif
		}
		splx(s);
	}
}

void
scif_txsoft(struct scif_softc *sc, struct tty *tp)
{
	CLR(tp->t_state, TS_BUSY);
	if (ISSET(tp->t_state, TS_FLUSH))
		CLR(tp->t_state, TS_FLUSH);
	else
		ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf));
	(*linesw[tp->t_line].l_start)(tp);
}

void
scif_stsoft(struct scif_softc *sc, struct tty *tp)
{
#if 0
/* XXX (msaitoh) */
	u_char msr, delta;
	int s;

	s = spltty();
	msr = sc->sc_msr;
	delta = sc->sc_msr_delta;
	sc->sc_msr_delta = 0;
	splx(s);

	if (ISSET(delta, sc->sc_msr_dcd)) {
		/*
		 * Inform the tty layer that carrier detect changed.
		 */
		(void) (*linesw[tp->t_line].l_modem)(tp, ISSET(msr, MSR_DCD));
	}

	if (ISSET(delta, sc->sc_msr_cts)) {
		/* Block or unblock output according to flow control. */
		if (ISSET(msr, sc->sc_msr_cts)) {
			sc->sc_tx_stopped = 0;
			(*linesw[tp->t_line].l_start)(tp);
		} else {
			sc->sc_tx_stopped = 1;
		}
	}

#ifdef SCIF_DEBUG
	if (scif_debug)
		scifstatus(sc, "scif_stsoft");
#endif
#endif
}

void
scifsoft(void *arg)
{
	struct scif_softc *sc = arg;
	struct tty *tp;

	tp = sc->sc_tty;

	if (sc->sc_rx_ready) {
		sc->sc_rx_ready = 0;
		scif_rxsoft(sc, tp);
	}

#if 0
	if (sc->sc_st_check) {
		sc->sc_st_check = 0;
		scif_stsoft(sc, tp);
	}
#endif

	if (sc->sc_tx_done) {
		sc->sc_tx_done = 0;
		scif_txsoft(sc, tp);
	}
}

int
scifintr(void *arg)
{
	struct scif_softc *sc = arg;
	u_char *put, *end;
	u_int cc;
	u_short ssr2;
	int count;

	end = sc->sc_ebuf;
	put = sc->sc_rbput;
	cc = sc->sc_rbavail;

	do {
		ssr2 = scif_ssr_read();
		if (ISSET(ssr2, SCSSR2_BRK)) {
			scif_ssr_write(scif_ssr_read()
				& ~(SCSSR2_ER | SCSSR2_BRK | SCSSR2_DR));
#ifdef DDB
			if (ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE) &&
			    db_console != 0) {
				Debugger();
			}
#endif /* DDB */
		}
		count = scif_fdr_read() & SCFDR2_RECVCNT;
		if (count != 0) {
			for (;;) {
				u_char c = scif_frdr_read();
				u_char err = (u_char)(scif_ssr_read() & 0x00ff);

				scif_ssr_write(scif_ssr_read()
				    & ~(SCSSR2_ER | SCSSR2_RDF | SCSSR2_DR));
#ifdef SH4
				if (CPU_IS_SH4)
					scif_lsr_write(scif_lsr_read()
						       & ~SCLSR2_ORER);
#endif
				if ((cc > 0) && (count > 0)) {
					put[0] = c;
					put[1] = err;
					put += 2;
					if (put >= end)
						put = sc->sc_rbuf;
					cc--;
					count--;
				} else
					break;
			}

			/*
			 * Current string of incoming characters ended because
			 * no more data was available or we ran out of space.
			 * Schedule a receive event if any data was received.
			 * If we're out of space, turn off receive interrupts.
			 */
			sc->sc_rbput = put;
			sc->sc_rbavail = cc;
			if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED))
				sc->sc_rx_ready = 1;

			/*
			 * See if we are in danger of overflowing a buffer. If
			 * so, use hardware flow control to ease the pressure.
			 */
			if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) &&
			    cc < sc->sc_r_hiwat) {
				SET(sc->sc_rx_flags, RX_IBUF_BLOCKED);
#if 0
				scif_hwiflow(sc);
#endif
			}

			/*
			 * If we're out of space, disable receive interrupts
			 * until the queue has drained a bit.
			 */
			if (!cc) {
				SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED);
				scif_scr_write(scif_scr_read() & ~SCSCR2_RIE);
			}
		} else {
			if (scif_ssr_read() & (SCSSR2_RDF | SCSSR2_DR)) {
				scif_scr_write(scif_scr_read()
					       & ~(SCSCR2_TIE | SCSCR2_RIE));
				delay(10);
				scif_scr_write(scif_scr_read()
					       | SCSCR2_TIE | SCSCR2_RIE);
				continue;
			}
		}
	} while (scif_ssr_read() & (SCSSR2_RDF | SCSSR2_DR));

#if 0
	msr = bus_space_read_1(iot, ioh, scif_msr);
	delta = msr ^ sc->sc_msr;
	sc->sc_msr = msr;
	if (ISSET(delta, sc->sc_msr_mask)) {
		SET(sc->sc_msr_delta, delta);

		/*
		 * Pulse-per-second clock signal on edge of DCD?
		 */
		if (ISSET(delta, sc->sc_ppsmask)) {
			struct timeval tv;
			if (ISSET(msr, sc->sc_ppsmask) ==
			    sc->sc_ppsassert) {
				/* XXX nanotime() */
				microtime(&tv);
				TIMEVAL_TO_TIMESPEC(&tv,
						    &sc->ppsinfo.assert_timestamp);
				if (sc->ppsparam.mode & PPS_OFFSETASSERT) {
					timespecadd(&sc->ppsinfo.assert_timestamp,
						    &sc->ppsparam.assert_offset,
						    &sc->ppsinfo.assert_timestamp);
					TIMESPEC_TO_TIMEVAL(&tv, &sc->ppsinfo.assert_timestamp);
				}

#ifdef PPS_SYNC
				if (sc->ppsparam.mode & PPS_HARDPPSONASSERT)
					hardpps(&tv, tv.tv_usec);
#endif
				sc->ppsinfo.assert_sequence++;
				sc->ppsinfo.current_mode =
					sc->ppsparam.mode;

			} else if (ISSET(msr, sc->sc_ppsmask) ==
				   sc->sc_ppsclear) {
				/* XXX nanotime() */
				microtime(&tv);
				TIMEVAL_TO_TIMESPEC(&tv,
						    &sc->ppsinfo.clear_timestamp);
				if (sc->ppsparam.mode & PPS_OFFSETCLEAR) {
					timespecadd(&sc->ppsinfo.clear_timestamp,
						    &sc->ppsparam.clear_offset,
						    &sc->ppsinfo.clear_timestamp);
					TIMESPEC_TO_TIMEVAL(&tv, &sc->ppsinfo.clear_timestamp);
				}

#ifdef PPS_SYNC
				if (sc->ppsparam.mode & PPS_HARDPPSONCLEAR)
					hardpps(&tv, tv.tv_usec);
#endif
				sc->ppsinfo.clear_sequence++;
				sc->ppsinfo.current_mode =
					sc->ppsparam.mode;
			}
		}

		/*
		 * Stop output immediately if we lose the output
		 * flow control signal or carrier detect.
		 */
		if (ISSET(~msr, sc->sc_msr_mask)) {
			sc->sc_tbc = 0;
			sc->sc_heldtbc = 0;
#ifdef SCIF_DEBUG
			if (scif_debug)
				scifstatus(sc, "scifintr  ");
#endif
		}

		sc->sc_st_check = 1;
	}
#endif

	/*
	 * Done handling any receive interrupts. See if data can be
	 * transmitted as well. Schedule tx done event if no data left
	 * and tty was marked busy.
	 */
	if (((scif_fdr_read() & SCFDR2_TXCNT) >> 8) != 16) { /* XXX (msaitoh) */
		/*
		 * If we've delayed a parameter change, do it now, and restart
		 * output.
		 */
		if (sc->sc_heldchange) {
			sc->sc_heldchange = 0;
			sc->sc_tbc = sc->sc_heldtbc;
			sc->sc_heldtbc = 0;
		}

		/* Output the next chunk of the contiguous buffer, if any. */
		if (sc->sc_tbc > 0) {
			int n;
			int maxchars;
			int i;

			n = sc->sc_tbc;
			maxchars = sc->sc_fifolen -
				((scif_fdr_read() & SCFDR2_TXCNT) >> 8);
			if (n > maxchars)
				n = maxchars;

			for (i = 0; i < n; i++) {
				scif_putc(*(sc->sc_tba));
				sc->sc_tba++;
			}
			sc->sc_tbc -= n;
		} else {
			/* Disable transmit completion interrupts if necessary. */
#if 0
			if (ISSET(sc->sc_ier, IER_ETXRDY))
#endif
				scif_scr_write(scif_scr_read() & ~SCSCR2_TIE);

			if (sc->sc_tx_busy) {
				sc->sc_tx_busy = 0;
				sc->sc_tx_done = 1;
			}
		}
	}

	/* Wake up the poller. */
	softintr_schedule(sc->sc_si);

	return (1);
}

void
scifcnprobe(struct consdev *cp)
{
	int maj;

	/* locate the major number */
	for (maj = 0; maj < nchrdev; maj++)
		if (cdevsw[maj].d_open == scifopen)
			break;

	cp->cn_dev = makedev(maj, 0);
#ifdef SCIFCONSOLE
	cp->cn_pri = CN_HIGHPRI;
#else
	cp->cn_pri = CN_LOWPRI;
#endif
}

void
scifcninit(struct consdev *cp)
{
	InitializeScif(scifcn_speed);
	scifisconsole = 1;
}

int
scifcngetc(dev_t dev)
{
	int c;
	int s;

	s = spltty();
	c = scif_getc();
	splx(s);

	return (c);
}

void
scifcnputc(dev_t dev, int c)
{
	int s;

	s = spltty();
	scif_putc((u_char)c);
	splx(s);
}


code:
/*	$OpenBSD: scifreg.h,v 1.1.1.1 2006/10/06 21:02:55 miod Exp $	*/
/* $NetBSD: scifreg.h,v 1.10 2006/02/18 00:41:32 uwe Exp $ */

/*-
 * Copyright (C) 1999 SAITOH Masanobu.  All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/*
 * Serial Communication Interface with FIFO (SCIF)
 */

#define SH3_SCIF0_BASE	0xa4000150
#define SH3_SCIF1_BASE	0xa4000140

#define SH4_SCIF_BASE	0xffe80000

#ifdef SH3

/* SH3 definitions */

#define	SCIF_SMR		0x0	/* serial mode */
#define	SCIF_BRR		0x2	/* bit rate */
#define	SCIF_SCR		0x4	/* serial control */
#define	SCIF_FTDR		0x6	/* transmit fifo data */
#define	SCIF_SSR		0x8	/* serial status */
#define	SCIF_FRDR		0xa	/* receive fifo data */
#define	SCIF_FCR		0xc	/* fifo control */
#define	SCIF_FDR		0xe	/* fifo data count set */

#define	SHREG_SCSMR2  (*(volatile uint8_t  *)(SH3_SCIF0_BASE + SCIF_SMR))
#define	SHREG_SCBRR2  (*(volatile uint8_t  *)(SH3_SCIF0_BASE + SCIF_BRR))
#define	SHREG_SCSCR2  (*(volatile uint8_t  *)(SH3_SCIF0_BASE + SCIF_SCR))
#define	SHREG_SCFTDR2 (*(volatile uint8_t  *)(SH3_SCIF0_BASE + SCIF_FTDR))
#define	SHREG_SCSSR2  (*(volatile uint16_t *)(SH3_SCIF0_BASE + SCIF_SSR))
#define	SHREG_SCFRDR2 (*(volatile uint8_t  *)(SH3_SCIF0_BASE + SCIF_FRDR))
#define	SHREG_SCFCR2  (*(volatile uint8_t  *)(SH3_SCIF0_BASE + SCIF_FCR))
#define	SHREG_SCFDR2  (*(volatile uint16_t *)(SH3_SCIF0_BASE + SCIF_FDR))

#else  /* !SH3 */

/* SH4 definitions */

#define	SCIF_SMR		0x00	/* serial mode */
#define	SCIF_BRR		0x04	/* bit rate */
#define	SCIF_SCR		0x08	/* serial control */
#define	SCIF_FTDR		0x0c	/* transmit fifo data */
#define	SCIF_SSR		0x10	/* serial status */
#define	SCIF_FRDR		0x14	/* receive fifo data */
#define	SCIF_FCR		0x18	/* fifo control */
#define	SCIF_FDR		0x1c	/* fifo data count set */

#define SCIF_SPTR		0x20	/* seial port */
#define SCIF_LSR		0x24	/* line status */

#define	SHREG_SCSMR2  (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_SMR))
#define	SHREG_SCBRR2  (*(volatile uint8_t  *)(SH4_SCIF_BASE + SCIF_BRR))
#define	SHREG_SCSCR2  (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_SCR))
#define	SHREG_SCFTDR2 (*(volatile uint8_t  *)(SH4_SCIF_BASE + SCIF_FTDR))
#define	SHREG_SCSSR2  (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_SSR))
#define	SHREG_SCFRDR2 (*(volatile uint8_t  *)(SH4_SCIF_BASE + SCIF_FRDR))
#define	SHREG_SCFCR2  (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_FCR))
#define	SHREG_SCFDR2  (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_FDR))

#define	SHREG_SCSPTR2 (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_SPTR))
#define	SHREG_SCLSR2  (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_LSR))

/* alias */
#define	SHREG_SCSFDR2	SHREG_SCFTDR2
#define	SHREG_SCFSR2	SHREG_SCSSR2

#define	SCSPTR2_RTSIO		0x0080
#define	SCSPTR2_RTSDT		0x0040
#define	SCSPTR2_CTSIO		0x0020
#define	SCSPTR2_CTSDT		0x0010
#define	SCSPTR2_SCKIO		0x0008
#define	SCSPTR2_SCKDT		0x0004
#define	SCSPTR2_SPB2IO		0x0002
#define	SCSPTR2_SPB2DT		0x0001

#define SCLSR2_ORER		0x0001	/* overrun error */

#endif /* !SH3 */

/* SMR: serial mode */
#define SCSMR2_CHR		0x40	/* character width (set = 7bit) */
#define SCSMR2_PE		0x20	/* Parity Enable */
#define SCSMR2_O		0x10	/* parity mode Odd */
#define SCSMR2_STOP		0x08	/* STOP bit (set = 2 stop bits) */
#define	SCSMR2_CKS1		0x02	/* ClocK Select 1 */
#define	SCSMR2_CKS0		0x01	/* ClocK Select 0 */

/* SMR: serial mode (for IrDA) */
#define SCSMR2_IRMOD		0x80	/* IrDA mode */
#define SCSMR2_ICK3		0x40
#define SCSMR2_ICK2		0x20
#define SCSMR2_ICK1		0x10
#define SCSMR2_ICK0		0x08
#define SCSMR2_PSEL		0x04	/* Pulse width SELelect */

/* SCR: serial control */
#define	SCSCR2_TIE		0x80	/* Transmit Interrupt Enable */
#define	SCSCR2_RIE		0x40	/* Recieve Interrupt Enable */
#define	SCSCR2_TE		0x20	/* Transmit Enable */
#define	SCSCR2_RE		0x10	/* Receive Enable */
#define	SCSCR2_CKE1		0x02	/* ClocK Enable 1 */
#define	SCSCR2_CKE0		0x01	/* ClocK Enable 0 (not in sh4) */

/* SSR: serial status */
#define	SCSSR2_ER		0x0080	/* ERror */
#define	SCSSR2_TEND		0x0040	/* Transmit END */
#define	SCSSR2_TDFE		0x0020	/* Transmit Data Fifo Empty */
#define	SCSSR2_BRK		0x0010	/* BReaK detection */
#define	SCSSR2_FER		0x0008	/* Framing ERror */
#define	SCSSR2_PER		0x0004	/* Parity ERror */
#define	SCSSR2_RDF		0x0002	/* Recieve fifo Data Full */
#define	SCSSR2_DR		0x0001	/* Data Ready */

/* FCR: fifo control */
#define	SCFCR2_RTRG1		0x80	/* Receive TRiGger 1 */
#define	SCFCR2_RTRG0		0x40	/* Receive TRiGger 0 */
#define	SCFCR2_TTRG1		0x20	/* Transmit TRiGger 1 */
#define	SCFCR2_TTRG0		0x10	/* Transmit TRiGger 0 */
#define	SCFCR2_MCE		0x08	/* Modem Control Enable */
#define	SCFCR2_TFRST		0x04	/* Transmit Fifo register ReSeT */
#define	SCFCR2_RFRST		0x02	/* Receive Fifo register ReSeT */
#define	SCFCR2_LOOP		0x01	/* LOOP back test */

#define	FIFO_RCV_TRIGGER_1	0x00
#define	FIFO_RCV_TRIGGER_4	0x40
#define	FIFO_RCV_TRIGGER_8	0x80
#define	FIFO_RCV_TRIGGER_14	0xc0

#define	FIFO_XMT_TRIGGER_8	0x00
#define	FIFO_XMT_TRIGGER_4	0x10
#define	FIFO_XMT_TRIGGER_2	0x20
#define	FIFO_XMT_TRIGGER_1	0x30

/* FDR: fifo data count set */
#define	SCFDR2_TXCNT		0xff00	/* Tx CouNT */
#define	SCFDR2_RECVCNT		0x00ff	/* Rx CouNT */
#define	SCFDR2_TXF_FULL		0x1000	/* Tx FULL */
#define	SCFDR2_RXF_EPTY		0x0000	/* Rx EMPTY */


code:
/*	$OpenBSD: scireg.h,v 1.1.1.1 2006/10/06 21:02:55 miod Exp $	*/
/* $NetBSD: scireg.h,v 1.8 2003/07/01 11:49:37 uwe Exp $ */

/*-
 * Copyright (C) 1999 SAITOH Masanobu.  All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/*
 * Serial Communication Interface (SCI)
 */

#if !defined(SH4)

/* SH3 definitions */

#define	SHREG_SCSMR	(*(volatile unsigned char *)	0xFFFFFE80)
#define	SHREG_SCBRR	(*(volatile unsigned char *)	0xFFFFFE82)
#define	SHREG_SCSCR	(*(volatile unsigned char *)	0xFFFFFE84)
#define	SHREG_SCTDR	(*(volatile unsigned char *)	0xFFFFFE86)
#define	SHREG_SCSSR	(*(volatile unsigned char *)	0xFFFFFE88)
#define	SHREG_SCRDR	(*(volatile unsigned char *)	0xFFFFFE8A)
#define	SHREG_SCSPDR	(*(volatile unsigned char *)	0xf4000136)

#else

/* SH4 definitions */

#define	SHREG_SCSMR	(*(volatile unsigned char *)	0xffe00000)
#define	SHREG_SCBRR	(*(volatile unsigned char *)	0xffe00004)
#define	SHREG_SCSCR	(*(volatile unsigned char *)	0xffe00008)
#define	SHREG_SCTDR	(*(volatile unsigned char *)	0xffe0000c)
#define	SHREG_SCSSR	(*(volatile unsigned char *)	0xffe00010)
#define	SHREG_SCRDR	(*(volatile unsigned char *)	0xffe00014)
#define	SHREG_SCSPTR	(*(volatile unsigned char *)	0xffe0001c)

#endif

#define	SCSCR_TIE	0x80	/* Transmit Interrupt Enable */
#define	SCSCR_RIE	0x40	/* Receive Interrupt Enable */
#define	SCSCR_TE	0x20	/* Transmit Enable */
#define	SCSCR_RE	0x10	/* Receive Enable */
#define	SCSCR_MPIE	0x08	/* Multi Processor Interrupt Enable */
#define	SCSCR_TEIE	0x04	/* Transmit End Interrupt Enable */
#define	SCSCR_CKE1	0x02	/* ClocK Enable 1 */
#define	SCSCR_CKE0	0x01	/* ClocK Enable 0 */

#define	SCSSR_TDRE	0x80
#define	SCSSR_RDRF	0x40
#define	SCSSR_ORER	0x20
#define	SCSSR_FER	0x10
#define	SCSSR_PER	0x08

#define	SCSPTR_SPB1IO	0x08
#define	SCSPTR_SPB1DT	0x04
#define	SCSPTR_SPB0IO	0x02
#define	SCSPTR_SPB0DT	0x01

#if defined(SH3)
#define	SCSPDR_SCP0DT	0x01
#endif


code:
/*	$OpenBSD: shb.c,v 1.2 2008/06/26 05:42:12 ray Exp $	*/
/*	$NetBSD: shb.c,v 1.10 2005/12/11 12:18:58 christos Exp $	*/

/*-
 * Copyright (c) 2002 The NetBSD Foundation, Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>

#include <machine/autoconf.h>

int shb_match(struct device *, void *, void *);
void shb_attach(struct device *, struct device *, void *);
int shb_print(void *, const char *);
int shb_search(struct device *, void *, void *);

struct cfattach shb_ca = {
	sizeof(struct device), shb_match, shb_attach
};

struct cfdriver shb_cd = {
	0, "shb", DV_DULL
};

int
shb_match(struct device *parent, void *vcf, void *aux)
{
	extern struct cfdriver shb_cd;
	struct mainbus_attach_args *ma = aux;

	if (strcmp(ma->ma_name, shb_cd.cd_name) != 0)
		return (0);

	return (1);
}

void
shb_attach(struct device *parent, struct device *self, void *aux)
{
	printf("\n");

	config_search(shb_search, self, aux);
}

int
shb_search(struct device *parent, void *vcf, void *aux)
{
	struct cfdata *cf = vcf;

	if ((*cf->cf_attach->ca_match)(parent, cf, NULL) == 0)
		return (0);
	config_attach(parent, cf, NULL, shb_print);
	return (1);
}

int
shb_print(void *aux, const char *pnp)
{
	return (UNCONF);
}