code:
/*	$OpenBSD: shpcic.c,v 1.12 2010/12/04 17:06:32 miod Exp $	*/
/*	$NetBSD: shpcic.c,v 1.10 2005/12/24 20:07:32 perry Exp $	*/

/*
 * Copyright (c) 2005 NONAKA Kimihiro
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/device.h>
#include <sys/extent.h>
#include <sys/malloc.h>

#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
#include <dev/pci/pcidevs.h>

#include <sh/bscreg.h>
#include <sh/cache.h>
#include <sh/trap.h>
#include <sh/dev/pcicreg.h>

#include <machine/autoconf.h>
#include <machine/bus.h>
#include <machine/intr.h>

#if defined(SHPCIC_DEBUG)
int shpcic_debug = 0;
#define	DPRINTF(arg)	if (shpcic_debug) printf arg
#else
#define	DPRINTF(arg)
#endif

#define	PCI_MODE1_ENABLE	0x80000000UL

static const struct shpcic_product {
	uint32_t	sp_product;
	const char	*sp_name;
} shpcic_products[] = {
	{ PCI_PRODUCT_HITACHI_SH7751,	"SH7751" },
	{ PCI_PRODUCT_HITACHI_SH7751R,	"SH7751R" },

	{ 0, NULL },
};

int	shpcic_match(struct device *, void *, void *);
void	shpcic_attach(struct device *, struct device *, void *);

struct cfattach shpcic_ca = {
	sizeof(struct shpcic_softc), shpcic_match, shpcic_attach
};

struct cfdriver shpcic_cd = {
	0, "shpcic", DV_DULL
};

/* There can be only one. */
int shpcic_found = 0;

static const struct shpcic_product *shpcic_lookup(void);

static const struct shpcic_product *
shpcic_lookup(void)
{
	const struct shpcic_product *spp;
	pcireg_t id;

	id = _reg_read_4(SH4_PCICONF0);
	switch (PCI_VENDOR(id)) {
	case PCI_VENDOR_HITACHI:
		break;

	default:
		return (NULL);
	}

	for (spp = shpcic_products; spp->sp_name != NULL; spp++) {
		if (PCI_PRODUCT(id) == spp->sp_product) {
			return (spp);
		}
	}
	return (NULL);
}

int
shpcic_match(struct device *parent, void *vcf, void *aux)
{
	struct mainbus_attach_args *ma = aux;

	if (strcmp(ma->ma_name, shpcic_cd.cd_name) != 0)
		return (0);

	if (!CPU_IS_SH4)
		return (0);

	switch (cpu_product) {
	default:
		return (0);

	case CPU_PRODUCT_7751:
	case CPU_PRODUCT_7751R:
		break;
	}

	if (shpcic_found)
		return (0);

	if (shpcic_lookup() == NULL)
		return (0);

	if (_reg_read_2(SH4_BCR2) & BCR2_PORTEN)
		return (0);

	return (1);
}

void
shpcic_attach(struct device *parent, struct device *self, void *aux)
{
	const struct shpcic_product *spp;
	struct shpcic_softc *sc = (struct shpcic_softc *)self;
	struct pcibus_attach_args pba;
	struct extent *io_ex;
	struct extent *mem_ex;

	shpcic_found = 1;

	spp = shpcic_lookup();
	if (spp == NULL) {
		printf("\n");
		panic("shpcic_attach: impossible");
	}

	if (_reg_read_2(SH4_BCR2) & BCR2_PORTEN) {
		printf("\n");
		panic("shpcic_attach: port enabled");
	}

	printf(": HITACHI %s\n", spp->sp_name);

	/* allow PCIC request */
	_reg_write_4(SH4_BCR1, _reg_read_4(SH4_BCR1) | BCR1_BREQEN);

	/* Initialize PCIC */
	_reg_write_4(SH4_PCICR, PCICR_BASE | PCICR_RSTCTL);
	delay(10 * 1000);
	_reg_write_4(SH4_PCICR, PCICR_BASE);

	/* Class: Host-Bridge */
	_reg_write_4(SH4_PCICONF2,
	    (PCI_CLASS_BRIDGE << PCI_CLASS_SHIFT) |
	    (PCI_SUBCLASS_BRIDGE_HOST << PCI_SUBCLASS_SHIFT));

#if !defined(DONT_INIT_PCIBSC)
#if defined(PCIBCR_BCR1_VAL)
	_reg_write_4(SH4_PCIBCR1, PCIBCR_BCR1_VAL);
#else
	_reg_write_4(SH4_PCIBCR1, _reg_read_4(SH4_BCR1) | BCR1_MASTER);
#endif
#if defined(PCIBCR_BCR2_VAL)
	_reg_write_4(SH4_PCIBCR2, PCIBCR_BCR2_VAL);
#else
	_reg_write_4(SH4_PCIBCR2, _reg_read_2(SH4_BCR2));
#endif
#if defined(SH4) && defined(SH7751R)
	if (cpu_product == CPU_PRODUCT_7751R) {
#if defined(PCIBCR_BCR3_VAL)
		_reg_write_4(SH4_PCIBCR3, PCIBCR_BCR3_VAL);
#else
		_reg_write_4(SH4_PCIBCR3, _reg_read_2(SH4_BCR3));
#endif
	}
#endif	/* SH4 && SH7751R && PCIBCR_BCR3_VAL */
#if defined(PCIBCR_WCR1_VAL)
	_reg_write_4(SH4_PCIWCR1, PCIBCR_WCR1_VAL);
#else
	_reg_write_4(SH4_PCIWCR1, _reg_read_4(SH4_WCR1));
#endif
#if defined(PCIBCR_WCR2_VAL)
	_reg_write_4(SH4_PCIWCR2, PCIBCR_WCR2_VAL);
#else
	_reg_write_4(SH4_PCIWCR2, _reg_read_4(SH4_WCR2));
#endif
#if defined(PCIBCR_WCR3_VAL)
	_reg_write_4(SH4_PCIWCR3, PCIBCR_WCR3_VAL);
#else
	_reg_write_4(SH4_PCIWCR3, _reg_read_4(SH4_WCR3));
#endif
#if defined(PCIBCR_MCR_VAL)
	_reg_write_4(SH4_PCIMCR, PCIBCR_MCR_VAL);
#else
	_reg_write_4(SH4_PCIMCR, _reg_read_4(SH4_MCR));
#endif
#endif	/* !DONT_INIT_PCIBSC */

	/* set PCI I/O, memory base address */
	_reg_write_4(SH4_PCIIOBR, SH4_PCIC_IO);
	_reg_write_4(SH4_PCIMBR, SH4_PCIC_MEM);

	/* set PCI local address 0 */
	_reg_write_4(SH4_PCILSR0, (64 - 1) << 20);
	_reg_write_4(SH4_PCILAR0, 0xac000000);
	_reg_write_4(SH4_PCICONF5, 0xac000000);

	/* set PCI local address 1 */
	_reg_write_4(SH4_PCILSR1, (64 - 1) << 20);
	_reg_write_4(SH4_PCILAR1, 0xac000000);
	_reg_write_4(SH4_PCICONF6, 0x8c000000);

	/* Enable I/O, memory, bus-master */
	_reg_write_4(SH4_PCICONF1, PCI_COMMAND_IO_ENABLE
	                           | PCI_COMMAND_MEM_ENABLE
	                           | PCI_COMMAND_MASTER_ENABLE
	                           | PCI_COMMAND_STEPPING_ENABLE
				   | PCI_STATUS_DEVSEL_MEDIUM);

	/* Initialize done. */
	_reg_write_4(SH4_PCICR, PCICR_BASE | PCICR_CFINIT);

	/* set PCI controller interrupt priority */
	intpri_intr_priority(SH4_INTEVT_PCIERR, IPL_BIO);	/* IPL_HIGH? */
	intpri_intr_priority(SH4_INTEVT_PCISERR, IPL_BIO);	/* IPL_HIGH? */

	sc->sc_membus_space.bus_base = SH4_PCIC_MEM;
	sc->sc_membus_space.bus_size = SH4_PCIC_MEM_SIZE;
	sc->sc_membus_space.bus_io = 0;
	sc->sc_iobus_space.bus_base = SH4_PCIC_IO; /* XXX */
	sc->sc_iobus_space.bus_size =  SH4_PCIC_IO_SIZE;
	sc->sc_iobus_space.bus_io = 1;;

	io_ex = extent_create("pciio", 0, 0xffffffff, M_DEVBUF, NULL, 0,
	    EX_NOWAIT | EX_FILLED);
	if (io_ex != NULL)
		extent_free(io_ex, SH4_PCIC_IO, SH4_PCIC_IO_SIZE, EX_NOWAIT);
	mem_ex = extent_create("pcimem", 0, 0xffffffff, M_DEVBUF, NULL, 0,
	    EX_NOWAIT | EX_FILLED);
	if (mem_ex != NULL)
		extent_free(mem_ex, SH4_PCIC_MEM, SH4_PCIC_MEM_SIZE, EX_NOWAIT);

	sc->sc_pci_chipset = shpcic_get_bus_mem_tag();

	/* PCI bus */
	memset(&pba, 0, sizeof(pba));
	pba.pba_busname = "pci";
	pba.pba_iot = shpcic_get_bus_io_tag();
	pba.pba_memt = shpcic_get_bus_mem_tag();
	pba.pba_dmat = shpcic_get_bus_dma_tag();
	pba.pba_ioex = io_ex;
	pba.pba_memex = mem_ex;
	pba.pba_pc = NULL;
	pba.pba_domain = pci_ndomains++;
	pba.pba_bus = 0;
	pba.pba_bridgetag = NULL;
	config_found(self, &pba, NULL);
}

int
shpcic_bus_maxdevs(void *v, int busno)
{
	/*
	 * Bus number is irrelevant.  Configuration Mechanism 1 is in
	 * use, can have devices 0-32 (i.e. the `normal' range).
	 */
	return (32);
}

pcitag_t
shpcic_make_tag(void *v, int bus, int device, int function)
{
	pcitag_t tag;

	if (bus >= 256 || device >= 32 || function >= 8)
		panic("pci_make_tag: bad request");

	tag = PCI_MODE1_ENABLE |
		    (bus << 16) | (device << 11) | (function << 8);

	return (tag);
}

void
shpcic_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp)
{
	if (bp != NULL)
		*bp = (tag >> 16) & 0xff;
	if (dp != NULL)
		*dp = (tag >> 11) & 0x1f;
	if (fp != NULL)
		*fp = (tag >> 8) & 0x7;
}

int
shpcic_conf_size(void *v, pcitag_t tag)
{
	return PCI_CONFIG_SPACE_SIZE;
}

pcireg_t
shpcic_conf_read(void *v, pcitag_t tag, int reg)
{
	pcireg_t data;
	int s;

	s = splhigh();
	_reg_write_4(SH4_PCIPAR, tag | reg);
	data = _reg_read_4(SH4_PCIPDR);
	_reg_write_4(SH4_PCIPAR, 0);
	splx(s);

	return data;
}

void
shpcic_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)
{
	int s;

	s = splhigh();
	_reg_write_4(SH4_PCIPAR, tag | reg);
	_reg_write_4(SH4_PCIPDR, data);
	_reg_write_4(SH4_PCIPAR, 0);
	splx(s);
}

/*
 * shpcic bus space
 */
int
shpcic_iomem_map(void *v, bus_addr_t bpa, bus_size_t size,
    int flags, bus_space_handle_t *bshp)
{
	*bshp = (bus_space_handle_t)bpa;

	return (0);
}

void
shpcic_iomem_unmap(void *v, bus_space_handle_t bsh, bus_size_t size)
{
	/* Nothing to do */
}

int
shpcic_iomem_subregion(void *v, bus_space_handle_t bsh,
    bus_size_t offset, bus_size_t size, bus_space_handle_t *nbshp)
{
	*nbshp = bsh + offset;

	return (0);
}

int
shpcic_iomem_alloc(void *v, bus_addr_t rstart, bus_addr_t rend,
    bus_size_t size, bus_size_t alignment, bus_size_t boundary, int flags,
    bus_addr_t *bpap, bus_space_handle_t *bshp)
{
	*bshp = *bpap = rstart;

	return (0);
}

void
shpcic_iomem_free(void *v, bus_space_handle_t bsh, bus_size_t size)
{
	/* Nothing to do */
}

void *
shpcic_iomem_vaddr(void *v, bus_space_handle_t bsh)
{
	return ((void *)bsh);
}

/*
 * shpcic bus space io/mem read/write
 */
/* read */
static inline uint8_t __shpcic_io_read_1(bus_space_handle_t bsh,
    bus_size_t offset);
static inline uint16_t __shpcic_io_read_2(bus_space_handle_t bsh,
    bus_size_t offset);
static inline uint32_t __shpcic_io_read_4(bus_space_handle_t bsh,
    bus_size_t offset);
static inline uint8_t __shpcic_mem_read_1(bus_space_handle_t bsh,
    bus_size_t offset);
static inline uint16_t __shpcic_mem_read_2(bus_space_handle_t bsh,
    bus_size_t offset);
static inline uint32_t __shpcic_mem_read_4(bus_space_handle_t bsh,
    bus_size_t offset);

static inline uint8_t
__shpcic_io_read_1(bus_space_handle_t bsh, bus_size_t offset)
{
	u_long adr = (u_long)(bsh + offset) & SH4_PCIC_IO_MASK;

	return *(volatile uint8_t *)(SH4_PCIC_IO + adr);
}

static inline uint16_t
__shpcic_io_read_2(bus_space_handle_t bsh, bus_size_t offset)
{
	u_long adr = (u_long)(bsh + offset) & SH4_PCIC_IO_MASK;

	return *(volatile uint16_t *)(SH4_PCIC_IO + adr);
}

static inline uint32_t
__shpcic_io_read_4(bus_space_handle_t bsh, bus_size_t offset)
{
	u_long adr = (u_long)(bsh + offset) & SH4_PCIC_IO_MASK;

	return *(volatile uint32_t *)(SH4_PCIC_IO + adr);
}

static inline uint8_t
__shpcic_mem_read_1(bus_space_handle_t bsh, bus_size_t offset)
{
	u_long adr = (u_long)(bsh + offset) & SH4_PCIC_MEM_MASK;

	return *(volatile uint8_t *)(SH4_PCIC_MEM + adr);
}

static inline uint16_t
__shpcic_mem_read_2(bus_space_handle_t bsh, bus_size_t offset)
{
	u_long adr = (u_long)(bsh + offset) & SH4_PCIC_MEM_MASK;

	return *(volatile uint16_t *)(SH4_PCIC_MEM + adr);
}

static inline uint32_t
__shpcic_mem_read_4(bus_space_handle_t bsh, bus_size_t offset)
{
	u_long adr = (u_long)(bsh + offset) & SH4_PCIC_MEM_MASK;

	return *(volatile uint32_t *)(SH4_PCIC_MEM + adr);
}

/*
 * read single
 */
uint8_t
shpcic_io_read_1(void *v, bus_space_handle_t bsh, bus_size_t offset)
{
	uint8_t value;

	value = __shpcic_io_read_1(bsh, offset);

	return value;
}

uint16_t
shpcic_io_read_2(void *v, bus_space_handle_t bsh, bus_size_t offset)
{
	uint16_t value;

	value = __shpcic_io_read_2(bsh, offset);

	return value;
}

uint32_t
shpcic_io_read_4(void *v, bus_space_handle_t bsh, bus_size_t offset)
{
	uint32_t value;

	value = __shpcic_io_read_4(bsh, offset);

	return value;
}

uint8_t
shpcic_mem_read_1(void *v, bus_space_handle_t bsh, bus_size_t offset)
{
	uint8_t value;

	value = __shpcic_mem_read_1(bsh, offset);

	return value;
}

uint16_t
shpcic_mem_read_2(void *v, bus_space_handle_t bsh, bus_size_t offset)
{
	uint16_t value;

	value = __shpcic_mem_read_2(bsh, offset);

	return value;
}

uint32_t
shpcic_mem_read_4(void *v, bus_space_handle_t bsh, bus_size_t offset)
{
	uint32_t value;

	value = __shpcic_mem_read_4(bsh, offset);

	return value;
}

/*
 * read multi
 */
void
shpcic_io_read_multi_1(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint8_t *addr, bus_size_t count)
{
	while (count--) {
		*addr++ = __shpcic_io_read_1(bsh, offset);
	}
}

void
shpcic_io_read_multi_2(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint16_t *addr, bus_size_t count)
{
	while (count--) {
		*addr++ = __shpcic_io_read_2(bsh, offset);
	}
}

void
shpcic_io_read_multi_4(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint32_t *addr, bus_size_t count)
{
	while (count--) {
		*addr++ = __shpcic_io_read_4(bsh, offset);
	}
}

void
shpcic_mem_read_multi_1(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint8_t *addr, bus_size_t count)
{
	while (count--) {
		*addr++ = __shpcic_mem_read_1(bsh, offset);
	}
}

void
shpcic_mem_read_multi_2(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint16_t *addr, bus_size_t count)
{
	while (count--) {
		*addr++ = __shpcic_mem_read_2(bsh, offset);
	}
}

void
shpcic_mem_read_multi_4(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint32_t *addr, bus_size_t count)
{
	while (count--) {
		*addr++ = __shpcic_mem_read_4(bsh, offset);
	}
}

/*
 * read raw multi
 */

void
shpcic_io_read_raw_multi_2(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint8_t *addr, bus_size_t count)
{
	count >>= 1;
	while (count--) {
		*(uint16_t *)addr = __shpcic_io_read_2(bsh, offset);
		addr += 2;
	}
}

void
shpcic_io_read_raw_multi_4(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint8_t *addr, bus_size_t count)
{
	count >>= 2;
	while (count--) {
		*(uint32_t *)addr = __shpcic_io_read_4(bsh, offset);
		addr += 4;
	}
}

void
shpcic_mem_read_raw_multi_2(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint8_t *addr, bus_size_t count)
{
	count >>= 1;
	while (count--) {
		*(uint16_t *)addr = __shpcic_mem_read_2(bsh, offset);
		addr += 2;
	}
}

void
shpcic_mem_read_raw_multi_4(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint8_t *addr, bus_size_t count)
{
	count >>= 2;
	while (count--) {
		*(uint32_t *)addr = __shpcic_mem_read_4(bsh, offset);
		addr += 4;
	}
}

/*
 * read region
 */
void
shpcic_io_read_region_1(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint8_t *addr, bus_size_t count)
{
	while (count--) {
		*addr++ = __shpcic_io_read_1(bsh, offset);
		offset += 1;
	}
}

void
shpcic_io_read_region_2(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint16_t *addr, bus_size_t count)
{
	while (count--) {
		*addr++ = __shpcic_io_read_2(bsh, offset);
		offset += 2;
	}
}

void
shpcic_io_read_region_4(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint32_t *addr, bus_size_t count)
{
	while (count--) {
		*addr++ = __shpcic_io_read_4(bsh, offset);
		offset += 4;
	}
}

void
shpcic_mem_read_region_1(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint8_t *addr, bus_size_t count)
{
	while (count--) {
		*addr++ = __shpcic_mem_read_1(bsh, offset);
		offset += 1;
	}
}

void
shpcic_mem_read_region_2(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint16_t *addr, bus_size_t count)
{
	while (count--) {
		*addr++ = __shpcic_mem_read_2(bsh, offset);
		offset += 2;
	}
}

void
shpcic_mem_read_region_4(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint32_t *addr, bus_size_t count)
{
	while (count--) {
		*addr++ = __shpcic_mem_read_4(bsh, offset);
		offset += 4;
	}
}

/*
 * read raw region
 */

void
shpcic_io_read_raw_region_2(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint8_t *addr, bus_size_t count)
{
	count >>= 1;
	while (count--) {
		*(uint16_t *)addr = __shpcic_io_read_2(bsh, offset);
		addr += 2;
		offset += 2;
	}
}

void
shpcic_io_read_raw_region_4(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint8_t *addr, bus_size_t count)
{
	count >>= 2;
	while (count--) {
		*(uint32_t *)addr = __shpcic_io_read_4(bsh, offset);
		addr += 4;
		offset += 4;
	}
}

void
shpcic_mem_read_raw_region_2(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint8_t *addr, bus_size_t count)
{
	count >>= 1;
	while (count--) {
		*(uint16_t *)addr = __shpcic_mem_read_2(bsh, offset);
		addr += 2;
		offset += 2;
	}
}

void
shpcic_mem_read_raw_region_4(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint8_t *addr, bus_size_t count)
{
	count >>= 2;
	while (count--) {
		*(uint32_t *)addr = __shpcic_mem_read_4(bsh, offset);
		addr += 4;
		offset += 4;
	}
}

/* write */
static inline void __shpcic_io_write_1(bus_space_handle_t bsh,
    bus_size_t offset, uint8_t value);
static inline void __shpcic_io_write_2(bus_space_handle_t bsh,
    bus_size_t offset, uint16_t value);
static inline void __shpcic_io_write_4(bus_space_handle_t bsh,
    bus_size_t offset, uint32_t value);
static inline void __shpcic_mem_write_1(bus_space_handle_t bsh,
    bus_size_t offset, uint8_t value);
static inline void __shpcic_mem_write_2(bus_space_handle_t bsh,
    bus_size_t offset, uint16_t value);
static inline void __shpcic_mem_write_4(bus_space_handle_t bsh,
    bus_size_t offset, uint32_t value);

static inline void
__shpcic_io_write_1(bus_space_handle_t bsh, bus_size_t offset,
    uint8_t value)
{
	u_long adr = (u_long)(bsh + offset) & SH4_PCIC_IO_MASK;

	*(volatile uint8_t *)(SH4_PCIC_IO + adr) = value;
}

static inline void
__shpcic_io_write_2(bus_space_handle_t bsh, bus_size_t offset,
    uint16_t value)
{
	u_long adr = (u_long)(bsh + offset) & SH4_PCIC_IO_MASK;

	*(volatile uint16_t *)(SH4_PCIC_IO + adr) = value;
}

static inline void
__shpcic_io_write_4(bus_space_handle_t bsh, bus_size_t offset,
    uint32_t value)
{
	u_long adr = (u_long)(bsh + offset) & SH4_PCIC_IO_MASK;

	*(volatile uint32_t *)(SH4_PCIC_IO + adr) = value;
}

static inline void
__shpcic_mem_write_1(bus_space_handle_t bsh, bus_size_t offset,
    uint8_t value)
{
	u_long adr = (u_long)(bsh + offset) & SH4_PCIC_MEM_MASK;

	*(volatile uint8_t *)(SH4_PCIC_MEM + adr) = value;
}

static inline void
__shpcic_mem_write_2(bus_space_handle_t bsh, bus_size_t offset,
    uint16_t value)
{
	u_long adr = (u_long)(bsh + offset) & SH4_PCIC_MEM_MASK;

	*(volatile uint16_t *)(SH4_PCIC_MEM + adr) = value;
}

static inline void
__shpcic_mem_write_4(bus_space_handle_t bsh, bus_size_t offset,
    uint32_t value)
{
	u_long adr = (u_long)(bsh + offset) & SH4_PCIC_MEM_MASK;

	*(volatile uint32_t *)(SH4_PCIC_MEM + adr) = value;
}

/*
 * write single
 */
void
shpcic_io_write_1(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint8_t value)
{
	__shpcic_io_write_1(bsh, offset, value);
}

void
shpcic_io_write_2(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint16_t value)
{
	__shpcic_io_write_2(bsh, offset, value);
}

void
shpcic_io_write_4(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint32_t value)
{
	__shpcic_io_write_4(bsh, offset, value);
}

void
shpcic_mem_write_1(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint8_t value)
{
	__shpcic_mem_write_1(bsh, offset, value);
}

void
shpcic_mem_write_2(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint16_t value)
{
	__shpcic_mem_write_2(bsh, offset, value);
}

void
shpcic_mem_write_4(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint32_t value)
{
	__shpcic_mem_write_4(bsh, offset, value);
}

/*
 * write multi
 */
void
shpcic_io_write_multi_1(void *v, bus_space_handle_t bsh,
    bus_size_t offset, const uint8_t *addr, bus_size_t count)
{
	while (count--) {
		__shpcic_io_write_1(bsh, offset, *addr++);
	}
}

void
shpcic_io_write_multi_2(void *v, bus_space_handle_t bsh,
    bus_size_t offset, const uint16_t *addr, bus_size_t count)
{
	while (count--) {
		__shpcic_io_write_2(bsh, offset, *addr++);
	}
}

void
shpcic_io_write_multi_4(void *v, bus_space_handle_t bsh,
    bus_size_t offset, const uint32_t *addr, bus_size_t count)
{
	while (count--) {
		__shpcic_io_write_4(bsh, offset, *addr++);
	}
}

void
shpcic_mem_write_multi_1(void *v, bus_space_handle_t bsh,
    bus_size_t offset, const uint8_t *addr, bus_size_t count)
{
	while (count--) {
		__shpcic_mem_write_1(bsh, offset, *addr++);
	}
}

void
shpcic_mem_write_multi_2(void *v, bus_space_handle_t bsh,
    bus_size_t offset, const uint16_t *addr, bus_size_t count)
{
	while (count--) {
		__shpcic_mem_write_2(bsh, offset, *addr++);
	}
}

void
shpcic_mem_write_multi_4(void *v, bus_space_handle_t bsh,
    bus_size_t offset, const uint32_t *addr, bus_size_t count)
{
	while (count--) {
		__shpcic_mem_write_4(bsh, offset, *addr++);
	}
}

/*
 * write raw multi
 */

void
shpcic_io_write_raw_multi_2(void *v, bus_space_handle_t bsh,
    bus_size_t offset, const uint8_t *addr, bus_size_t count)
{
	count >>= 1;
	while (count--) {
		__shpcic_io_write_2(bsh, offset, *(uint16_t *)addr);
		addr += 2;
	}
}

void
shpcic_io_write_raw_multi_4(void *v, bus_space_handle_t bsh,
    bus_size_t offset, const uint8_t *addr, bus_size_t count)
{
	count >>= 2;
	while (count--) {
		__shpcic_io_write_4(bsh, offset, *(uint32_t *)addr);
		addr += 4;
	}
}

void
shpcic_mem_write_raw_multi_2(void *v, bus_space_handle_t bsh,
    bus_size_t offset, const uint8_t *addr, bus_size_t count)
{
	count >>= 1;
	while (count--) {
		__shpcic_mem_write_2(bsh, offset, *(uint16_t *)addr);
		addr += 2;
	}
}

void
shpcic_mem_write_raw_multi_4(void *v, bus_space_handle_t bsh,
    bus_size_t offset, const uint8_t *addr, bus_size_t count)
{
	count >>= 2;
	while (count--) {
		__shpcic_mem_write_4(bsh, offset, *(uint32_t *)addr);
		addr += 4;
	}
}

/*
 * write region
 */
void
shpcic_io_write_region_1(void *v, bus_space_handle_t bsh,
    bus_size_t offset, const uint8_t *addr, bus_size_t count)
{
	while (count--) {
		__shpcic_io_write_1(bsh, offset, *addr++);
		offset += 1;
	}
}

void
shpcic_io_write_region_2(void *v, bus_space_handle_t bsh,
    bus_size_t offset, const uint16_t *addr, bus_size_t count)
{
	while (count--) {
		__shpcic_io_write_2(bsh, offset, *addr++);
		offset += 2;
	}
}

void
shpcic_io_write_region_4(void *v, bus_space_handle_t bsh,
    bus_size_t offset, const uint32_t *addr, bus_size_t count)
{
	while (count--) {
		__shpcic_io_write_4(bsh, offset, *addr++);
		offset += 4;
	}
}

void
shpcic_mem_write_region_1(void *v, bus_space_handle_t bsh,
    bus_size_t offset, const uint8_t *addr, bus_size_t count)
{
	while (count--) {
		__shpcic_mem_write_1(bsh, offset, *addr++);
		offset += 1;
	}
}

void
shpcic_mem_write_region_2(void *v, bus_space_handle_t bsh,
    bus_size_t offset, const uint16_t *addr, bus_size_t count)
{
	while (count--) {
		__shpcic_mem_write_2(bsh, offset, *addr++);
		offset += 2;
	}
}

void
shpcic_mem_write_region_4(void *v, bus_space_handle_t bsh,
    bus_size_t offset, const uint32_t *addr, bus_size_t count)
{
	while (count--) {
		__shpcic_mem_write_4(bsh, offset, *addr++);
		offset += 4;
	}
}

/*
 * write raw region
 */

void
shpcic_io_write_raw_region_2(void *v, bus_space_handle_t bsh,
    bus_size_t offset, const uint8_t *addr, bus_size_t count)
{
	count >>= 1;
	while (count--) {
		__shpcic_io_write_2(bsh, offset, *(uint16_t *)addr);
		addr += 2;
		offset += 2;
	}
}

void
shpcic_io_write_raw_region_4(void *v, bus_space_handle_t bsh,
    bus_size_t offset, const uint8_t *addr, bus_size_t count)
{
	count >>= 1;
	while (count--) {
		__shpcic_io_write_4(bsh, offset, *(uint32_t *)addr);
		addr += 4;
		offset += 4;
	}
}

void
shpcic_mem_write_raw_region_2(void *v, bus_space_handle_t bsh,
    bus_size_t offset, const uint8_t *addr, bus_size_t count)
{
	count >>= 1;
	while (count--) {
		__shpcic_mem_write_2(bsh, offset, *(uint16_t *)addr);
		addr += 2;
		offset += 2;
	}
}

void
shpcic_mem_write_raw_region_4(void *v, bus_space_handle_t bsh,
    bus_size_t offset, const uint8_t *addr, bus_size_t count)
{
	count >>= 2;
	while (count--) {
		__shpcic_mem_write_4(bsh, offset, *(uint32_t *)addr);
		addr += 4;
		offset += 4;
	}
}

/*
 * set multi
 */
void
shpcic_io_set_multi_1(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint8_t value, bus_size_t count)
{
	while (count--) {
		__shpcic_io_write_1(bsh, offset, value);
	}
}

void
shpcic_io_set_multi_2(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint16_t value, bus_size_t count)
{
	while (count--) {
		__shpcic_io_write_2(bsh, offset, value);
	}
}

void
shpcic_io_set_multi_4(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint32_t value, bus_size_t count)
{
	while (count--) {
		__shpcic_io_write_4(bsh, offset, value);
	}
}

void
shpcic_mem_set_multi_1(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint8_t value, bus_size_t count)
{
	while (count--) {
		__shpcic_mem_write_1(bsh, offset, value);
	}
}

void
shpcic_mem_set_multi_2(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint16_t value, bus_size_t count)
{
	while (count--) {
		__shpcic_mem_write_2(bsh, offset, value);
	}
}

void
shpcic_mem_set_multi_4(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint32_t value, bus_size_t count)
{
	while (count--) {
		__shpcic_mem_write_4(bsh, offset, value);
	}
}

/*
 * set region
 */
void
shpcic_io_set_region_1(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint8_t value, bus_size_t count)
{
	while (count--) {
		__shpcic_io_write_1(bsh, offset, value);
		offset += 1;
	}
}

void
shpcic_io_set_region_2(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint16_t value, bus_size_t count)
{
	while (count--) {
		__shpcic_io_write_2(bsh, offset, value);
		offset += 2;
	}
}

void
shpcic_io_set_region_4(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint32_t value, bus_size_t count)
{
	while (count--) {
		__shpcic_io_write_4(bsh, offset, value);
		offset += 4;
	}
}

void
shpcic_mem_set_region_1(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint8_t value, bus_size_t count)
{
	while (count--) {
		__shpcic_mem_write_1(bsh, offset, value);
		offset += 1;
	}
}

void
shpcic_mem_set_region_2(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint16_t value, bus_size_t count)
{
	while (count--) {
		__shpcic_mem_write_2(bsh, offset, value);
		offset += 2;
	}
}

void
shpcic_mem_set_region_4(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint32_t value, bus_size_t count)
{
	while (count--) {
		__shpcic_mem_write_4(bsh, offset, value);
		offset += 4;
	}
}

/*
 * copy region
 */
void
shpcic_io_copy_1(void *v, bus_space_handle_t bsh1,
    bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, bus_size_t count)
{
	u_long addr1 = bsh1 + off1;
	u_long addr2 = bsh2 + off2;
	uint8_t value;

	if (addr1 >= addr2) {	/* src after dest: copy forward */
		while (count--) {
			value = __shpcic_io_read_1(bsh1, off1);
			__shpcic_io_write_1(bsh2, off2, value);
			off1 += 1;
			off2 += 1;
		}
	} else {		/* dest after src: copy backwards */
		off1 += (count - 1) * 1;
		off2 += (count - 1) * 1;
		while (count--) {
			value = __shpcic_io_read_1(bsh1, off1);
			__shpcic_io_write_1(bsh2, off2, value);
			off1 -= 1;
			off2 -= 1;
		}
	}
}

void
shpcic_io_copy_2(void *v, bus_space_handle_t bsh1,
    bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, bus_size_t count)
{
	u_long addr1 = bsh1 + off1;
	u_long addr2 = bsh2 + off2;
	uint16_t value;

	if (addr1 >= addr2) {	/* src after dest: copy forward */
		while (count--) {
			value = __shpcic_io_read_2(bsh1, off1);
			__shpcic_io_write_2(bsh2, off2, value);
			off1 += 2;
			off2 += 2;
		}
	} else {		/* dest after src: copy backwards */
		off1 += (count - 1) * 2;
		off2 += (count - 1) * 2;
		while (count--) {
			value = __shpcic_io_read_2(bsh1, off1);
			__shpcic_io_write_2(bsh2, off2, value);
			off1 -= 2;
			off2 -= 2;
		}
	}
}

void
shpcic_io_copy_4(void *v, bus_space_handle_t bsh1,
    bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, bus_size_t count)
{
	u_long addr1 = bsh1 + off1;
	u_long addr2 = bsh2 + off2;
	uint32_t value;

	if (addr1 >= addr2) {	/* src after dest: copy forward */
		while (count--) {
			value = __shpcic_io_read_4(bsh1, off1);
			__shpcic_io_write_4(bsh2, off2, value);
			off1 += 4;
			off2 += 4;
		}
	} else {		/* dest after src: copy backwards */
		off1 += (count - 1) * 4;
		off2 += (count - 1) * 4;
		while (count--) {
			value = __shpcic_io_read_4(bsh1, off1);
			__shpcic_io_write_4(bsh2, off2, value);
			off1 -= 4;
			off2 -= 4;
		}
	}
}

void
shpcic_mem_copy_1(void *v, bus_space_handle_t bsh1,
    bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, bus_size_t count)
{
	u_long addr1 = bsh1 + off1;
	u_long addr2 = bsh2 + off2;
	uint8_t value;

	if (addr1 >= addr2) {	/* src after dest: copy forward */
		while (count--) {
			value = __shpcic_mem_read_1(bsh1, off1);
			__shpcic_mem_write_1(bsh2, off2, value);
			off1 += 1;
			off2 += 1;
		}
	} else {		/* dest after src: copy backwards */
		off1 += (count - 1) * 1;
		off2 += (count - 1) * 1;
		while (count--) {
			value = __shpcic_mem_read_1(bsh1, off1);
			__shpcic_mem_write_1(bsh2, off2, value);
			off1 -= 1;
			off2 -= 1;
		}
	}
}

void
shpcic_mem_copy_2(void *v, bus_space_handle_t bsh1,
    bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, bus_size_t count)
{
	u_long addr1 = bsh1 + off1;
	u_long addr2 = bsh2 + off2;
	uint16_t value;

	if (addr1 >= addr2) {	/* src after dest: copy forward */
		while (count--) {
			value = __shpcic_mem_read_2(bsh1, off1);
			__shpcic_mem_write_2(bsh2, off2, value);
			off1 += 2;
			off2 += 2;
		}
	} else {		/* dest after src: copy backwards */
		off1 += (count - 1) * 2;
		off2 += (count - 1) * 2;
		while (count--) {
			value = __shpcic_mem_read_2(bsh1, off1);
			__shpcic_mem_write_2(bsh2, off2, value);
			off1 -= 2;
			off2 -= 2;
		}
	}
}

void
shpcic_mem_copy_4(void *v, bus_space_handle_t bsh1,
    bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, bus_size_t count)
{
	u_long addr1 = bsh1 + off1;
	u_long addr2 = bsh2 + off2;
	uint32_t value;

	if (addr1 >= addr2) {	/* src after dest: copy forward */
		while (count--) {
			value = __shpcic_mem_read_4(bsh1, off1);
			__shpcic_mem_write_4(bsh2, off2, value);
			off1 += 4;
			off2 += 4;
		}
	} else {		/* dest after src: copy backwards */
		off1 += (count - 1) * 4;
		off2 += (count - 1) * 4;
		while (count--) {
			value = __shpcic_mem_read_4(bsh1, off1);
			__shpcic_mem_write_4(bsh2, off2, value);
			off1 -= 4;
			off2 -= 4;
		}
	}
}


code:
/*	$OpenBSD: shpcicvar.h,v 1.6 2010/12/04 17:06:32 miod Exp $	*/
/*	$NetBSD: shpcicvar.h,v 1.6 2005/12/11 12:18:58 christos Exp $	*/

/*-
 * Copyright (c) 2005 NONAKA Kimihiro
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */

#ifndef SH_DEV_PCICVAR_H
#define SH_DEV_PCICVAR_H

#include <machine/bus.h>

bus_space_tag_t shpcic_get_bus_io_tag(void);
bus_space_tag_t shpcic_get_bus_mem_tag(void);
bus_dma_tag_t shpcic_get_bus_dma_tag(void);

int shpcic_bus_maxdevs(void *v, int busno);
pcitag_t shpcic_make_tag(void *v, int bus, int device, int function);
void shpcic_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp);
int shpcic_conf_size(void *, pcitag_t);
pcireg_t shpcic_conf_read(void *v, pcitag_t tag, int reg);
void shpcic_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data);

int shpcic_set_intr_priority(int intr, int level);
void *shpcic_intr_establish(int evtcode, int (*ih_func)(void *), void *ih_arg,
    const char *ih_name);
void shpcic_intr_disestablish(void *ih);

struct config_bus_space {
        u_int32_t bus_base;
        u_int32_t bus_size;
        int bus_io;
};

struct shpcic_softc {
        struct device s_dev;

	pci_chipset_tag_t sc_pci_chipset;

        /* Structures to do bus fixup */
        int nbogus;
        struct extent *extent_mem;
        struct extent *extent_port;
        struct config_bus_space sc_membus_space;
        struct config_bus_space sc_iobus_space;
};

void pci_addr_fixup(void *v, int maxbus);

/*
 * shpcic io/mem bus space
 */
int shpcic_iomem_map(void *v, bus_addr_t bpa, bus_size_t size, int flags,
    bus_space_handle_t *bshp);
void shpcic_iomem_unmap(void *v, bus_space_handle_t bsh, bus_size_t size);
int shpcic_iomem_subregion(void *v, bus_space_handle_t bsh, bus_size_t offset,
    bus_size_t size, bus_space_handle_t *nbshp);
int shpcic_iomem_alloc(void *v, bus_addr_t rstart, bus_addr_t rend,
    bus_size_t size, bus_size_t alignment, bus_size_t boundary, int flags,
    bus_addr_t *bpap, bus_space_handle_t *bshp);
void shpcic_iomem_free(void *v, bus_space_handle_t bsh, bus_size_t size);
void *shpcic_iomem_vaddr(void *v, bus_space_handle_t bsh);

/* read single */
uint8_t shpcic_io_read_1(void *v, bus_space_handle_t bsh, bus_size_t offset);
uint16_t shpcic_io_read_2(void *v, bus_space_handle_t bsh, bus_size_t offset);
uint32_t shpcic_io_read_4(void *v, bus_space_handle_t bsh, bus_size_t offset);
uint8_t shpcic_mem_read_1(void *v, bus_space_handle_t bsh, bus_size_t offset);
uint16_t shpcic_mem_read_2(void *v, bus_space_handle_t bsh, bus_size_t offset);
uint32_t shpcic_mem_read_4(void *v, bus_space_handle_t bsh, bus_size_t offset);

/* read multi */
void shpcic_io_read_multi_1(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint8_t *addr, bus_size_t count);
void shpcic_io_read_multi_2(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint16_t *addr, bus_size_t count);
void shpcic_io_read_multi_4(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint32_t *addr, bus_size_t count);
void shpcic_mem_read_multi_1(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint8_t *addr, bus_size_t count);
void shpcic_mem_read_multi_2(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint16_t *addr, bus_size_t count);
void shpcic_mem_read_multi_4(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint32_t *addr, bus_size_t count);

/* read raw multi */
void shpcic_io_read_raw_multi_2(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint8_t *addr, bus_size_t count);
void shpcic_io_read_raw_multi_4(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint8_t *addr, bus_size_t count);
void shpcic_mem_read_raw_multi_2(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint8_t *addr, bus_size_t count);
void shpcic_mem_read_raw_multi_4(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint8_t *addr, bus_size_t count);

/* read region */
void shpcic_io_read_region_1(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint8_t *addr, bus_size_t count);
void shpcic_io_read_region_2(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint16_t *addr, bus_size_t count);
void shpcic_io_read_region_4(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint32_t *addr, bus_size_t count);
void shpcic_mem_read_region_1(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint8_t *addr, bus_size_t count);
void shpcic_mem_read_region_2(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint16_t *addr, bus_size_t count);
void shpcic_mem_read_region_4(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint32_t *addr, bus_size_t count);

/* read raw region */
void shpcic_io_read_raw_region_2(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint8_t *addr, bus_size_t count);
void shpcic_io_read_raw_region_4(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint8_t *addr, bus_size_t count);
void shpcic_mem_read_raw_region_2(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint8_t *addr, bus_size_t count);
void shpcic_mem_read_raw_region_4(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint8_t *addr, bus_size_t count);

/* write single */
void shpcic_io_write_1(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint8_t data);
void shpcic_io_write_2(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint16_t data);
void shpcic_io_write_4(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint32_t data);
void shpcic_mem_write_1(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint8_t data);
void shpcic_mem_write_2(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint16_t data);
void shpcic_mem_write_4(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint32_t data);

/* write multi */
void shpcic_io_write_multi_1(void *v, bus_space_handle_t bsh,
    bus_size_t offset, const uint8_t *addr, bus_size_t count);
void shpcic_io_write_multi_2(void *v, bus_space_handle_t bsh,
    bus_size_t offset, const uint16_t *addr, bus_size_t count);
void shpcic_io_write_multi_4(void *v, bus_space_handle_t bsh,
    bus_size_t offset, const uint32_t *addr, bus_size_t count);
void shpcic_mem_write_multi_1(void *v, bus_space_handle_t bsh,
    bus_size_t offset, const uint8_t *addr, bus_size_t count);
void shpcic_mem_write_multi_2(void *v, bus_space_handle_t bsh,
    bus_size_t offset, const uint16_t *addr, bus_size_t count);
void shpcic_mem_write_multi_4(void *v, bus_space_handle_t bsh,
    bus_size_t offset, const uint32_t *addr, bus_size_t count);

/* write raw multi */
void shpcic_io_write_raw_multi_2(void *v, bus_space_handle_t bsh,
    bus_size_t offset, const uint8_t *addr, bus_size_t count);
void shpcic_io_write_raw_multi_4(void *v, bus_space_handle_t bsh,
    bus_size_t offset, const uint8_t *addr, bus_size_t count);
void shpcic_mem_write_raw_multi_2(void *v, bus_space_handle_t bsh,
    bus_size_t offset, const uint8_t *addr, bus_size_t count);
void shpcic_mem_write_raw_multi_4(void *v, bus_space_handle_t bsh,
    bus_size_t offset, const uint8_t *addr, bus_size_t count);

/* write region */
void shpcic_io_write_region_1(void *v, bus_space_handle_t bsh,
    bus_size_t offset, const uint8_t *addr, bus_size_t count);
void shpcic_io_write_region_2(void *v, bus_space_handle_t bsh,
    bus_size_t offset, const uint16_t *addr, bus_size_t count);
void shpcic_io_write_region_4(void *v, bus_space_handle_t bsh,
    bus_size_t offset, const uint32_t *addr, bus_size_t count);
void shpcic_mem_write_region_1(void *v, bus_space_handle_t bsh,
    bus_size_t offset, const uint8_t *addr, bus_size_t count);
void shpcic_mem_write_region_2(void *v, bus_space_handle_t bsh,
    bus_size_t offset, const uint16_t *addr, bus_size_t count);
void shpcic_mem_write_region_4(void *v, bus_space_handle_t bsh,
    bus_size_t offset, const uint32_t *addr, bus_size_t count);

/* write raw region */
void shpcic_io_write_raw_region_2(void *v, bus_space_handle_t bsh,
    bus_size_t offset, const uint8_t *addr, bus_size_t count);
void shpcic_io_write_raw_region_4(void *v, bus_space_handle_t bsh,
    bus_size_t offset, const uint8_t *addr, bus_size_t count);
void shpcic_mem_write_raw_region_2(void *v, bus_space_handle_t bsh,
    bus_size_t offset, const uint8_t *addr, bus_size_t count);
void shpcic_mem_write_raw_region_4(void *v, bus_space_handle_t bsh,
    bus_size_t offset, const uint8_t *addr, bus_size_t count);

/* set multi */
void shpcic_io_set_multi_1(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint8_t val, bus_size_t count);
void shpcic_io_set_multi_2(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint16_t val, bus_size_t count);
void shpcic_io_set_multi_4(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint32_t val, bus_size_t count);
void shpcic_mem_set_multi_1(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint8_t val, bus_size_t count);
void shpcic_mem_set_multi_2(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint16_t val, bus_size_t count);
void shpcic_mem_set_multi_4(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint32_t val, bus_size_t count);

/* set region */
void shpcic_io_set_region_1(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint8_t val, bus_size_t count);
void shpcic_io_set_region_2(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint16_t val, bus_size_t count);
void shpcic_io_set_region_4(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint32_t val, bus_size_t count);
void shpcic_mem_set_region_1(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint8_t val, bus_size_t count);
void shpcic_mem_set_region_2(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint16_t val, bus_size_t count);
void shpcic_mem_set_region_4(void *v, bus_space_handle_t bsh,
    bus_size_t offset, uint32_t val, bus_size_t count);

/* copy region */
void shpcic_io_copy_1(void *v, bus_space_handle_t bsh1,
    bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2,
    bus_size_t count);
void shpcic_io_copy_2(void *v, bus_space_handle_t bsh1,
    bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2,
    bus_size_t count);
void shpcic_io_copy_4(void *v, bus_space_handle_t bsh1,
    bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2,
    bus_size_t count);
void shpcic_mem_copy_1(void *v, bus_space_handle_t bsh1,
    bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2,
    bus_size_t count);
void shpcic_mem_copy_2(void *v, bus_space_handle_t bsh1,
    bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2,
    bus_size_t count);
void shpcic_mem_copy_4(void *v, bus_space_handle_t bsh1,
    bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2,
    bus_size_t count);
#endif /* SH_DEV_PCICVAR_H */

license: unknown


code: src/sys/arch/sh/include

path: sys/arch/sh/include/CVS/Repository


code:
/*	$OpenBSD: _float.h,v 1.1 2012/06/26 16:12:44 deraadt Exp $	*/

/*
 * Copyright (c) 1989 Regents of the University of California.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of the University nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */

#ifndef _MACHINE__FLOAT_H_
#define _MACHINE__FLOAT_H_

#define __FLT_RADIX		2		/* b */
#define __FLT_ROUNDS		__flt_rounds()
#define __FLT_EVAL_METHOD	0		/* no promotions */

#define __FLT_MANT_DIG		24		/* p */
#define __FLT_EPSILON		1.19209290E-07F	/* b**(1-p) */
#define __FLT_DIG		6		/* floor((p-1)*log10(b))+(b == 10) */
#define __FLT_MIN_EXP		(-125)		/* emin */
#define __FLT_MIN		1.17549435E-38F	/* b**(emin-1) */
#define __FLT_MIN_10_EXP	(-37)		/* ceil(log10(b**(emin-1))) */
#define __FLT_MAX_EXP		128		/* emax */
#define __FLT_MAX		3.40282347E+38F	/* (1-b**(-p))*b**emax */
#define __FLT_MAX_10_EXP	38		/* floor(log10((1-b**(-p))*b**emax)) */

#define __DBL_MANT_DIG		53
#define __DBL_EPSILON		2.2204460492503131E-16
#define __DBL_DIG		15
#define __DBL_MIN_EXP		(-1021)
#define __DBL_MIN		2.2250738585072014E-308
#define __DBL_MIN_10_EXP	(-307)
#define __DBL_MAX_EXP		1024
#define __DBL_MAX		1.7976931348623157E+308
#define __DBL_MAX_10_EXP	308

#define __LDBL_MANT_DIG		DBL_MANT_DIG
#define __LDBL_EPSILON		DBL_EPSILON
#define __LDBL_DIG		DBL_DIG
#define __LDBL_MIN_EXP		DBL_MIN_EXP
#define __LDBL_MIN		DBL_MIN
#define __LDBL_MIN_10_EXP	DBL_MIN_10_EXP
#define __LDBL_MAX_EXP		DBL_MAX_EXP
#define __LDBL_MAX		DBL_MAX
#define __LDBL_MAX_10_EXP	DBL_MAX_10_EXP

#define __DECIMAL_DIG		17

#endif /* _MACHINE__FLOAT_H_ */


code:
/*	$OpenBSD: _types.h,v 1.18 2014/03/19 05:14:13 guenther Exp $	*/

/*-
 * Copyright (c) 1990, 1993
 *	The Regents of the University of California.  All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of the University nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 *	@(#)types.h	8.3 (Berkeley) 1/5/94
 *	@(#)ansi.h	8.2 (Berkeley) 1/4/94
 */

#ifndef _SH__TYPES_H_
#define _SH__TYPES_H_

#if defined(_KERNEL)
typedef struct label_t {
	long val[9];
} label_t;
#endif

/*
 * _ALIGN(p) rounds p (pointer or byte index) up to a correctly-aligned
 * value for all data types (int, long, ...).   The result is an
 * unsigned long and must be cast to any desired pointer type.
 *
 * _ALIGNED_POINTER is a boolean macro that checks whether an address
 * is valid to fetch data elements of type t from on this architecture.
 * This does not reflect the optimal alignment, just the possibility
 * (within reasonable limits).
 */
#define	_ALIGNBYTES		(sizeof(int) - 1)
#define	_STACKALIGNBYTES	_ALIGNBYTES
#define	_ALIGN(p)		(((unsigned long)(p) + _ALIGNBYTES) & ~_ALIGNBYTES)
#define	_ALIGNED_POINTER(p,t)	((((unsigned long)(p)) & (sizeof(t) - 1)) == 0)

/* 7.18.1.1 Exact-width integer types */
typedef	signed char		__int8_t;
typedef	unsigned char		__uint8_t;
typedef	short			__int16_t;
typedef	unsigned short		__uint16_t;
typedef	int			__int32_t;
typedef	unsigned int		__uint32_t;
/* LONGLONG */
typedef	long long		__int64_t;
/* LONGLONG */
typedef	unsigned long long	__uint64_t;

/* 7.18.1.2 Minimum-width integer types */
typedef	__int8_t		__int_least8_t;
typedef	__uint8_t		__uint_least8_t;
typedef	__int16_t		__int_least16_t;
typedef	__uint16_t		__uint_least16_t;
typedef	__int32_t		__int_least32_t;
typedef	__uint32_t		__uint_least32_t;
typedef	__int64_t		__int_least64_t;
typedef	__uint64_t		__uint_least64_t;

/* 7.18.1.3 Fastest minimum-width integer types */
typedef	__int32_t		__int_fast8_t;
typedef	__uint32_t		__uint_fast8_t;
typedef	__int32_t		__int_fast16_t;
typedef	__uint32_t		__uint_fast16_t;
typedef	__int32_t		__int_fast32_t;
typedef	__uint32_t		__uint_fast32_t;
typedef	__int64_t		__int_fast64_t;
typedef	__uint64_t		__uint_fast64_t;
#define	__INT_FAST8_MIN		INT32_MIN
#define	__INT_FAST16_MIN	INT32_MIN
#define	__INT_FAST32_MIN	INT32_MIN
#define	__INT_FAST64_MIN	INT64_MIN
#define	__INT_FAST8_MAX		INT32_MAX
#define	__INT_FAST16_MAX	INT32_MAX
#define	__INT_FAST32_MAX	INT32_MAX
#define	__INT_FAST64_MAX	INT64_MAX
#define	__UINT_FAST8_MAX	UINT32_MAX
#define	__UINT_FAST16_MAX	UINT32_MAX
#define	__UINT_FAST32_MAX	UINT32_MAX
#define	__UINT_FAST64_MAX	UINT64_MAX

/* 7.18.1.4 Integer types capable of holding object pointers */
typedef	long			__intptr_t;
typedef	unsigned long		__uintptr_t;

/* 7.18.1.5 Greatest-width integer types */
typedef	__int64_t		__intmax_t;
typedef	__uint64_t		__uintmax_t;

/* Register size */
typedef long			__register_t;

/* VM system types */
typedef unsigned long		__vaddr_t;
typedef unsigned long		__paddr_t;
typedef unsigned long		__vsize_t;
typedef unsigned long		__psize_t;

/* Standard system types */
typedef double			__double_t;
typedef float			__float_t;
typedef long			__ptrdiff_t;
typedef	unsigned long		__size_t;
typedef	long			__ssize_t;
#if defined(__GNUC__) && __GNUC__ >= 3
typedef	__builtin_va_list	__va_list;
#else
struct __va_list_tag;
typedef	struct __va_list_tag *	__va_list;
#endif

/* Wide character support types */
#ifndef __cplusplus
typedef	int			__wchar_t;
#endif
typedef int			__wint_t;
typedef	int			__rune_t;
typedef	void *			__wctrans_t;
typedef	void *			__wctype_t;

#endif	/* _SH__TYPES_H_ */


code:
/*	$OpenBSD: asm.h,v 1.4 2013/03/28 17:41:04 martynas Exp $	*/
/*	$NetBSD: asm.h,v 1.25 2006/01/20 22:02:40 christos Exp $	*/

/*-
 * Copyright (c) 1990 The Regents of the University of California.
 * All rights reserved.
 *
 * This code is derived from software contributed to Berkeley by
 * William Jolitz.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of the University nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 *	@(#)asm.h	5.5 (Berkeley) 5/7/91
 */

#ifndef _SH_ASM_H_
#define	_SH_ASM_H_

#ifdef __ELF__
# define _C_LABEL(x)	x
#else
#ifdef __STDC__
# define _C_LABEL(x)	_ ## x
#else
# define _C_LABEL(x)	_/**/x
#endif
#endif
#define	_ASM_LABEL(x)	x

#ifdef __STDC__
# define __CONCAT(x,y)	x ## y
# define __STRING(x)	#x
#else
# define __CONCAT(x,y)	x/**/y
# define __STRING(x)	"x"
#endif

/* let kernels and others override entrypoint alignment */
#ifndef _ALIGN_TEXT
# define _ALIGN_TEXT .align 2
#endif

#ifdef __ELF__
#define	_ENTRY(x)							\
	.text								;\
	_ALIGN_TEXT							;\
	.globl x							;\
	.type x,@function						;\
	x:
#else /* !__ELF__ */
#define	_ENTRY(x)							\
	.text								;\
	_ALIGN_TEXT							;\
	.globl x							;\
	x:
#endif /* !__ELF__ */

#ifdef GPROF
#define	_PROF_PROLOGUE				  \
	mov.l	1f,r1				; \
	mova	2f,r0				; \
	jmp	@r1				; \
	 nop					; \
	.align	2				; \
1:	.long	__mcount			; \
2:
#else  /* !GPROF */
#define	_PROF_PROLOGUE
#endif /* !GPROF */

#define	ENTRY(y)	_ENTRY(_C_LABEL(y)) _PROF_PROLOGUE
#define	NENTRY(y)	_ENTRY(_C_LABEL(y))
#define	ASENTRY(y)	_ENTRY(_ASM_LABEL(y)) _PROF_PROLOGUE

#define SET_ENTRY_SIZE(y) \
	.size	_C_LABEL(y), . - _C_LABEL(y)

#define SET_ASENTRY_SIZE(y) \
	.size	_ASM_LABEL(y), . - _ASM_LABEL(y)

#ifdef __ELF__
#define	ALTENTRY(name)				 \
	.globl _C_LABEL(name)			;\
	.type _C_LABEL(name),@function		;\
	_C_LABEL(name):
#else
#define	ALTENTRY(name)				 \
	.globl _C_LABEL(name)			;\
	_C_LABEL(name):
#endif

/*
 * Hide the gory details of PIC calls vs. normal calls.  Use as in the
 * following example:
 *
 *	sts.l	pr, @-sp
 *	PIC_PROLOGUE(.L_got, r0)	! saves old r12 on stack
 *	...
 *	mov.l	.L_function_1, r0
 * 1:	CALL	r0			! each call site needs a label
 *	 nop
 *      ...
 *	mov.l	.L_function_2, r0
 * 2:	CALL	r0
 *	 nop
 *	...
 *	PIC_EPILOGUE			! restores r12 from stack
 *	lds.l	@sp+, pr		!  so call in right order
 *	rts
 *	 nop
 *
 *	.align 2
 * .L_got:
 *	PIC_GOT_DATUM
 * .L_function_1:			! if you call the same function twice
 *	CALL_DATUM(function, 1b)	!  provide call datum for each call
 * .L_function_2:
 * 	CALL_DATUM(function, 2b)
 */

#ifdef __PIC__

#define	PIC_PLT(x)	x@PLT
#define	PIC_GOT(x)	x@GOT
#define	PIC_GOTOFF(x)	x@GOTOFF

#define	PIC_PROLOGUE(got)			\
        	mov.l	r12, @-sp;		\
		PIC_PROLOGUE_NOSAVE(got)

/*
 * Functions that do non local jumps don't need to preserve r12,
 * so we can shave off two instructions to save/restore it.
 */
#define	PIC_PROLOGUE_NOSAVE(got)		\
        	mov.l	got, r12;		\
        	mova	got, r0;		\
        	add	r0, r12

#define	PIC_EPILOGUE				\
		mov.l	@sp+, r12

#define PIC_EPILOGUE_SLOT 			\
		PIC_EPILOGUE

#define PIC_GOT_DATUM \
		.long	_GLOBAL_OFFSET_TABLE_

#define CALL	bsrf
#define JUMP	braf

#define CALL_DATUM(function, lpcs) \
		.long	PIC_PLT(function) - ((lpcs) + 4 - (.))

/*
 * This will result in text relocations in the shared library,
 * unless the function is local or has hidden or protected visibility.
 * Does not require PIC prologue.
 */
#define CALL_DATUM_LOCAL(function, lpcs) \
		.long	function - ((lpcs) + 4)

#else  /* !PIC */

#define	PIC_PROLOGUE(label)
#define	PIC_PROLOGUE_NOSAVE(label)
#define	PIC_EPILOGUE
#define	PIC_EPILOGUE_SLOT	nop
#define PIC_GOT_DATUM

#define CALL	jsr @
#define JUMP	jmp @

#define CALL_DATUM(function, lpcs) \
		.long	function

#define CALL_DATUM_LOCAL(function, lpcs) \
		.long	function

#endif /* !PIC */

#define	ASMSTR		.asciz

#ifdef __ELF__
#define	STRONG_ALIAS(alias,sym)						\
	.global _C_LABEL(alias);					\
	_C_LABEL(alias) = _C_LABEL(sym)
#define	WEAK_ALIAS(alias,sym)						\
	.weak _C_LABEL(alias);						\
	_C_LABEL(alias) = _C_LABEL(sym)
#endif

#define	WARN_REFERENCES(_sym,_msg)				\
	.section .gnu.warning._sym; .ascii _msg; .previous

#endif /* !_SH_ASM_H_ */


code:
/*	$OpenBSD: atomic.h,v 1.8 2014/11/17 23:51:32 dlg Exp $	*/

/* Public Domain */

#ifndef _SH_ATOMIC_H_
#define _SH_ATOMIC_H_

#if defined(_KERNEL)

#include <sh/psl.h>

static inline unsigned int
__atomic_enter(void)
{
	unsigned int sr;

	asm volatile ("stc sr, %0" : "=r"(sr));
	asm volatile ("ldc %0, sr" : : "r"(sr | PSL_IMASK));

	return (sr);
}

static inline void
__atomic_leave(unsigned int sr)
{
	asm volatile ("ldc %0, sr" : : "r"(sr));
}

static inline unsigned int
_atomic_cas_uint(volatile unsigned int *uip, unsigned int o, unsigned int n)
{
	unsigned int sr;
	unsigned int rv;

	sr = __atomic_enter();
	rv = *uip;
	if (rv == o)
		*uip = n;
	__atomic_leave(sr);

	return (rv);
}
#define atomic_cas_uint(_p, _o, _n) _atomic_cas_uint((_p), (_o), (_n))

static inline unsigned long
_atomic_cas_ulong(volatile unsigned long *uip, unsigned long o, unsigned long n)
{
	unsigned int sr;
	unsigned long rv;

	sr = __atomic_enter();
	rv = *uip;
	if (rv == o)
		*uip = n;
	__atomic_leave(sr);

	return (rv);
}
#define atomic_cas_ulong(_p, _o, _n) _atomic_cas_ulong((_p), (_o), (_n))

static inline void *
_atomic_cas_ptr(volatile void *uip, void *o, void *n)
{
	unsigned int sr;
	void * volatile *uipp = (void * volatile *)uip;
	void *rv;

	sr = __atomic_enter();
	rv = *uipp;
	if (rv == o)
		*uipp = n;
	__atomic_leave(sr);

	return (rv);
}
#define atomic_cas_ptr(_p, _o, _n) _atomic_cas_ptr((_p), (_o), (_n))

static inline unsigned int
_atomic_swap_uint(volatile unsigned int *uip, unsigned int n)
{
	unsigned int sr;
	unsigned int rv;

	sr = __atomic_enter();
	rv = *uip;
	*uip = n;
	__atomic_leave(sr);

	return (rv);
}
#define atomic_swap_uint(_p, _n) _atomic_swap_uint((_p), (_n))

static inline unsigned long
_atomic_swap_ulong(volatile unsigned long *uip, unsigned long n)
{
	unsigned int sr;
	unsigned long rv;

	sr = __atomic_enter();
	rv = *uip;
	*uip = n;
	__atomic_leave(sr);

	return (rv);
}
#define atomic_swap_ulong(_p, _n) _atomic_swap_ulong((_p), (_n))

static inline void *
_atomic_swap_ptr(volatile void *uip, void *n)
{
	unsigned int sr;
	void * volatile *uipp = (void * volatile *)uip;
	void *rv;

	sr = __atomic_enter();
	rv = *uipp;
	*uipp = n;
	__atomic_leave(sr);

	return (rv);
}
#define atomic_swap_ptr(_p, _n) _atomic_swap_ptr((_p), (_n))

static inline unsigned int
_atomic_add_int_nv(volatile unsigned int *uip, unsigned int v)
{
	unsigned int sr;
	unsigned int rv;

	sr = __atomic_enter();
	rv = *uip + v;
	*uip = rv;
	__atomic_leave(sr);

	return (rv);
}
#define atomic_add_int_nv(_p, _v) _atomic_add_int_nv((_p), (_v))

static inline unsigned long
_atomic_add_long_nv(volatile unsigned long *uip, unsigned long v)
{
	unsigned int sr;
	unsigned long rv;

	sr = __atomic_enter();
	rv = *uip + v;
	*uip = rv;
	__atomic_leave(sr);

	return (rv);
}
#define atomic_add_long_nv(_p, _v) _atomic_add_long_nv((_p), (_v))

static inline unsigned int
_atomic_sub_int_nv(volatile unsigned int *uip, unsigned int v)
{
	unsigned int sr;
	unsigned int rv;

	sr = __atomic_enter();
	rv = *uip - v;
	*uip = rv;
	__atomic_leave(sr);

	return (rv);
}
#define atomic_sub_int_nv(_p, _v) _atomic_sub_int_nv((_p), (_v))

static inline unsigned long
_atomic_sub_long_nv(volatile unsigned long *uip, unsigned long v)
{
	unsigned int sr;
	unsigned long rv;

	sr = __atomic_enter();
	rv = *uip - v;
	*uip = rv;
	__atomic_leave(sr);

	return (rv);
}
#define atomic_sub_long_nv(_p, _v) _atomic_sub_long_nv((_p), (_v))

static inline void
atomic_setbits_int(volatile unsigned int *uip, unsigned int v)
{
	unsigned int sr;

	sr = __atomic_enter();
	*uip |= v;
	__atomic_leave(sr);
}

static inline void
atomic_clearbits_int(volatile unsigned int *uip, unsigned int v)
{
	unsigned int sr;

	sr = __atomic_enter();
	*uip &= ~v;
	__atomic_leave(sr);
}

#endif /* defined(_KERNEL) */
#endif /* _SH_ATOMIC_H_ */


code:
/*	$OpenBSD: bscreg.h,v 1.1.1.1 2006/10/06 21:02:55 miod Exp $	*/
/*	$NetBSD: bscreg.h,v 1.6 2005/12/11 12:18:58 christos Exp $	*/

/*-
 * Copyright (C) 1999 SAITOH Masanobu.  All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef _SH_BSCREG_H_
#define	_SH_BSCREG_H_
#include <sh/devreg.h>

/*
 * Bus State Controller
 */

#define	SH3_BCR1		0xffffff60	/* 16bit */
#define	SH3_BCR2		0xffffff62	/* 16bit */
#define	SH3_WCR1		0xffffff64	/* 16bit */
#define	SH3_WCR2		0xffffff66	/* 16bit */
#define	SH3_MCR			0xffffff68	/* 16bit */
#define	SH3_DCR			0xffffff6a	/* 16bit */
#define	SH3_PCR			0xffffff6c	/* 16bit */
#define	SH3_RTCSR		0xffffff6e	/* 16bit */
#define	SH3_RTCNT		0xffffff70	/* 16bit */
#define	SH3_RTCOR		0xffffff72	/* 16bit */
#define	SH3_RFCR		0xffffff74	/* 16bit */
#define	SH3_BCR3		0xffffff7e	/* 16bit */

#define	SH4_BCR1		0xff800000	/* 32bit */
#define	SH4_BCR2		0xff800004	/* 16bit */
#define	SH4_WCR1		0xff800008	/* 32bit */
#define	SH4_WCR2		0xff80000c	/* 32bit */
#define	SH4_WCR3		0xff800010	/* 32bit */
#define	SH4_MCR			0xff800014	/* 32bit */
#define	SH4_PCR			0xff800018	/* 16bit */
#define	SH4_RTCSR		0xff80001c	/* 16bit */
#define	SH4_RTCNT		0xff800020	/* 16bit */
#define	SH4_RTCOR		0xff800024	/* 16bit */
#define	SH4_RFCR		0xff800028	/* 16bit */
#define	SH4_BCR3		0xff800050	/* 16bit: SH7751R */
#define	SH4_BCR4		0xfe0a00f0	/* 32bit: SH7751R */

#define	BCR1_MASTER		(1 << 30)
#define	BCR1_BREQEN		(1 << 19)

#define	BCR2_PORTEN		(1 << 0)

#endif	/* !_SH_BSCREG_H_ */


code:
/*	$OpenBSD: cache.h,v 1.3 2008/06/26 05:42:12 ray Exp $	*/
/*	$NetBSD: cache.h,v 1.7 2006/01/21 00:46:36 uwe Exp $	*/

/*-
 * Copyright (c) 2002 The NetBSD Foundation, Inc.
 * All rights reserved.
 *
 * This code is derived from software contributed to The NetBSD Foundation
 * by UCHIYAMA Yasushi.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

/*
 * Cache configurations.
 *
 * SH3 I/D unified virtual-index physical-tag cache.
 * SH4 I/D separated virtual-index physical-tag cache.
 *
 *
 *         size       line-size entry way type
 * SH7708  4/8K       16B       128   2/4 P0,P2,U0 [1]
 *                                        P1 [2]
 * SH7709  4/8K       16B       128   2/4 [1]
 * SH7709A 16K        16B       256   4   [1]
 *
 * SH7750  I$  D$     line-size entry way
 *         8K  8/16K  32B       256   1   [1]
 * SH7750
 * SH7750S
 * SH7751  I$  D$     line-size entry way
 *         8K  8/16K  32B       256   1   [1]
 *
 * SH7750R
 * SH7751R I$  D$     line-size entry way
 *         16K 16/32K 32B       512   2   [1]
 *
 * [1]	write-through/back selectable
 * [2]	write-through only
 *
 * Cache operations.
 *
 * There are some rules that must be followed:
 *
 *	I-cache Sync (all or range):
 *		The goal is to synchronize the instruction stream,
 *		so you may need to write-back dirty data cache
 *		blocks first.  If a range is requested, and you
 *		can't synchronize just a range, you have to hit
 *		the whole thing.
 *
 *	D-cache Write-back Invalidate range:
 *		If you can't WB-Inv a range, you must WB-Inv the
 *		entire D-cache.
 *
 *	D-cache Invalidate:
 *		If you can't Inv the D-cache without doing a
 *		Write-back, YOU MUST PANIC.  This is to catch
 *		errors in calling code.  Callers must be aware
 *		of this scenario, and must handle it appropriately
 *		(consider the bus_dma(9) operations).
 *
 *	D-cache Write-back:
 *		If you can't Write-back without doing an invalidate,
 *		that's fine.  Then treat this as a WB-Inv.  Skipping
 *		the invalidate is merely an optimization.
 *
 *	All operations:
 *		Valid virtual addresses must be passed to the
 *		cache operation.
 *
 *
 *	sh_icache_sync_all	Synchronize I-cache
 *
 *	sh_icache_sync_range	Synchronize I-cache range
 *
 *	sh_icache_sync_range_index (index ops)
 *
 *	sh_dcache_wbinv_all	Write-back Invalidate D-cache
 *
 *	sh_dcache_wbinv_range	Write-back Invalidate D-cache range
 *
 *	sh_dcache_wbinv_range_index (index ops)
 *
 *	sh_dcache_inv_range	Invalidate D-cache range
 *
 *	sh_dcache_wb_range	Write-back D-cache range
 *
 *	If I/D unified cache (SH3), I-cache ops are writeback invalidate
 *	operation.
 *	If write-through mode, sh_dcache_wb_range is no-operation.
 *
 */

#ifndef _SH_CACHE_H_
#define	_SH_CACHE_H_

#ifdef _KERNEL
struct sh_cache_ops {
	void (*_icache_sync_all)(void);
	void (*_icache_sync_range)(vaddr_t, vsize_t);
	void (*_icache_sync_range_index)(vaddr_t, vsize_t);

	void (*_dcache_wbinv_all)(void);
	void (*_dcache_wbinv_range)(vaddr_t, vsize_t);
	void (*_dcache_wbinv_range_index)(vaddr_t, vsize_t);
	void (*_dcache_inv_range)(vaddr_t, vsize_t);
	void (*_dcache_wb_range)(vaddr_t, vsize_t);
};

/* Cache configurations */
#define	sh_cache_enable_unified		sh_cache_enable_icache
extern int sh_cache_enable_icache;
extern int sh_cache_enable_dcache;
extern int sh_cache_write_through;
extern int sh_cache_write_through_p0_u0_p3;
extern int sh_cache_write_through_p1;
extern int sh_cache_ways;
extern int sh_cache_unified;
#define	sh_cache_size_unified		sh_cache_size_icache
extern int sh_cache_size_icache;
extern int sh_cache_size_dcache;
extern int sh_cache_line_size;
/* for n-way set associative cache */
extern int sh_cache_way_size;
extern int sh_cache_way_shift;
extern int sh_cache_entry_mask;

/* Special mode */
extern int sh_cache_ram_mode;
extern int sh_cache_index_mode_icache;
extern int sh_cache_index_mode_dcache;

extern int sh_cache_prefer_mask;

extern struct sh_cache_ops sh_cache_ops;

#define	sh_icache_sync_all()						\
	(*sh_cache_ops._icache_sync_all)()

#define	sh_icache_sync_range(v, s)					\
	(*sh_cache_ops._icache_sync_range)((v), (s))

#define	sh_icache_sync_range_index(v, s)				\
	(*sh_cache_ops._icache_sync_range_index)((v), (s))

#define	sh_dcache_wbinv_all()						\
	(*sh_cache_ops._dcache_wbinv_all)()

#define	sh_dcache_wbinv_range(v, s)					\
	(*sh_cache_ops._dcache_wbinv_range)((v), (s))

#define	sh_dcache_wbinv_range_index(v, s)				\
	(*sh_cache_ops._dcache_wbinv_range_index)((v), (s))

#define	sh_dcache_inv_range(v, s)					\
	(*sh_cache_ops._dcache_inv_range)((v), (s))

#define	sh_dcache_wb_range(v, s)					\
	(*sh_cache_ops._dcache_wb_range)((v), (s))

void sh_cache_init(void);
void sh_cache_information(void);

#define	SH_HAS_UNIFIED_CACHE	CPU_IS_SH3
#define	SH_HAS_VIRTUAL_ALIAS	CPU_IS_SH4
#define	SH_HAS_WRITEBACK_CACHE	(!sh_cache_write_through)

#endif /* _KERNEL */
#endif /* _SH_CACHE_H_ */


code:
/*	$OpenBSD: cache_sh3.h,v 1.2 2008/06/26 05:42:12 ray Exp $	*/
/*	$NetBSD: cache_sh3.h,v 1.8 2006/03/04 01:55:03 uwe Exp $	*/

/*-
 * Copyright (c) 2002 The NetBSD Foundation, Inc.
 * All rights reserved.
 *
 * This code is derived from software contributed to The NetBSD Foundation
 * by UCHIYAMA Yasushi.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

/*
 * SH3: SH7708, SH7708S, SH7708R, SH7709, SH7709A
 */
#ifndef _SH_CACHE_SH3_H_
#define	_SH_CACHE_SH3_H_
#include <sh/devreg.h>
#ifdef _KERNEL

#define	SH3_CCR			0xffffffec
#define	  SH3_CCR_CE		  0x00000001
#define	  SH3_CCR_WT		  0x00000002
/* SH7708 don't have CB bit */
#define	  SH3_CCR_CB		  0x00000004
#define	  SH3_CCR_CF		  0x00000008
/* SH7709A don't have RA bit */
#define	  SH3_CCR_RA		  0x00000020

/* SH7709A specific cache-lock control register */
#define	SH7709A_CCR2		0xa40000b0
#define	  SH7709A_CCR2_W2LOCK	  0x00000001
#define	  SH7709A_CCR2_W2LOAD	  0x00000002
#define	  SH7709A_CCR2_W3LOCK	  0x00000100
#define	  SH7709A_CCR2_W3LOAD	  0x00000200

#define	SH3_CCA			0xf0000000
/* Address specification */
#define	  CCA_A			  0x00000008
#define	  CCA_ENTRY_SHIFT	  4
/* 8KB cache (SH7708, SH7708S, SH7708R, SH7709) */
#define	  CCA_8K_ENTRY		  128
#define	  CCA_8K_ENTRY_MASK	  0x000007f0	/* [10:4] */
#define	  CCA_8K_WAY_SHIFT	  11
#define	  CCA_8K_WAY_MASK	  0x00001800	/* [12:11] */
/* 16KB cache (SH7709A) */
#define	  CCA_16K_ENTRY		  256
#define	  CCA_16K_ENTRY_MASK	  0x00000ff0	/* [11:4] */
#define	  CCA_16K_WAY_SHIFT	  12
#define	  CCA_16K_WAY_MASK	  0x00003000	/* [13:12] */

/* Data specification */
#define	  CCA_V			  0x00000001
#define	  CCA_U			  0x00000002
#define	  CCA_LRU_SHIFT		  4
#define	  CCA_LRU_MASK		  0x000003f0	/* [9:4] */
#define	  CCA_TAGADDR_SHIFT	  10
#define	  CCA_TAGADDR_MASK	  0xfffffc00	/* [31:10] */

#define	SH3_CCD			0xf1000000
/* Address specification */
#define	  CCD_L_SHIFT		  2
#define	  CCD_L_MASK		  0x0000000c	/* [3:2] */
#define	  CCD_E_SHIFT		  4
#define	  CCD_8K_E_MASK		  0x000007f0	/* [10:4] */
#define	  CCD_16K_E_MASK	  0x00000ff0	/* [11:4] */
#define	  CCD_8K_W_SHIFT	  11
#define	  CCD_8K_W_MASK		  0x00001800	/* [12:11] */
#define	  CCD_16K_W_SHIFT	  12
#define	  CCD_16K_W_MASK	  0x00003000	/* [13:12] */
/* Data specification */

/*
 * Configuration
 */
#define	SH3_CACHE_LINESZ		16
#define	SH3_CACHE_NORMAL_WAY		4
#define	SH3_CACHE_RAMMODE_WAY		2

#define	SH3_CACHE_8K_ENTRY		128
#define	SH3_CACHE_8K_WAY_NORMAL		4
#define	SH3_CACHE_8K_WAY_RAMMODE	2

#define	SH3_CACHE_16K_ENTRY		256
#define	SH3_CACHE_16K_WAY		4

/*
 * cache flush macro for locore level code.
 */
#define	SH3_CACHE_8K_FLUSH(maxway)					\
do {									\
	uint32_t __e, __w, __wa, __a;					\
									\
	for (__w = 0; __w < maxway; __w++) {				\
		__wa = SH3_CCA | __w << CCA_8K_WAY_SHIFT;		\
		for (__e = 0; __e < CCA_8K_ENTRY; __e++)	{	\
			__a = __wa |(__e << CCA_ENTRY_SHIFT);		\
			(*(volatile uint32_t *)__a) &=		\
				~(CCA_U | CCA_V);			\
		}							\
	}								\
} while (/*CONSTCOND*/0)

#define	SH3_CACHE_16K_FLUSH()						\
do {									\
	uint32_t __e, __w, __wa, __a;					\
									\
	for (__w = 0; __w < SH3_CACHE_16K_WAY; __w++) {			\
		__wa = SH3_CCA | __w << CCA_16K_WAY_SHIFT;		\
		for (__e = 0; __e < CCA_16K_ENTRY; __e++)	{	\
			__a = __wa |(__e << CCA_ENTRY_SHIFT);		\
			(*(volatile uint32_t *)__a) &=		\
				~(CCA_U | CCA_V);			\
		}							\
	}								\
} while (/*CONSTCOND*/0)

#define	SH7708_CACHE_FLUSH()		SH3_CACHE_8K_FLUSH(4)
#define	SH7708_CACHE_FLUSH_RAMMODE()	SH3_CACHE_8K_FLUSH(2)
#define	SH7708S_CACHE_FLUSH()		SH3_CACHE_8K_FLUSH(4)
#define	SH7708S_CACHE_FLUSH_RAMMODE()	SH3_CACHE_8K_FLUSH(2)
#define	SH7708R_CACHE_FLUSH()		SH3_CACHE_8K_FLUSH(4)
#define	SH7708R_CACHE_FLUSH_RAMMODE()	SH3_CACHE_8K_FLUSH(2)
#define	SH7709_CACHE_FLUSH()		SH3_CACHE_8K_FLUSH(4)
#define	SH7709_CACHE_FLUSH_RAMMODE()	SH3_CACHE_8K_FLUSH(2)
#define	SH7709A_CACHE_FLUSH()		SH3_CACHE_16K_FLUSH()

#ifndef _LOCORE
extern void sh3_cache_config(void);
#endif
#endif /* _KERNEL */
#endif /* !_SH_CACHE_SH3_H_ */


code:
/*	$OpenBSD: cache_sh4.h,v 1.3 2010/01/01 13:18:37 miod Exp $	*/
/*	$NetBSD: cache_sh4.h,v 1.11 2006/03/04 01:55:03 uwe Exp $	*/

/*-
 * Copyright (c) 2002 The NetBSD Foundation, Inc.
 * All rights reserved.
 *
 * This code is derived from software contributed to The NetBSD Foundation
 * by UCHIYAMA Yasushi.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

/*
 * SH4: SH7750 SH7750S SH7750R SH7751 SH7751R
 */

#ifndef _SH_CACHE_SH4_H_
#define	_SH_CACHE_SH4_H_
#include <sh/devreg.h>
#ifdef _KERNEL

#define	SH4_ICACHE_SIZE		8192
#define	SH4_DCACHE_SIZE		16384
#define	SH4_EMODE_ICACHE_SIZE	16384
#define	SH4_EMODE_DCACHE_SIZE	32768
#define	SH4_CACHE_LINESZ	32

#define	SH4_CCR			0xff00001c
#define   SH4_CCR_EMODE		  0x80000000
#define	  SH4_CCR_IIX		  0x00008000
#define	  SH4_CCR_ICI		  0x00000800
#define	  SH4_CCR_ICE		  0x00000100
#define	  SH4_CCR_OIX		  0x00000080
#define	  SH4_CCR_ORA		  0x00000020
#define	  SH4_CCR_OCI		  0x00000008
#define	  SH4_CCR_CB		  0x00000004
#define	  SH4_CCR_WT		  0x00000002
#define	  SH4_CCR_OCE		  0x00000001

#define	SH4_QACR0		0xff000038
#define	SH4_QACR1		0xff00003c
#define	  SH4_QACR_AREA_SHIFT	  2
#define	  SH4_QACR_AREA_MASK	  0x0000001c

/* I-cache address/data array  */
#define	SH4_CCIA		0xf0000000
/* address specification */
#define	  CCIA_A		  0x00000008	/* associate bit */
#define	  CCIA_ENTRY_SHIFT	  5		/* line size 32B */
#define	  CCIA_ENTRY_MASK	  0x00001fe0	/* [12:5] 256-entries */
/* data specification */
#define	  CCIA_V		  0x00000001
#define	  CCIA_TAGADDR_MASK	  0xfffffc00	/* [31:10] */

#define	SH4_CCID		0xf1000000
/* address specification */
#define	  CCID_L_SHIFT		  2
#define	  CCID_L_MASK		  0x1c		/* line-size is 32B */
#define	  CCID_ENTRY_MASK	  0x00001fe0	/* [12:5] 256-entries */

/* D-cache address/data array  */
#define	SH4_CCDA		0xf4000000
/* address specification */
#define	  CCDA_A		  0x00000008	/* associate bit */
#define	  CCDA_ENTRY_SHIFT	  5		/* line size 32B */
#define	  CCDA_ENTRY_MASK	  0x00003fe0	/* [13:5] 512-entries */
/* data specification */
#define	  CCDA_V		  0x00000001
#define	  CCDA_U		  0x00000002
#define	  CCDA_TAGADDR_MASK	  0xfffffc00	/* [31:10] */

#define	SH4_CCDD		0xf5000000

/* Store Queue */
#define	SH4_SQ			0xe0000000

#ifndef _LOCORE
extern void sh4_cache_config(void);
#endif
#endif /* _KERNEL */
#endif /* !_SH_CACHE_SH4_H_ */


code:
/*	$OpenBSD: cdefs.h,v 1.2 2013/03/28 17:30:45 martynas Exp $	*/

#ifndef	_SH_CDEFS_H_
#define	_SH_CDEFS_H_

#define __strong_alias(alias,sym)					\
	__asm__(".global " __STRING(alias) " ; " __STRING(alias)	\
	    " = " __STRING(sym))
#define __weak_alias(alias,sym)						\
	__asm__(".weak " __STRING(alias) " ; " __STRING(alias)		\
	    " = " __STRING(sym))
#define	__warn_references(sym,msg)					\
	__asm__(".section .gnu.warning." __STRING(sym)			\
	    " ; .ascii \"" msg "\" ; .text")

#endif /* !_SH_CDEFS_H_ */


code:
/*	$OpenBSD: clock.h,v 1.2 2008/06/26 05:42:12 ray Exp $	*/
/*	$NetBSD: clock.h,v 1.2 2002/04/28 17:10:33 uch Exp $	*/

/*-
 * Copyright (c) 2002 The NetBSD Foundation, Inc.
 * All rights reserved.
 *
 * This code is derived from software contributed to The NetBSD Foundation
 * by UCHIYAMA Yasushi.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

/*
 * void sh_clock_init(int flags, struct rtc_ops *):
 *   flags:
 *	SH_CLOCK_NORTC		... If SH RTC module is disabled, set this.
 *				    internal module don't use RTCCLK.
 *	SH_CLOCK_NOINITTODR	... Don't initialize RTC time.
 *   rtc_ops:
 *	Machine dependent RTC ops pointer. If NULL is specified, use SH
 *	internal RTC.
 *
 * void machine_clock_init(void):
 *	Implement machine specific part of clock routines.
 *	must call sh_clock_init() at exit.
 *
 * int sh_clock_get_cpuclock(void):
 *	returns CPU clock estimated by sh_clock_init().
 *
 * int sh_clock_get_pclock(void):
 *	returns PCLOCK. when PCLOCK is not specified by kernel configuration
 *	file, this value is estimated by sh_clock_init().
 *
 */
struct rtc_ops;
struct clock_ymdhms;

void sh_clock_init(int, struct rtc_ops *);
#define	SH_CLOCK_NORTC			0x00000001
#define	SH_CLOCK_NOINITTODR		0x00000002
void machine_clock_init(void);

int sh_clock_get_cpuclock(void);
int sh_clock_get_pclock(void);

/*
 * SH RTC module interface.
 */
void sh_rtc_init(void *);
void sh_rtc_get(void *, time_t, struct clock_ymdhms *);
void sh_rtc_set(void *, struct clock_ymdhms *);

/*
 * machine specific RTC ops
 */
struct clock_ymdhms;
struct rtc_ops {
	void *_cookie;
	void (*init)(void *);
	void (*get)(void *, time_t, struct clock_ymdhms *);
	void (*set)(void *, struct clock_ymdhms *);
};


code:
/*	$OpenBSD: cpgreg.h,v 1.1.1.1 2006/10/06 21:02:55 miod Exp $	*/
/*	$NetBSD: cpgreg.h,v 1.5 2002/04/28 17:10:34 uch Exp $	*/

/*-
 * Copyright (C) 1999 SAITOH Masanobu.  All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef _SH_CPGREG_H_
#define	_SH_CPGREG_H_

/*
 * Clock Pulse Generator
 */
#define	SH3_FRQCR		0xffffff80	/* 16bit */
#define	SH4_FRQCR		0xffc00000	/* 16bit */

/*
 * Standby Control
 */
#define	SH3_STBCR		0xffffff82	/* 8bit */
#define	SH7709_STBCR2		0xffffff88	/* 8bit */

#define	SH4_STBCR		0xffc00004	/* 8bit */
#define	SH4_STBCR2		0xffc00010	/* 8bit */

#endif /* !_SH_CPGREG_H_ */


code:
/*	$OpenBSD: cpu.h,v 1.27 2014/07/11 10:53:07 uebayasi Exp $	*/
/*	$NetBSD: cpu.h,v 1.41 2006/01/21 04:24:12 uwe Exp $	*/

/*-
 * Copyright (c) 2002 The NetBSD Foundation, Inc. All rights reserved.
 * Copyright (c) 1990 The Regents of the University of California.
 * All rights reserved.
 *
 * This code is derived from software contributed to Berkeley by
 * William Jolitz.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of the University nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 *	@(#)cpu.h	5.4 (Berkeley) 5/9/91
 */

/*
 * SH3/SH4 support.
 *
 *  T.Horiuchi    Brains Corp.   5/22/98
 */

#ifndef _SH_CPU_H_
#define	_SH_CPU_H_

#include <sh/psl.h>
#include <sh/frame.h>

#ifdef _KERNEL

/*
 * Per-CPU information.
 */

#include <machine/intr.h>
#include <sys/sched.h>

struct cpu_info {
	struct proc *ci_curproc;

	struct schedstate_percpu ci_schedstate; /* scheduler state */
	u_int32_t ci_randseed;
#ifdef DIAGNOSTIC
	int	ci_mutex_level;
#endif
#ifdef GPROF
	struct gmonparam *ci_gmon;
#endif
};

extern struct cpu_info cpu_info_store;
#define	curcpu()	(&cpu_info_store)
#define cpu_number()	0
#define CPU_IS_PRIMARY(ci)	1
#define CPU_INFO_ITERATOR	int
#define CPU_INFO_FOREACH(cii, ci) \
	for (cii = 0, ci = curcpu(); ci != NULL; ci = NULL)
#define CPU_INFO_UNIT(ci)	0
#define MAXCPUS	1
#define cpu_unidle(ci)

#define CPU_BUSY_CYCLE()	do {} while (0)

/*
 * Arguments to hardclock and gatherstats encapsulate the previous
 * machine state in an opaque clockframe.
 */
struct clockframe {
	int	spc;	/* program counter at time of interrupt */
	int	ssr;	/* status register at time of interrupt */
	int	ssp;	/* stack pointer at time of interrupt */
};

#define	CLKF_USERMODE(cf)	(!KERNELMODE((cf)->ssr))
#define	CLKF_PC(cf)		((cf)->spc)
#define	CLKF_INTR(cf)		0	/* XXX */

/*
 * This is used during profiling to integrate system time.  It can safely
 * assume that the process is resident.
 */
#define	PROC_PC(p)	((p)->p_md.md_regs->tf_spc)
#define	PROC_STACK(p)	((p)->p_md.md_regs->tf_r15)

/*
 * Preempt the current process if in interrupt from user mode,
 * or after the current trap/syscall if in system mode.
 */
#define	need_resched(ci)						\
do {									\
	want_resched = 1;						\
	if (curproc != NULL)						\
		aston(curproc);					\
} while (/*CONSTCOND*/0)
#define clear_resched(ci) 	want_resched = 0

/*
 * Give a profiling tick to the current process when the user profiling
 * buffer pages are invalid.  On the MIPS, request an ast to send us
 * through trap, marking the proc as needing a profiling tick.
 */
#define	need_proftick(p)	aston(p)

/*
 * Notify the current process (p) that it has a signal pending,
 * process as soon as possible.
 */
#define	signotify(p)	aston(p)

#define	aston(p)	((p)->p_md.md_astpending = 1)

extern int want_resched;		/* need_resched() was called */

/*
 * We need a machine-independent name for this.
 */
#define	DELAY(x)		delay(x)

#define	cpu_idle_enter()	do { /* nothing */ } while (0)
#define	cpu_idle_cycle()	__asm volatile("sleep")
#define	cpu_idle_leave()	do { /* nothing */ } while (0)

#endif /* _KERNEL */

/*
 * Logical address space of SH3/SH4 CPU.
 */
#define	SH3_PHYS_MASK	0x1fffffff

#define	SH3_P0SEG_BASE	0x00000000	/* TLB mapped, also U0SEG */
#define	SH3_P0SEG_END	0x7fffffff
#define	SH3_P1SEG_BASE	0x80000000	/* pa == va */
#define	SH3_P1SEG_END	0x9fffffff
#define	SH3_P2SEG_BASE	0xa0000000	/* pa == va, non-cacheable */
#define	SH3_P2SEG_END	0xbfffffff
#define	SH3_P3SEG_BASE	0xc0000000	/* TLB mapped, kernel mode */
#define	SH3_P3SEG_END	0xdfffffff
#define	SH3_P4SEG_BASE	0xe0000000	/* peripheral space */
#define	SH3_P4SEG_END	0xffffffff

#define	SH3_P1SEG_TO_PHYS(x)	((uint32_t)(x) & SH3_PHYS_MASK)
#define	SH3_P2SEG_TO_PHYS(x)	((uint32_t)(x) & SH3_PHYS_MASK)
#define	SH3_PHYS_TO_P1SEG(x)	((uint32_t)(x) | SH3_P1SEG_BASE)
#define	SH3_PHYS_TO_P2SEG(x)	((uint32_t)(x) | SH3_P2SEG_BASE)
#define	SH3_P1SEG_TO_P2SEG(x)	((uint32_t)(x) | 0x20000000)
#define	SH3_P2SEG_TO_P1SEG(x)	((uint32_t)(x) & ~0x20000000)

#ifdef _KERNEL
#ifndef __lint__

/*
 * Switch from P1 (cached) to P2 (uncached).  This used to be written
 * using gcc's assigned goto extension, but gcc4 aggressive optimizations
 * tend to optimize that away under certain circumstances.
 */
#define RUN_P2						\
	do {						\
		register uint32_t r0 asm("r0");		\
		uint32_t pc;				\
		__asm volatile(				\
			"	mov.l	1f, %1	;"	\
			"	mova	2f, %0	;"	\
			"	or	%0, %1	;"	\
			"	jmp	@%1	;"	\
			"	 nop		;"	\
			"	.align 2	;"	\
			"1:	.long	0x20000000;"	\
			"2:;"				\
			: "=r"(r0), "=r"(pc));		\
	} while (0)

/*
 * Switch from P2 (uncached) back to P1 (cached).  We need to be
 * running on P2 to access cache control, memory-mapped cache and TLB
 * arrays, etc. and after touching them at least 8 instructinos are
 * necessary before jumping to P1, so provide that padding here.
 */
#define RUN_P1						\
	do {						\
		register uint32_t r0 asm("r0");		\
		uint32_t pc;				\
		__asm volatile(				\
		/*1*/	"	mov.l	1f, %1	;"	\
		/*2*/	"	mova	2f, %0	;"	\
		/*3*/	"	nop		;"	\
		/*4*/	"	and	%0, %1	;"	\
		/*5*/	"	nop		;"	\
		/*6*/	"	nop		;"	\
		/*7*/	"	nop		;"	\
		/*8*/	"	nop		;"	\
			"	jmp	@%1	;"	\
			"	 nop		;"	\
			"	.align 2	;"	\
			"1:	.long	~0x20000000;"	\
			"2:;"				\
			: "=r"(r0), "=r"(pc));		\
	} while (0)

/*
 * If RUN_P1 is the last thing we do in a function we can omit it, b/c
 * we are going to return to a P1 caller anyway, but we still need to
 * ensure there's at least 8 instructions before jump to P1.
 */
#define PAD_P1_SWITCH	__asm volatile ("nop;nop;nop;nop;nop;nop;nop;nop;")

#else  /* __lint__ */
#define	RUN_P2		do {} while (/* CONSTCOND */ 0)
#define	RUN_P1		do {} while (/* CONSTCOND */ 0)
#define	PAD_P1_SWITCH	do {} while (/* CONSTCOND */ 0)
#endif
#endif

#if defined(SH4)
/* SH4 Processor Version Register */
#define	SH4_PVR_ADDR	0xff000030	/* P4  address */
#define	SH4_PVR		(*(volatile uint32_t *) SH4_PVR_ADDR)
#define	SH4_PRR_ADDR	0xff000044	/* P4  address */
#define	SH4_PRR		(*(volatile uint32_t *) SH4_PRR_ADDR)

#define	SH4_PVR_MASK	0xffffff00
#define	SH4_PVR_SH7750	0x04020500	/* SH7750  */
#define	SH4_PVR_SH7750S	0x04020600	/* SH7750S */
#define	SH4_PVR_SH775xR	0x04050000	/* SH775xR */
#define	SH4_PVR_SH7751	0x04110000	/* SH7751  */

#define	SH4_PRR_MASK	0xfffffff0
#define SH4_PRR_7750R	0x00000100	/* SH7750R */
#define SH4_PRR_7751R	0x00000110	/* SH7751R */
#endif

/*
 * pull in #defines for kinds of processors
 */
#include <machine/cputypes.h>

#ifdef _KERNEL
void sh_cpu_init(int, int);
void sh_startup(void);
__dead void cpu_reset(void);	/* soft reset */
void _cpu_spin(uint32_t);	/* for delay loop. */
void delay(int);
struct pcb;
void savectx(struct pcb *);
struct fpreg;
void fpu_save(struct fpreg *);
void fpu_restore(struct fpreg *);
u_int cpu_dump(int (*)(dev_t, daddr_t, caddr_t, size_t), daddr_t *);
u_int cpu_dumpsize(void);
void dumpconf(void);
void dumpsys(void);
#endif /* _KERNEL */
#endif /* !_SH_CPU_H_ */


code:
/*	$OpenBSD: cputypes.h,v 1.2 2008/06/26 05:42:12 ray Exp $	*/
/*	$NetBSD: cputypes.h,v 1.10 2006/01/21 00:40:36 uwe Exp $	*/

/*-
 * Copyright (c) 2002 The NetBSD Foundation, Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef _SH_CPUTYPES_H_
#define	_SH_CPUTYPES_H_

#ifdef _KERNEL

#define	CPU_ARCH_SH3		3
#define	CPU_ARCH_SH4		4

/* SH3 series */
#define	CPU_PRODUCT_7708	1
#define	CPU_PRODUCT_7708S	2
#define	CPU_PRODUCT_7708R	3
#define	CPU_PRODUCT_7709	4
#define	CPU_PRODUCT_7709A	5

/* SH4 series */
#define	CPU_PRODUCT_7750	6
#define	CPU_PRODUCT_7750S	7
#define	CPU_PRODUCT_7750R	8
#define	CPU_PRODUCT_7751	9
#define	CPU_PRODUCT_7751R	10

#ifndef _LOCORE
extern int cpu_arch;
extern int cpu_product;
#if defined(SH3) && defined(SH4)
#define	CPU_IS_SH3		(cpu_arch == CPU_ARCH_SH3)
#define	CPU_IS_SH4		(cpu_arch == CPU_ARCH_SH4)
#elif defined(SH3)
#define	CPU_IS_SH3		(/* CONSTCOND */1)
#define	CPU_IS_SH4		(/* CONSTCOND */0)
#elif defined(SH4)
#define	CPU_IS_SH3		(/* CONSTCOND */0)
#define	CPU_IS_SH4		(/* CONSTCOND */1)
#else
#error "define SH3 and/or SH4"
#endif
#endif /* !_LOCORE */

#endif /* _KERNEL */

#endif /* !_SH_CPUTYPES_H_ */


code:
/*	$OpenBSD: db_machdep.h,v 1.6 2014/03/16 20:31:46 guenther Exp $	*/
/*	$NetBSD: db_machdep.h,v 1.12 2006/05/10 06:24:03 skrll Exp $	*/

/*
 * Mach Operating System
 * Copyright (c) 1991,1990 Carnegie Mellon University
 * All Rights Reserved.
 *
 * Permission to use, copy, modify and distribute this software and its
 * documentation is hereby granted, provided that both the copyright
 * notice and this permission notice appear in all copies of the
 * software, derivative works or modified versions, and any portions
 * thereof, and that both notices appear in supporting documentation.
 *
 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
 * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
 *
 * Carnegie Mellon requests users of this software to return to
 *
 *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
 *  School of Computer Science
 *  Carnegie Mellon University
 *  Pittsburgh PA 15213-3890
 *
 * any improvements or extensions that they make and grant Carnegie Mellon
 * the rights to redistribute these changes.
 */

#ifndef	_SH_DB_MACHDEP_H_
#define	_SH_DB_MACHDEP_H_

/*
 * Machine-dependent defines for the kernel debugger.
 */

#include <sys/param.h>
#include <uvm/uvm_extern.h>
#include <sh/trap.h>

typedef	vaddr_t		db_addr_t;	/* address - unsigned */
typedef	long		db_expr_t;	/* expression - signed */

typedef struct trapframe db_regs_t;
extern db_regs_t	ddb_regs;	/* register state */
#define	DDB_REGS	(&ddb_regs)

#define	PC_REGS(regs)	((db_addr_t)(regs)->tf_spc)
#define PC_ADVANCE(regs) ((regs)->tf_spc += BKPT_SIZE)

#define	BKPT_INST	0xc3c3		/* breakpoint instruction */
#define	BKPT_SIZE	2		/* size of breakpoint inst */
#define	BKPT_SET(inst)	BKPT_INST

#define	FIXUP_PC_AFTER_BREAK(regs)	((regs)->tf_spc -= BKPT_SIZE)

#define	IS_BREAKPOINT_TRAP(type, code)	((type) == EXPEVT_TRAPA)
#define	IS_WATCHPOINT_TRAP(type, code)	(0) /* XXX (msaitoh) */

int kdb_trap(int, int, db_regs_t *);
void db_machine_init (void);
boolean_t inst_call(int);
boolean_t inst_return(int);
boolean_t inst_trap_return(int);

/*
 * We have machine-dependent commands.
 */
#define	DB_MACHINE_COMMANDS

#endif	/* !_SH_DB_MACHDEP_H_ */


code:
/*	$OpenBSD: devreg.h,v 1.3 2008/06/26 05:42:12 ray Exp $	*/
/*	$NetBSD: devreg.h,v 1.5 2006/01/21 04:57:07 uwe Exp $	*/

/*-
 * Copyright (c) 2002 The NetBSD Foundation, Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef _SH_DEVREG_H_
#define	_SH_DEVREG_H_
/*
 * SH embedded device register defines.
 */

/*
 * Access method
 */
#define	_reg_read_1(a)		(*(volatile uint8_t *)((vaddr_t)(a)))
#define	_reg_read_2(a)		(*(volatile uint16_t *)((vaddr_t)(a)))
#define	_reg_read_4(a)		(*(volatile uint32_t *)((vaddr_t)(a)))
#define	_reg_write_1(a, v)						\
	(*(volatile uint8_t *)(a)  = (uint8_t)(v))
#define	_reg_write_2(a, v)						\
	(*(volatile uint16_t *)(a) = (uint16_t)(v))
#define	_reg_write_4(a, v)						\
	(*(volatile uint32_t *)(a) = (uint32_t)(v))
#define	_reg_bset_1(a, v)						\
	(*(volatile uint8_t *)(a)  |= (uint8_t)(v))
#define	_reg_bset_2(a, v)						\
	(*(volatile uint16_t *)(a) |= (uint16_t)(v))
#define	_reg_bset_4(a, v)						\
	(*(volatile uint32_t *)(a) |= (uint32_t)(v))
#define	_reg_bclr_1(a, v)						\
	(*(volatile uint8_t *)(a)  &= ~(uint8_t)(v))
#define	_reg_bclr_2(a, v)						\
	(*(volatile uint16_t *)(a) &= ~(uint16_t)(v))
#define	_reg_bclr_4(a, v)						\
	(*(volatile uint32_t *)(a) &= ~(uint32_t)(v))

/*
 * Register address.
 */
#if defined(SH3) && defined(SH4)
#define	SH_(x)		__sh_ ## x
#elif defined(SH3)
#define	SH_(x)		SH3_ ## x
#elif defined(SH4)
#define	SH_(x)		SH4_ ## x
#endif

#ifndef _LOCORE
/* Initialize register address for SH3 && SH4 kernel. */
void sh_devreg_init(void);
#endif
#endif /* !_SH_DEVREG_H_ */