code:
/*	$OpenBSD: ar9003reg.h,v 1.8 2012/10/20 09:53:32 stsp Exp $	*/

/*-
 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr>
 * Copyright (c) 2010 Atheros Communications Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

/*
 * MAC registers.
 */
#define AR_ISR_S2_S			0x00d0
#define AR_ISR_S3_S			0x00d4
#define AR_ISR_S4_S			0x00d8
#define AR_ISR_S5_S			0x00dc
#define AR_GPIO_IN_OUT			0x4048
#define AR_GPIO_IN			0x404c
#define AR9300_GPIO_IN_VAL		0x0001FFFF
#define AR_GPIO_OE_OUT			0x4050
#define AR_GPIO_INTR_POL		0x4058
#define AR_GPIO_INPUT_EN_VAL		0x405c
#define AR_GPIO_INPUT_MUX1		0x4060
#define AR_GPIO_INPUT_MUX2		0x4064
#define AR_GPIO_OUTPUT_MUX(i)		(0x4068 + (i) * 4)
#define AR_INPUT_STATE			0x4074
#define AR_EEPROM_STATUS_DATA		0x4084
#define AR_OBS				0x4088
#define AR_GPIO_PDPU			0x4090
#define AR_PCIE_MSI			0x40a4
#define AR_ENT_OTP			0x40d8

/* Bits for AR_ENT_OTP. */
#define AR_ENT_OTP_CHAIN2_DISABLE	0x00020000
#define AR_ENT_OTP_MPSD			0x00800000

/*
 * PHY registers.
 */
#define AR_PHY_TIMING1			0x09800
#define AR_PHY_TIMING2			0x09804
#define AR_PHY_TIMING3			0x09808
#define AR_PHY_TIMING4			0x0980c
#define AR_PHY_TIMING5			0x09810
#define AR_PHY_TIMING6			0x09814
#define AR_PHY_TIMING11			0x09818
#define AR_PHY_SPUR_REG			0x0981c
#define AR_PHY_FIND_SIG_LOW		0x09820
#define AR_PHY_SFCORR			0x09824
#define AR_PHY_SFCORR_LOW		0x09828
#define AR_PHY_SFCORR_EXT		0x0982c
#define AR_PHY_EXT_CCA(i)		(0x09830 + (i) * 0x1000)
#define AR_PHY_RADAR_0			0x09834
#define AR_PHY_RADAR_1			0x09838
#define AR_PHY_RADAR_EXT		0x0983c
#define AR_PHY_MULTICHAIN_CTRL		0x09880
#define AR_PHY_PERCHAIN_CSD		0x09884
#define AR_PHY_TX_CRC			0x098a0
#define AR_PHY_TST_DAC_CONST		0x098a4
#define AR_PHY_SPUR_REPORT_0		0x098a8
#define AR_PHY_TX_IQCAL_CONTROL_3	0x098b0
#define AR_PHY_IQ_ADC_MEAS_0_B(i)	(0x098c0 + (i) * 0x1000)
#define AR_PHY_IQ_ADC_MEAS_1_B(i)	(0x098c4 + (i) * 0x1000)
#define AR_PHY_IQ_ADC_MEAS_2_B(i)	(0x098c8 + (i) * 0x1000)
#define AR_PHY_IQ_ADC_MEAS_3_B(i)	(0x098cc + (i) * 0x1000)
#define AR_PHY_TX_PHASE_RAMP_0		0x098d0
#define AR_PHY_ADC_DC_GAIN_CORR(i)	(0x098d4 + (i) * 0x1000)
#define AR_PHY_RX_IQCAL_CORR_B(i)	(0x098dc + (i) * 0x1000)
#define AR_PHY_PAPRD_AM2AM		0x098e4
#define AR_PHY_PAPRD_AM2PM		0x098e8
#define AR_PHY_PAPRD_HT40		0x098ec
#define AR_PHY_PAPRD_CTRL0_B(i)		(0x098f0 + (i) * 0x1000)
#define AR_PHY_PAPRD_CTRL1_B(i)		(0x098f4 + (i) * 0x1000)
#define AR_PHY_PA_GAIN123_B(i)		(0x098f8 + (i) * 0x1000)
#define AR_PHY_PAPRD_PRE_POST_SCALE_B0(i)	\
					(0x09900 + (i) * 4)
#define AR_PHY_PAPRD_MEM_TAB_B(i, j)	(0x09920 + (i) * 0x1000 + (j) * 4)
#define AR_PHY_CHAN_INFO_TAB(i, j)	(0x09b00 + (i) * 0x1000 + (j) * 4)
#define AR_PHY_TIMING_3A		0x09c00
#define AR_PHY_LDPC_CNTL1		0x09c04
#define AR_PHY_LDPC_CNTL2		0x09c08
#define AR_PHY_PILOT_SPUR_MASK		0x09c0c
#define AR_PHY_CHAN_SPUR_MASK		0x09c10
#define AR_PHY_SGI_DELTA		0x09c14
#define AR_PHY_ML_CNTL_1		0x09c18
#define AR_PHY_ML_CNTL_2		0x09c1c
#define AR_PHY_TST_ADC			0x09c20
#define AR_PHY_SETTLING			0x09e00
#define AR_PHY_RXGAIN(i)		(0x09e04 + (i) * 0x1000)
#define AR_PHY_GAINS_MINOFF0		0x09e08
#define AR_PHY_DESIRED_SZ		0x09e0c
#define AR_PHY_FIND_SIG			0x09e10
#define AR_PHY_AGC			0x09e14
#define AR_PHY_EXT_ATTEN_CTL(i)		(0x09e18 + (i) * 0x1000)
#define AR_PHY_CCA(i)			(0x09e1c + (i) * 0x1000)
#define AR_PHY_CCA_CTRL(i)		(0x09e20 + (i) * 0x1000)
#define AR_PHY_RESTART			0x09e24
#define AR_PHY_MC_GAIN_CTRL		0x09e28
#define AR_PHY_EXTCHN_PWRTHR1		0x09e2c
#define AR_PHY_EXT_CHN_WIN		0x09e30
#define AR_PHY_20_40_DET_THR		0x09e34
#define AR_PHY_RIFS_SRCH		0x09e38
#define AR_PHY_PEAK_DET_CTRL_1		0x09e3c
#define AR_PHY_PEAK_DET_CTRL_2		0x09e40
#define AR_PHY_RX_GAIN_BOUNDS_1		0x09e44
#define AR_PHY_RX_GAIN_BOUNDS_2		0x09e48
#define AR_PHY_RSSI(i)			(0x09f80 + (i) * 0x1000)
#define AR_PHY_SPUR_CCK_REP0		0x09f84
#define AR_PHY_CCK_DETECT		0x09fc0
#define AR_PHY_DAG_CTRLCCK		0x09fc4
#define AR_PHY_IQCORR_CTRL_CCK		0x09fc8
#define AR_PHY_CCK_SPUR_MIT		0x09fcc
#define AR_PHY_RX_OCGAIN		0x0a000
#define AR_PHY_D2_CHIP_ID		0x0a200
#define AR_PHY_GEN_CTRL			0x0a204
#define AR_PHY_MODE			0x0a208
#define AR_PHY_ACTIVE			0x0a20c
#define AR_PHY_SPUR_MASK_A		0x0a220
#define AR_PHY_SPUR_MASK_B		0x0a224
#define AR_PHY_SPECTRAL_SCAN		0x0a228
#define AR_PHY_RADAR_BW_FILTER		0x0a22c
#define AR_PHY_SEARCH_START_DELAY	0x0a230
#define AR_PHY_MAX_RX_LEN		0x0a234
#define AR_PHY_FRAME_CTL		0x0a238
#define AR_PHY_RFBUS_REQ		0x0a23c
#define AR_PHY_RFBUS_GRANT		0x0a240
#define AR_PHY_RIFS			0x0a244
#define AR_PHY_RX_CLR_DELAY		0x0a250
#define AR_PHY_RX_DELAY			0x0a254
#define AR_PHY_XPA_TIMING_CTL		0x0a264
#define AR_PHY_MISC_PA_CTL		0x0a280
#define AR_PHY_SWITCH_CHAIN(i)		(0x0a284 + (i) * 0x1000)
#define AR_PHY_SWITCH_COM		0x0a288
#define AR_PHY_SWITCH_COM_2		0x0a28c
#define AR_PHY_RX_CHAINMASK		0x0a2a0
#define AR_PHY_CAL_CHAINMASK		0x0a2c0
#define AR_PHY_AGC_CONTROL		0x0a2c4
#define AR_PHY_CALMODE			0x0a2c8
#define AR_PHY_FCAL_1			0x0a2cc
#define AR_PHY_FCAL_2_0			0x0a2d0
#define AR_PHY_DFT_TONE_CTL_0		0x0a2d4
#define AR_PHY_CL_CAL_CTL		0x0a2d8
#define AR_PHY_CL_TAB_0			0x0a300
#define AR_PHY_SYNTH_CONTROL		0x0a340
#define AR_PHY_ADDAC_CLK_SEL		0x0a344
#define AR_PHY_PLL_CTL			0x0a348
#define AR_PHY_ANALOG_SWAP		0x0a34c
#define AR_PHY_ADDAC_PARA_CTL		0x0a350
#define AR_PHY_XPA_CFG			0x0a358
#define AR_PHY_TEST			0x0a360
#define AR_PHY_TEST_CTL_STATUS		0x0a364
#define AR_PHY_TSTDAC			0x0a368
#define AR_PHY_CHAN_STATUS		0x0a36c
#define AR_PHY_CHAN_INFO_MEMORY		0x0a370
#define AR_PHY_CHNINFO_NOISEPWR		0x0a374
#define AR_PHY_CHNINFO_GAINDIFF		0x0a378
#define AR_PHY_CHNINFO_FINETIM		0x0a37c
#define AR_PHY_CHAN_INFO_GAIN_0		0x0a380
#define AR_PHY_SCRAMBLER_SEED		0x0a390
#define AR_PHY_CCK_TX_CTRL		0x0a394
#define AR_PHY_HEAVYCLIP_CTL		0x0a3a4
#define AR_PHY_HEAVYCLIP_20		0x0a3a8
#define AR_PHY_HEAVYCLIP_40		0x0a3ac
#define AR_PHY_ILLEGAL_TXRATE		0x0a3b0
#define AR_PHY_PWRTX_RATE1		0x0a3c0
#define AR_PHY_PWRTX_RATE2		0x0a3c4
#define AR_PHY_PWRTX_RATE3		0x0a3c8
#define AR_PHY_PWRTX_RATE4		0x0a3cc
#define AR_PHY_PWRTX_RATE5		0x0a3d0
#define AR_PHY_PWRTX_RATE6		0x0a3d4
#define AR_PHY_PWRTX_RATE7		0x0a3d8
#define AR_PHY_PWRTX_RATE8		0x0a3dc
#define AR_PHY_PWRTX_RATE10		0x0a3e4
#define AR_PHY_PWRTX_RATE11		0x0a3e8
#define AR_PHY_PWRTX_RATE12		0x0a3ec
#define AR_PHY_PWRTX_MAX		0x0a3f0
#define AR_PHY_POWER_TX_SUB		0x0a3f4
#define AR_PHY_TPC_1			0x0a3f8
#define AR_PHY_TPC_4_B(i)		(0x0a404 + (i) * 0x1000)
#define AR_PHY_TPC_5_B(i)		(0x0a408 + (i) * 0x1000)
#define AR_PHY_TPC_6_B(i)		(0x0a40c + (i) * 0x1000)
#define AR_PHY_TPC_11_B(i)		(0x0a420 + (i) * 0x1000)
#define AR_PHY_TPC_12			0x0a424
#define AR_PHY_TPC_18			0x0a43c
#define AR_PHY_TPC_19			0x0a440
#define AR_PHY_BB_THERM_ADC_1		0x0a448
#define AR_PHY_BB_THERM_ADC_4		0x0a454
#define AR_PHY_TX_FORCED_GAIN		0x0a458
#define AR_PHY_PDADC_TAB(i)		(0x0a480 + (i) * 0x1000)
#define AR_PHY_TXGAIN_TABLE(i)		(0x0a500 + (i) * 4)
#define AR_PHY_TX_IQCAL_CONTROL_1	0x0a648
#define AR_PHY_TX_IQCAL_START		0x0a640
#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B(i)	\
					(0x0a650 + (i) * 0x1000)
#define AR_PHY_TX_IQCAL_STATUS_B(i)	(0x0a68c + (i) * 0x1000)
#define AR_PHY_PAPRD_TRAINER_CNTL1	0x0a690
#define AR_PHY_PAPRD_TRAINER_CNTL2	0x0a694
#define AR_PHY_PAPRD_TRAINER_CNTL3	0x0a698
#define AR_PHY_PAPRD_TRAINER_CNTL4	0x0a69c
#define AR_PHY_PAPRD_TRAINER_STAT1	0x0a6a0
#define AR_PHY_PAPRD_TRAINER_STAT2	0x0a6a4
#define AR_PHY_PAPRD_TRAINER_STAT3	0x0a6a8
#define AR_PHY_PANIC_WD_STATUS		0x0a7c0
#define AR_PHY_PANIC_WD_CTL_1		0x0a7c4
#define AR_PHY_PANIC_WD_CTL_2		0x0a7c8
#define AR_PHY_BT_CTL			0x0a7cc
#define AR_PHY_ONLY_WARMRESET		0x0a7d0
#define AR_PHY_ONLY_CTL			0x0a7d4
#define AR_PHY_ECO_CTRL			0x0a7dc

/*
 * Analog registers.
 */
#define AR_IS_ANALOG_REG(reg)		((reg) >= 0x16000 && (reg) <= 0x17000)
#define AR_PHY_65NM_CH0_SYNTH4		0x1608c
#define AR_PHY_65NM_CH0_SYNTH7		0x16098
#define AR_PHY_65NM_CH0_BIAS1		0x160c0
#define AR_PHY_65NM_CH0_BIAS2		0x160c4
#define AR_PHY_65NM_CH0_BIAS4		0x160cc
#define AR_PHY_65NM_CH0_RXTX1		0x16100
#define AR_PHY_65NM_CH0_RXTX2		0x16104
#define AR_PHY_65NM_CH0_RXTX4		0x1610c
#define AR9485_PHY_65NM_CH0_TOP2	0x16284
#define AR_PHY_65NM_CH0_TOP		0x16288
#define AR_PHY_65NM_CH0_THERM		0x16290
#define AR9485_PHY_CH0_XTAL		0x16290
#define AR_PHY_65NM_CH1_RXTX1		0x16500
#define AR_PHY_65NM_CH1_RXTX2		0x16504
#define AR_PHY_65NM_CH2_RXTX1		0x16900
#define AR_PHY_65NM_CH2_RXTX2		0x16904
#define AR_PHY_PMU1			0x16c40
#define AR_PHY_PMU2			0x16c44

/* Bits for AR_PHY_TIMING2. */
#define AR_PHY_TIMING2_FORCE_PPM_VAL_M	0x00000fff
#define AR_PHY_TIMING2_FORCE_PPM_VAL_S	0
#define AR_PHY_TIMING2_USE_FORCE_PPM	0x00001000

/* Bits for AR_PHY_TIMING3. */
#define AR_PHY_TIMING3_DSC_EXP_M	0x0001e000
#define AR_PHY_TIMING3_DSC_EXP_S	13
#define AR_PHY_TIMING3_DSC_MAN_M	0xfffe0000
#define AR_PHY_TIMING3_DSC_MAN_S	17

/* Bits for AR_PHY_TIMING4. */
#define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX_M	0x0000f000
#define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX_S	12
#define AR_PHY_TIMING4_DO_CAL			0x00010000
#define AR_PHY_TIMING4_ENABLE_PILOT_MASK	0x10000000
#define AR_PHY_TIMING4_ENABLE_CHAN_MASK		0x20000000
#define AR_PHY_TIMING4_ENABLE_SPUR_FILTER	0x40000000
#define AR_PHY_TIMING4_ENABLE_SPUR_RSSI		0x80000000

/* Bits for AR_PHY_TIMING5. */
#define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE	0x00000001
#define AR_PHY_TIMING5_CYCPWR_THR1_M		0x000000fe
#define AR_PHY_TIMING5_CYCPWR_THR1_S		1
#define AR_PHY_TIMING5_RSSI_THR1A_ENA		0x00008000
#define AR_PHY_TIMING5_CYCPWR_THR1A_M		0x007f0000
#define AR_PHY_TIMING5_CYCPWR_THR1A_S		16
#define AR_PHY_TIMING5_RSSI_THR1A_M		0x007f0000
#define AR_PHY_TIMING5_RSSI_THR1A_S		16

/* Bits for AR_PHY_TIMING11. */
#define AR_PHY_TIMING11_SPUR_DELTA_PHASE_M		0x000fffff
#define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S		0
#define AR_PHY_TIMING11_SPUR_FREQ_SD_M			0x3ff00000
#define AR_PHY_TIMING11_SPUR_FREQ_SD_S			20
#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC		0x40000000
#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR	0x80000000

/* Bits for AR_PHY_SPUR_REG. */
#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_M	0x000000ff
#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S	0
#define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI	0x00000100
#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM		0x00020000
#define AR_PHY_SPUR_REG_MASK_RATE_CNTL_M	0x03fc0000
#define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S	18
#define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT	0x04000000

/* Bits for AR_PHY_FIND_SIG_LOW. */
#define AR_PHY_FIND_SIG_LOW_RELSTEP_M		0x0000001f
#define AR_PHY_FIND_SIG_LOW_RELSTEP_S		0
#define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW_M	0x00000fc0
#define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW_S	6
#define AR_PHY_FIND_SIG_LOW_FIRPWR_M		0x0007f000
#define AR_PHY_FIND_SIG_LOW_FIRPWR_S		12

/* Bits for AR_PHY_SFCORR. */
#define AR_PHY_SFCORR_M2COUNT_THR_M		0x0000001f
#define AR_PHY_SFCORR_M2COUNT_THR_S		0
#define AR_PHY_SFCORR_M1_THRESH_M		0x00fe0000
#define AR_PHY_SFCORR_M1_THRESH_S		17
#define AR_PHY_SFCORR_M2_THRESH_M		0x7f000000
#define AR_PHY_SFCORR_M2_THRESH_S		24

/* Bits for AR_PHY_SFCORR_LOW. */
#define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW	0x00000001
#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_M	0x00003f00
#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S	8
#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_M	0x001fc000
#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S	14
#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_M	0x0fe00000
#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S	21

/* Bits for AR_PHY_SFCORR_EXT. */
#define AR_PHY_SFCORR_EXT_M1_THRESH_M		0x0000007f
#define AR_PHY_SFCORR_EXT_M1_THRESH_S		0
#define AR_PHY_SFCORR_EXT_M2_THRESH_M		0x00003f80
#define AR_PHY_SFCORR_EXT_M2_THRESH_S		7
#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_M	0x001fc000
#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S	14
#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_M	0x0fe00000
#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S	21
#define AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD	0x10000000

/* Bits for AR_PHY_RADAR_0. */
#define AR_PHY_RADAR_0_ENA		0x00000001
#define AR_PHY_RADAR_0_INBAND_M		0x0000003e
#define AR_PHY_RADAR_0_INBAND_S		1
#define AR_PHY_RADAR_0_PRSSI_M		0x00000fc0
#define AR_PHY_RADAR_0_PRSSI_S		6
#define AR_PHY_RADAR_0_HEIGHT_M		0x0003f000
#define AR_PHY_RADAR_0_HEIGHT_S		12
#define AR_PHY_RADAR_0_RRSSI_M		0x00fc0000
#define AR_PHY_RADAR_0_RRSSI_S		18
#define AR_PHY_RADAR_0_FIRPWR_M		0x7f000000
#define AR_PHY_RADAR_0_FIRPWR_S		24
#define AR_PHY_RADAR_0_FFT_ENA		0x80000000

/* Bits for AR_PHY_RADAR_1. */
#define AR_PHY_RADAR_1_MAXLEN_M		0x000000ff
#define AR_PHY_RADAR_1_MAXLEN_S		0
#define AR_PHY_RADAR_1_RELSTEP_THRESH_M	0x00001f00
#define AR_PHY_RADAR_1_RELSTEP_THRESH_S	8
#define AR_PHY_RADAR_1_RELSTEP_CHECK	0x00002000
#define AR_PHY_RADAR_1_MAX_RRSSI	0x00004000
#define AR_PHY_RADAR_1_BLOCK_CHECK	0x00008000
#define AR_PHY_RADAR_1_RELPWR_THRESH_M	0x003f0000
#define AR_PHY_RADAR_1_RELPWR_THRESH_S	16
#define AR_PHY_RADAR_1_USE_FIR128	0x00400000
#define AR_PHY_RADAR_1_RELPWR_ENA	0x00800000

/* Bits for AR_PHY_RADAR_EXT. */
#define AR_PHY_RADAR_EXT_ENA		0x00004000
#define AR_PHY_RADAR_DC_PWR_THRESH_M	0x007f8000
#define AR_PHY_RADAR_DC_PWR_THRESH_S	15
#define AR_PHY_RADAR_LB_DC_CAP_M  	0x7f800000
#define AR_PHY_RADAR_LB_DC_CAP_S	23

/* Bits for AR_PHY_TX_IQCAL_CONTROL_3. */
#define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN	0x80000000

/* Bits for AR_PHY_RX_IQCAL_CORR_B(0). */
#define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF_M		0x0000007f
#define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF_S		0
#define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF_M		0x00003f80
#define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF_S		7
#define AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE		0x00004000
#define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF_M	0x003f8000
#define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF_S	15
#define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF_M	0x1fc00000
#define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF_S	22
#define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN	0x20000000

/* Bits for AR_PHY_PAPRD_AM2AM. */
#define AR_PHY_PAPRD_AM2AM_MASK_M	0x01ffffff
#define AR_PHY_PAPRD_AM2AM_MASK_S	0

/* Bits for AR_PHY_PAPRD_AM2PM. */
#define AR_PHY_PAPRD_AM2PM_MASK_M	0x01ffffff
#define AR_PHY_PAPRD_AM2PM_MASK_S	0

/* Bits for AR_PHY_PAPRD_HT40. */
#define AR_PHY_PAPRD_HT40_MASK_M	0x01ffffff
#define AR_PHY_PAPRD_HT40_MASK_S	0

/* Bits for AR_PHY_PAPRD_CTRL0_B(i). */
#define AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE		0x00000001
#define AR_PHY_PAPRD_CTRL0_USE_SINGLE_TABLE	0x00000002
#define AR_PHY_PAPRD_CTRL0_PAPRD_MAG_THRSH_M	0xf8000000
#define AR_PHY_PAPRD_CTRL0_PAPRD_MAG_THRSH_S	27

/* Bits for AR_PHY_PAPRD_CTRL1_B(i). */
#define AR_PHY_PAPRD_CTRL1_ADAPTIVE_SCALING_ENA		0x00000001
#define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2AM_ENA		0x00000002
#define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2PM_ENA		0x00000004
#define AR_PHY_PAPRD_CTRL1_POWER_AT_AM2AM_CAL_M		0x000001f8
#define AR_PHY_PAPRD_CTRL1_POWER_AT_AM2AM_CAL_S		3
#define AR_PHY_PAPRD_CTRL1_PA_GAIN_SCALE_FACT_M		0x0001fe00
#define AR_PHY_PAPRD_CTRL1_PA_GAIN_SCALE_FACT_S		9
#define AR_PHY_PAPRD_CTRL1_MAG_SCALE_FACT_M		0x0ffe0000
#define AR_PHY_PAPRD_CTRL1_MAG_SCALE_FACT_S		17

/* Bits for AR_PHY_PA_GAIN123_B(i). */
#define AR_PHY_PA_GAIN123_PA_GAIN1_M	0x000003ff
#define AR_PHY_PA_GAIN123_PA_GAIN1_S	0

/* Bits for AR_PHY_PAPRD_PRE_POST_SCALE_B0(i). */
#define AR_PHY_PAPRD_PRE_POST_SCALING_M	0x0003ffff
#define AR_PHY_PAPRD_PRE_POST_SCALING_S	0

/* Bits for AR_PHY_PAPRD_MEM_TAB_B(i). */
#define AR_PHY_PAPRD_ANGLE_M	0x000007ff
#define AR_PHY_PAPRD_ANGLE_S	0
#define AR_PHY_PAPRD_PA_IN_M	0x003ff800
#define AR_PHY_PAPRD_PA_IN_S	11

/* Bits for AR_PHY_PILOT_SPUR_MASK. */
#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A_M	0x0000001f
#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A_S	0
#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_M	0x00000fe0
#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_S	5

/* Bits for AR_PHY_CHAN_SPUR_MASK. */
#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A_M		0x0000001f
#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A_S		0
#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_M	0x00000fe0
#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_S	5

/* Bits for AR_PHY_SGI_DELTA. */
#define AR_PHY_SGI_DSC_EXP_M	0x0000000f
#define AR_PHY_SGI_DSC_EXP_S	0
#define AR_PHY_SGI_DSC_MAN_M	0x0007fff0
#define AR_PHY_SGI_DSC_MAN_S	4

/* Bits for AR_PHY_SETTLING. */
#define AR_PHY_SETTLING_SWITCH_M	0x00003f80
#define AR_PHY_SETTLING_SWITCH_S	7

/* Bits for AR_PHY_RXGAIN(i). */
#define AR_PHY_RXGAIN_TXRX_ATTEN_M	0x0003f000
#define AR_PHY_RXGAIN_TXRX_ATTEN_S	12
#define AR_PHY_RXGAIN_TXRX_RF_MAX_M	0x007c0000
#define AR_PHY_RXGAIN_TXRX_RF_MAX_S	18

/* Bits for AR_PHY_DESIRED_SZ. */
#define AR_PHY_DESIRED_SZ_ADC_M		0x000000ff
#define AR_PHY_DESIRED_SZ_ADC_S		0
#define AR_PHY_DESIRED_SZ_PGA_M		0x0000ff00
#define AR_PHY_DESIRED_SZ_PGA_S		8
#define AR_PHY_DESIRED_SZ_TOT_DES_M	0x0ff00000
#define AR_PHY_DESIRED_SZ_TOT_DES_S	20

/* Bits for AR_PHY_FIND_SIG. */
#define AR_PHY_FIND_SIG_RELSTEP_M	0x0000001f
#define AR_PHY_FIND_SIG_RELSTEP_S	0
#define AR_PHY_FIND_SIG_RELPWR_M	0x000007c0
#define AR_PHY_FIND_SIG_RELPWR_S	6
#define AR_PHY_FIND_SIG_FIRSTEP_M	0x0003f000
#define AR_PHY_FIND_SIG_FIRSTEP_S	12
#define AR_PHY_FIND_SIG_FIRPWR_M	0x03fc0000
#define AR_PHY_FIND_SIG_FIRPWR_S	18

/* Bits for AR_PHY_AGC. */
#define AR_PHY_AGC_COARSE_PWR_CONST_M	0x0000007f
#define AR_PHY_AGC_COARSE_PWR_CONST_S	0
#define AR_PHY_AGC_COARSE_LOW_M		0x00007f80
#define AR_PHY_AGC_COARSE_LOW_S		7
#define AR_PHY_AGC_COARSE_HIGH_M	0x003f8000
#define AR_PHY_AGC_COARSE_HIGH_S	15

/* Bits for AR_PHY_EXT_ATTEN_CTL(i). */
#define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN_M	0x0000001f
#define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN_S	0
#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB_M	0x0000003f
#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB_S	0
#define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB_M	0x00000fc0
#define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB_S	6
#define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN_M	0x00003c00
#define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN_S	10
#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN_M	0x0001f000
#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN_S	12
#define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN_M	0x003e0000
#define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN_S	17
#define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN_M	0x00fc0000
#define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN_S	18

/* Bits for AR_PHY_CCA(i). */
#define AR_PHY_MAXCCA_PWR_M	0x000001ff
#define AR_PHY_MAXCCA_PWR_S	0
#define AR_PHY_MINCCA_PWR_M	0x1ff00000
#define AR_PHY_MINCCA_PWR_S	20

/* Bits for AR_PHY_EXT_CCA(i). */
#define AR_PHY_EXT_MAXCCA_PWR_M		0x000001ff
#define AR_PHY_EXT_MAXCCA_PWR_S		0
#define AR_PHY_EXT_MINCCA_PWR_M		0x01ff0000
#define AR_PHY_EXT_MINCCA_PWR_S		16

/* Bits for AR_PHY_RESTART. */
#define AR_PHY_RESTART_ENA	0x00000001
#define AR_PHY_RESTART_DIV_GC_M	0x001c0000
#define AR_PHY_RESTART_DIV_GC_S	18

/* Bits for AR_PHY_MC_GAIN_CTRL. */
#define AR_PHY_MC_GAIN_CTRL_ENABLE_ANT_DIV	0x01000000
#define AR_PHY_MC_GAIN_CTRL_ANT_DIV_CTRL_ALL_M	0x7e000000
#define AR_PHY_MC_GAIN_CTRL_ANT_DIV_CTRL_ALL_S	25

/* Bits for AR_PHY_CCK_DETECT. */
#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_M		0x0000003f
#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S		0
#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_M		0x00001fc0
#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S		6
#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV	0x00002000

/* Bits for AR_PHY_DAG_CTRLCCK. */
#define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR	0x00000200
#define AR_PHY_DAG_CTRLCCK_RSSI_THR_M	0x0001fc00
#define AR_PHY_DAG_CTRLCCK_RSSI_THR_S	10

/* Bits for AR_PHY_CCK_SPUR_MIT. */
#define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT	0x00000001
#define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR_M	0x000001fe
#define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR_S	1
#define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ_M	0x1ffffe00
#define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ_S	9
#define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE_M	0x60000000
#define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE_S  29

/* Bits for AR_PHY_GEN_CTRL. */
#define AR_PHY_GC_TURBO_MODE		0x00000001
#define AR_PHY_GC_TURBO_SHORT		0x00000002
#define AR_PHY_GC_DYN2040_EN		0x00000004
#define AR_PHY_GC_DYN2040_PRI_ONLY	0x00000008
#define AR_PHY_GC_DYN2040_PRI_CH	0x00000010
#define AR_PHY_GC_DYN2040_EXT_CH	0x00000020
#define AR_PHY_GC_HT_EN			0x00000040
#define AR_PHY_GC_SHORT_GI_40		0x00000080
#define AR_PHY_GC_WALSH			0x00000100
#define AR_PHY_GC_SINGLE_HT_LTF1	0x00000200
#define AR_PHY_GC_GF_DETECT_EN		0x00000400
#define AR_PHY_GC_ENABLE_DAC_FIFO	0x00000800

/* Bits for AR_PHY_MODE. */
#define AR_PHY_MODE_OFDM		0x00000000
#define AR_PHY_MODE_CCK			0x00000001
#define AR_PHY_MODE_DYNAMIC		0x00000004
#define AR_PHY_MODE_HALF		0x00000020
#define AR_PHY_MODE_QUARTER		0x00000040
#define AR_PHY_MODE_DYN_CCK_DISABLE	0x00000100
#define AR_PHY_MODE_SVD_HALF		0x00000200

/* Bits for AR_PHY_ACTIVE. */
#define AR_PHY_ACTIVE_DIS	0x00000000
#define AR_PHY_ACTIVE_EN	0x00000001

/* Bits for AR_PHY_SPUR_MASK_A. */
#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A_M	0x000003ff
#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A_S	0
#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_M	0x0001fc00
#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_S	10

/* Bits for AR_PHY_SPECTRAL_SCAN. */
#define AR_PHY_SPECTRAL_SCAN_ENABLE		0x00000001
#define AR_PHY_SPECTRAL_SCAN_ACTIVE		0x00000002
#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_M	0x000000f0
#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S	4
#define AR_PHY_SPECTRAL_SCAN_PERIOD_M		0x0000ff00
#define AR_PHY_SPECTRAL_SCAN_PERIOD_S		8
#define AR_PHY_SPECTRAL_SCAN_COUNT_M		0x00ff0000
#define AR_PHY_SPECTRAL_SCAN_COUNT_S		16
#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT	0x01000000

/* Bits for AR_PHY_RFBUS_REQ. */
#define AR_PHY_RFBUS_REQ_EN	0x00000001

/* Bits for AR_PHY_RFBUS_GRANT. */
#define AR_PHY_RFBUS_GRANT_EN	0x00000001

/* Bits for AR_PHY_RIFS. */
#define AR_PHY_RIFS_INIT_DELAY	0x3ff0000

/* Bits for AR_PHY_RX_DELAY. */
#define AR_PHY_RX_DELAY_DELAY_M	0x00003fff
#define AR_PHY_RX_DELAY_DELAY_S	0

/* Bits for AR_PHY_XPA_TIMING_CTL. */
#define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON_M	0x000000ff
#define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON_S	0
#define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON_M	0x0000ff00
#define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON_S	8
#define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF_M	0x00ff0000
#define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF_S	16
#define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF_M	0xff000000
#define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF_S	24

/* Bits for AR_PHY_SWITCH_CHAIN. */
#define AR_SWITCH_TABLE_ALL_M	0x00000fff
#define AR_SWITCH_TABLE_ALL_S	0

/* Bits for AR_PHY_SWITCH_COM. */
#define AR_SWITCH_TABLE_COM_ALL_M	0x0000ffff
#define AR_SWITCH_TABLE_COM_ALL_S	0

/* Bits for AR_SWITCH_TABLE_COM_2. */
#define AR_SWITCH_TABLE_COM_2_ALL_M	0x00ffffff
#define AR_SWITCH_TABLE_COM_2_ALL_S	0

/* Bits for AR_PHY_AGC_CONTROL. */
#define AR_PHY_AGC_CONTROL_CAL			0x00000001
#define AR_PHY_AGC_CONTROL_NF			0x00000002
#define AR_PHY_AGC_CONTROL_YCOK_MAX_M		0x000003c0
#define AR_PHY_AGC_CONTROL_YCOK_MAX_S		6
#define AR_PHY_AGC_CONTROL_OFFSET_CAL		0x00000800
#define AR_PHY_AGC_CONTROL_ENABLE_NF		0x00008000
#define AR_PHY_AGC_CONTROL_FLTR_CAL		0x00010000
#define AR_PHY_AGC_CONTROL_NO_UPDATE_NF		0x00020000
#define AR_PHY_AGC_CONTROL_EXT_NF_PWR_MEAS	0x00040000
#define AR_PHY_AGC_CONTROL_CLC_SUCCESS		0x00080000

/* Bits for AR_PHY_CALMODE. */
#define AR_PHY_CALMODE_IQ		0x00000000
#define AR_PHY_CALMODE_ADC_GAIN		0x00000001
#define AR_PHY_CALMODE_ADC_DC_PER	0x00000002
#define AR_PHY_CALMODE_ADC_DC_INIT	0x00000003

/* Bits for AR_PHY_FCAL_2_0. */
#define AR_PHY_FCAL20_CAP_STATUS_0_M	0x01f00000
#define AR_PHY_FCAL20_CAP_STATUS_0_S	20

/* Bits for AR_PHY_SYNTH_CONTROL. */
#define AR9380_BMODE	0x20000000

/* Bits for AR_PHY_ANALOG_SWAP. */
#define AR_PHY_SWAP_ALT_CHAIN	0x00000040

/* Bits for AR_PHY_ADDAC_PARA_CTL. */
#define AR_PHY_ADDAC_PARACTL_OFF_PWDADC	0x00008000

/* Bits for AR_PHY_TEST. */
#define AR_PHY_TEST_RFSILENT_BB		0x00002000
#define AR_PHY_TEST_BBB_OBS_SEL_M	0x00780000
#define AR_PHY_TEST_BBB_OBS_SEL_S	19
#define AR_PHY_TEST_RX_OBS_SEL_BIT5	0x00800000
#define AR_PHY_TEST_CHAIN_SEL_M		0xc0000000
#define AR_PHY_TEST_CHAIN_SEL_S		30

/* Bits for AR_PHY_TEST_CTL_STATUS. */
#define AR_PHY_TEST_CTL_TSTDAC_EN		0x00000001
#define AR_PHY_TEST_CTL_TX_OBS_SEL_M		0x0000001c
#define AR_PHY_TEST_CTL_TX_OBS_SEL_S		2
#define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL_M	0x00000060
#define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL_S	5
#define AR_PHY_TEST_CTL_TSTADC_EN		0x00000100
#define AR_PHY_TEST_CTL_RX_OBS_SEL_M		0x00003c00
#define AR_PHY_TEST_CTL_RX_OBS_SEL_S		10

/* Bits for AR_PHY_CHAN_INFO_MEMORY. */
#define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK	0x00000001
#define AR_PHY_CHAN_INFO_TAB_S2_READ		0x00000008

/* Bits for AR_PHY_CHAN_INFO_GAIN_0. */
#define AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK	0x00000fff
#define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT	320

/* Bits for AR_PHY_CCK_TX_CTRL. */
#define AR_PHY_CCK_TX_CTRL_JAPAN	0x00000010

/* Bits for AR_PHY_PWRTX_RATE5. */
#define AR_PHY_PWRTX_RATE5_POWERTXHT20_0_M	0x0000003f
#define AR_PHY_PWRTX_RATE5_POWERTXHT20_0_S	0

/* Bits for AR_PHY_PWRTX_MAX. */
#define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE	0x00000040

/* Bits for AR_PHY_TPC_1. */
#define AR_PHY_TPC_1_FORCE_DAC_GAIN	0x00000001
#define AR_PHY_TPC_1_FORCED_DAC_GAIN_M	0x0000003e
#define AR_PHY_TPC_1_FORCED_DAC_GAIN_S	1

/* Bits for AR_PHY_TPC_5_B(i). */
#define AR_PHY_TPC_5_PD_GAIN_OVERLAP_M		0x0000000f
#define AR_PHY_TPC_5_PD_GAIN_OVERLAP_S		0
#define AR_PHY_TPC_5_PD_GAIN_BOUNDARY_1_M	0x000003f0
#define AR_PHY_TPC_5_PD_GAIN_BOUNDARY_1_S	4
#define AR_PHY_TPC_5_PD_GAIN_BOUNDARY_2_M	0x0000fc00
#define AR_PHY_TPC_5_PD_GAIN_BOUNDARY_2_S	10
#define AR_PHY_TPC_5_PD_GAIN_BOUNDARY_3_M	0x003f0000
#define AR_PHY_TPC_5_PD_GAIN_BOUNDARY_3_S	16
#define AR_PHY_TPC_5_PD_GAIN_BOUNDARY_4_M	0x0fc00000
#define AR_PHY_TPC_5_PD_GAIN_BOUNDARY_4_S	22

/* Bits for AR_PHY_TPC_6_B(i). */
#define AR_PHY_TPC_6_ERROR_EST_MODE_M	0x03000000
#define AR_PHY_TPC_6_ERROR_EST_MODE_S	24

/* Bits for AR_PHY_TPC_11_B(i). */
#define AR_PHY_TPC_11_OLPC_GAIN_DELTA_M		0x00ff0000
#define AR_PHY_TPC_11_OLPC_GAIN_DELTA_S		16
#define AR_PHY_TPC_11_OLPC_GAIN_DELTA_PAL_ON_M	0xff000000
#define AR_PHY_TPC_11_OLPC_GAIN_DELTA_PAL_ON_S	24

/* Bits for AR_PHY_TPC_12. */
#define AR_PHY_TPC_12_DESIRED_SCALE_HT40_5_M	0x3e000000
#define AR_PHY_TPC_12_DESIRED_SCALE_HT40_5_S	25

/* Bits for AR_PHY_TPC_18. */
#define AR_PHY_TPC_18_THERM_CAL_M	0x000000ff
#define AR_PHY_TPC_18_THERM_CAL_S	0
#define AR_PHY_TPC_18_VOLT_CAL_M	0x0000ff00
#define AR_PHY_TPC_18_VOLT_CAL_S	8

/* Bits for AR_PHY_TPC_19. */
#define AR_PHY_TPC_19_ALPHA_THERM_M	0x000000ff
#define AR_PHY_TPC_19_ALPHA_THERM_S	0
#define AR_PHY_TPC_19_ALPHA_VOLT_M	0x001f0000
#define AR_PHY_TPC_19_ALPHA_VOLT_S	16

/* Bits for AR_PHY_BB_THERM_ADC_1. */
#define AR_PHY_BB_THERM_ADC_1_INIT_THERM_M	0x000000ff
#define AR_PHY_BB_THERM_ADC_1_INIT_THERM_S	0

/* Bits for AR_PHY_BB_THERM_ADC_4. */
#define AR_PHY_BB_THERM_ADC_4_LATEST_THERM_M	0x000000ff
#define AR_PHY_BB_THERM_ADC_4_LATEST_THERM_S	0
#define AR_PHY_BB_THERM_ADC_4_LATEST_VOLT_M	0x0000ff00
#define AR_PHY_BB_THERM_ADC_4_LATEST_VOLT_S	8

/* Bits for AR_PHY_TX_FORCED_GAIN. */
#define AR_PHY_TX_FORCED_GAIN_FORCE_TX_GAIN	0x00000001
#define AR_PHY_TX_FORCED_GAIN_TXBB1DBGAIN_M	0x0000000e
#define AR_PHY_TX_FORCED_GAIN_TXBB1DBGAIN_S	1
#define AR_PHY_TX_FORCED_GAIN_TXBB6DBGAIN_M	0x00000030
#define AR_PHY_TX_FORCED_GAIN_TXBB6DBGAIN_S	4
#define AR_PHY_TX_FORCED_GAIN_TXMXRGAIN_M	0x000003c0
#define AR_PHY_TX_FORCED_GAIN_TXMXRGAIN_S	6
#define AR_PHY_TX_FORCED_GAIN_PADRVGNA_M	0x00003c00
#define AR_PHY_TX_FORCED_GAIN_PADRVGNA_S	10
#define AR_PHY_TX_FORCED_GAIN_PADRVGNB_M	0x0003c000
#define AR_PHY_TX_FORCED_GAIN_PADRVGNB_S	14
#define AR_PHY_TX_FORCED_GAIN_PADRVGNC_M	0x003c0000
#define AR_PHY_TX_FORCED_GAIN_PADRVGNC_S	18
#define AR_PHY_TX_FORCED_GAIN_PADRVGND_M	0x00c00000
#define AR_PHY_TX_FORCED_GAIN_PADRVGND_S	22
#define AR_PHY_TX_FORCED_GAIN_ENABLE_PAL	0x01000000

/* Bits for AR_PHY_TXGAIN_TABLE(i). */
#define AR_PHY_TXGAIN_TXBB1DBGAIN_M	0x00000007
#define AR_PHY_TXGAIN_TXBB1DBGAIN_S	0
#define AR_PHY_TXGAIN_TXBB6DBGAIN_M	0x00000018
#define AR_PHY_TXGAIN_TXBB6DBGAIN_S	3
#define AR_PHY_TXGAIN_TXMXRGAIN_M	0x000001e0
#define AR_PHY_TXGAIN_TXMXRGAIN_S	5
#define AR_PHY_TXGAIN_PADRVGNA_M	0x00001e00
#define AR_PHY_TXGAIN_PADRVGNA_S	9
#define AR_PHY_TXGAIN_PADRVGNB_M	0x0001e000
#define AR_PHY_TXGAIN_PADRVGNB_S	13
#define AR_PHY_TXGAIN_PADRVGNC_M	0x001e0000
#define AR_PHY_TXGAIN_PADRVGNC_S	17
#define AR_PHY_TXGAIN_PADRVGND_M	0x00600000
#define AR_PHY_TXGAIN_PADRVGND_S	21
#define AR_PHY_TXGAIN_INDEX_M		0xff000000
#define AR_PHY_TXGAIN_INDEX_S		24

/* Bits for AR_PHY_TX_IQCAL_CONTROL_1. */
#define AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_M	0x01fc0000
#define AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_S	18

/* Bits for AR_PHY_TX_IQCAL_START. */
#define AR_PHY_TX_IQCAL_START_DO_CAL	0x00000001

/* Bits for AR_PHY_TX_IQCAL_CORR_COEFF_01_B(i). */
#define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE_M	0x00003fff
#define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE_S	0

/* Bits for AR_PHY_TX_IQCAL_STATUS_B(i). */
#define AR_PHY_TX_IQCAL_STATUS_FAILED	0x00000001

/* Bits for AR_PHY_PAPRD_TRAINER_CNTL1. */
#define AR_PHY_PAPRD_TRAINER_CNTL1_TRAIN_ENABLE		0x00000001
#define AR_PHY_PAPRD_TRAINER_CNTL1_AGC2_SETTLING_M	0x0000007e
#define AR_PHY_PAPRD_TRAINER_CNTL1_AGC2_SETTLING_S	1
#define AR_PHY_PAPRD_TRAINER_CNTL1_IQCORR_ENABLE	0x00000100
#define AR_PHY_PAPRD_TRAINER_CNTL1_RX_BB_GAIN_FORCE	0x00000200
#define AR_PHY_PAPRD_TRAINER_CNTL1_TX_GAIN_FORCE	0x00000400
#define AR_PHY_PAPRD_TRAINER_CNTL1_LB_ENABLE		0x00000800
#define AR_PHY_PAPRD_TRAINER_CNTL1_LB_SKIP_M		0x0003f000
#define AR_PHY_PAPRD_TRAINER_CNTL1_LB_SKIP_S		12

/* Bits for AR_PHY_PAPRD_TRAINER_CNTL3. */
#define AR_PHY_PAPRD_TRAINER_CNTL3_ADC_DESIRED_SIZE_M	0x0000003f
#define AR_PHY_PAPRD_TRAINER_CNTL3_ADC_DESIRED_SIZE_S	0
#define AR_PHY_PAPRD_TRAINER_CNTL3_QUICK_DROP_M		0x00000fc0
#define AR_PHY_PAPRD_TRAINER_CNTL3_QUICK_DROP_S		6
#define AR_PHY_PAPRD_TRAINER_CNTL3_MIN_LOOPBACK_DEL_M	0x0001f000
#define AR_PHY_PAPRD_TRAINER_CNTL3_MIN_LOOPBACK_DEL_S	12
#define AR_PHY_PAPRD_TRAINER_CNTL3_NUM_CORR_STAGES_M	0x000e0000
#define AR_PHY_PAPRD_TRAINER_CNTL3_NUM_CORR_STAGES_S	17
#define AR_PHY_PAPRD_TRAINER_CNTL3_COARSE_CORR_LEN_M	0x00f00000
#define AR_PHY_PAPRD_TRAINER_CNTL3_COARSE_CORR_LEN_S	20
#define AR_PHY_PAPRD_TRAINER_CNTL3_FINE_CORR_LEN_M	0x0f000000
#define AR_PHY_PAPRD_TRAINER_CNTL3_FINE_CORR_LEN_S	24
#define AR_PHY_PAPRD_TRAINER_CNTL3_BBTXMIX_DISABLE	0x20000000

/* Bits for AR_PHY_PAPRD_TRAINER_CNTL4. */
#define AR_PHY_PAPRD_TRAINER_CNTL4_MIN_CORR_M		0x00000fff
#define AR_PHY_PAPRD_TRAINER_CNTL4_MIN_CORR_S		0
#define AR_PHY_PAPRD_TRAINER_CNTL4_SAFETY_DELTA_M	0x0000f000
#define AR_PHY_PAPRD_TRAINER_CNTL4_SAFETY_DELTA_S	12
#define AR_PHY_PAPRD_TRAINER_CNTL4_NUM_TRAIN_SAMPLES_M	0x03ff0000
#define AR_PHY_PAPRD_TRAINER_CNTL4_NUM_TRAIN_SAMPLES_S	16

/* Bits for AR_PHY_PAPRD_TRAINER_STAT1. */
#define AR_PHY_PAPRD_TRAINER_STAT1_TRAIN_DONE		0x00000001
#define AR_PHY_PAPRD_TRAINER_STAT1_TRAIN_INCOMPLETE	0x00000002
#define AR_PHY_PAPRD_TRAINER_STAT1_CORR_ERR		0x00000004
#define AR_PHY_PAPRD_TRAINER_STAT1_TRAIN_ACTIVE		0x00000008
#define AR_PHY_PAPRD_TRAINER_STAT1_RX_GAIN_IDX_M	0x000001f0
#define AR_PHY_PAPRD_TRAINER_STAT1_RX_GAIN_IDX_S	4
#define AR_PHY_PAPRD_TRAINER_STAT1_AGC2_PWR_M		0x0001fe00
#define AR_PHY_PAPRD_TRAINER_STAT1_AGC2_PWR_S		9

/* Bits for AR_PHY_PAPRD_TRAINER_STAT2. */
#define AR_PHY_PAPRD_TRAINER_STAT2_FINE_VAL_M	0x0000ffff
#define AR_PHY_PAPRD_TRAINER_STAT2_FINE_VAL_S	0
#define AR_PHY_PAPRD_TRAINER_STAT2_COARSE_IDX_M	0x001f0000
#define AR_PHY_PAPRD_TRAINER_STAT2_COARSE_IDX_S	16
#define AR_PHY_PAPRD_TRAINER_STAT2_FINE_IDX_M	0x00600000
#define AR_PHY_PAPRD_TRAINER_STAT2_FINE_IDX_S	21

/* Bits for AR_PHY_PAPRD_TRAINER_STAT3. */
#define AR_PHY_PAPRD_TRAINER_STAT3_TRAIN_SAMPLES_CNT_M	0x000fffff
#define AR_PHY_PAPRD_TRAINER_STAT3_TRAIN_SAMPLES_CNT_S	0

/* Bits for AR_PHY_65NM_CH0_SYNTH4. */
#define AR_PHY_SYNTH4_LONG_SHIFT_SELECT	0x00000002

/* Bits for AR_PHY_65NM_CH0_SYNTH7. */
#define AR9380_FRACMODE		0x40000000
#define AR9380_LOAD_SYNTH	0x80000000

/* Bits for AR_PHY_65NM_CH0_BIAS1. */
#define AR_PHY_65NM_CH0_BIAS1_0_M	0x000001c0
#define AR_PHY_65NM_CH0_BIAS1_0_S	6
#define AR_PHY_65NM_CH0_BIAS1_1_M	0x00000e00
#define AR_PHY_65NM_CH0_BIAS1_1_S	9
#define AR_PHY_65NM_CH0_BIAS1_2_M	0x00007000
#define AR_PHY_65NM_CH0_BIAS1_2_S	12
#define AR_PHY_65NM_CH0_BIAS1_3_M	0x00038000
#define AR_PHY_65NM_CH0_BIAS1_3_S	15
#define AR_PHY_65NM_CH0_BIAS1_4_M	0x001c0000
#define AR_PHY_65NM_CH0_BIAS1_4_S	18
#define AR_PHY_65NM_CH0_BIAS1_5_M	0x00e00000
#define AR_PHY_65NM_CH0_BIAS1_5_S	21

/* Bits for AR_PHY_65NM_CH0_BIAS2. */
#define AR_PHY_65NM_CH0_BIAS2_0_M	0x000000e0
#define AR_PHY_65NM_CH0_BIAS2_0_S	5
#define AR_PHY_65NM_CH0_BIAS2_1_M	0x00000700
#define AR_PHY_65NM_CH0_BIAS2_1_S	8
#define AR_PHY_65NM_CH0_BIAS2_2_M	0x00003800
#define AR_PHY_65NM_CH0_BIAS2_2_S	11
#define AR_PHY_65NM_CH0_BIAS2_3_M	0x0001c000
#define AR_PHY_65NM_CH0_BIAS2_3_S	14
#define AR_PHY_65NM_CH0_BIAS2_4_M	0x000e0000
#define AR_PHY_65NM_CH0_BIAS2_4_S	17
#define AR_PHY_65NM_CH0_BIAS2_5_M	0x00700000
#define AR_PHY_65NM_CH0_BIAS2_5_S	20
#define AR_PHY_65NM_CH0_BIAS2_6_M	0x03800000
#define AR_PHY_65NM_CH0_BIAS2_6_S	23
#define AR_PHY_65NM_CH0_BIAS2_7_M	0x1c000000
#define AR_PHY_65NM_CH0_BIAS2_7_S	26
#define AR_PHY_65NM_CH0_BIAS2_8_M	0xe0000000
#define AR_PHY_65NM_CH0_BIAS2_8_S	29

/* Bits for AR_PHY_65NM_CH0_BIAS4. */
#define AR_PHY_65NM_CH0_BIAS4_0_M	0x03800000
#define AR_PHY_65NM_CH0_BIAS4_0_S	23
#define AR_PHY_65NM_CH0_BIAS4_1_M	0x1c000000
#define AR_PHY_65NM_CH0_BIAS4_1_S	26
#define AR_PHY_65NM_CH0_BIAS4_2_M	0xe0000000
#define AR_PHY_65NM_CH0_BIAS4_2_S	29

/* Bits for AR_PHY_65NM_CH0_RXTX4. */
#define AR_PHY_65NM_CH0_RXTX4_THERM_ON  0x10000000

/* Bits for AR9485_PHY_65NM_CH0_TOP2. */
#define AR9485_PHY_65NM_CH0_TOP2_XPABIASLVL_M	0x0000f000
#define AR9485_PHY_65NM_CH0_TOP2_XPABIASLVL_S	12

/* Bits for AR_PHY_65NM_CH0_TOP. */
#define AR_PHY_65NM_CH0_TOP_XPABIASLVL_M	0x00000300
#define AR_PHY_65NM_CH0_TOP_XPABIASLVL_S	8

/* Bits for AR_PHY_65NM_CH0_THERM. */
#define AR_PHY_65NM_CH0_THERM_XPABIASLVL_MSB_M	0x00000003
#define AR_PHY_65NM_CH0_THERM_XPABIASLVL_MSB_S	0
#define AR_PHY_65NM_CH0_THERM_XPASHORT2GND	0x00000004
#define AR_PHY_65NM_CH0_THERM_SAR_ADC_OUT_M	0x0000ff00
#define AR_PHY_65NM_CH0_THERM_SAR_ADC_OUT_S	8
#define AR_PHY_65NM_CH0_THERM_START		0x20000000
#define AR_PHY_65NM_CH0_THERM_LOCAL		0x80000000

/* Bits for AR9485_PHY_CH0_XTAL. */
#define AR9485_PHY_CH0_XTAL_CAPINDAC_M	0x7f000000
#define AR9485_PHY_CH0_XTAL_CAPINDAC_S	24
#define AR9485_PHY_CH0_XTAL_CAPOUTDAC_M	0x00fe0000
#define AR9485_PHY_CH0_XTAL_CAPOUTDAC_S	17

/* Bits for AR_PHY_PMU1. */
#define AR_PHY_PMU1_PWD	0x00000001

/* Bits for AR_PHY_PMU2. */
#define AR_PHY_PMU2_PGM	0x00200000

/*
 * OTP registers.
 */
#define AR_OTP_BASE(i)			(0x14000 + (i) * 4)
#define AR_OTP_STATUS			0x15f18
#define AR_OTP_READ_DATA		0x15f1c

/* Bits for AR_OTP_STATUS. */
#define AR_OTP_STATUS_TYPE_M		0x00000007
#define AR_OTP_STATUS_TYPE_S		0
#define AR_OTP_STATUS_SM_BUSY		0x1
#define AR_OTP_STATUS_ACCESS_BUSY	0x2
#define AR_OTP_STATUS_VALID		0x4

#define AR9003_MAX_CHAINS	3

#define AR9003_TX_QDEPTH	8
#define AR9003_RX_LP_QDEPTH	128
#define AR9003_RX_HP_QDEPTH	16

#define AR9003_NTXSTATUS	64

/* Maximum number of DMA segments per Tx descriptor. */
#define AR9003_MAX_SCATTER	4

/*
 * Tx DMA descriptor.
 */
struct ar_tx_desc {
	uint32_t	ds_info;
	uint32_t	ds_link;
	struct {
		uint32_t	ds_data;
		uint32_t	ds_ctl;
	} __packed	ds_segs[AR9003_MAX_SCATTER];
	uint32_t	ds_ctl10;
	uint32_t	ds_ctl11;
	uint32_t	ds_ctl12;
	uint32_t	ds_ctl13;
	uint32_t	ds_ctl14;
	uint32_t	ds_ctl15;
	uint32_t	ds_ctl16;
	uint32_t	ds_ctl17;
	uint32_t	ds_ctl18;
	uint32_t	ds_ctl19;
	uint32_t	ds_ctl20;
	uint32_t	ds_ctl21;
	uint32_t	ds_ctl22;
	/*
	 * Padding to make Tx descriptors 128 bytes such that they will
	 * not cross a 4KB boundary.
	 */
	uint32_t	pad[9];
} __packed  __attribute__((aligned(4)));

/* Bits for ds_info. */
#define AR_TXI_DESC_NDWORDS_M		0x000000ff
#define AR_TXI_DESC_NDWORDS_S		0
#define AR_TXI_QCU_NUM_M		0x00000f00
#define AR_TXI_QCU_NUM_S		8
#define AR_TXI_CTRL_STAT		0x00004000
#define AR_TXI_DESC_TX			0x00008000
#define AR_TXI_DESC_ID_M		0xffff0000
#define AR_TXI_DESC_ID_S		16
#define AR_VENDOR_ATHEROS		0x168c	/* NB: PCI_VENDOR_ATHEROS */

/* Bits for ds_ctl. */
#define AR_TXC_BUF_LEN_M		0x0fff0000
#define AR_TXC_BUF_LEN_S		16

/* Bits for ds_ctl10. */
#define AR_TXC10_PTR_CHK_SUM_M		0x0000ffff
#define AR_TXC10_PTR_CHK_SUM_S		0

/* Bits for ds_ctl11. */
#define AR_TXC11_FRAME_LEN_M		0x00000fff
#define AR_TXC11_FRAME_LEN_S		0
#define AR_TXC11_XMIT_POWER_M		0x003f0000
#define AR_TXC11_XMIT_POWER_S		16
#define AR_TXC11_RTS_ENABLE		0x00400000
#define AR_TXC11_CLR_DEST_MASK		0x01000000
#define AR_TXC11_DEST_IDX_VALID		0x40000000
#define AR_TXC11_CTS_ENABLE		0x80000000

/* Bits for ds_ctl12. */
#define AR_TXC12_PAPRD_CHAIN_MASK_M	0x00000e00
#define AR_TXC12_PAPRD_CHAIN_MASK_S	9
#define AR_TXC12_DEST_IDX_M		0x000fe000
#define AR_TXC12_DEST_IDX_S		13
#define AR_TXC12_FRAME_TYPE_M		0x00f00000
#define AR_TXC12_FRAME_TYPE_S		20
#define AR_FRAME_TYPE_NORMAL		0
#define AR_FRAME_TYPE_ATIM		1
#define AR_FRAME_TYPE_PSPOLL		2
#define AR_FRAME_TYPE_BEACON		3
#define AR_FRAME_TYPE_PROBE_RESP	4
#define AR_TXC12_NO_ACK			0x01000000

/* Bits for ds_ctl13. */
#define AR_TXC13_BURST_DUR_M		0x00007fff
#define AR_TXC13_BURST_DUR_S		0
#define AR_TXC13_DUR_UPDATE_ENA		0x00008000
#define AR_TXC13_XMIT_DATA_TRIES0_M	0x000f0000
#define AR_TXC13_XMIT_DATA_TRIES0_S	16
#define AR_TXC13_XMIT_DATA_TRIES1_M	0x00f00000
#define AR_TXC13_XMIT_DATA_TRIES1_S	20
#define AR_TXC13_XMIT_DATA_TRIES2_M	0x0f000000
#define AR_TXC13_XMIT_DATA_TRIES2_S	24
#define AR_TXC13_XMIT_DATA_TRIES3_M	0xf0000000
#define AR_TXC13_XMIT_DATA_TRIES3_S	28

/* Bits for ds_ctl14. */
#define AR_TXC14_XMIT_RATE0_M		0x000000ff
#define AR_TXC14_XMIT_RATE0_S		0
#define AR_TXC14_XMIT_RATE1_M		0x0000ff00
#define AR_TXC14_XMIT_RATE1_S		8
#define AR_TXC14_XMIT_RATE2_M		0x00ff0000
#define AR_TXC14_XMIT_RATE2_S		16
#define AR_TXC14_XMIT_RATE3_M		0xff000000
#define AR_TXC14_XMIT_RATE3_S		24

/* Bits for ds_ctl15. */
#define AR_TXC15_PACKET_DUR0_M		0x00007fff
#define AR_TXC15_PACKET_DUR0_S		0
#define AR_TXC15_RTSCTS_QUAL0		0x00008000
#define AR_TXC15_PACKET_DUR1_M		0x7fff0000
#define AR_TXC15_PACKET_DUR1_S		16
#define AR_TXC15_RTSCTS_QUAL1		0x80000000
/* Shortcut. */
#define AR_TXC15_RTSCTS_QUAL01	\
	(AR_TXC15_RTSCTS_QUAL0 | AR_TXC15_RTSCTS_QUAL1)

/* Bits for ds_ctl16. */
#define AR_TXC16_PACKET_DUR2_M		0x00007fff
#define AR_TXC16_PACKET_DUR2_S		0
#define AR_TXC16_RTSCTS_QUAL2		0x00008000
#define AR_TXC16_PACKET_DUR3_M		0x7fff0000
#define AR_TXC16_PACKET_DUR3_S		16
#define AR_TXC16_RTSCTS_QUAL3		0x80000000
/* Shortcut. */
#define AR_TXC16_RTSCTS_QUAL23	\
	(AR_TXC16_RTSCTS_QUAL2 | AR_TXC16_RTSCTS_QUAL3)

/* Bits for ds_ctl17. */
#define AR_TXC17_ENCR_TYPE_M		0x0c000000
#define AR_TXC17_ENCR_TYPE_S		26
#define AR_ENCR_TYPE_CLEAR		0
#define AR_ENCR_TYPE_WEP		1
#define AR_ENCR_TYPE_AES		2
#define AR_ENCR_TYPE_TKIP		3

/* Bits for ds_ctl18. */
#define AR_TXC18_2040_0			0x00000001
#define AR_TXC18_GI0			0x00000002
#define AR_TXC18_CHAIN_SEL0_M		0x0000001c
#define AR_TXC18_CHAIN_SEL0_S		2
#define AR_TXC18_2040_1			0x00000020
#define AR_TXC18_GI1			0x00000040
#define AR_TXC18_CHAIN_SEL1_M		0x00000380
#define AR_TXC18_CHAIN_SEL1_S		7
#define AR_TXC18_2040_2			0x00000400
#define AR_TXC18_GI2			0x00000800
#define AR_TXC18_CHAIN_SEL2_M		0x00007000
#define AR_TXC18_CHAIN_SEL2_S		12
#define AR_TXC18_2040_3			0x00008000
#define AR_TXC18_GI3			0x00010000
#define AR_TXC18_CHAIN_SEL3_M		0x000e0000
#define AR_TXC18_CHAIN_SEL3_S		17
#define AR_TXC18_RTSCTS_RATE_M		0x0ff00000
#define AR_TXC18_RTSCTS_RATE_S		20
/* Shortcuts. */
#define AR_TXC18_2040_0123	\
	(AR_TXC18_2040_0 | AR_TXC18_2040_1 | AR_TXC18_2040_2 | AR_TXC18_2040_3)
#define AR_TXC18_GI0123		\
	(AR_TXC18_GI0 | AR_TXC18_GI1 | AR_TXC18_GI2 | AR_TXC18_GI3)

/* Bits for ds_ctl19. */
#define AR_TXC19_NOT_SOUNDING		0x20000000

/*
 * Tx status DMA descriptor.
 */
struct ar_tx_status {
	uint32_t	ds_info;
	uint32_t	ds_status1;
	uint32_t	ds_status2;
	uint32_t	ds_status3;
	uint32_t	ds_status4;
	uint32_t	ds_status5;
	uint32_t	ds_status6;
	uint32_t	ds_status7;
	uint32_t	ds_status8;
} __packed  __attribute__((aligned(4)));

/* Bits for ds_status3. */
#define AR_TXS3_EXCESSIVE_RETRIES	0x00000002
#define AR_TXS3_FIFO_UNDERRUN		0x00000004
#define AR_TXS3_RTS_FAIL_CNT_M		0x000000f0
#define AR_TXS3_RTS_FAIL_CNT_S		4
#define AR_TXS3_DATA_FAIL_CNT_M		0x00000f00
#define AR_TXS3_DATA_FAIL_CNT_S		8
#define AR_TXS3_TX_DELIM_UNDERRUN	0x00010000
#define AR_TXS3_TX_DATA_UNDERRUN	0x00020000
/* Shortcut. */
#define AR_TXS3_UNDERRUN		\
	(AR_TXS3_FIFO_UNDERRUN |	\
	 AR_TXS3_TX_DELIM_UNDERRUN |	\
	 AR_TXS3_TX_DATA_UNDERRUN)

/* Bits for ds_status8. */
#define AR_TXS8_DONE			0x00000001
#define AR_TXS8_FINAL_IDX_M		0x00600000
#define AR_TXS8_FINAL_IDX_S		21

/*
 * Rx status DMA descriptor.
 */
struct ar_rx_status {
	uint32_t	ds_info;
	uint32_t	ds_status1;
	uint32_t	ds_status2;
	uint32_t	ds_status3;
	uint32_t	ds_status4;
	uint32_t	ds_status5;
	uint32_t	ds_status6;
	uint32_t	ds_status7;
	uint32_t	ds_status8;
	uint32_t	ds_status9;
	uint32_t	ds_status10;
	uint32_t	ds_status11;
} __packed  __attribute__((aligned(4)));

/* Bits for ds_info. */
#define AR_RXI_CTRL_STAT		0x00004000
#define AR_RXI_DESC_TX			0x00008000
#define AR_RXI_DESC_ID_M		0xffff0000
#define AR_RXI_DESC_ID_S		16

/* Bits for ds_status1. */
#define AR_RXS1_DONE			0x00000001
#define AR_RXS1_RATE_M			0x000003fc
#define AR_RXS1_RATE_S			2

/* Bits for ds_status2. */
#define AR_RXS2_DATA_LEN_M		0x00000fff
#define AR_RXS2_DATA_LEN_S		0

/* Bits for ds_status4. */
#define AR_RXS4_GI			0x00000001
#define AR_RXS4_ANTENNA_M		0xffffff00
#define AR_RXS4_ANTENNA_S		8

/* Bits for ds_status5. */
#define AR_RXS5_RSSI_COMBINED_M		0xff000000
#define AR_RXS5_RSSI_COMBINED_S		24

/* Bits for ds_status11. */
#define AR_RXS11_FRAME_OK		0x00000002
#define AR_RXS11_CRC_ERR		0x00000004
#define AR_RXS11_DECRYPT_CRC_ERR	0x00000008
#define AR_RXS11_PHY_ERR		0x00000010
#define AR_RXS11_PHY_ERR_CODE_M		0x0000ff00
#define AR_RXS11_PHY_ERR_CODE_S		8
#define AR_RXS11_MICHAEL_ERR		0x00000020

/*
 * AR9003 family common ROM structures.
 */
#define AR_EEP_COMPRESS_NONE	0
#define AR_EEP_COMPRESS_LZMA	1
#define AR_EEP_COMPRESS_PAIRS	2
#define AR_EEP_COMPRESS_BLOCK	3

struct ar_cal_target_power_leg {
	uint8_t	tPow2x[4];
} __packed;

struct ar_cal_target_power_ht {
	uint8_t	tPow2x[14];
} __packed;

license: unknown


code:
/*	$OpenBSD: ar9280.c,v 1.21 2014/12/19 22:44:58 guenther Exp $	*/

/*-
 * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
 * Copyright (c) 2008-2009 Atheros Communications Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

/*
 * Driver for Atheros 802.11a/g/n chipsets.
 * Routines for AR9220, AR9223, AR9280 and AR9281 chipsets.
 */

#include "bpfilter.h"

#include <sys/param.h>
#include <sys/sockio.h>
#include <sys/mbuf.h>
#include <sys/kernel.h>
#include <sys/socket.h>
#include <sys/systm.h>
#include <sys/malloc.h>
#include <sys/queue.h>
#include <sys/timeout.h>
#include <sys/conf.h>
#include <sys/device.h>
#include <sys/endian.h>

#include <machine/bus.h>
#include <machine/intr.h>

#if NBPFILTER > 0
#include <net/bpf.h>
#endif
#include <net/if.h>
#include <net/if_arp.h>
#include <net/if_dl.h>
#include <net/if_media.h>
#include <net/if_types.h>

#include <netinet/in.h>
#include <netinet/if_ether.h>

#include <net80211/ieee80211_var.h>
#include <net80211/ieee80211_amrr.h>
#include <net80211/ieee80211_radiotap.h>

#include <dev/ic/athnreg.h>
#include <dev/ic/athnvar.h>

#include <dev/ic/ar5008reg.h>
#include <dev/ic/ar5416reg.h>	/* We share the ROM layout. */
#include <dev/ic/ar9280reg.h>

int	ar9280_attach(struct athn_softc *);
void	ar9280_setup(struct athn_softc *);
int	ar9280_set_synth(struct athn_softc *, struct ieee80211_channel *,
	    struct ieee80211_channel *);
void	ar9280_init_from_rom(struct athn_softc *, struct ieee80211_channel *,
	    struct ieee80211_channel *);
void	ar9280_spur_mitigate(struct athn_softc *, struct ieee80211_channel *,
	    struct ieee80211_channel *);
void	ar9280_olpc_get_pdadcs(struct athn_softc *,
	    struct ieee80211_channel *, int, uint8_t *, uint8_t *, uint8_t *);
void	ar9280_reset_rx_gain(struct athn_softc *, struct ieee80211_channel *);
void	ar9280_reset_tx_gain(struct athn_softc *, struct ieee80211_channel *);
void	ar9280_olpc_init(struct athn_softc *);
void	ar9280_olpc_temp_compensation(struct athn_softc *);

/* Extern functions. */
uint8_t	athn_chan2fbin(struct ieee80211_channel *);
void	athn_get_pier_ival(uint8_t, const uint8_t *, int, int *, int *);
int	ar5008_attach(struct athn_softc *);
void	ar5008_set_viterbi_mask(struct athn_softc *, int);
void	ar5416_swap_rom(struct athn_softc *);
void	ar5416_set_txpower(struct athn_softc *, struct ieee80211_channel *,
	    struct ieee80211_channel *);
const struct ar_spur_chan *
	ar5416_get_spur_chans(struct athn_softc *, int);

int
ar9280_attach(struct athn_softc *sc)
{
	sc->eep_base = AR5416_EEP_START_LOC;
	sc->eep_size = sizeof(struct ar5416_eeprom);
	sc->def_nf = AR9280_PHY_CCA_MAX_GOOD_VALUE;
	sc->ngpiopins = (sc->flags & ATHN_FLAG_USB) ? 16 : 10;
	sc->led_pin = 1;
	sc->workaround = AR9280_WA_DEFAULT;
	sc->ops.setup = ar9280_setup;
	sc->ops.swap_rom = ar5416_swap_rom;
	sc->ops.init_from_rom = ar9280_init_from_rom;
	sc->ops.set_txpower = ar5416_set_txpower;
	sc->ops.set_synth = ar9280_set_synth;
	sc->ops.spur_mitigate = ar9280_spur_mitigate;
	sc->ops.get_spur_chans = ar5416_get_spur_chans;
	sc->ops.olpc_init = ar9280_olpc_init;
	sc->ops.olpc_temp_compensation = ar9280_olpc_temp_compensation;
	sc->ini = &ar9280_2_0_ini;
	sc->serdes = &ar9280_2_0_serdes;

	return (ar5008_attach(sc));
}

void
ar9280_setup(struct athn_softc *sc)
{
	const struct ar5416_eeprom *eep = sc->eep;
	uint8_t type;

	/* Determine if open loop power control should be used. */
	if (sc->eep_rev >= AR_EEP_MINOR_VER_19 &&
	    eep->baseEepHeader.openLoopPwrCntl)
		sc->flags |= ATHN_FLAG_OLPC;

	/* Determine if fast PLL clock is supported. */
	if (AR_SREV_9280_20(sc) &&
	    (sc->eep_rev <= AR_EEP_MINOR_VER_16 ||
	     eep->baseEepHeader.fastClk5g))
		sc->flags |= ATHN_FLAG_FAST_PLL_CLOCK;

	/*
	 * Determine if initialization value for AR_AN_TOP2 must be fixed.
	 * This is required for some AR9220 devices such as Ubiquiti SR71-12.
	 */
	if (AR_SREV_9280_20(sc) &&
	    sc->eep_rev > AR_EEP_MINOR_VER_10 &&
	    !eep->baseEepHeader.pwdclkind) {
		DPRINTF(("AR_AN_TOP2 fixup required\n"));
		sc->flags |= ATHN_FLAG_AN_TOP2_FIXUP;
	}

	if (AR_SREV_9280_20(sc)) {
		/* Check if we have a valid rxGainType field in ROM. */
		if (sc->eep_rev >= AR_EEP_MINOR_VER_17) {
			/* Select initialization values based on ROM. */
			type = eep->baseEepHeader.rxGainType;
			DPRINTF(("Rx gain type=0x%x\n", type));
			if (type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
				sc->rx_gain = &ar9280_2_0_rx_gain_23db_backoff;
			else if (type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
				sc->rx_gain = &ar9280_2_0_rx_gain_13db_backoff;
			else
				sc->rx_gain = &ar9280_2_0_rx_gain;
		} else
			sc->rx_gain = &ar9280_2_0_rx_gain;

		/* Check if we have a valid txGainType field in ROM. */
		if (sc->eep_rev >= AR_EEP_MINOR_VER_19) {
			/* Select initialization values based on ROM. */
			type = eep->baseEepHeader.txGainType;
			DPRINTF(("Tx gain type=0x%x\n", type));
			if (type == AR_EEP_TXGAIN_HIGH_POWER)
				sc->tx_gain = &ar9280_2_0_tx_gain_high_power;
			else
				sc->tx_gain = &ar9280_2_0_tx_gain;
		} else
			sc->tx_gain = &ar9280_2_0_tx_gain;
	}
}

int
ar9280_set_synth(struct athn_softc *sc, struct ieee80211_channel *c,
    struct ieee80211_channel *extc)
{
	uint32_t phy, reg, ndiv = 0;
	uint32_t freq = c->ic_freq;

	phy = AR_READ(sc, AR9280_PHY_SYNTH_CONTROL) & ~0x3fffffff;

	if (IEEE80211_IS_CHAN_2GHZ(c)) {
		phy |= (freq << 16) / 15;
		phy |= AR9280_BMODE | AR9280_FRACMODE;

		if (AR_SREV_9287_11_OR_LATER(sc)) {
			/* NB: Magic values from the Linux driver. */
			if (freq == 2484) {	/* Channel 14. */
				/* Japanese regulatory requirements. */
				AR_WRITE(sc, AR_PHY(637), 0x00000000);
				AR_WRITE(sc, AR_PHY(638), 0xefff0301);
				AR_WRITE(sc, AR_PHY(639), 0xca9228ee);
			} else {
				AR_WRITE(sc, AR_PHY(637), 0x00fffeff);
				AR_WRITE(sc, AR_PHY(638), 0x00f5f9ff);
				AR_WRITE(sc, AR_PHY(639), 0xb79f6427);
			}
		} else {
			reg = AR_READ(sc, AR_PHY_CCK_TX_CTRL);
			if (freq == 2484)	/* Channel 14. */
				reg |= AR_PHY_CCK_TX_CTRL_JAPAN;
			else
				reg &= ~AR_PHY_CCK_TX_CTRL_JAPAN;
			AR_WRITE(sc, AR_PHY_CCK_TX_CTRL, reg);
		}
	} else {
		if (AR_SREV_9285_10_OR_LATER(sc) ||
		    sc->eep_rev < AR_EEP_MINOR_VER_22 ||
		    !((struct ar5416_base_eep_header *)sc->eep)->frac_n_5g) {
			if ((freq % 20) == 0) {
				ndiv = (freq * 3) / 60;
				phy |= SM(AR9280_AMODE_REFSEL, 3);
			} else if ((freq % 10) == 0) {
				ndiv = (freq * 6) / 60;
				phy |= SM(AR9280_AMODE_REFSEL, 2);
			}
		}
		if (ndiv != 0) {
			phy |= (ndiv & 0x1ff) << 17;
			phy |= (ndiv & ~0x1ff) * 2;
		} else {
			phy |= (freq << 15) / 15;
			phy |= AR9280_FRACMODE;

			reg = AR_READ(sc, AR_AN_SYNTH9);
			reg = RW(reg, AR_AN_SYNTH9_REFDIVA, 1);
			AR_WRITE(sc, AR_AN_SYNTH9, reg);
		}
	}
	AR_WRITE_BARRIER(sc);
	DPRINTFN(4, ("AR9280_PHY_SYNTH_CONTROL=0x%08x\n", phy));
	AR_WRITE(sc, AR9280_PHY_SYNTH_CONTROL, phy);
	AR_WRITE_BARRIER(sc);
	return (0);
}

void
ar9280_init_from_rom(struct athn_softc *sc, struct ieee80211_channel *c,
    struct ieee80211_channel *extc)
{
	static const uint32_t chainoffset[] = { 0x0000, 0x2000, 0x1000 };
	const struct ar5416_eeprom *eep = sc->eep;
	const struct ar5416_modal_eep_header *modal;
	uint32_t reg, offset;
	uint8_t txRxAtten;
	int i;

	modal = &eep->modalHeader[IEEE80211_IS_CHAN_2GHZ(c)];

	AR_WRITE(sc, AR_PHY_SWITCH_COM, modal->antCtrlCommon);

	for (i = 0; i < AR9280_MAX_CHAINS; i++) {
		if (sc->rxchainmask == 0x5 || sc->txchainmask == 0x5)
			offset = chainoffset[i];
		else
			offset = i * 0x1000;

		AR_WRITE(sc, AR_PHY_SWITCH_CHAIN_0 + offset,
		    modal->antCtrlChain[i]);

		reg = AR_READ(sc, AR_PHY_TIMING_CTRL4_0 + offset);
		reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
		    modal->iqCalICh[i]);
		reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
		    modal->iqCalQCh[i]);
		AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0 + offset, reg);

		if (sc->eep_rev >= AR_EEP_MINOR_VER_3) {
			reg = AR_READ(sc, AR_PHY_GAIN_2GHZ + offset);
			reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
			    modal->bswMargin[i]);
			reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB,
			    modal->bswAtten[i]);
			reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
			    modal->xatten2Margin[i]);
			reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_DB,
			    modal->xatten2Db[i]);
			AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg);
		}
		if (sc->eep_rev >= AR_EEP_MINOR_VER_3)
			txRxAtten = modal->txRxAttenCh[i];
		else	/* Workaround for ROM versions < 14.3. */
			txRxAtten = IEEE80211_IS_CHAN_2GHZ(c) ? 23 : 44;
		reg = AR_READ(sc, AR_PHY_RXGAIN + offset);
		reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN,
		    txRxAtten);
		reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN,
		    modal->rxTxMarginCh[i]);
		AR_WRITE(sc, AR_PHY_RXGAIN + offset, reg);
	}
	if (IEEE80211_IS_CHAN_2GHZ(c)) {
		reg = AR_READ(sc, AR_AN_RF2G1_CH0);
		reg = RW(reg, AR_AN_RF2G1_CH0_OB, modal->ob);
		reg = RW(reg, AR_AN_RF2G1_CH0_DB, modal->db);
		AR_WRITE(sc, AR_AN_RF2G1_CH0, reg);
		AR_WRITE_BARRIER(sc);
		DELAY(100);

		reg = AR_READ(sc, AR_AN_RF2G1_CH1);
		reg = RW(reg, AR_AN_RF2G1_CH1_OB, modal->ob_ch1);
		reg = RW(reg, AR_AN_RF2G1_CH1_DB, modal->db_ch1);
		AR_WRITE(sc, AR_AN_RF2G1_CH1, reg);
		AR_WRITE_BARRIER(sc);
		DELAY(100);
	} else {
		reg = AR_READ(sc, AR_AN_RF5G1_CH0);
		reg = RW(reg, AR_AN_RF5G1_CH0_OB5, modal->ob);
		reg = RW(reg, AR_AN_RF5G1_CH0_DB5, modal->db);
		AR_WRITE(sc, AR_AN_RF5G1_CH0, reg);
		AR_WRITE_BARRIER(sc);
		DELAY(100);

		reg = AR_READ(sc, AR_AN_RF5G1_CH1);
		reg = RW(reg, AR_AN_RF5G1_CH1_OB5, modal->ob_ch1);
		reg = RW(reg, AR_AN_RF5G1_CH1_DB5, modal->db_ch1);
		AR_WRITE(sc, AR_AN_RF5G1_CH1, reg);
		AR_WRITE_BARRIER(sc);
		DELAY(100);
	}
	reg = AR_READ(sc, AR_AN_TOP2);
	if ((sc->flags & ATHN_FLAG_USB) && IEEE80211_IS_CHAN_5GHZ(c)) {
		/*
		 * Hardcode the output voltage of x-PA bias LDO to the
		 * lowest value for UB94 such that the card doesn't get
		 * too hot.
		 */
		reg = RW(reg, AR_AN_TOP2_XPABIAS_LVL, 0);
	} else
		reg = RW(reg, AR_AN_TOP2_XPABIAS_LVL, modal->xpaBiasLvl);
	if (modal->flagBits & AR5416_EEP_FLAG_LOCALBIAS)
		reg |= AR_AN_TOP2_LOCALBIAS;
	else
		reg &= ~AR_AN_TOP2_LOCALBIAS;
	AR_WRITE(sc, AR_AN_TOP2, reg);
	AR_WRITE_BARRIER(sc);
	DELAY(100);

	reg = AR_READ(sc, AR_PHY_XPA_CFG);
	if (modal->flagBits & AR5416_EEP_FLAG_FORCEXPAON)
		reg |= AR_PHY_FORCE_XPA_CFG;
	else
		reg &= ~AR_PHY_FORCE_XPA_CFG;
	AR_WRITE(sc, AR_PHY_XPA_CFG, reg);

	reg = AR_READ(sc, AR_PHY_SETTLING);
	reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling);
	AR_WRITE(sc, AR_PHY_SETTLING, reg);

	reg = AR_READ(sc, AR_PHY_DESIRED_SZ);
	reg = RW(reg, AR_PHY_DESIRED_SZ_ADC, modal->adcDesiredSize);
	AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg);

	reg =  SM(AR_PHY_RF_CTL4_TX_END_XPAA_OFF, modal->txEndToXpaOff);
	reg |= SM(AR_PHY_RF_CTL4_TX_END_XPAB_OFF, modal->txEndToXpaOff);
	reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAA_ON, modal->txFrameToXpaOn);
	reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAB_ON, modal->txFrameToXpaOn);
	AR_WRITE(sc, AR_PHY_RF_CTL4, reg);

	reg = AR_READ(sc, AR_PHY_RF_CTL3);
	reg = RW(reg, AR_PHY_TX_END_TO_A2_RX_ON, modal->txEndToRxOn);
	AR_WRITE(sc, AR_PHY_RF_CTL3, reg);

	reg = AR_READ(sc, AR_PHY_CCA(0));
	reg = RW(reg, AR9280_PHY_CCA_THRESH62, modal->thresh62);
	AR_WRITE(sc, AR_PHY_CCA(0), reg);

	reg = AR_READ(sc, AR_PHY_EXT_CCA0);
	reg = RW(reg, AR_PHY_EXT_CCA0_THRESH62, modal->thresh62);
	AR_WRITE(sc, AR_PHY_EXT_CCA0, reg);

	if (sc->eep_rev >= AR_EEP_MINOR_VER_2) {
		reg = AR_READ(sc, AR_PHY_RF_CTL2);
		reg = RW(reg, AR_PHY_TX_END_DATA_START,
		    modal->txFrameToDataStart);
		reg = RW(reg, AR_PHY_TX_END_PA_ON, modal->txFrameToPaOn);
		AR_WRITE(sc, AR_PHY_RF_CTL2, reg);
	}
#ifndef IEEE80211_NO_HT
	if (sc->eep_rev >= AR_EEP_MINOR_VER_3 && extc != NULL) {
		/* Overwrite switch settling with HT-40 value. */
		reg = AR_READ(sc, AR_PHY_SETTLING);
		reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->swSettleHt40);
		AR_WRITE(sc, AR_PHY_SETTLING, reg);
	}
#endif
	if (sc->eep_rev >= AR_EEP_MINOR_VER_19) {
		reg = AR_READ(sc, AR_PHY_CCK_TX_CTRL);
		reg = RW(reg, AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK,
		    MS(modal->miscBits, AR5416_EEP_MISC_TX_DAC_SCALE_CCK));
		AR_WRITE(sc, AR_PHY_CCK_TX_CTRL, reg);
	}
	if (AR_SREV_9280_20(sc) &&
	    sc->eep_rev >= AR_EEP_MINOR_VER_20) {
		reg = AR_READ(sc, AR_AN_TOP1);
		if (eep->baseEepHeader.dacLpMode &&
		    (IEEE80211_IS_CHAN_2GHZ(c) ||
		     !eep->baseEepHeader.dacHiPwrMode_5G))
			reg |= AR_AN_TOP1_DACLPMODE;
		else
			reg &= ~AR_AN_TOP1_DACLPMODE;
		AR_WRITE(sc, AR_AN_TOP1, reg);
		AR_WRITE_BARRIER(sc);
		DELAY(100);

		reg = AR_READ(sc, AR_PHY_FRAME_CTL);
		reg = RW(reg, AR_PHY_FRAME_CTL_TX_CLIP,
		    MS(modal->miscBits, AR5416_EEP_MISC_TX_CLIP));
		AR_WRITE(sc, AR_PHY_FRAME_CTL, reg);

		reg = AR_READ(sc, AR_PHY_TX_PWRCTRL9);
		reg = RW(reg, AR_PHY_TX_DESIRED_SCALE_CCK,
		    eep->baseEepHeader.desiredScaleCCK);
		AR_WRITE(sc, AR_PHY_TX_PWRCTRL9, reg);
	}
	AR_WRITE_BARRIER(sc);
}

void
ar9280_olpc_get_pdadcs(struct athn_softc *sc, struct ieee80211_channel *c,
    int chain, uint8_t *boundaries, uint8_t *pdadcs, uint8_t *txgain)
{
	const struct ar5416_eeprom *eep = sc->eep;
	const struct ar_cal_data_per_freq_olpc *pierdata;
	const uint8_t *pierfreq;
	uint8_t fbin, pcdac, pwr, idx;
	int i, lo, hi, npiers;

	if (IEEE80211_IS_CHAN_2GHZ(c)) {
		pierfreq = eep->calFreqPier2G;
		pierdata = (const struct ar_cal_data_per_freq_olpc *)
		    eep->calPierData2G[chain];
		npiers = AR5416_NUM_2G_CAL_PIERS;
	} else {
		pierfreq = eep->calFreqPier5G;
		pierdata = (const struct ar_cal_data_per_freq_olpc *)
		    eep->calPierData5G[chain];
		npiers = AR5416_NUM_5G_CAL_PIERS;
	}
	/* Find channel in ROM pier table. */
	fbin = athn_chan2fbin(c);
	athn_get_pier_ival(fbin, pierfreq, npiers, &lo, &hi);

	/* Get average. */
	pwr = (pierdata[lo].pwrPdg[0][0] + pierdata[hi].pwrPdg[0][0]) / 2;
	pwr /= 2;	/* Convert to dB. */

	/* Find power control digital-to-analog converter (PCDAC) value. */
	pcdac = pierdata[hi].pcdac[0][0];
	for (idx = 0; idx < AR9280_TX_GAIN_TABLE_SIZE - 1; idx++)
		if (pcdac <= sc->tx_gain_tbl[idx])
			break;
	*txgain = idx;

	DPRINTFN(3, ("fbin=%d lo=%d hi=%d pwr=%d pcdac=%d txgain=%d\n",
	    fbin, lo, hi, pwr, pcdac, idx));

	/* Fill phase domain analog-to-digital converter (PDADC) table. */
	for (i = 0; i < AR_NUM_PDADC_VALUES; i++)
		pdadcs[i] = (i < pwr) ? 0x00 : 0xff;

	for (i = 0; i < AR_PD_GAINS_IN_MASK; i++)
		boundaries[i] = AR9280_PD_GAIN_BOUNDARY_DEFAULT;
}

void
ar9280_spur_mitigate(struct athn_softc *sc, struct ieee80211_channel *c,
    struct ieee80211_channel *extc)
{
	const struct ar_spur_chan *spurchans;
	int spur, bin, spur_delta_phase, spur_freq_sd, spur_subchannel_sd;
	int spur_off, range, i;

	/* NB: Always clear. */
	AR_CLRBITS(sc, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);

	range = (extc != NULL) ? 19 : 10;

	spurchans = sc->ops.get_spur_chans(sc, IEEE80211_IS_CHAN_2GHZ(c));
	for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
		spur = spurchans[i].spurChan;
		if (spur == AR_NO_SPUR)
			return;	/* XXX disable if it was enabled! */
		spur /= 10;
		if (IEEE80211_IS_CHAN_2GHZ(c))
			spur += AR_BASE_FREQ_2GHZ;
		else
			spur += AR_BASE_FREQ_5GHZ;
		spur -= c->ic_freq;
		if (abs(spur) < range)
			break;
	}
	if (i == AR_EEPROM_MODAL_SPURS)
		return;	/* XXX disable if it was enabled! */
	DPRINTFN(2, ("enabling spur mitigation\n"));

	AR_SETBITS(sc, AR_PHY_TIMING_CTRL4_0,
	    AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
	    AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
	    AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
	    AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);

	AR_WRITE(sc, AR_PHY_SPUR_REG,
	    AR_PHY_SPUR_REG_MASK_RATE_CNTL |
	    AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
	    AR_PHY_SPUR_REG_MASK_RATE_SELECT |
	    AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
	    SM(AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, AR_SPUR_RSSI_THRESH));

#ifndef IEEE80211_NO_HT
	if (extc != NULL) {
		spur_delta_phase = (spur * 262144) / 10;
		if (spur < 0) {
			spur_subchannel_sd = 1;
			spur_off = spur + 10;
		} else {
			spur_subchannel_sd = 0;
			spur_off = spur - 10;
		}
	} else
#endif
	{
		spur_delta_phase = (spur * 524288) / 10;
		spur_subchannel_sd = 0;
		spur_off = spur;
	}
	if (IEEE80211_IS_CHAN_2GHZ(c))
		spur_freq_sd = (spur_off * 2048) / 44;
	else
		spur_freq_sd = (spur_off * 2048) / 40;

	AR_WRITE(sc, AR_PHY_TIMING11,
	    AR_PHY_TIMING11_USE_SPUR_IN_AGC |
	    SM(AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd) |
	    SM(AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase));

	AR_WRITE(sc, AR_PHY_SFCORR_EXT,
	    SM(AR_PHY_SFCORR_SPUR_SUBCHNL_SD, spur_subchannel_sd));
	AR_WRITE_BARRIER(sc);

	bin = spur * 320;
	ar5008_set_viterbi_mask(sc, bin);
}

void
ar9280_reset_rx_gain(struct athn_softc *sc, struct ieee80211_channel *c)
{
	const struct athn_gain *prog = sc->rx_gain;
	const uint32_t *pvals;
	int i;

	if (IEEE80211_IS_CHAN_2GHZ(c))
		pvals = prog->vals_2g;
	else
		pvals = prog->vals_5g;
	for (i = 0; i < prog->nregs; i++)
		AR_WRITE(sc, prog->regs[i], pvals[i]);
}

void
ar9280_reset_tx_gain(struct athn_softc *sc, struct ieee80211_channel *c)
{
	const struct athn_gain *prog = sc->tx_gain;
	const uint32_t *pvals;
	int i;

	if (IEEE80211_IS_CHAN_2GHZ(c))
		pvals = prog->vals_2g;
	else
		pvals = prog->vals_5g;
	for (i = 0; i < prog->nregs; i++)
		AR_WRITE(sc, prog->regs[i], pvals[i]);
}

void
ar9280_olpc_init(struct athn_softc *sc)
{
	uint32_t reg;
	int i;

	/* Save original Tx gain values. */
	for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++) {
		reg = AR_READ(sc, AR_PHY_TX_GAIN_TBL(i));
		sc->tx_gain_tbl[i] = MS(reg, AR_PHY_TX_GAIN);
	}
	/* Initial Tx gain temperature compensation. */
	sc->tcomp = 0;
}

void
ar9280_olpc_temp_compensation(struct athn_softc *sc)
{
	const struct ar5416_eeprom *eep = sc->eep;
	int8_t pdadc, txgain, tcomp;
	uint32_t reg;
	int i;

	reg = AR_READ(sc, AR_PHY_TX_PWRCTRL4);
	pdadc = MS(reg, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
	DPRINTFN(3, ("PD Avg Out=%d\n", pdadc));

	if (sc->pdadc == 0 || pdadc == 0)
		return;	/* No frames transmitted yet. */

	/* Compute Tx gain temperature compensation. */
	if (sc->eep_rev >= AR_EEP_MINOR_VER_20 &&
	    eep->baseEepHeader.dacHiPwrMode_5G)
		tcomp = (pdadc - sc->pdadc + 4) / 8;
	else
		tcomp = (pdadc - sc->pdadc + 5) / 10;
	DPRINTFN(3, ("OLPC temp compensation=%d\n", tcomp));

	if (tcomp == sc->tcomp)
		return;	/* Don't rewrite the same values. */
	sc->tcomp = tcomp;

	/* Adjust Tx gain values. */
	for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++) {
		txgain = sc->tx_gain_tbl[i] - tcomp;
		if (txgain < 0)
			txgain = 0;
		reg = AR_READ(sc, AR_PHY_TX_GAIN_TBL(i));
		reg = RW(reg, AR_PHY_TX_GAIN, txgain);
		AR_WRITE(sc, AR_PHY_TX_GAIN_TBL(i), reg);
	}
	AR_WRITE_BARRIER(sc);
}


code:
/*	$OpenBSD: ar9280reg.h,v 1.6 2012/10/20 09:54:20 stsp Exp $	*/

/*-
 * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
 * Copyright (c) 2008-2009 Atheros Communications Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#define AR9280_MAX_CHAINS	2

#define AR9280_PD_GAIN_BOUNDARY_DEFAULT	56
#define AR9280_PHY_CCA_MAX_GOOD_VALUE	(-112)

#define AR9280_PHY_SYNTH_CONTROL	0x9874

/* Bits for AR9280_PHY_SYNTH_CONTROL. */
#define AR9280_BMODE		0x20000000
#define AR9280_FRACMODE		0x10000000
#define AR9280_AMODE_REFSEL_M	0x0c000000
#define AR9280_AMODE_REFSEL_S	26

/*
 * NB: The AR9280 uses the same ROM layout than the AR5416.
 */

/* Macro to "pack" registers to 16-bit to save some .rodata space. */
#define P(x)	(x)

/*
 * AR9280 2.0 initialization values.
 */
static const uint16_t ar9280_2_0_regs[] = {
	P(0x01030), P(0x01070), P(0x010b0), P(0x010f0), P(0x08014),
	P(0x0801c), P(0x08120), P(0x081d0), P(0x08318), P(0x09804),
	P(0x09820), P(0x09824), P(0x09828), P(0x09834), P(0x09838),
	P(0x09840), P(0x09844), P(0x09850), P(0x09858), P(0x0985c),
	P(0x09860), P(0x09864), P(0x09868), P(0x0986c), P(0x09914),
	P(0x09918), P(0x09924), P(0x09944), P(0x09960), P(0x0a960),
	P(0x09964), P(0x0c968), P(0x099b8), P(0x099bc), P(0x099c0),
	P(0x0a204), P(0x0a20c), P(0x0b20c), P(0x0a21c), P(0x0a230),
	P(0x0a23c), P(0x0a250), P(0x0a358), P(0x0a388), P(0x0a3d8),
	P(0x07894)
};

static const uint32_t ar9280_2_0_vals_5g20[] = {
	0x00000230, 0x00000168, 0x00000e60, 0x00000000, 0x03e803e8,
	0x128d8027, 0x08f04800, 0x00003210, 0x00003e80, 0x00000300,
	0x02020200, 0x01000e0e, 0x0a020001, 0x00000e0e, 0x00000007,
	0x206a022e, 0x0372161e, 0x6c4000e2, 0x7ec88d2e, 0x31395d5e,
	0x00048d18, 0x0001ce00, 0x5ac640d0, 0x06903081, 0x000007d0,
	0x0000000a, 0xd00a8a0b, 0xffbc1010, 0x00000010, 0x00000010,
	0x00000210, 0x000003b5, 0x0000001c, 0x00000a00, 0x05eea6d4,
	0x00000444, 0x00000014, 0x00000014, 0x1883800a, 0x00000000,
	0x13c88000, 0x001ff000, 0x7999aa02, 0x0c000000, 0x00000000,
	0x5a508000
};

#ifndef IEEE80211_NO_HT
static const uint32_t ar9280_2_0_vals_5g40[] = {
	0x00000460, 0x000002d0, 0x00001cc0, 0x00000000, 0x07d007d0,
	0x128d804f, 0x08f04800, 0x00003210, 0x00007d00, 0x000003c4,
	0x02020200, 0x01000e0e, 0x0a020001, 0x00000e0e, 0x00000007,
	0x206a022e, 0x0372161e, 0x6d4000e2, 0x7ec88d2e, 0x3139605e,
	0x00048d18, 0x0001ce00, 0x5ac640d0, 0x06903081, 0x00000fa0,
	0x00000014, 0xd00a8a0b, 0xffbc1010, 0x00000010, 0x00000010,
	0x00000210, 0x000003b5, 0x0000001c, 0x00000a00, 0x05eea6d4,
	0x00000444, 0x00000014, 0x00000014, 0x1883800a, 0x00000000,
	0x13c88000, 0x001ff000, 0x7999aa02, 0x0c000000, 0x00000000,
	0x5a508000
};

static const uint32_t ar9280_2_0_vals_2g40[] = {
	0x000002c0, 0x00000318, 0x00007c70, 0x00000000, 0x10801600,
	0x12e00057, 0x08f04810, 0x0000320a, 0x00006880, 0x000003c4,
	0x02020200, 0x01000e0e, 0x0a020001, 0x00000e0e, 0x00000007,
	0x206a012e, 0x037216a0, 0x6d4000e2, 0x7ec84d2e, 0x3139605e,
	0x00048d20, 0x0001ce00, 0x5ac640d0, 0x06903881, 0x00001130,
	0x00000268, 0xd00a8a0d, 0xffbc1010, 0x00000010, 0x00000010,
	0x00000210, 0x000003ce, 0x0000001c, 0x00000c00, 0x05eea6d4,
	0x00000444, 0x0001f019, 0x0001f019, 0x1883800a, 0x00000210,
	0x13c88001, 0x0004a000, 0x7999aa0e, 0x08000000, 0x00000000,
	0x5a508000
};
#endif

static const uint32_t ar9280_2_0_vals_2g20[] = {
	0x00000160, 0x0000018c, 0x00003e38, 0x00000000, 0x08400b00,
	0x12e0002b, 0x08f04810, 0x0000320a, 0x00003440, 0x00000300,
	0x02020200, 0x01000e0e, 0x0a020001, 0x00000e0e, 0x00000007,
	0x206a012e, 0x037216a0, 0x6c4000e2, 0x7ec84d2e, 0x31395d5e,
	0x00048d20, 0x0001ce00, 0x5ac640d0, 0x06903881, 0x00000898,
	0x0000000b, 0xd00a8a0d, 0xffbc1010, 0x00000010, 0x00000010,
	0x00000210, 0x000003ce, 0x0000001c, 0x00000c00, 0x05eea6d4,
	0x00000444, 0x0001f019, 0x0001f019, 0x1883800a, 0x00000108,
	0x13c88000, 0x0004a000, 0x7999aa0e, 0x0c000000, 0x00000000,
	0x5a508000
};

static const uint16_t ar9280_2_0_cm_regs[] = {
	P(0x0000c), P(0x00030), P(0x00034), P(0x00040), P(0x00044),
	P(0x00048), P(0x0004c), P(0x00050), P(0x00054), P(0x00800),
	P(0x00804), P(0x00808), P(0x0080c), P(0x00810), P(0x00814),
	P(0x00818), P(0x0081c), P(0x00820), P(0x00824), P(0x01040),
	P(0x01044), P(0x01048), P(0x0104c), P(0x01050), P(0x01054),
	P(0x01058), P(0x0105c), P(0x01060), P(0x01064), P(0x01230),
	P(0x01270), P(0x01038), P(0x01078), P(0x010b8), P(0x010f8),
	P(0x01138), P(0x01178), P(0x011b8), P(0x011f8), P(0x01238),
	P(0x01278), P(0x012b8), P(0x012f8), P(0x01338), P(0x01378),
	P(0x013b8), P(0x013f8), P(0x01438), P(0x01478), P(0x014b8),
	P(0x014f8), P(0x01538), P(0x01578), P(0x015b8), P(0x015f8),
	P(0x01638), P(0x01678), P(0x016b8), P(0x016f8), P(0x01738),
	P(0x01778), P(0x017b8), P(0x017f8), P(0x0103c), P(0x0107c),
	P(0x010bc), P(0x010fc), P(0x0113c), P(0x0117c), P(0x011bc),
	P(0x011fc), P(0x0123c), P(0x0127c), P(0x012bc), P(0x012fc),
	P(0x0133c), P(0x0137c), P(0x013bc), P(0x013fc), P(0x0143c),
	P(0x0147c), P(0x04030), P(0x0403c), P(0x04024), P(0x04060),
	P(0x04064), P(0x07010), P(0x07034), P(0x07038), P(0x08004),
	P(0x08008), P(0x0800c), P(0x08018), P(0x08020), P(0x08038),
	P(0x0803c), P(0x08048), P(0x08054), P(0x08058), P(0x0805c),
	P(0x08060), P(0x08064), P(0x08070), P(0x080c0), P(0x080c4),
	P(0x080c8), P(0x080cc), P(0x080d0), P(0x080d4), P(0x080d8),
	P(0x080e0), P(0x080e4), P(0x080e8), P(0x080ec), P(0x080f0),
	P(0x080f4), P(0x080f8), P(0x080fc), P(0x08100), P(0x08104),
	P(0x08108), P(0x0810c), P(0x08110), P(0x08118), P(0x0811c),
	P(0x08124), P(0x08128), P(0x0812c), P(0x08130), P(0x08134),
	P(0x08138), P(0x0813c), P(0x08144), P(0x08168), P(0x0816c),
	P(0x08170), P(0x08174), P(0x08178), P(0x0817c), P(0x081c0),
	P(0x081ec), P(0x081f0), P(0x081f4), P(0x081f8), P(0x081fc),
	P(0x08200), P(0x08204), P(0x08208), P(0x0820c), P(0x08210),
	P(0x08214), P(0x08218), P(0x0821c), P(0x08220), P(0x08224),
	P(0x08228), P(0x0822c), P(0x08230), P(0x08234), P(0x08238),
	P(0x0823c), P(0x08240), P(0x08244), P(0x08248), P(0x0824c),
	P(0x08250), P(0x08254), P(0x08258), P(0x0825c), P(0x08260),
	P(0x08264), P(0x08270), P(0x08274), P(0x08278), P(0x0827c),
	P(0x08284), P(0x08288), P(0x0828c), P(0x08294), P(0x08298),
	P(0x0829c), P(0x08300), P(0x08314), P(0x08328), P(0x0832c),
	P(0x08330), P(0x08334), P(0x08338), P(0x0833c), P(0x08340),
	P(0x08344), P(0x09808), P(0x0980c), P(0x09810), P(0x09814),
	P(0x0981c), P(0x0982c), P(0x09830), P(0x0983c), P(0x0984c),
	P(0x0a84c), P(0x09854), P(0x09900), P(0x09904), P(0x09908),
	P(0x0990c), P(0x09910), P(0x0991c), P(0x09920), P(0x0a920),
	P(0x09928), P(0x0992c), P(0x09934), P(0x09938), P(0x0993c),
	P(0x09948), P(0x0994c), P(0x09954), P(0x09958), P(0x09940),
	P(0x0c95c), P(0x09970), P(0x09974), P(0x09978), P(0x0997c),
	P(0x09980), P(0x09984), P(0x09988), P(0x0998c), P(0x09990),
	P(0x09994), P(0x09998), P(0x0999c), P(0x099a0), P(0x099a4),
	P(0x099a8), P(0x099ac), P(0x099b0), P(0x099b4), P(0x099c4),
	P(0x099c8), P(0x099cc), P(0x099d0), P(0x099d4), P(0x099d8),
	P(0x099dc), P(0x099e0), P(0x099e4), P(0x099e8), P(0x099ec),
	P(0x099f0), P(0x099fc), P(0x0a208), P(0x0a210), P(0x0a214),
	P(0x0a218), P(0x0a220), P(0x0a224), P(0x0a228), P(0x0a22c),
	P(0x0a234), P(0x0a238), P(0x0a240), P(0x0a244), P(0x0a248),
	P(0x0a24c), P(0x0a254), P(0x0a258), P(0x0a25c), P(0x0a260),
	P(0x0a268), P(0x0a26c), P(0x0b26c), P(0x0d270), P(0x0a278),
	P(0x0d35c), P(0x0d360), P(0x0d364), P(0x0d368), P(0x0d36c),
	P(0x0d370), P(0x0d374), P(0x0d378), P(0x0d37c), P(0x0d380),
	P(0x0d384), P(0x0a38c), P(0x0a390), P(0x0a394), P(0x0a398),
	P(0x0a39c), P(0x0a3a0), P(0x0a3a4), P(0x0a3a8), P(0x0a3ac),
	P(0x0a3b0), P(0x0a3b4), P(0x0a3b8), P(0x0a3bc), P(0x0a3c0),
	P(0x0a3c4), P(0x0a3c8), P(0x0a3cc), P(0x0a3d0), P(0x0a3d4),
	P(0x0a3dc), P(0x0a3e0), P(0x0a3e4), P(0x0a3e8), P(0x07800),
	P(0x07804), P(0x07808), P(0x0780c), P(0x07810), P(0x07818),
	P(0x07824), P(0x07828), P(0x0782c), P(0x07830), P(0x07834),
	P(0x0783c), P(0x07848), P(0x0784c), P(0x07850), P(0x07854),
	P(0x07858), P(0x07860), P(0x07864), P(0x07868), P(0x0786c),
	P(0x07870), P(0x07874), P(0x07878), P(0x0787c), P(0x07880),
	P(0x07884), P(0x07888), P(0x0788c), P(0x07890), P(0x07898)
};

static const uint32_t ar9280_2_0_cm_vals[] = {
	0x00000000, 0x00020015, 0x00000005, 0x00000000, 0x00000008,
	0x00000008, 0x00000010, 0x00000000, 0x0000001f, 0x00000000,
	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x002ffc0f,
	0x002ffc0f, 0x002ffc0f, 0x002ffc0f, 0x002ffc0f, 0x002ffc0f,
	0x002ffc0f, 0x002ffc0f, 0x002ffc0f, 0x002ffc0f, 0x00000000,
	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
	0x00000000, 0x00000002, 0x00000002, 0x0000001f, 0x00000000,
	0x00000000, 0x00000033, 0x00000002, 0x000004c2, 0x00000000,
	0x00000000, 0x00000000, 0x00000700, 0x00000000, 0x00000000,
	0x00000000, 0x40000000, 0x00000000, 0x00000000, 0x000fc78f,
	0x0000000f, 0x00000000, 0x00000000, 0x2a80001a, 0x05dc01e0,
	0x1f402710, 0x01f40000, 0x00001e00, 0x00000000, 0x00400000,
	0xffffffff, 0x0000ffff, 0x003f3f3f, 0x00000000, 0x00000000,
	0x00000000, 0x00000000, 0x00020000, 0x00020000, 0x00000001,
	0x00000052, 0x00000000, 0x00000168, 0x000100aa, 0x00003210,
	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
	0x00000000, 0x00000000, 0xffffffff, 0x00000000, 0x00000000,
	0x32143320, 0xfaa4fa50, 0x00000100, 0x00000000, 0x00000000,
	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
	0x00000000, 0x00100000, 0x0010f400, 0x00000100, 0x0001e800,
	0x00000000, 0x00000000, 0x00000000, 0x400000ff, 0x00080922,
	0x88a00010, 0x00000000, 0x40000000, 0x003e4180, 0x00000000,
	0x0000002c, 0x0000002c, 0x00000000, 0x00000000, 0x00000000,
	0x00000000, 0x00000040, 0x00000000, 0x00000000, 0x00000007,
	0x00000302, 0x00000e00, 0x00ff0000, 0x00000000, 0x000107ff,
	0x00481043, 0x00000000, 0xafa68e30, 0xfd14e000, 0x9c0a9f6b,
	0x00000000, 0x0000a000, 0x00000000, 0x00200400, 0x0040233c,
	0x0040233c, 0x00000044, 0x00000000, 0x00000000, 0x00000000,
	0x00000000, 0x01002310, 0x10000fff, 0x04900000, 0x04900000,
	0x00000001, 0x00000004, 0x1e1f2022, 0x0a0b0c0d, 0x00000000,
	0x9280c00a, 0x00020028, 0x5f3ca3de, 0x2108ecff, 0x14750604,
	0x004b6a8e, 0x190fb514, 0x00000000, 0x00000001, 0x00000000,
	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000001,
	0x201fff00, 0x006f0000, 0x03051000, 0x00000820, 0x06336f77,
	0x6af6532f, 0x08f186c8, 0x00046384, 0x00000000, 0x00000000,
	0x00000000, 0x00000000, 0xaaaaaaaa, 0x3c466478, 0x0cc80caa,
	0x00000000, 0x00001042, 0x803e4788, 0x4080a333, 0x40206c10,
	0x009c4060, 0x01834061, 0x00000400, 0x000003b5, 0x233f7180,
	0x20202020, 0x20202020, 0x38490a20, 0x00007bb6, 0x0fff3ffc,
	0x00000000, 0x00000000, 0x0cdbd380, 0x0f0f0f01, 0xdfa91f01,
	0x00000000, 0x0e79e5c6, 0x0e79e5c6, 0x00820820, 0x1ce739ce,
	0x07ffffef, 0x0fffffe7, 0x17ffffe5, 0x1fffffe4, 0x37ffffe3,
	0x3fffffe3, 0x57ffffe3, 0x5fffffe2, 0x7fffffe2, 0x7f3c7bba,
	0xf3307ff0, 0x20202020, 0x20202020, 0x1ce739ce, 0x000001ce,
	0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
	0x00000000, 0x00000246, 0x20202020, 0x20202020, 0x20202020,
	0x1ce739ce, 0x000001ce, 0x00000000, 0x18c43433, 0x00040000,
	0xdb005012, 0x04924914, 0x21084210, 0x6d801300, 0x07e41000,
	0x00040000, 0xdb005012, 0x04924914, 0x21084210, 0x6d801300,
	0x07e40000, 0x00100000, 0x773f0567, 0x54214514, 0x12035828,
	0x9259269a, 0x52802000, 0x0a8e370e, 0xc0102850, 0x812d4000,
	0x807ec400, 0x001b6db0, 0x00376b63, 0x06db6db6, 0x006d8000,
	0xffeffffe, 0xffeffffe, 0x00010000, 0x02060aeb, 0x2a850160
};

static const uint16_t ar9280_2_0_fast_clock_regs[] = {
	P(0x01030), P(0x01070), P(0x010b0), P(0x08014), P(0x0801c),
	P(0x08318), P(0x09820), P(0x09824), P(0x09828), P(0x09834),
	P(0x09844), P(0x09914), P(0x09918)
};

static const uint32_t ar9280_2_0_fast_clock_vals_5g20[] = {
	0x00000268, 0x0000018c, 0x00000fd0, 0x044c044c, 0x148ec02b,
	0x000044c0, 0x02020200, 0x01000f0f, 0x0b020001, 0x00000f0f,
	0x03721821, 0x00000898, 0x0000000b
};

#ifndef IEEE80211_NO_HT
static const uint32_t ar9280_2_0_fast_clock_vals_5g40[] = {
	0x000004d0, 0x00000318, 0x00001fa0, 0x08980898, 0x148ec057,
	0x00008980, 0x02020200, 0x01000f0f, 0x0b020001, 0x00000f0f,
	0x03721821, 0x00001130, 0x00000016
};
#endif

static const struct athn_ini ar9280_2_0_ini = {
	nitems(ar9280_2_0_regs),
	ar9280_2_0_regs,
	ar9280_2_0_vals_5g20,
#ifndef IEEE80211_NO_HT
	ar9280_2_0_vals_5g40,
	ar9280_2_0_vals_2g40,
#endif
	ar9280_2_0_vals_2g20,
	nitems(ar9280_2_0_cm_regs),
	ar9280_2_0_cm_regs,
	ar9280_2_0_cm_vals,
	nitems(ar9280_2_0_fast_clock_regs),
	ar9280_2_0_fast_clock_regs,
	ar9280_2_0_fast_clock_vals_5g20,
#ifndef IEEE80211_NO_HT
	ar9280_2_0_fast_clock_vals_5g40
#endif
};

/*
 * AR9280 2.0 Tx gains.
 */
static const uint16_t ar9280_2_0_tx_gain_regs[] = {
	P(0x0a274), P(0x0a27c), P(0x0a300), P(0x0a304), P(0x0a308),
	P(0x0a30c), P(0x0a310), P(0x0a314), P(0x0a318), P(0x0a31c),
	P(0x0a320), P(0x0a324), P(0x0a328), P(0x0a32c), P(0x0a330),
	P(0x0a334), P(0x0a338), P(0x0a33c), P(0x0a340), P(0x0a344),
	P(0x0a348), P(0x0a34c), P(0x0a350), P(0x0a354), P(0x0a3ec),
	P(0x07814), P(0x07838), P(0x0781c), P(0x07840), P(0x07820),
	P(0x07844)
};

static const uint32_t ar9280_2_0_tx_gain_vals_5g[] = {
	0x0a19c652, 0x050701ce, 0x00000000, 0x00003002, 0x00006004,
	0x0000a006, 0x0000e012, 0x00011014, 0x0001504a, 0x0001904c,
	0x0001c04e, 0x00020092, 0x0002410a, 0x0002710c, 0x0002b18b,
	0x0002e1cc, 0x000321ec, 0x000321ec, 0x000321ec, 0x000321ec,
	0x000321ec, 0x000321ec, 0x000321ec, 0x000321ec, 0x00f70081,
	0x0019beff, 0x0019beff, 0x00392000, 0x00392000, 0x92592480,
	0x92592480
};

static const uint32_t ar9280_2_0_tx_gain_vals_2g[] = {
	0x0a1aa652, 0x050701ce, 0x00000000, 0x00003002, 0x00008009,
	0x0000b00b, 0x0000e012, 0x00012048, 0x0001604a, 0x0001a211,
	0x0001e213, 0x0002121b, 0x00024412, 0x00028414, 0x0002b44a,
	0x00030649, 0x0003364b, 0x00038a49, 0x0003be48, 0x0003ee4a,
	0x00042e88, 0x00046e8a, 0x00049ec9, 0x0004bf42, 0x00f70081,
	0x0019beff, 0x0019beff, 0x00392000, 0x00392000, 0x92592480,
	0x92592480
};

static const struct athn_gain ar9280_2_0_tx_gain = {
	nitems(ar9280_2_0_tx_gain_regs),
	ar9280_2_0_tx_gain_regs,
	ar9280_2_0_tx_gain_vals_5g,
	ar9280_2_0_tx_gain_vals_2g
};

static const uint32_t ar9280_2_0_tx_gain_high_power_vals_5g[] = {
	0x0a19e652, 0x050739ce, 0x00000000, 0x00003002, 0x00006004,
	0x0000a006, 0x0000e012, 0x00011014, 0x0001504a, 0x0001904c,
	0x0001c04e, 0x00021092, 0x0002510a, 0x0002910c, 0x0002c18b,
	0x0002f1cc, 0x000321eb, 0x000341ec, 0x000341ec, 0x000341ec,
	0x000341ec, 0x000341ec, 0x000341ec, 0x000341ec, 0x00f70081,
	0x00198eff, 0x00198eff, 0x00172000, 0x00172000, 0xf258a480,
	0xf258a480
};

static const uint32_t ar9280_2_0_tx_gain_high_power_vals_2g[] = {
	0x0a1aa652, 0x050739ce, 0x00000000, 0x00004002, 0x00007008,
	0x0000c010, 0x00010012, 0x00013014, 0x0001820a, 0x0001b211,
	0x0001e213, 0x00022411, 0x00025413, 0x00029811, 0x0002c813,
	0x00030a14, 0x00035a50, 0x00039c4c, 0x0003de8a, 0x00042e92,
	0x00046ed2, 0x0004bed5, 0x0004ff54, 0x00055fd5, 0x00f70081,
	0x00198eff, 0x00198eff, 0x00172000, 0x00172000, 0xf258a480,
	0xf258a480
};

static const struct athn_gain ar9280_2_0_tx_gain_high_power = {
	nitems(ar9280_2_0_tx_gain_regs),
	ar9280_2_0_tx_gain_regs,
	ar9280_2_0_tx_gain_high_power_vals_5g,
	ar9280_2_0_tx_gain_high_power_vals_2g
};

/*
 * AR9280 2.0 Rx gains.
 */
static const uint16_t ar9280_2_0_rx_gain_regs[] = {
	P(0x09a00), P(0x09a04), P(0x09a08), P(0x09a0c), P(0x09a10),
	P(0x09a14), P(0x09a18), P(0x09a1c), P(0x09a20), P(0x09a24),
	P(0x09a28), P(0x09a2c), P(0x09a30), P(0x09a34), P(0x09a38),
	P(0x09a3c), P(0x09a40), P(0x09a44), P(0x09a48), P(0x09a4c),
	P(0x09a50), P(0x09a54), P(0x09a58), P(0x09a5c), P(0x09a60),
	P(0x09a64), P(0x09a68), P(0x09a6c), P(0x09a70), P(0x09a74),
	P(0x09a78), P(0x09a7c), P(0x09a80), P(0x09a84), P(0x09a88),
	P(0x09a8c), P(0x09a90), P(0x09a94), P(0x09a98), P(0x09a9c),
	P(0x09aa0), P(0x09aa4), P(0x09aa8), P(0x09aac), P(0x09ab0),
	P(0x09ab4), P(0x09ab8), P(0x09abc), P(0x09ac0), P(0x09ac4),
	P(0x09ac8), P(0x09acc), P(0x09ad0), P(0x09ad4), P(0x09ad8),
	P(0x09adc), P(0x09ae0), P(0x09ae4), P(0x09ae8), P(0x09aec),
	P(0x09af0), P(0x09af4), P(0x09af8), P(0x09afc), P(0x09b00),
	P(0x09b04), P(0x09b08), P(0x09b0c), P(0x09b10), P(0x09b14),
	P(0x09b18), P(0x09b1c), P(0x09b20), P(0x09b24), P(0x09b28),
	P(0x09b2c), P(0x09b30), P(0x09b34), P(0x09b38), P(0x09b3c),
	P(0x09b40), P(0x09b44), P(0x09b48), P(0x09b4c), P(0x09b50),
	P(0x09b54), P(0x09b58), P(0x09b5c), P(0x09b60), P(0x09b64),
	P(0x09b68), P(0x09b6c), P(0x09b70), P(0x09b74), P(0x09b78),
	P(0x09b7c), P(0x09b80), P(0x09b84), P(0x09b88), P(0x09b8c),
	P(0x09b90), P(0x09b94), P(0x09b98), P(0x09b9c), P(0x09ba0),
	P(0x09ba4), P(0x09ba8), P(0x09bac), P(0x09bb0), P(0x09bb4),
	P(0x09bb8), P(0x09bbc), P(0x09bc0), P(0x09bc4), P(0x09bc8),
	P(0x09bcc), P(0x09bd0), P(0x09bd4), P(0x09bd8), P(0x09bdc),
	P(0x09be0), P(0x09be4), P(0x09be8), P(0x09bec), P(0x09bf0),
	P(0x09bf4), P(0x09bf8), P(0x09bfc), P(0x09848), P(0x0a848)
};

static const uint32_t ar9280_2_0_rx_gain_vals_5g[] = {
	0x00008184, 0x00008188, 0x0000818c, 0x00008190, 0x00008194,
	0x00008200, 0x00008204, 0x00008208, 0x0000820c, 0x00008210,
	0x00008214, 0x00008280, 0x00008284, 0x00008288, 0x0000828c,
	0x00008290, 0x00008300, 0x00008304, 0x00008308, 0x0000830c,
	0x00008310, 0x00008314, 0x00008380, 0x00008384, 0x00008388,
	0x0000838c, 0x00008390, 0x00008394, 0x0000a380, 0x0000a384,
	0x0000a388, 0x0000a38c, 0x0000a390, 0x0000a394, 0x0000a780,
	0x0000a784, 0x0000a788, 0x0000a78c, 0x0000a790, 0x0000a794,
	0x0000ab84, 0x0000ab88, 0x0000ab8c, 0x0000ab90, 0x0000ab94,
	0x0000af80, 0x0000af84, 0x0000af88, 0x0000af8c, 0x0000af90,
	0x0000af94, 0x0000b380, 0x0000b384, 0x0000b388, 0x0000b38c,
	0x0000b390, 0x0000b394, 0x0000b398, 0x0000b780, 0x0000b784,
	0x0000b788, 0x0000b78c, 0x0000b790, 0x0000b794, 0x0000b798,
	0x0000d784, 0x0000d788, 0x0000d78c, 0x0000d790, 0x0000f780,
	0x0000f784, 0x0000f788, 0x0000f78c, 0x0000f790, 0x0000f794,
	0x0000f7a4, 0x0000f7a8, 0x0000f7ac, 0x0000f7b0, 0x0000f7b4,
	0x0000f7a1, 0x0000f7a5, 0x0000f7a9, 0x0000f7ad, 0x0000f7b1,
	0x0000f7b5, 0x0000f7c5, 0x0000f7c9, 0x0000f7cd, 0x0000f7d1,
	0x0000f7d5, 0x0000f7c2, 0x0000f7c6, 0x0000f7ca, 0x0000f7ce,
	0x0000f7d2, 0x0000f7d6, 0x0000f7c3, 0x0000f7c7, 0x0000f7cb,
	0x0000f7d3, 0x0000f7d7, 0x0000f7db, 0x0000f7db, 0x0000f7db,
	0x0000f7db, 0x0000f7db, 0x0000f7db, 0x0000f7db, 0x0000f7db,
	0x0000f7db, 0x0000f7db, 0x0000f7db, 0x0000f7db, 0x0000f7db,
	0x0000f7db, 0x0000f7db, 0x0000f7db, 0x0000f7db, 0x0000f7db,
	0x0000f7db, 0x0000f7db, 0x0000f7db, 0x0000f7db, 0x0000f7db,
	0x0000f7db, 0x0000f7db, 0x0000f7db, 0x00001066, 0x00001066
};

static const uint32_t ar9280_2_0_rx_gain_vals_2g[] = {
	0x00008000, 0x00008000, 0x00008000, 0x00008000, 0x00008000,
	0x00008000, 0x00008004, 0x00008008, 0x0000800c, 0x00008080,
	0x00008084, 0x00008088, 0x0000808c, 0x00008100, 0x00008104,
	0x00008108, 0x0000810c, 0x00008110, 0x00008114, 0x00008180,
	0x00008184, 0x00008188, 0x0000818c, 0x00008190, 0x00008194,
	0x000081a0, 0x0000820c, 0x000081a8, 0x00008284, 0x00008288,
	0x00008224, 0x00008290, 0x00008300, 0x00008304, 0x00008308,
	0x0000830c, 0x00008380, 0x00008384, 0x00008700, 0x00008704,
	0x00008708, 0x0000870c, 0x00008780, 0x00008784, 0x00008b00,
	0x00008b04, 0x00008b08, 0x00008b0c, 0x00008b80, 0x00008b84,
	0x00008b88, 0x00008b8c, 0x00008b90, 0x00008f80, 0x00008f84,
	0x00008f88, 0x00008f8c, 0x00008f90, 0x0000930c, 0x00009310,
	0x00009384, 0x00009388, 0x00009324, 0x00009704, 0x000096a4,
	0x000096a8, 0x00009710, 0x00009714, 0x00009720, 0x00009724,
	0x00009728, 0x0000972c, 0x000097a0, 0x000097a4, 0x000097a8,
	0x000097b0, 0x000097b4, 0x000097b8, 0x000097a5, 0x000097a9,
	0x000097ad, 0x000097b1, 0x000097b5, 0x000097b9, 0x000097c5,
	0x000097c9, 0x000097d1, 0x000097d5, 0x000097d9, 0x000097c6,
	0x000097ca, 0x000097ce, 0x000097d2, 0x000097d6, 0x000097c3,
	0x000097c7, 0x000097cb, 0x000097cf, 0x000097d7, 0x000097db,
	0x000097db, 0x000097db, 0x000097db, 0x000097db, 0x000097db,
	0x000097db, 0x000097db, 0x000097db, 0x000097db, 0x000097db,
	0x000097db, 0x000097db, 0x000097db, 0x000097db, 0x000097db,
	0x000097db, 0x000097db, 0x000097db, 0x000097db, 0x000097db,
	0x000097db, 0x000097db, 0x000097db, 0x000097db, 0x000097db,
	0x000097db, 0x000097db, 0x000097db, 0x00001063, 0x00001063
};

static const struct athn_gain ar9280_2_0_rx_gain = {
	nitems(ar9280_2_0_rx_gain_regs),
	ar9280_2_0_rx_gain_regs,
	ar9280_2_0_rx_gain_vals_5g,
	ar9280_2_0_rx_gain_vals_2g
};

static const uint32_t ar9280_2_0_rx_gain_13db_backoff_vals_5g[] = {
	0x00008184, 0x00008188, 0x0000818c, 0x00008190, 0x00008194,
	0x00008200, 0x00008204, 0x00008208, 0x0000820c, 0x00008210,
	0x00008214, 0x00008280, 0x00008284, 0x00008288, 0x0000828c,
	0x00008290, 0x00008300, 0x00008304, 0x00008308, 0x0000830c,
	0x00008310, 0x00008314, 0x00008380, 0x00008384, 0x00008388,
	0x0000838c, 0x00008390, 0x00008394, 0x0000a380, 0x0000a384,
	0x0000a388, 0x0000a38c, 0x0000a390, 0x0000a394, 0x0000a780,
	0x0000a784, 0x0000a788, 0x0000a78c, 0x0000a790, 0x0000a794,
	0x0000ab84, 0x0000ab88, 0x0000ab8c, 0x0000ab90, 0x0000ab94,
	0x0000af80, 0x0000af84, 0x0000af88, 0x0000af8c, 0x0000af90,
	0x0000af94, 0x0000b380, 0x0000b384, 0x0000b388, 0x0000b38c,
	0x0000b390, 0x0000b394, 0x0000b398, 0x0000b780, 0x0000b784,
	0x0000b788, 0x0000b78c, 0x0000b790, 0x0000b794, 0x0000b798,
	0x0000d784, 0x0000d788, 0x0000d78c, 0x0000d790, 0x0000f780,
	0x0000f784, 0x0000f788, 0x0000f78c, 0x0000f790, 0x0000f794,
	0x0000f7a4, 0x0000f7a8, 0x0000f7ac, 0x0000f7b0, 0x0000f7b4,
	0x0000f7a1, 0x0000f7a5, 0x0000f7a9, 0x0000f7ad, 0x0000f7b1,
	0x0000f7b5, 0x0000f7c5, 0x0000f7c9, 0x0000f7cd, 0x0000f7d1,
	0x0000f7d5, 0x0000f7c2, 0x0000f7c6, 0x0000f7ca, 0x0000f7ce,
	0x0000f7d2, 0x0000f7d6, 0x0000f7c3, 0x0000f7c7, 0x0000f7cb,
	0x0000f7d3, 0x0000f7d7, 0x0000f7db, 0x0000f7db, 0x0000f7db,
	0x0000f7db, 0x0000f7db, 0x0000f7db, 0x0000f7db, 0x0000f7db,
	0x0000f7db, 0x0000f7db, 0x0000f7db, 0x0000f7db, 0x0000f7db,
	0x0000f7db, 0x0000f7db, 0x0000f7db, 0x0000f7db, 0x0000f7db,
	0x0000f7db, 0x0000f7db, 0x0000f7db, 0x0000f7db, 0x0000f7db,
	0x0000f7db, 0x0000f7db, 0x0000f7db, 0x00001066, 0x00001066
};

static const uint32_t ar9280_2_0_rx_gain_13db_backoff_vals_2g[] = {
	0x00000290, 0x00000300, 0x00000304, 0x00000308, 0x0000030c,
	0x00008000, 0x00008004, 0x00008008, 0x0000800c, 0x00008080,
	0x00008084, 0x00008088, 0x0000808c, 0x00008100, 0x00008104,
	0x00008108, 0x0000810c, 0x00008110, 0x00008114, 0x00008180,
	0x00008184, 0x00008188, 0x0000818c, 0x00008190, 0x00008194,
	0x000081a0, 0x0000820c, 0x000081a8, 0x00008284, 0x00008288,
	0x00008224, 0x00008290, 0x00008300, 0x00008304, 0x00008308,
	0x0000830c, 0x00008380, 0x00008384, 0x00008700, 0x00008704,
	0x00008708, 0x0000870c, 0x00008780, 0x00008784, 0x00008b00,
	0x00008b04, 0x00008b08, 0x00008b0c, 0x00008b80, 0x00008b84,
	0x00008b88, 0x00008b8c, 0x00008b90, 0x00008f80, 0x00008f84,
	0x00008f88, 0x00008f8c, 0x00008f90, 0x00009310, 0x00009314,
	0x00009320, 0x00009324, 0x00009328, 0x0000932c, 0x00009330,
	0x00009334, 0x00009321, 0x00009325, 0x00009329, 0x0000932d,
	0x00009331, 0x00009335, 0x00009322, 0x00009326, 0x0000932a,
	0x0000932e, 0x00009332, 0x00009336, 0x00009323, 0x00009327,
	0x0000932b, 0x0000932f, 0x00009333, 0x00009337, 0x00009343,
	0x00009347, 0x0000934b, 0x0000934f, 0x00009353, 0x00009357,
	0x0000935b, 0x0000935b, 0x0000935b, 0x0000935b, 0x0000935b,
	0x0000935b, 0x0000935b, 0x0000935b, 0x0000935b, 0x0000935b,
	0x0000935b, 0x0000935b, 0x0000935b, 0x0000935b, 0x0000935b,
	0x0000935b, 0x0000935b, 0x0000935b, 0x0000935b, 0x0000935b,
	0x0000935b, 0x0000935b, 0x0000935b, 0x0000935b, 0x0000935b,
	0x0000935b, 0x0000935b, 0x0000935b, 0x0000935b, 0x0000935b,
	0x0000935b, 0x0000935b, 0x0000935b, 0x0000935b, 0x0000935b,
	0x0000935b, 0x0000935b, 0x0000935b, 0x0000105a, 0x0000105a
};

static const struct athn_gain ar9280_2_0_rx_gain_13db_backoff = {
	nitems(ar9280_2_0_rx_gain_regs),
	ar9280_2_0_rx_gain_regs,
	ar9280_2_0_rx_gain_13db_backoff_vals_5g,
	ar9280_2_0_rx_gain_13db_backoff_vals_2g
};

static const uint32_t ar9280_2_0_rx_gain_23db_backoff_vals_5g[] = {
	0x00008184, 0x00008188, 0x0000818c, 0x00008190, 0x00008194,
	0x00008200, 0x00008204, 0x00008208, 0x0000820c, 0x00008210,
	0x00008214, 0x00008280, 0x00008284, 0x00008288, 0x0000828c,
	0x00008290, 0x00008300, 0x00008304, 0x00008308, 0x0000830c,
	0x00008310, 0x00008314, 0x00008380, 0x00008384, 0x00008388,
	0x0000838c, 0x00008390, 0x00008394, 0x0000a380, 0x0000a384,
	0x0000a388, 0x0000a38c, 0x0000a390, 0x0000a394, 0x0000a780,
	0x0000a784, 0x0000a788, 0x0000a78c, 0x0000a790, 0x0000a794,
	0x0000ab84, 0x0000ab88, 0x0000ab8c, 0x0000ab90, 0x0000ab94,
	0x0000af80, 0x0000af84, 0x0000af88, 0x0000af8c, 0x0000af90,
	0x0000af94, 0x0000b380, 0x0000b384, 0x0000b388, 0x0000b38c,
	0x0000b390, 0x0000b394, 0x0000b398, 0x0000b780, 0x0000b784,
	0x0000b788, 0x0000b78c, 0x0000b790, 0x0000b794, 0x0000b798,
	0x0000d784, 0x0000d788, 0x0000d78c, 0x0000d790, 0x0000f780,
	0x0000f784, 0x0000f788, 0x0000f78c, 0x0000f790, 0x0000f794,
	0x0000f7a4, 0x0000f7a8, 0x0000f7ac, 0x0000f7b0, 0x0000f7b4,
	0x0000f7a1, 0x0000f7a5, 0x0000f7a9, 0x0000f7ad, 0x0000f7b1,
	0x0000f7b5, 0x0000f7c5, 0x0000f7c9, 0x0000f7cd, 0x0000f7d1,
	0x0000f7d5, 0x0000f7c2, 0x0000f7c6, 0x0000f7ca, 0x0000f7ce,
	0x0000f7d2, 0x0000f7d6, 0x0000f7c3, 0x0000f7c7, 0x0000f7cb,
	0x0000f7d3, 0x0000f7d7, 0x0000f7db, 0x0000f7db, 0x0000f7db,
	0x0000f7db, 0x0000f7db, 0x0000f7db, 0x0000f7db, 0x0000f7db,
	0x0000f7db, 0x0000f7db, 0x0000f7db, 0x0000f7db, 0x0000f7db,
	0x0000f7db, 0x0000f7db, 0x0000f7db, 0x0000f7db, 0x0000f7db,
	0x0000f7db, 0x0000f7db, 0x0000f7db, 0x0000f7db, 0x0000f7db,
	0x0000f7db, 0x0000f7db, 0x0000f7db, 0x00001066, 0x00001066
};

static const uint32_t ar9280_2_0_rx_gain_23db_backoff_vals_2g[] = {
	0x00000290, 0x00000300, 0x00000304, 0x00000308, 0x0000030c,
	0x00008000, 0x00008004, 0x00008008, 0x0000800c, 0x00008080,
	0x00008084, 0x00008088, 0x0000808c, 0x00008100, 0x00008104,
	0x00008108, 0x0000810c, 0x00008110, 0x00008114, 0x00008180,
	0x00008184, 0x00008188, 0x0000818c, 0x00008190, 0x00008194,
	0x000081a0, 0x0000820c, 0x000081a8, 0x00008284, 0x00008288,
	0x00008224, 0x00008290, 0x00008300, 0x00008304, 0x00008308,
	0x0000830c, 0x00008380, 0x00008384, 0x00008700, 0x00008704,
	0x00008708, 0x0000870c, 0x00008780, 0x00008784, 0x00008b00,
	0x00008b04, 0x00008b08, 0x00008b0c, 0x00008b10, 0x00008b80,
	0x00008b84, 0x00008b88, 0x00008b8c, 0x00008b90, 0x00008b94,
	0x00008b98, 0x00008ba4, 0x00008ba8, 0x00008bac, 0x00008bb0,
	0x00008bb4, 0x00008ba1, 0x00008ba5, 0x00008ba9, 0x00008bad,
	0x00008bb1, 0x00008bb5, 0x00008ba2, 0x00008ba6, 0x00008baa,
	0x00008bae, 0x00008bb2, 0x00008bb6, 0x00008ba3, 0x00008ba7,
	0x00008bab, 0x00008baf, 0x00008bb3, 0x00008bb7, 0x00008bc3,
	0x00008bc7, 0x00008bcb, 0x00008bcf, 0x00008bd3, 0x00008bd7,
	0x00008bdb, 0x00008bdb, 0x00008bdb, 0x00008bdb, 0x00008bdb,
	0x00008bdb, 0x00008bdb, 0x00008bdb, 0x00008bdb, 0x00008bdb,
	0x00008bdb, 0x00008bdb, 0x00008bdb, 0x00008bdb, 0x00008bdb,
	0x00008bdb, 0x00008bdb, 0x00008bdb, 0x00008bdb, 0x00008bdb,
	0x00008bdb, 0x00008bdb, 0x00008bdb, 0x00008bdb, 0x00008bdb,
	0x00008bdb, 0x00008bdb, 0x00008bdb, 0x00008bdb, 0x00008bdb,
	0x00008bdb, 0x00008bdb, 0x00008bdb, 0x00008bdb, 0x00008bdb,
	0x00008bdb, 0x00008bdb, 0x00008bdb, 0x00008bdb, 0x00008bdb,
	0x00008bdb, 0x00008bdb, 0x00008bdb, 0x00001055, 0x00001055
};

static const struct athn_gain ar9280_2_0_rx_gain_23db_backoff = {
	nitems(ar9280_2_0_rx_gain_regs),
	ar9280_2_0_rx_gain_regs,
	ar9280_2_0_rx_gain_23db_backoff_vals_5g,
	ar9280_2_0_rx_gain_23db_backoff_vals_2g
};

/*
 * Serializer/Deserializer programming.
 */

static const uint32_t ar9280_2_0_serdes_regs[] = {
	AR_PCIE_SERDES,
	AR_PCIE_SERDES,
	AR_PCIE_SERDES,
	AR_PCIE_SERDES,
	AR_PCIE_SERDES,
	AR_PCIE_SERDES,
	AR_PCIE_SERDES,
	AR_PCIE_SERDES,
	AR_PCIE_SERDES,
	AR_PCIE_SERDES2,
};

static const uint32_t ar9280_2_0_serdes_vals[] = {
	0x9248fd00,
	0x24924924,
	0xa8000019,
	0x13160820,
	0xe5980560,
#ifdef ATHN_PCIE_CLKREQ
	0xc01dcffc,
#else
	0xc01dcffd,
#endif
	0x1aaabe41,
	0xbe105554,
	0x00043007,
	0x00000000
};

static const struct athn_serdes ar9280_2_0_serdes = {
	nitems(ar9280_2_0_serdes_vals),
	ar9280_2_0_serdes_regs,
	ar9280_2_0_serdes_vals
};