code:
/*	$OpenBSD: bwireg.h,v 1.9 2014/06/07 11:55:02 stsp Exp $	*/

/*
 * Copyright (c) 2007 The DragonFly Project.  All rights reserved.
 *
 * This code is derived from software contributed to The DragonFly Project
 * by Sepherosa Ziehau <sepherosa@gmail.com>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 * 3. Neither the name of The DragonFly Project nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific, prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 * $DragonFly: src/sys/dev/netif/bwi/if_bwireg.h,v 1.1 2007/09/08 06:15:54 sephe Exp $
 */

#ifndef _IF_BWIREG_H
#define _IF_BWIREG_H

/*
 * Registers for all of the register windows
 */
#define BWI_FLAGS			0x00000f18
#define BWI_FLAGS_INTR_MASK		0x0000003f

#define BWI_IMSTATE			0x00000f90
#define BWI_IMSTATE_INBAND_ERR		(1 << 17)
#define BWI_IMSTATE_TIMEOUT		(1 << 18)

#define BWI_INTRVEC			0x00000f94

#define BWI_STATE_LO			0x00000f98
#define BWI_STATE_LO_RESET		(1 << 0)
#define BWI_STATE_LO_DISABLE1		(1 << 1)
#define BWI_STATE_LO_DISABLE2		(1 << 2)
#define BWI_STATE_LO_CLOCK		(1 << 16)
#define BWI_STATE_LO_GATED_CLOCK	(1 << 17)
#define BWI_STATE_LO_FLAG_PHYCLKEN	(1 << 0)
#define BWI_STATE_LO_FLAG_PHYRST	(1 << 1)
#define BWI_STATE_LO_FLAG_PHYLNK	(1 << 11)
#define BWI_STATE_LO_FLAGS_MASK		0x3ffc0000

#define BWI_STATE_HI			0x00000f9c
#define BWI_STATE_HI_SERROR		(1 << 0)
#define BWI_STATE_HI_BUSY		(1 << 2)
#define BWI_STATE_HI_FLAG_MAGIC1	0x1
#define BWI_STATE_HI_FLAG_MAGIC2	0x2
#define BWI_STATE_HI_FLAG_64BIT		0x1000
#define BWI_STATE_HI_FLAGS_MASK		0x1fff0000

#define BWI_CONF_LO			0x00000fa8
#define BWI_CONF_LO_SERVTO_MASK		0x00000007	/* service timeout */
#define BWI_CONF_LO_SERVTO		2
#define BWI_CONF_LO_REQTO_MASK		0x00000070	/* request timeout */
#define BWI_CONF_LO_REQTO		3

#define BWI_ID_LO			0x00000ff8
#define BWI_ID_LO_BUSREV_MASK		0xf0000000
/* Bus revision */
#define BWI_BUSREV_0			0
#define BWI_BUSREV_1			1

#define BWI_ID_HI			0x00000ffc
#define BWI_ID_HI_REGWIN_REV(v)		(((v) & 0xf) | (((v) & 0x7000) >> 8))
#define BWI_ID_HI_REGWIN_TYPE(v)	(((v) & 0x8ff0) >> 4)
#define BWI_ID_HI_REGWIN_VENDOR_MASK	0xffff0000

/*
 * Registers for common register window
 */
#define BWI_INFO			0x00000000
#define BWI_INFO_BBPID_MASK		0x0000ffff
#define BWI_INFO_BBPREV_MASK		0x000f0000
#define BWI_INFO_BBPPKG_MASK		0x00f00000
#define BWI_INFO_NREGWIN_MASK		0x0f000000

#define BWI_CAPABILITY			0x00000004
#define BWI_CAP_CLKMODE			(1 << 18)

#define BWI_CONTROL			0x00000028
#define BWI_CONTROL_MAGIC0		0x3a4
#define BWI_CONTROL_MAGIC1		0xa4
#define BWI_PLL_ON_DELAY		0xb0
#define BWI_FREQ_SEL_DELAY		0xb4

#define BWI_CLOCK_CTRL			0x000000b8
#define BWI_CLOCK_CTRL_CLKSRC		(7 << 0)
#define BWI_CLOCK_CTRL_SLOW		(1 << 11)
#define BWI_CLOCK_CTRL_IGNPLL		(1 << 12)
#define BWI_CLOCK_CTRL_NODYN		(1 << 13)
#define BWI_CLOCK_CTRL_FDIV		(0xffff << 16)	/* freq divisor */

/* Possible values for BWI_CLOCK_CTRL_CLKSRC */
#define BWI_CLKSRC_LP_OSC		0	/* Low power oscillator */
#define BWI_CLKSRC_CS_OSC		1	/* Crystal oscillator */
#define BWI_CLKSRC_PCI			2
#define BWI_CLKSRC_MAX			3	/* Maximum of clock source */
/* Min/Max frequency for given clock source */
#define BWI_CLKSRC_LP_OSC_FMIN		25000
#define BWI_CLKSRC_LP_OSC_FMAX		43000
#define BWI_CLKSRC_CS_OSC_FMIN		19800000
#define BWI_CLKSRC_CS_OSC_FMAX		20200000
#define BWI_CLKSRC_PCI_FMIN		25000000
#define BWI_CLKSRC_PCI_FMAX		34000000

#define BWI_CLOCK_INFO			0x000000c0
#define BWI_CLOCK_INFO_FDIV		(0xffff << 16)	/* freq divisor */

/*
 * Registers for bus register window
 */
#define BWI_BUS_ADDR			0x00000050
#define BWI_BUS_ADDR_MAGIC		0xfd8

#define BWI_BUS_DATA			0x00000054

#define BWI_BUS_CONFIG			0x00000108
#define BWI_BUS_CONFIG_PREFETCH		(1 << 2)
#define BWI_BUS_CONFIG_BURST		(1 << 3)
#define BWI_BUS_CONFIG_MRM		(1 << 5)

/*
 * Register for MAC
 */
#define BWI_TXRX_INTR_STATUS_BASE	0x20
#define BWI_TXRX_INTR_MASK_BASE		0x24
#define BWI_TXRX_INTR_STATUS(i)		(BWI_TXRX_INTR_STATUS_BASE + ((i) * 8))
#define BWI_TXRX_INTR_MASK(i)		(BWI_TXRX_INTR_MASK_BASE + ((i) * 8))

#define BWI_MAC_STATUS			0x00000120
#define BWI_MAC_STATUS_ENABLE		(1U << 0)
#define BWI_MAC_STATUS_UCODE_START	(1U << 1)
#define BWI_MAC_STATUS_UCODE_JUMP0	(1U << 2)
#define BWI_MAC_STATUS_IHREN		(1U << 10)
#define BWI_MAC_STATUS_GPOSEL_MASK	(3U << 14)
#define BWI_MAC_STATUS_BSWAP		(1U << 16)
#define BWI_MAC_STATUS_INFRA		(1U << 17)
#define BWI_MAC_STATUS_OPMODE_HOSTAP	(1U << 18)
#define BWI_MAC_STATUS_RFLOCK		(1U << 19)
#define BWI_MAC_STATUS_PASS_BCN		(1U << 20)
#define BWI_MAC_STATUS_PASS_BADPLCP	(1U << 21)
#define BWI_MAC_STATUS_PASS_CTL		(1U << 22)
#define BWI_MAC_STATUS_PASS_BADFCS	(1U << 23)
#define BWI_MAC_STATUS_PROMISC		(1U << 24)
#define BWI_MAC_STATUS_HW_PS		(1U << 25)
#define BWI_MAC_STATUS_WAKEUP		(1U << 26)
#define BWI_MAC_STATUS_PHYLNK		(1U << 31)

#define BWI_MAC_INTR_STATUS		0x00000128
#define BWI_MAC_INTR_MASK		0x0000012c

#define BWI_MAC_TMPLT_CTRL		0x00000130
#define BWI_MAC_TMPLT_DATA		0x00000134

#define BWI_MAC_PS_STATUS		0x00000140

#define BWI_MOBJ_CTRL			0x00000160
#define BWI_MOBJ_CTRL_VAL(objid, ofs)	((objid) << 16 | (ofs))
#define BWI_MOBJ_DATA			0x00000164
#define BWI_MOBJ_DATA_UNALIGN		0x0166

/*
 * Memory object IDs
 */
#define BWI_WR_MOBJ_AUTOINC		0x100	/* Auto-increment wr */
#define BWI_RD_MOBJ_AUTOINC		0x200	/* Auto-increment rd */
/* Firmware ucode object */
#define BWI_FW_UCODE_MOBJ		0x0
/* Common object */
#define BWI_COMM_MOBJ			0x1
#define BWI_COMM_MOBJ_FWREV		0x0
#define BWI_COMM_MOBJ_FWPATCHLV		0x2
#define BWI_COMM_MOBJ_SLOTTIME		0x10
#define BWI_COMM_MOBJ_MACREV		0x16
#define BWI_COMM_MOBJ_TX_ACK		0x22
#define BWI_COMM_MOBJ_UCODE_STATE	0x40
#define BWI_COMM_MOBJ_SHRETRY_FB	0x44
#define BWI_COMM_MOBJ_LGRETEY_FB	0x46
#define BWI_COMM_MOBJ_TX_BEACON		0x54
#define BWI_COMM_MOBJ_KEYTABLE_OFS	0x56
#define BWI_COMM_MOBJ_TSSI_DS		0x58
#define BWI_COMM_MOBJ_HFLAGS_LO		0x5e
#define BWI_COMM_MOBJ_HFLAGS_MI		0x60
#define BWI_COMM_MOBJ_HFLAGS_HI		0x62
#define BWI_COMM_MOBJ_RF_ATTEN		0x64
#define BWI_COMM_MOBJ_TSSI_OFDM		0x70
#define BWI_COMM_MOBJ_PROBE_RESP_TO	0x74
#define BWI_COMM_MOBJ_CHAN		0xa0
#define BWI_COMM_MOBJ_KEY_ALGO		0x100
#define BWI_COMM_MOBJ_TX_PROBE_RESP	0x188
#define BWI_HFLAG_AUTO_ANTDIV		0x1ULL
#define BWI_HFLAG_SYM_WA		0x2ULL	/* ??? SYM work around */
#define BWI_HFLAG_PWR_BOOST_DS		0x8ULL
#define BWI_HFLAG_GDC_WA		0x20ULL	/* ??? GDC work around */
#define BWI_HFLAG_OFDM_PA		0x40ULL
#define BWI_HFLAG_NOT_JAPAN		0x80ULL
#define BWI_HFLAG_MAGIC1		0x200ULL
#define BWI_UCODE_STATE_PS		4
#define BWI_LO_TSSI_MASK		0x00ff
#define BWI_HI_TSSI_MASK		0xff00
#define BWI_INVALID_TSSI		0x7f
/* 802.11 object */
#define BWI_80211_MOBJ			0x2
#define BWI_80211_MOBJ_CWMIN		0xc
#define BWI_80211_MOBJ_CWMAX		0x10
#define BWI_80211_MOBJ_SHRETRY		0x18
#define BWI_80211_MOBJ_LGRETRY		0x1c
/* Firmware PCM object */
#define BWI_FW_PCM_MOBJ			0x3
/* MAC address of pairwise keys */
#define BWI_PKEY_ADDR_MOBJ		0x4

#define BWI_TXSTATUS_0			0x00000170
#define BWI_TXSTATUS_0_MORE		(1 << 0)
#define BWI_TXSTATUS_0_TXID_MASK	0xffff0000
#define BWI_TXSTATUS_0_INFO(st)		(((st) & 0xfff0) | (((st) & 0xf) >> 1))
#define BWI_TXSTATUS_1			0x00000174

#define BWI_TXRX_CTRL_BASE		0x200
#define BWI_TX32_CTRL			0x0
#define BWI_TX32_RINGINFO		0x4
#define BWI_TX32_INDEX			0x8
#define BWI_TX32_STATUS			0xc
#define BWI_TX32_STATUS_STATE_MASK	0xf000
#define BWI_TX32_STATUS_STATE_DISABLED	0
#define BWI_TX32_STATUS_STATE_IDLE	2
#define BWI_TX32_STATUS_STATE_STOPPED	3
#define BWI_RX32_CTRL			0x10
#define BWI_RX32_CTRL_HDRSZ_MASK	0x00fe
#define BWI_RX32_RINGINFO		0x14
#define BWI_RX32_INDEX			0x18
#define BWI_RX32_STATUS			0x1c
#define BWI_RX32_STATUS_INDEX_MASK	0x0fff
#define BWI_RX32_STATUS_STATE_MASK	0xf000
#define BWI_RX32_STATUS_STATE_DISABLED	0
/* Shared by 32bit TX/RX CTRL */
#define BWI_TXRX32_CTRL_ENABLE		(1 << 0)
#define BWI_TXRX32_CTRL_ADDRHI_MASK	0x00030000
/* Shared by 32bit TX/RX RINGINFO */
#define BWI_TXRX32_RINGINFO_FUNC_TXRX	0x1
#define BWI_TXRX32_RINGINFO_FUNC_MASK	0xc0000000
#define BWI_TXRX32_RINGINFO_ADDR_MASK	0x3fffffff

#define BWI_PHYINFO			0x03e0
#define BWI_PHYINFO_REV_MASK		0x000f
#define BWI_PHYINFO_TYPE_MASK		0x0f00
#define BWI_PHYINFO_TYPE_11A		0
#define BWI_PHYINFO_TYPE_11B		1
#define BWI_PHYINFO_TYPE_11G		2
#define BWI_PHYINFO_TYPE_11N		5
#define BWI_PHYINFO_VER_MASK		0xf000

#define BWI_RF_ANTDIV			0x03e2	/* Antenna Diversity ?? */

#define BWI_PHY_MAGIC_REG1		0x03e4
#define BWI_PHY_MAGIC_REG1_VAL1		0x3000
#define BWI_PHY_MAGIC_REG1_VAL2		0x0009

#define BWI_BBP_ATTEN			0x03e6
#define BWI_BBP_ATTEN_MAGIC		0x00f4
#define BWI_BBP_ATTEN_MAGIC2		0x8140

#define BWI_BPHY_CTRL			0x03ec
#define BWI_BPHY_CTRL_INIT		0x3f22

#define BWI_RF_CHAN			0x03f0
#define BWI_RF_CHAN_EX			0x03f4

#define BWI_RF_CTRL			0x03f6
/* Register values for BWI_RF_CTRL */
#define BWI_RF_CTRL_RFINFO		0x1
/* XXX extra bits for reading from radio */
#define BWI_RF_CTRL_RD_11A		0x40
#define BWI_RF_CTRL_RD_11BG		0x80
#define BWI_RF_DATA_HI			0x3f8
#define BWI_RF_DATA_LO			0x3fa
/* Values read from BWI_RF_DATA_{HI,LO} after BWI_RF_CTRL_RFINFO */
#define BWI_RFINFO_MANUFACT_MASK	0x0fff
#define BWI_RF_MANUFACT_BCM		0x17f		/* XXX */
#define BWI_RFINFO_TYPE_MASK		0x0ffff000
#define BWI_RF_T_BCM2050		0x2050
#define BWI_RF_T_BCM2053		0x2053
#define BWI_RF_T_BCM2060		0x2060
#define BWI_RFINFO_REV_MASK		0xf0000000

#define BWI_PHY_CTRL			0x03fc
#define BWI_PHY_DATA			0x03fe

#define BWI_ADDR_FILTER_CTRL		0x0420
#define BWI_ADDR_FILTER_CTRL_SET	0x0020
#define BWI_ADDR_FILTER_MYADDR		0
#define BWI_ADDR_FILTER_BSSID		3
#define BWI_ADDR_FILTER_DATA		0x422

#define BWI_MAC_GPIO_CTRL		0x049c
#define BWI_MAC_GPIO_MASK		0x049e
#define BWI_MAC_PRE_TBTT		0x0612
#define BWI_MAC_SLOTTIME		0x0684
#define BWI_MAC_SLOTTIME_ADJUST		510
#define BWI_MAC_POWERUP_DELAY		0x06a8

/*
 * Special registers
 */
/*
 * GPIO control
 * If common regwin exists, then it is within common regwin,
 * else it is in bus regwin.
 */
#define BWI_GPIO_CTRL			0x0000006c

/*
 * Extended PCI registers
 */
#define BWI_PCIR_BAR			PCIR_BAR(0)
#define BWI_PCIR_SEL_REGWIN		0x00000080
/* Register value for BWI_PCIR_SEL_REGWIN */
#define BWI_PCIM_REGWIN(id)		(((id) * 0x1000) + 0x18000000)
#define BWI_PCIR_GPIO_IN		0x000000b0
#define BWI_PCIR_GPIO_OUT		0x000000b4
#define BWI_PCIM_GPIO_OUT_CLKSRC	(1 << 4)
#define BWI_PCIR_GPIO_ENABLE		0x000000b8
/* Register values for BWI_PCIR_GPIO_{IN,OUT,ENABLE} */
#define BWI_PCIM_GPIO_PWR_ON		(1 << 6)
#define BWI_PCIM_GPIO_PLL_PWR_OFF	(1 << 7)
#define BWI_PCIR_INTCTL			0x00000094

/*
 * PCI subdevice IDs
 */
#define BWI_PCI_SUBDEVICE_BU4306	0x416
#define BWI_PCI_SUBDEVICE_BCM4309G	0x421

#define BWI_IS_BRCM_BU4306(sc)					\
	((sc)->sc_pci_subvid == PCI_VENDOR_BROADCOM &&		\
	 (sc)->sc_pci_subdid == BWI_PCI_SUBDEVICE_BU4306)
#define BWI_IS_BRCM_BCM4309G(sc)				\
	((sc)->sc_pci_subvid == PCI_VENDOR_BROADCOM &&		\
	 (sc)->sc_pci_subdid == BWI_PCI_SUBDEVICE_BCM4309G)

/*
 * EEPROM start address
 */
#define BWI_SPROM_START			0x1000
#define BWI_SPROM_11BG_EADDR		0x48
#define BWI_SPROM_11A_EADDR		0x54
#define BWI_SPROM_CARD_INFO		0x5c
#define BWI_SPROM_CARD_INFO_LOCALE	(0x0f << 8)
#define BWI_SPROM_LOCALE_JAPAN		5
#define BWI_SPROM_PA_PARAM_11BG		0x5e
#define BWI_SPROM_GPIO01		0x64
#define BWI_SPROM_GPIO_0		0x00ff
#define BWI_SPROM_GPIO_1		0xff00
#define BWI_SPROM_GPIO23		0x0066
#define BWI_SPROM_GPIO_2		0x00ff
#define BWI_SPROM_GPIO_3		0xff00
#define BWI_SPROM_MAX_TXPWR		0x68
#define BWI_SPROM_MAX_TXPWR_MASK_11BG	0x00ff		/* XXX */
#define BWI_SPROM_MAX_TXPWR_MASK_11A	0xff00		/* XXX */
#define BWI_SPROM_PA_PARAM_11A		0x6a
#define BWI_SPROM_IDLE_TSSI		0x70
#define BWI_SPROM_IDLE_TSSI_MASK_11BG	0x00ff		/* XXX */
#define BWI_SPROM_IDLE_TSSI_MASK_11A	0xff00		/* XXX */
#define BWI_SPROM_CARD_FLAGS		0x72
#define BWI_SPROM_ANT_GAIN		0x74
#define BWI_SPROM_ANT_GAIN_MASK_11A	0x00ff
#define BWI_SPROM_ANT_GAIN_MASK_11BG	0xff00

/*
 * SPROM card flags
 */
#define BWI_CARD_F_PA_GPIO9		(1 << 1)	/* GPIO 9 controls PA */
#define BWI_CARD_F_SW_NRSSI		(1 << 3)
#define BWI_CARD_F_NO_SLOWCLK		(1 << 5)	/* no slow clock */
#define BWI_CARD_F_EXT_LNA		(1 << 12)	/* external LNA */
#define BWI_CARD_F_ALT_IQ		(1 << 15)	/* alternate I/Q */

/*
 * PROM GPIO
 */
#define BWI_LED_ACT_LOW			(1 << 7)
#define BWI_LED_ACT_MASK		0x7f
#define BWI_LED_ACT_OFF			0
#define BWI_LED_ACT_ON			1
#define BWI_LED_ACT_BLINK		2
#define BWI_LED_ACT_RF_ENABLED		3
#define BWI_LED_ACT_5GHZ		4
#define BWI_LED_ACT_2GHZ		5
#define BWI_LED_ACT_11G			6
#define BWI_LED_ACT_BLINK_SLOW		7
#define BWI_LED_ACT_BLINK_POLL		8
#define BWI_LED_ACT_UNKN		9
#define BWI_LED_ACT_ASSOC		10
#define BWI_LED_ACT_NULL		11

#define BWI_VENDOR_LED_ACT_COMPAQ	\
	BWI_LED_ACT_RF_ENABLED,		\
	BWI_LED_ACT_2GHZ,		\
	BWI_LED_ACT_5GHZ,		\
	BWI_LED_ACT_OFF

#define BWI_VENDOR_LED_ACT_LINKSYS	\
	BWI_LED_ACT_ASSOC,		\
	BWI_LED_ACT_2GHZ,		\
	BWI_LED_ACT_5GHZ,		\
	BWI_LED_ACT_OFF

#define BWI_VENDOR_LED_ACT_DEFAULT	\
	BWI_LED_ACT_BLINK,		\
	BWI_LED_ACT_2GHZ,		\
	BWI_LED_ACT_5GHZ,		\
	BWI_LED_ACT_OFF

/*
 * BBP IDs
 */
#define BWI_BBPID_BCM4301		0x4301
#define BWI_BBPID_BCM4306		0x4306
#define BWI_BBPID_BCM4317		0x4317
#define BWI_BBPID_BCM4320		0x4320
#define BWI_BBPID_BCM4321		0x4321

/*
 * Register window types
 */
#define BWI_REGWIN_T_COM		0x800
#define BWI_REGWIN_T_BUSPCI		0x804
#define BWI_REGWIN_T_MAC		0x812
#define BWI_REGWIN_T_BUSPCIE		0x820

/*
 * MAC interrupts
 */
#define BWI_INTR_READY			(1 << 0)
#define BWI_INTR_BEACON			(1 << 1)
#define BWI_INTR_TBTT			(1 << 2)
#define BWI_INTR_EO_ATIM		(1 << 5)	/* End of ATIM */
#define BWI_INTR_PMQ			(1 << 6)	/* XXX?? */
#define BWI_INTR_MAC_TXERR		(1 << 9)
#define BWI_INTR_PHY_TXERR		(1 << 11)
#define BWI_INTR_TIMER1			(1 << 14)
#define BWI_INTR_RX_DONE		(1 << 15)
#define BWI_INTR_TX_FIFO		(1 << 16)	/* XXX?? */
#define BWI_INTR_NOISE			(1 << 18)
#define BWI_INTR_RF_DISABLED		(1 << 28)
#define BWI_INTR_TX_DONE		(1 << 29)

#define BWI_INIT_INTRS							\
	(BWI_INTR_READY | BWI_INTR_BEACON | BWI_INTR_TBTT |		\
	 BWI_INTR_EO_ATIM | BWI_INTR_PMQ | BWI_INTR_MAC_TXERR |		\
	 BWI_INTR_PHY_TXERR | BWI_INTR_RX_DONE | BWI_INTR_TX_FIFO |	\
	 BWI_INTR_NOISE | BWI_INTR_RF_DISABLED | BWI_INTR_TX_DONE)
#define BWI_ALL_INTRS			0xffffffff

/*
 * TX/RX interrupts
 */

/* from brcmsmac */
#define	BWI_I_PC		(1 << 10)	/* pci descriptor error */
#define	BWI_I_PD		(1 << 11)	/* pci data error */
#define	BWI_I_DE		(1 << 12)	/* descriptor protocol error */
#define	BWI_I_RU		(1 << 13)	/* receive descriptor underflow */
#define	BWI_I_RO		(1 << 14)	/* receive fifo overflow */
#define	BWI_I_XU		(1 << 15)	/* transmit fifo underflow */
#define	BWI_I_RI		(1 << 16)	/* receive interrupt */
#define	BWI_I_XI		(1 << 24)	/* transmit interrupt */

#define BWI_TXRX_INTR_ERROR		(BWI_I_XU | BWI_I_RO | BWI_I_DE | \
					 BWI_I_PD | BWI_I_PC)
#define BWI_TXRX_INTR_RX		BWI_I_RI
#define BWI_TXRX_TX_INTRS		BWI_TXRX_INTR_ERROR
#define BWI_TXRX_RX_INTRS		(BWI_TXRX_INTR_ERROR | BWI_TXRX_INTR_RX)
#define BWI_TXRX_IS_RX(i)		((i) % 3 == 0)

/* PHY */

#define BWI_PHYR_NRSSI_THR_11B		0x020
#define BWI_PHYR_BBP_ATTEN		0x060
#define BWI_PHYR_TBL_CTRL_11A		0x072
#define BWI_PHYR_TBL_DATA_LO_11A	0x073
#define BWI_PHYR_TBL_DATA_HI_11A	0x074
#define BWI_PHYR_TBL_CTRL_11G		0x472
#define BWI_PHYR_TBL_DATA_LO_11G	0x473
#define BWI_PHYR_TBL_DATA_HI_11G	0x474
#define BWI_PHYR_NRSSI_THR_11G		0x48a
#define BWI_PHYR_NRSSI_CTRL		0x803
#define BWI_PHYR_NRSSI_DATA		0x804
#define BWI_PHYR_RF_LO			0x810

/*
 * PHY Tables
 */
/*
 * http://bcm-specs.sipsolutions.net/APHYSetup/FineFrequency
 * G PHY
 */
#define BWI_PHY_FREQ_11G_REV1						\
	0x0089,	0x02e9,	0x0409,	0x04e9,	0x05a9,	0x0669,	0x0709,	0x0789,	\
	0x0829,	0x08a9,	0x0929,	0x0989,	0x0a09,	0x0a69,	0x0ac9,	0x0b29,	\
	0x0ba9,	0x0be9,	0x0c49,	0x0ca9,	0x0d09,	0x0d69,	0x0da9,	0x0e09,	\
	0x0e69,	0x0ea9,	0x0f09,	0x0f49,	0x0fa9,	0x0fe9,	0x1029,	0x1089,	\
	0x10c9,	0x1109,	0x1169,	0x11a9,	0x11e9,	0x1229,	0x1289,	0x12c9,	\
	0x1309,	0x1349,	0x1389,	0x13c9,	0x1409,	0x1449,	0x14a9,	0x14e9,	\
	0x1529,	0x1569,	0x15a9,	0x15e9,	0x1629,	0x1669,	0x16a9,	0x16e8,	\
	0x1728,	0x1768,	0x17a8,	0x17e8,	0x1828,	0x1868,	0x18a8,	0x18e8,	\
	0x1928,	0x1968,	0x19a8,	0x19e8,	0x1a28,	0x1a68,	0x1aa8,	0x1ae8,	\
	0x1b28,	0x1b68,	0x1ba8,	0x1be8,	0x1c28,	0x1c68,	0x1ca8,	0x1ce8,	\
	0x1d28,	0x1d68,	0x1dc8,	0x1e08,	0x1e48,	0x1e88,	0x1ec8,	0x1f08,	\
	0x1f48,	0x1f88,	0x1fe8,	0x2028,	0x2068,	0x20a8,	0x2108,	0x2148,	\
	0x2188,	0x21c8,	0x2228,	0x2268,	0x22c8,	0x2308,	0x2348,	0x23a8,	\
	0x23e8,	0x2448,	0x24a8,	0x24e8,	0x2548,	0x25a8,	0x2608,	0x2668,	\
	0x26c8,	0x2728,	0x2787,	0x27e7,	0x2847,	0x28c7,	0x2947,	0x29a7,	\
	0x2a27,	0x2ac7,	0x2b47,	0x2be7,	0x2ca7,	0x2d67,	0x2e47,	0x2f67,	\
	0x3247,	0x3526,	0x3646,	0x3726,	0x3806,	0x38a6,	0x3946,	0x39e6,	\
	0x3a66,	0x3ae6,	0x3b66,	0x3bc6,	0x3c45,	0x3ca5,	0x3d05,	0x3d85,	\
	0x3de5,	0x3e45,	0x3ea5,	0x3ee5,	0x3f45,	0x3fa5,	0x4005,	0x4045,	\
	0x40a5,	0x40e5,	0x4145,	0x4185,	0x41e5,	0x4225,	0x4265,	0x42c5,	\
	0x4305,	0x4345,	0x43a5,	0x43e5,	0x4424,	0x4464,	0x44c4,	0x4504,	\
	0x4544,	0x4584,	0x45c4,	0x4604,	0x4644,	0x46a4,	0x46e4,	0x4724,	\
	0x4764,	0x47a4,	0x47e4,	0x4824,	0x4864,	0x48a4,	0x48e4,	0x4924,	\
	0x4964,	0x49a4,	0x49e4,	0x4a24,	0x4a64,	0x4aa4,	0x4ae4,	0x4b23,	\
	0x4b63,	0x4ba3,	0x4be3,	0x4c23,	0x4c63,	0x4ca3,	0x4ce3,	0x4d23,	\
	0x4d63,	0x4da3,	0x4de3,	0x4e23,	0x4e63,	0x4ea3,	0x4ee3,	0x4f23,	\
	0x4f63,	0x4fc3,	0x5003,	0x5043,	0x5083,	0x50c3,	0x5103,	0x5143,	\
	0x5183,	0x51e2,	0x5222,	0x5262,	0x52a2,	0x52e2,	0x5342,	0x5382,	\
	0x53c2,	0x5402,	0x5462,	0x54a2,	0x5502,	0x5542,	0x55a2,	0x55e2,	\
	0x5642,	0x5682,	0x56e2,	0x5722,	0x5782,	0x57e1,	0x5841,	0x58a1,	\
	0x5901,	0x5961,	0x59c1,	0x5a21,	0x5aa1,	0x5b01,	0x5b81,	0x5be1,	\
	0x5c61,	0x5d01,	0x5d80,	0x5e20,	0x5ee0,	0x5fa0,	0x6080,	0x61c0

/*
 * http://bcm-specs.sipsolutions.net/APHYSetup/noise_table
 */
/* G PHY Revision 1 */
#define BWI_PHY_NOISE_11G_REV1 \
	0x013c,	0x01f5,	0x031a,	0x0631,	0x0001,	0x0001,	0x0001,	0x0001
/* G PHY generic */
#define BWI_PHY_NOISE_11G \
	0x5484, 0x3c40, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000

/*
 * http://bcm-specs.sipsolutions.net/APHYSetup/rotor_table
 * G PHY Revision 1
 */
#define BWI_PHY_ROTOR_11G_REV1				\
	0xfeb93ffd, 0xfec63ffd, 0xfed23ffd, 0xfedf3ffd,	\
	0xfeec3ffe, 0xfef83ffe, 0xff053ffe, 0xff113ffe,	\
	0xff1e3ffe, 0xff2a3fff, 0xff373fff, 0xff443fff,	\
	0xff503fff, 0xff5d3fff, 0xff693fff, 0xff763fff,	\
	0xff824000, 0xff8f4000, 0xff9b4000, 0xffa84000,	\
	0xffb54000, 0xffc14000, 0xffce4000, 0xffda4000,	\
	0xffe74000, 0xfff34000, 0x00004000, 0x000d4000,	\
	0x00194000, 0x00264000, 0x00324000, 0x003f4000,	\
	0x004b4000, 0x00584000, 0x00654000, 0x00714000,	\
	0x007e4000, 0x008a3fff, 0x00973fff, 0x00a33fff,	\
	0x00b03fff, 0x00bc3fff, 0x00c93fff, 0x00d63fff,	\
	0x00e23ffe, 0x00ef3ffe, 0x00fb3ffe, 0x01083ffe,	\
	0x01143ffe, 0x01213ffd, 0x012e3ffd, 0x013a3ffd,	\
	0x01473ffd

/*
 * http://bcm-specs.sipsolutions.net/APHYSetup/noise_scale_table
 */
/* G PHY Revision [0,2] */
#define BWI_PHY_NOISE_SCALE_11G_REV2					\
	0x6c77,	0x5162,	0x3b40,	0x3335,	0x2f2d,	0x2a2a,	0x2527,	0x1f21,	\
	0x1a1d,	0x1719,	0x1616,	0x1414,	0x1414,	0x1400,	0x1414,	0x1614,	\
	0x1716,	0x1a19,	0x1f1d,	0x2521,	0x2a27,	0x2f2a,	0x332d,	0x3b35,	\
	0x5140,	0x6c62,	0x0077
/* G PHY Revsion 7 */
#define BWI_PHY_NOISE_SCALE_11G_REV7					\
	0xa4a4,	0xa4a4,	0xa4a4,	0xa4a4,	0xa4a4,	0xa4a4,	0xa4a4,	0xa4a4,	\
	0xa4a4,	0xa4a4,	0xa4a4,	0xa4a4,	0xa4a4,	0xa400,	0xa4a4,	0xa4a4,	\
	0xa4a4,	0xa4a4,	0xa4a4,	0xa4a4,	0xa4a4,	0xa4a4,	0xa4a4,	0xa4a4,	\
	0xa4a4,	0xa4a4,	0x00a4
/* G PHY generic */
#define BWI_PHY_NOISE_SCALE_11G						\
	0xd8dd,	0xcbd4,	0xbcc0,	0xb6b7,	0xb2b0,	0xadad,	0xa7a9,	0x9fa1,	\
	0x969b,	0x9195,	0x8f8f,	0x8a8a,	0x8a8a,	0x8a00,	0x8a8a,	0x8f8a,	\
	0x918f,	0x9695,	0x9f9b,	0xa7a1,	0xada9,	0xb2ad,	0xb6b0,	0xbcb7,	\
	0xcbc0,	0xd8d4,	0x00dd

/*
 * http://bcm-specs.sipsolutions.net/APHYSetup/sigma_square_table
 */
/* G PHY Revision 2 */
#define BWI_PHY_SIGMA_SQ_11G_REV2					\
	0x007a,	0x0075,	0x0071,	0x006c,	0x0067,	0x0063,	0x005e,	0x0059,	\
	0x0054,	0x0050,	0x004b,	0x0046,	0x0042,	0x003d,	0x003d,	0x003d,	\
	0x003d,	0x003d,	0x003d,	0x003d,	0x003d,	0x003d,	0x003d,	0x003d,	\
	0x003d,	0x003d,	0x0000,	0x003d,	0x003d,	0x003d,	0x003d,	0x003d,	\
	0x003d,	0x003d,	0x003d,	0x003d,	0x003d,	0x003d,	0x003d,	0x003d,	\
	0x0042,	0x0046,	0x004b,	0x0050,	0x0054,	0x0059,	0x005e,	0x0063,	\
	0x0067,	0x006c,	0x0071,	0x0075,	0x007a
/* G PHY Revision (2,7] */
#define BWI_PHY_SIGMA_SQ_11G_REV7					\
	0x00de,	0x00dc,	0x00da,	0x00d8,	0x00d6,	0x00d4,	0x00d2,	0x00cf,	\
	0x00cd,	0x00ca,	0x00c7,	0x00c4,	0x00c1,	0x00be,	0x00be,	0x00be,	\
	0x00be,	0x00be,	0x00be,	0x00be,	0x00be,	0x00be,	0x00be,	0x00be,	\
	0x00be,	0x00be,	0x0000,	0x00be,	0x00be,	0x00be,	0x00be,	0x00be,	\
	0x00be,	0x00be,	0x00be,	0x00be,	0x00be,	0x00be,	0x00be,	0x00be,	\
	0x00c1,	0x00c4,	0x00c7,	0x00ca,	0x00cd,	0x00cf,	0x00d2,	0x00d4,	\
	0x00d6,	0x00d8,	0x00da,	0x00dc,	0x00de

/*
 * http://bcm-specs.sipsolutions.net/APHYSetup/retard_table
 * G PHY
 */
#define BWI_PHY_DELAY_11G_REV1				\
	0xdb93cb87, 0xd666cf64, 0xd1fdd358, 0xcda6d826,	\
	0xca38dd9f, 0xc729e2b4, 0xc469e88e, 0xc26aee2b,	\
	0xc0def46c, 0xc073fa62, 0xc01d00d5, 0xc0760743,	\
	0xc1560d1e, 0xc2e51369, 0xc4ed18ff, 0xc7ac1ed7,	\
	0xcb2823b2, 0xcefa28d9, 0xd2f62d3f, 0xd7bb3197,	\
	0xdce53568, 0xe1fe3875, 0xe7d13b35, 0xed663d35,	\
	0xf39b3ec4, 0xf98e3fa7, 0x00004000, 0x06723fa7,	\
	0x0c653ec4, 0x129a3d35, 0x182f3b35, 0x1e023875,	\
	0x231b3568, 0x28453197, 0x2d0a2d3f, 0x310628d9,	\
	0x34d823b2, 0x38541ed7, 0x3b1318ff, 0x3d1b1369,	\
	0x3eaa0d1e, 0x3f8a0743, 0x3fe300d5, 0x3f8dfa62,	\
	0x3f22f46c, 0x3d96ee2b, 0x3b97e88e, 0x38d7e2b4,	\
	0x35c8dd9f, 0x325ad826, 0x2e03d358, 0x299acf64,	\
	0x246dcb87

/* RF */

#define BWI_RFR_ATTEN			0x43

#define BWI_RFR_TXPWR			0x52
#define BWI_RFR_TXPWR1_MASK		0x0070

#define BWI_RFR_BBP_ATTEN		0x60
#define BWI_RFR_BBP_ATTEN_CALIB_BIT	(1 << 0)
#define BWI_RFR_BBP_ATTEN_CALIB_IDX	(0x0f << 1)

/*
 * TSSI -- TX power maps
 */
/*
 * http://bcm-specs.sipsolutions.net/TSSI_to_DBM_Table
 * B PHY
 */
#define BWI_TXPOWER_MAP_11B						\
	0x4d,	0x4c,	0x4b,	0x4a,	0x4a,	0x49,	0x48,	0x47,	\
	0x47,	0x46,	0x45,	0x45,	0x44,	0x43,	0x42,	0x42,	\
	0x41,	0x40,	0x3f,	0x3e,	0x3d,	0x3c,	0x3b,	0x3a,	\
	0x39,	0x38,	0x37,	0x36,	0x35,	0x34,	0x32,	0x31,	\
	0x30,	0x2f,	0x2d,	0x2c,	0x2b,	0x29,	0x28,	0x26,	\
	0x25,	0x23,	0x21,	0x1f,	0x1d,	0x1a,	0x17,	0x14,	\
	0x10,	0x0c,	0x06,	0x00,	-7,	-7,	-7,	-7, 	\
	-7,	-7,	-7,	-7,	-7,	-7,	-7,	-7
/*
 * http://bcm-specs.sipsolutions.net/TSSI_to_DBM_Table
 * G PHY
 */
#define BWI_TXPOWER_MAP_11G						\
	77,	77,	77,	76,	76,	76,	75,	75,	\
	74,	74,	73,	73,	73,	72,	72,	71,	\
	71,	70,	70,	69,	68,	68,	67,	67,	\
	66,	65,	65,	64,	63,	63,	62,	61,	\
	60,	59,	58,	57,	56,	55,	54,	53,	\
	52,	50,	49,	47,	45,	43,	40,	37,	\
	33,	28,	22,	14,	5,	-7,	-20,	-20,	\
	-20,	-20,	-20,	-20,	-20,	-20,	-20,	-20

/* Find least significant bit that is set */
#define	__LOWEST_SET_BIT(__mask) ((((__mask) - 1) & (__mask)) ^ (__mask))

#define	__SHIFTOUT(__x, __mask) (((__x) & (__mask)) / __LOWEST_SET_BIT(__mask))
#define	__SHIFTIN(__x, __mask) ((__x) * __LOWEST_SET_BIT(__mask))
#define	__SHIFTOUT_MASK(__mask) __SHIFTOUT((__mask), (__mask))

#endif	/* !_IF_BWIREG_H */

license: unknown


code:
/*	$OpenBSD: bwivar.h,v 1.31 2014/11/05 01:02:10 daniel Exp $	*/

/*
 * Copyright (c) 2007 The DragonFly Project.  All rights reserved.
 *
 * This code is derived from software contributed to The DragonFly Project
 * by Sepherosa Ziehau <sepherosa@gmail.com>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 * 3. Neither the name of The DragonFly Project nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific, prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 * $DragonFly: src/sys/dev/netif/bwi/if_bwivar.h,v 1.1 2007/09/08 06:15:54 sephe Exp $
 */

#ifndef _IF_BWIVAR_H
#define _IF_BWIVAR_H

#define BWI_ALIGN		0x1000
#define BWI_RING_ALIGN		BWI_ALIGN
#define BWI_BUS_SPACE_MAXADDR	0x3fffffff

#define BWI_TX_NRING		6
#define BWI_TXRX_NRING		6
#define BWI_TX_NDESC		128
#define BWI_RX_NDESC		64
#define BWI_TXSTATS_NDESC	64
#define BWI_TX_NSPRDESC		2
#define BWI_TX_DATA_RING	1

/* XXX Onoe/Sample/AMRR probably need different configuration */
#define BWI_SHRETRY		7
#define BWI_LGRETRY		4
#define BWI_SHRETRY_FB		3
#define BWI_LGRETRY_FB		2

#define BWI_LED_EVENT_NONE	-1
#define BWI_LED_EVENT_POLL	0
#define BWI_LED_EVENT_TX	1
#define BWI_LED_EVENT_RX	2
#define BWI_LED_SLOWDOWN(dur)	(dur) = (((dur) * 3) / 2)

enum bwi_txpwrcb_type {
	BWI_TXPWR_INIT = 0,
	BWI_TXPWR_FORCE = 1,
	BWI_TXPWR_CALIB = 2
};

#define BWI_NOISE_FLOOR		-95	/* TODO: noise floor calc */

#define CSR_READ_4(sc, reg)			\
	bus_space_read_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg))
#define CSR_READ_2(sc, reg)			\
	bus_space_read_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg))

#define CSR_WRITE_4(sc, reg, val)		\
	bus_space_write_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))
#define CSR_WRITE_2(sc, reg, val)		\
	bus_space_write_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))

#define CSR_SETBITS_4(sc, reg, bits)		\
	CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) | (bits))
#define CSR_SETBITS_2(sc, reg, bits)		\
	CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (bits))

#define CSR_FILT_SETBITS_4(sc, reg, filt, bits) \
	CSR_WRITE_4((sc), (reg), (CSR_READ_4((sc), (reg)) & (filt)) | (bits))
#define CSR_FILT_SETBITS_2(sc, reg, filt, bits)	\
	CSR_WRITE_2((sc), (reg), (CSR_READ_2((sc), (reg)) & (filt)) | (bits))

#define CSR_CLRBITS_4(sc, reg, bits)		\
	CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) & ~(bits))
#define CSR_CLRBITS_2(sc, reg, bits)		\
	CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(bits))

struct bwi_desc32 {
	/* Little endian */
	uint32_t	ctrl;
	uint32_t	addr;	/* BWI_DESC32_A_ */
} __packed;

#define BWI_DESC32_A_FUNC_TXRX		0x1
#define BWI_DESC32_A_FUNC_MASK		0xc0000000
#define BWI_DESC32_A_ADDR_MASK		0x3fffffff

#define BWI_DESC32_C_BUFLEN_MASK	0x00001fff
#define BWI_DESC32_C_ADDRHI_MASK	0x00030000
#define BWI_DESC32_C_EOR		(1 << 28)
#define BWI_DESC32_C_INTR		(1 << 29)
#define BWI_DESC32_C_FRAME_END		(1 << 30)
#define BWI_DESC32_C_FRAME_START	(1U << 31)

struct bwi_desc64 {
	/* Little endian */
	uint32_t	ctrl0;
	uint32_t	ctrl1;
	uint32_t	addr_lo;
	uint32_t	addr_hi;
} __packed;

struct bwi_rxbuf_hdr {
	/* Little endian */
	uint16_t	rxh_buflen;	/* exclude bwi_rxbuf_hdr */
	uint8_t		rxh_pad1[2];
	uint16_t	rxh_flags1;
	uint8_t		rxh_rssi;
	uint8_t		rxh_sq;
	uint16_t	rxh_phyinfo;	/* BWI_RXH_PHYINFO_ */
	uint16_t	rxh_flags3;
	uint16_t	rxh_flags2;	/* BWI_RXH_F2_ */
	uint16_t	rxh_tsf;
	uint8_t		rxh_pad3[14];	/* Padded to 30bytes */
} __packed;

#define BWI_RXH_F1_BCM2053_RSSI (1 << 14)
#define BWI_RXH_F1_OFDM		(1 << 0)

#define BWI_RXH_F2_TYPE2FRAME	(1 << 2)

#define BWI_RXH_F3_BCM2050_RSSI	(1 << 10)

#define BWI_RXH_PHYINFO_LNAGAIN	(3 << 14)

struct bwi_txbuf_hdr {
	/* Little endian */
	uint32_t	txh_mac_ctrl;	/* BWI_TXH_MAC_C_ */
	uint8_t		txh_fc[2];
	uint16_t	txh_unknown1;
	uint16_t	txh_phy_ctrl;	/* BWI_TXH_PHY_C_ */
	uint8_t		txh_ivs[16];
	uint8_t		txh_addr1[IEEE80211_ADDR_LEN];
	uint16_t	txh_unknown2;
	uint8_t		txh_rts_fb_plcp[4];
	uint16_t	txh_rts_fb_duration;
	uint8_t		txh_fb_plcp[4];
	uint16_t	txh_fb_duration;
	uint8_t		txh_pad2[2];
	uint16_t	txh_id;		/* BWI_TXH_ID_ */
	uint16_t	txh_unknown3;
	uint8_t		txh_rts_plcp[6];
	uint8_t		txh_rts_fc[2];
	uint16_t	txh_rts_duration;
	uint8_t		txh_rts_ra[IEEE80211_ADDR_LEN];
	uint8_t		txh_rts_ta[IEEE80211_ADDR_LEN];
	uint8_t		txh_pad3[2];
	uint8_t		txh_plcp[6];
} __packed;

#define BWI_TXH_ID_RING_MASK		0xe000
#define BWI_TXH_ID_IDX_MASK		0x1fff

#define BWI_TXH_PHY_C_OFDM		(1 << 0)
#define BWI_TXH_PHY_C_SHPREAMBLE	(1 << 4)
#define BWI_TXH_PHY_C_ANTMODE_MASK	0x0300

#define BWI_TXH_MAC_C_ACK		(1 << 0)
#define BWI_TXH_MAC_C_FIRST_FRAG	(1 << 3)
#define BWI_TXH_MAC_C_HWSEQ		(1 << 4)
#define BWI_TXH_MAC_C_FB_OFDM		(1 << 8)

struct bwi_txstats {
	/* Little endian */
	uint8_t		txs_pad1[4];
	uint16_t	txs_id;
	uint8_t		txs_flags;
	uint8_t		txs_retry_cnt;
	uint8_t		txs_pad2[2];
	uint16_t	txs_seq;
	uint16_t	txs_unknown;
	uint8_t		txs_pad3[2];	/* Padded to 16bytes */
} __packed;

struct bwi_ring_data {
	uint32_t		 rdata_txrx_ctrl;
	bus_size_t		 rdata_ring_sz;
	bus_dmamap_t		 rdata_dmap;
	bus_addr_t		 rdata_paddr;
	void			*rdata_desc;
};

struct bwi_txbuf {
	struct mbuf		*tb_mbuf;
	bus_dmamap_t		 tb_dmap;

	struct ieee80211_node	*tb_ni;
	int			 tb_rate_idx[2];
};

struct bwi_txbuf_data {
	struct bwi_txbuf	tbd_buf[BWI_TX_NDESC];
	int			tbd_used;
	int			tbd_idx;
};

struct bwi_rxbuf {
	struct mbuf		*rb_mbuf;
	bus_addr_t		 rb_paddr;
	bus_dmamap_t		 rb_dmap;
};

struct bwi_rxbuf_data {
	struct bwi_rxbuf	rbd_buf[BWI_RX_NDESC];
	bus_dmamap_t		rbd_tmp_dmap;
	int			rbd_idx;
};

struct bwi_txstats_data {
	bus_dma_segment_t	 stats_ring_seg;
	bus_dmamap_t		 stats_ring_dmap;
	bus_addr_t		 stats_ring_paddr;
	void			*stats_ring;

	bus_dma_segment_t	 stats_seg;
	bus_dmamap_t		 stats_dmap;
	bus_addr_t		 stats_paddr;
	struct bwi_txstats	*stats;

	uint32_t		 stats_ctrl_base;
	int			 stats_idx;
};

struct bwi_fwhdr {
	/* Big endian */
	uint8_t		fw_type;	/* BWI_FW_T_ */
	uint8_t		fw_gen;		/* BWI_FW_GEN */
	uint8_t		fw_pad[2];
	uint32_t	fw_size;
#define fw_iv_cnt	fw_size
} __packed;

#define BWI_FWHDR_SZ		sizeof(struct bwi_fwhdr)
#define BWI_FW_VERSION3		3
#define BWI_FW_VERSION4		4
#define BWI_FW_VERSION3_REVMAX	0x128
#define BWI_FW_T_UCODE          'u'
#define BWI_FW_T_PCM            'p'
#define BWI_FW_T_IV             'i'
#define BWI_FW_GEN_1            1
#define BWI_FW_IV_OFS_MASK	0x7fff
#define BWI_FW_IV_IS_32BIT	(1 << 15)

struct fwheader {
	char	filename[64];
	int	filesize;
	int	fileoffset;
};

struct bwi_fw_iv {
	/* Big endian */
	uint16_t		iv_ofs;
	union {
		uint32_t	val32;
		uint16_t	val16;
	}			iv_val;
} __packed;

struct bwi_led {
	uint8_t			l_flags;	/* BWI_LED_F_ */
	uint8_t			l_act;		/* BWI_LED_ACT_ */
	uint8_t			l_mask;
};

#define BWI_LED_F_ACTLOW	0x1
#define BWI_LED_F_BLINK		0x2
#define BWI_LED_F_POLLABLE	0x4
#define BWI_LED_F_SLOW		0x8

enum bwi_clock_mode {
	BWI_CLOCK_MODE_SLOW,
	BWI_CLOCK_MODE_FAST,
	BWI_CLOCK_MODE_DYN
};

struct bwi_regwin {
	uint32_t		rw_flags;	/* BWI_REGWIN_F_ */
	uint16_t		rw_type;	/* BWI_REGWIN_T_ */
	uint8_t			rw_id;
	uint8_t			rw_rev;
};

#define BWI_REGWIN_F_EXIST	0x1

#define BWI_CREATE_REGWIN(rw, id, type, rev)	\
do {						\
	(rw)->rw_flags = BWI_REGWIN_F_EXIST;	\
	(rw)->rw_type = (type);			\
	(rw)->rw_id = (id);			\
	(rw)->rw_rev = (rev);			\
} while (0)

#define BWI_REGWIN_EXIST(rw)	((rw)->rw_flags & BWI_REGWIN_F_EXIST)
#define BWI_GPIO_REGWIN(sc)				\
	(BWI_REGWIN_EXIST(&(sc)->sc_com_regwin) ?	\
	&(sc)->sc_com_regwin : &(sc)->sc_bus_regwin)

struct bwi_mac;

struct bwi_phy {
	enum ieee80211_phymode	phy_mode;
	int			phy_rev;
	int			phy_version;

	uint32_t		phy_flags;		/* BWI_PHY_F_ */
	uint16_t		phy_tbl_ctrl;
	uint16_t		phy_tbl_data_lo;
	uint16_t		phy_tbl_data_hi;

	void			(*phy_init)(struct bwi_mac *);
};

#define BWI_PHY_F_CALIBRATED	0x1
#define BWI_PHY_F_LINKED	0x2
#define BWI_CLEAR_PHY_FLAGS	(BWI_PHY_F_CALIBRATED)

/* TX power control */
struct bwi_tpctl {
	uint16_t		bbp_atten;	/* BBP attenuation: 4bits */
	uint16_t		rf_atten;	/* RF attenuation */
	uint16_t		tp_ctrl1;	/* ??: 3bits */
	uint16_t		tp_ctrl2;	/* ??: 4bits */
};

#define BWI_RF_ATTEN_FACTOR	4
#define BWI_RF_ATTEN_MAX0	9
#define BWI_RF_ATTEN_MAX1	31
#define BWI_BBP_ATTEN_MAX	11
#define BWI_TPCTL1_MAX		7

struct bwi_rf_lo {
	int8_t			ctrl_lo;
	int8_t			ctrl_hi;
};

struct bwi_rf {
	uint16_t		rf_type;	/* BWI_RF_T_ */
	uint16_t		rf_manu;
	int			rf_rev;

	uint32_t		rf_flags;	/* BWI_RF_F_ */

#define BWI_RFLO_MAX		56
	struct bwi_rf_lo	rf_lo[BWI_RFLO_MAX];
	uint8_t			rf_lo_used[8];

#define BWI_INVALID_NRSSI	-1000
	int16_t			rf_nrssi[2];	/* Narrow RSSI */
	int32_t			rf_nrssi_slope;

#define BWI_NRSSI_TBLSZ		64
	int8_t			rf_nrssi_table[BWI_NRSSI_TBLSZ];

	uint16_t		rf_lo_gain;	/* loopback gain */
	uint16_t		rf_rx_gain;	/* TRSW RX gain */

	uint16_t		rf_calib;	/* RF calibration value */
	uint			rf_curchan;	/* current channel */

	uint16_t		rf_ctrl_rd;
	int			rf_ctrl_adj;
	void			(*rf_off)(struct bwi_mac *);
	void			(*rf_on)(struct bwi_mac *);

	void			(*rf_set_nrssi_thr)(struct bwi_mac *);
	void			(*rf_calc_nrssi_slope)(struct bwi_mac *);
	int			(*rf_calc_rssi)
				(struct bwi_mac *,
				 const struct bwi_rxbuf_hdr *);

	void			(*rf_lo_update)(struct bwi_mac *);

#define BWI_TSSI_MAX		64
	int8_t			rf_txpower_map0[BWI_TSSI_MAX];
						/* Indexed by TSSI */
	int			rf_idle_tssi0;

	int8_t			rf_txpower_map[BWI_TSSI_MAX];
	int			rf_idle_tssi;

	int			rf_base_tssi;

	int			rf_txpower_max;	/* dBm */

	int			rf_ant_mode;	/* BWI_ANT_MODE_ */
};

#define BWI_RF_F_INITED		0x1
#define BWI_RF_F_ON		0x2
#define BWI_RF_CLEAR_FLAGS	(BWI_RF_F_INITED)

#define BWI_ANT_MODE_0		0
#define BWI_ANT_MODE_1		1
#define BWI_ANT_MODE_UNKN	2
#define BWI_ANT_MODE_AUTO	3

struct fw_image;

struct bwi_mac {
	struct bwi_regwin	 mac_regwin;	/* MUST be first field */
#define mac_rw_flags		 mac_regwin.rw_flags
#define mac_type		 mac_regwin.rw_type
#define mac_id			 mac_regwin.rw_id
#define mac_rev			 mac_regwin.rw_rev
	struct bwi_softc	*mac_sc;

	struct bwi_phy		 mac_phy;	/* PHY I/F */
	struct bwi_rf		 mac_rf;	/* RF I/F */

	struct bwi_tpctl	 mac_tpctl;	/* TX power control */
	uint32_t		 mac_flags;	/* BWI_MAC_F_ */

	uint8_t			*mac_fw;
	size_t			 mac_fw_size;
	uint8_t			*mac_ucode;
	size_t			 mac_ucode_size;
	uint8_t			*mac_pcm;
	size_t			 mac_pcm_size;
	uint8_t			*mac_iv;
	size_t			 mac_iv_size;
	uint8_t			*mac_iv_ext;
	size_t			 mac_iv_ext_size;
};

#define BWI_MAC_F_BSWAP		0x1
#define BWI_MAC_F_TPCTL_INITED	0x2
#define BWI_MAC_F_HAS_TXSTATS	0x4
#define BWI_MAC_F_INITED	0x8
#define BWI_MAC_F_ENABLED	0x10
#define BWI_MAC_F_LOCKED	0x20	/* for debug */
#define BWI_MAC_F_TPCTL_ERROR	0x40
#define BWI_MAC_F_PHYE_RESET	0x80

#define BWI_CREATE_MAC(mac, sc, id, rev)	\
do {						\
	BWI_CREATE_REGWIN(&(mac)->mac_regwin,	\
	    (id), BWI_REGWIN_T_MAC, (rev));	\
	(mac)->mac_sc = (sc);			\
} while (0)

#define BWI_MAC_MAX		2
#define BWI_LED_MAX		4

enum bwi_bus_space {
	BWI_BUS_SPACE_30BIT = 1,
	BWI_BUS_SPACE_32BIT,
	BWI_BUS_SPACE_64BIT
};

#define BWI_TX_RADIOTAP_PRESENT 		\
	((1 << IEEE80211_RADIOTAP_FLAGS) |	\
	 (1 << IEEE80211_RADIOTAP_RATE) |	\
	 (1 << IEEE80211_RADIOTAP_CHANNEL))

struct bwi_tx_radiotap_hdr {
	struct ieee80211_radiotap_header wt_ihdr;
	uint8_t		wt_flags;
	uint8_t		wt_rate;
	uint16_t	wt_chan_freq;
	uint16_t	wt_chan_flags;
};

#define BWI_RX_RADIOTAP_PRESENT				\
	((1 << IEEE80211_RADIOTAP_TSFT) |		\
	 (1 << IEEE80211_RADIOTAP_FLAGS) |		\
	 (1 << IEEE80211_RADIOTAP_RATE) |		\
	 (1 << IEEE80211_RADIOTAP_CHANNEL) |		\
	 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |	\
	 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE))

struct bwi_rx_radiotap_hdr {
	struct ieee80211_radiotap_header wr_ihdr;
	uint64_t	wr_tsf;
	uint8_t		wr_flags;
	uint8_t		wr_rate;
	uint16_t	wr_chan_freq;
	uint16_t	wr_chan_flags;
	int8_t		wr_antsignal;
	int8_t		wr_antnoise;
	/* TODO: sq */
};

struct bwi_node {
	struct ieee80211_node		ni;
	struct ieee80211_amrr_node	amn;
};

struct bwi_softc {
	struct device		 sc_dev;
	struct ieee80211com	 sc_ic;
	uint32_t		 sc_flags;	/* BWI_F_ */

	uint32_t		 sc_cap;	/* BWI_CAP_ */
	uint16_t		 sc_bbp_id;	/* BWI_BBPID_ */
	uint8_t			 sc_bbp_rev;
	uint8_t			 sc_bbp_pkg;

	uint8_t			 sc_pci_revid;
	uint16_t		 sc_pci_did;
	uint16_t		 sc_pci_subvid;
	uint16_t		 sc_pci_subdid;

	uint16_t		 sc_card_flags;	/* BWI_CARD_F_ */
	uint16_t		 sc_pwron_delay;
	int			 sc_locale;

	bus_dma_tag_t		 sc_dmat;
	bus_space_tag_t		 sc_mem_bt;
	bus_space_handle_t	 sc_mem_bh;

	struct timeout		 sc_scan_ch;
	struct timeout		 sc_calib_ch;
	struct timeout		 sc_amrr_ch;

	struct ieee80211_amrr	 sc_amrr;

	struct bwi_regwin	*sc_cur_regwin;
	struct bwi_regwin	 sc_com_regwin;
	struct bwi_regwin	 sc_bus_regwin;

	int			 sc_nmac;
	struct bwi_mac		 sc_mac[BWI_MAC_MAX];

	int			 sc_rx_rate;
	int			 sc_tx_rate;
	enum bwi_txpwrcb_type	 sc_txpwrcb_type;

	int			 sc_led_blinking;
	int			 sc_led_ticks;
	struct bwi_led		*sc_blink_led;
	struct timeout		 sc_led_blink_next_ch;
	struct timeout		 sc_led_blink_end_ch;
	int			 sc_led_blink_offdur;
	struct bwi_led		 sc_leds[BWI_LED_MAX];

	enum bwi_bus_space	 sc_bus_space;

	/* bounce buffers for 30 bit bus space devices */
	caddr_t			 sc_bounce_tx_data[BWI_TX_NRING];
	caddr_t			 sc_bounce_rx_data;

	struct bwi_txbuf_data	 sc_tx_bdata[BWI_TX_NRING];
	struct bwi_rxbuf_data	 sc_rx_bdata;

	struct bwi_ring_data	 sc_tx_rdata[BWI_TX_NRING];
	struct bwi_ring_data	 sc_rx_rdata;

	struct bwi_txstats_data	*sc_txstats;

	int			 sc_tx_timer;

	int			 (*sc_newstate)
				 (struct ieee80211com *,
				     enum ieee80211_state, int);

	int			 (*sc_init_tx_ring)(struct bwi_softc *, int);
	void			 (*sc_free_tx_ring)(struct bwi_softc *, int);

	int			 (*sc_init_rx_ring)(struct bwi_softc *);
	void			 (*sc_free_rx_ring)(struct bwi_softc *);
	int			 (*sc_newbuf)(struct bwi_softc *, int, int);

	int			 (*sc_init_txstats)(struct bwi_softc *);
	void			 (*sc_free_txstats)(struct bwi_softc *);

	void			 (*sc_setup_rxdesc)
				 (struct bwi_softc *, int, bus_addr_t, int);
	int			 (*sc_rxeof)(struct bwi_softc *);

	void			 (*sc_setup_txdesc)
				 (struct bwi_softc *, struct bwi_ring_data *,
				     int, bus_addr_t, int);
	void			 (*sc_start_tx)
				 (struct bwi_softc *, uint32_t, int);

	void			 (*sc_txeof_status)(struct bwi_softc *);

	int			 (*sc_enable)(struct bwi_softc *);
	void			 (*sc_disable)(struct bwi_softc *);

	void			 (*sc_conf_write)(void *, uint32_t, uint32_t);
	uint32_t		 (*sc_conf_read)(void *, uint32_t);

	/* Sysctl variables */
	int			 sc_fw_version;	/* BWI_FW_VERSION[34] */
	int			 sc_dwell_time;	/* milliseconds */
	int			 sc_led_idle;
	int			 sc_led_blink;

#if NBPFILTER > 0
        caddr_t                  sc_drvbpf;

        union {
                struct bwi_rx_radiotap_hdr th;
                uint8_t pad[64];
        }                        sc_rxtapu;
#define sc_rxtap                 sc_rxtapu.th
        int                      sc_rxtap_len;

        union {
                struct bwi_tx_radiotap_hdr th;
                uint8_t pad[64];
        }                        sc_txtapu;
#define sc_txtap                 sc_txtapu.th
        int                      sc_txtap_len;
#endif
};

#define BWI_F_BUS_INITED	0x1
#define BWI_F_PROMISC		0x2

#define MOBJ_WRITE_2(mac, objid, ofs, val)			\
	bwi_memobj_write_2((mac), (objid), (ofs), (val))
#define MOBJ_WRITE_4(mac, objid, ofs, val)			\
	bwi_memobj_write_4((mac), (objid), (ofs), (val))
#define MOBJ_READ_2(mac, objid, ofs)				\
	bwi_memobj_read_2((mac), (objid), (ofs))
#define MOBJ_READ_4(mac, objid, ofs)				\
	bwi_memobj_read_4((mac), (objid), (ofs))

#define MOBJ_SETBITS_4(mac, objid, ofs, bits)			\
	MOBJ_WRITE_4((mac), (objid), (ofs),			\
	MOBJ_READ_4((mac), (objid), (ofs)) | (bits))
#define MOBJ_CLRBITS_4(mac, objid, ofs, bits)			\
	MOBJ_WRITE_4((mac), (objid), (ofs),			\
	MOBJ_READ_4((mac), (objid), (ofs)) & ~(bits))

#define MOBJ_FILT_SETBITS_2(mac, objid, ofs, filt, bits)	\
	MOBJ_WRITE_2((mac), (objid), (ofs),			\
	(MOBJ_READ_2((mac), (objid), (ofs)) & (filt)) | (bits))

#define TMPLT_WRITE_4(mac, ofs, val)	bwi_tmplt_write_4((mac), (ofs), (val))

#define HFLAGS_WRITE(mac, flags)	bwi_hostflags_write((mac), (flags))
#define HFLAGS_READ(mac)		bwi_hostflags_read((mac))
#define HFLAGS_CLRBITS(mac, bits)				\
	HFLAGS_WRITE((mac), HFLAGS_READ((mac)) | (bits))
#define HFLAGS_SETBITS(mac, bits)				\
	HFLAGS_WRITE((mac), HFLAGS_READ((mac)) & ~(bits))

/* PHY */

struct bwi_gains {
	int16_t	tbl_gain1;
	int16_t	tbl_gain2;
	int16_t	phy_gain;
};

static __inline void
bwi_phy_init(struct bwi_mac *_mac)
{
	_mac->mac_phy.phy_init(_mac);
}

#define PHY_WRITE(mac, ctrl, val)	bwi_phy_write((mac), (ctrl), (val))
#define PHY_READ(mac, ctrl)		bwi_phy_read((mac), (ctrl))

#define PHY_SETBITS(mac, ctrl, bits)		\
	PHY_WRITE((mac), (ctrl), PHY_READ((mac), (ctrl)) | (bits))
#define PHY_CLRBITS(mac, ctrl, bits)		\
	PHY_WRITE((mac), (ctrl), PHY_READ((mac), (ctrl)) & ~(bits))
#define PHY_FILT_SETBITS(mac, ctrl, filt, bits)	\
	PHY_WRITE((mac), (ctrl), (PHY_READ((mac), (ctrl)) & (filt)) | (bits))

static __inline void
bwi_rf_off(struct bwi_mac *_mac)
{
	_mac->mac_rf.rf_off(_mac);
	/* TODO: LED */

	_mac->mac_rf.rf_flags &= ~BWI_RF_F_ON;
}

static __inline void
bwi_rf_on(struct bwi_mac *_mac)
{
	if (_mac->mac_rf.rf_flags & BWI_RF_F_ON)
		return;

	_mac->mac_rf.rf_on(_mac);
	/* TODO: LED */

	_mac->mac_rf.rf_flags |= BWI_RF_F_ON;
}

static __inline void
bwi_rf_calc_nrssi_slope(struct bwi_mac *_mac)
{
	_mac->mac_rf.rf_calc_nrssi_slope(_mac);
}

static __inline void
bwi_rf_set_nrssi_thr(struct bwi_mac *_mac)
{
	_mac->mac_rf.rf_set_nrssi_thr(_mac);
}

static __inline int
bwi_rf_calc_rssi(struct bwi_mac *_mac, const struct bwi_rxbuf_hdr *_hdr)
{
	return (_mac->mac_rf.rf_calc_rssi(_mac, _hdr));
}

static __inline void
bwi_rf_lo_update(struct bwi_mac *_mac)
{
	_mac->mac_rf.rf_lo_update(_mac);
}

#define RF_WRITE(mac, ofs, val)		bwi_rf_write((mac), (ofs), (val))
#define RF_READ(mac, ofs)		bwi_rf_read((mac), (ofs))

#define RF_SETBITS(mac, ofs, bits)		\
	RF_WRITE((mac), (ofs), RF_READ((mac), (ofs)) | (bits))
#define RF_CLRBITS(mac, ofs, bits)		\
	RF_WRITE((mac), (ofs), RF_READ((mac), (ofs)) & ~(bits))
#define RF_FILT_SETBITS(mac, ofs, filt, bits)	\
	RF_WRITE((mac), (ofs), (RF_READ((mac), (ofs)) & (filt)) | (bits))

#endif	/* !_IF_BWIVAR_H */

int		bwi_intr(void *);
int		bwi_attach(struct bwi_softc *);
int		bwi_detach(void *);
int		bwi_init(struct ifnet *);
int		bwi_stop(struct bwi_softc *, int);


code:
/*	$OpenBSD: cac.c,v 1.54 2014/12/19 07:23:57 deraadt Exp $	*/
/*	$NetBSD: cac.c,v 1.15 2000/11/08 19:20:35 ad Exp $	*/

/*
 * Copyright (c) 2001,2003 Michael Shalayeff
 * All rights reserved.
 *
 * The SCSI emulation layer is derived from gdt(4) driver,
 * Copyright (c) 1999, 2000 Niklas Hallqvist. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
 * THE POSSIBILITY OF SUCH DAMAGE.
 */
/*-
 * Copyright (c) 2000 The NetBSD Foundation, Inc.
 * All rights reserved.
 *
 * This code is derived from software contributed to The NetBSD Foundation
 * by Andrew Doran.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

/*
 * Driver for Compaq array controllers.
 */

#include "bio.h"

/* #define	CAC_DEBUG */

#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/ioctl.h>
#include <sys/device.h>
#include <sys/queue.h>
#include <sys/buf.h>
#include <sys/endian.h>
#include <sys/malloc.h>
#include <sys/pool.h>

#include <machine/bus.h>

#include <scsi/scsi_all.h>
#include <scsi/scsi_disk.h>
#include <scsi/scsiconf.h>

#include <dev/ic/cacreg.h>
#include <dev/ic/cacvar.h>

#if NBIO > 0
#include <dev/biovar.h>
#endif
#include <sys/sensors.h>

struct cfdriver cac_cd = {
	NULL, "cac", DV_DULL
};

void    cac_scsi_cmd(struct scsi_xfer *);
void	cacminphys(struct buf *bp, struct scsi_link *sl);

struct scsi_adapter cac_switch = {
	cac_scsi_cmd, cacminphys, 0, 0,
};

void	*cac_ccb_alloc(void *);
void	cac_ccb_done(struct cac_softc *, struct cac_ccb *);
void	cac_ccb_free(void *, void *);
int	cac_ccb_poll(struct cac_softc *, struct cac_ccb *, int);
int	cac_ccb_start(struct cac_softc *, struct cac_ccb *);
int	cac_cmd(struct cac_softc *sc, int command, void *data, int datasize,
	int drive, int blkno, int flags, struct scsi_xfer *xs);
int	cac_get_dinfo(struct cac_softc *sc, int target);
void	cac_copy_internal_data(struct scsi_xfer *xs, void *v, size_t size);

struct	cac_ccb *cac_l0_completed(struct cac_softc *);
int	cac_l0_fifo_full(struct cac_softc *);
void	cac_l0_intr_enable(struct cac_softc *, int);
int	cac_l0_intr_pending(struct cac_softc *);
void	cac_l0_submit(struct cac_softc *, struct cac_ccb *);

#if NBIO > 0
int	cac_ioctl(struct device *, u_long, caddr_t);
int	cac_ioctl_vol(struct cac_softc *, struct bioc_vol *);

#ifndef SMALL_KERNEL
int	cac_create_sensors(struct cac_softc *);
void	cac_sensor_refresh(void *);
#endif
#endif /* NBIO > 0 */

const
struct cac_linkage cac_l0 = {
	cac_l0_completed,
	cac_l0_fifo_full,
	cac_l0_intr_enable,
	cac_l0_intr_pending,
	cac_l0_submit
};

/*
 * Initialise our interface to the controller.
 */
int
cac_init(struct cac_softc *sc, int startfw)
{
	struct scsibus_attach_args saa;
	struct cac_controller_info cinfo;
	int error, rseg, size, i;
	bus_dma_segment_t seg[1];
	struct cac_ccb *ccb;

	SIMPLEQ_INIT(&sc->sc_ccb_free);
	SIMPLEQ_INIT(&sc->sc_ccb_queue);
	mtx_init(&sc->sc_ccb_mtx, IPL_BIO);
	scsi_iopool_init(&sc->sc_iopool, sc, cac_ccb_alloc, cac_ccb_free);

        size = sizeof(struct cac_ccb) * CAC_MAX_CCBS;

	if ((error = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, seg, 1,
	    &rseg, BUS_DMA_NOWAIT | BUS_DMA_ZERO)) != 0) {
		printf("%s: unable to allocate CCBs, error = %d\n",
		    sc->sc_dv.dv_xname, error);
		return (-1);
	}

	if ((error = bus_dmamem_map(sc->sc_dmat, seg, rseg, size,
	    &sc->sc_ccbs, BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) {
		printf("%s: unable to map CCBs, error = %d\n",
		    sc->sc_dv.dv_xname, error);
		return (-1);
	}

	if ((error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0,
	    BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) {
		printf("%s: unable to create CCB DMA map, error = %d\n",
		    sc->sc_dv.dv_xname, error);
		return (-1);
	}

	if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, sc->sc_ccbs,
	    size, NULL, BUS_DMA_NOWAIT)) != 0) {
		printf("%s: unable to load CCB DMA map, error = %d\n",
		    sc->sc_dv.dv_xname, error);
		return (-1);
	}

	sc->sc_ccbs_paddr = sc->sc_dmamap->dm_segs[0].ds_addr;
	ccb = (struct cac_ccb *)sc->sc_ccbs;

	for (i = 0; i < CAC_MAX_CCBS; i++, ccb++) {
		/* Create the DMA map for this CCB's data */
		error = bus_dmamap_create(sc->sc_dmat, CAC_MAX_XFER,
		    CAC_SG_SIZE, CAC_MAX_XFER, 0,
		    BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW,
		    &ccb->ccb_dmamap_xfer);

		if (error) {
			printf("%s: can't create ccb dmamap (%d)\n",
			    sc->sc_dv.dv_xname, error);
			break;
		}

		ccb->ccb_paddr = sc->sc_ccbs_paddr + i * sizeof(struct cac_ccb);
		mtx_enter(&sc->sc_ccb_mtx);
		SIMPLEQ_INSERT_TAIL(&sc->sc_ccb_free, ccb, ccb_chain);
		mtx_leave(&sc->sc_ccb_mtx);
	}

	/* Start firmware background tasks, if needed. */
	if (startfw) {
		if (cac_cmd(sc, CAC_CMD_START_FIRMWARE, &cinfo, sizeof(cinfo),
		    0, 0, CAC_CCB_DATA_IN, NULL)) {
			printf("%s: CAC_CMD_START_FIRMWARE failed\n",
			    sc->sc_dv.dv_xname);
			return (-1);
		}
	}

	if (cac_cmd(sc, CAC_CMD_GET_CTRL_INFO, &cinfo, sizeof(cinfo), 0, 0,
	    CAC_CCB_DATA_IN, NULL)) {
		printf("%s: CAC_CMD_GET_CTRL_INFO failed\n",
		    sc->sc_dv.dv_xname);
		return (-1);
	}

	if (!cinfo.num_drvs) {
		printf("%s: no volumes defined\n", sc->sc_dv.dv_xname);
		return (-1);
	}

	sc->sc_nunits = cinfo.num_drvs;
	sc->sc_dinfos = mallocarray(cinfo.num_drvs,
	    sizeof(struct cac_drive_info), M_DEVBUF, M_NOWAIT | M_ZERO);
	if (sc->sc_dinfos == NULL) {
		printf("%s: cannot allocate memory for drive_info\n",
		    sc->sc_dv.dv_xname);
		return (-1);
	}

	sc->sc_link.adapter_softc = sc;
	sc->sc_link.adapter = &cac_switch;
	sc->sc_link.adapter_target = cinfo.num_drvs;
	sc->sc_link.adapter_buswidth = cinfo.num_drvs;
	sc->sc_link.openings = CAC_MAX_CCBS / sc->sc_nunits;
	if (sc->sc_link.openings < 4 )
		sc->sc_link.openings = 4;
	sc->sc_link.pool = &sc->sc_iopool;

	bzero(&saa, sizeof(saa));
	saa.saa_sc_link = &sc->sc_link;

	config_found(&sc->sc_dv, &saa, scsiprint);

	(*sc->sc_cl->cl_intr_enable)(sc, 1);

#if NBIO > 0
	if (bio_register(&sc->sc_dv, cac_ioctl) != 0)
		printf("%s: controller registration failed\n",
		    sc->sc_dv.dv_xname);
	else
		sc->sc_ioctl = cac_ioctl;

#ifndef SMALL_KERNEL
	if (cac_create_sensors(sc) != 0)
		printf("%s: unable to create sensors\n", sc->sc_dv.dv_xname);
#endif
#endif

	return (0);
}

int
cac_flush(sc)
	struct cac_softc *sc;
{
	u_int8_t buf[512];

	memset(buf, 0, sizeof(buf));
	buf[0] = 1;
	return cac_cmd(sc, CAC_CMD_FLUSH_CACHE, buf, sizeof(buf), 0, 0,
	    CAC_CCB_DATA_OUT, NULL);
}

/*
 * Handle an interrupt from the controller: process finished CCBs and
 * dequeue any waiting CCBs.
 */
int
cac_intr(v)
	void *v;
{
	struct cac_softc *sc = v;
	struct cac_ccb *ccb;
	int istat, ret = 0;

	if (!(istat = (*sc->sc_cl->cl_intr_pending)(sc)))
		return 0;

	if (istat & CAC_INTR_FIFO_NEMPTY)
		while ((ccb = (*sc->sc_cl->cl_completed)(sc)) != NULL) {
			ret = 1;
			cac_ccb_done(sc, ccb);
		}
	cac_ccb_start(sc, NULL);

	return (ret);
}

/*
 * Execute a [polled] command.
 */
int
cac_cmd(struct cac_softc *sc, int command, void *data, int datasize,
	int drive, int blkno, int flags, struct scsi_xfer *xs)
{
	struct cac_ccb *ccb;
	struct cac_sgb *sgb;
	int i, rv, size, nsegs;

#ifdef CAC_DEBUG
	printf("cac_cmd op=%x drv=%d blk=%d data=%p[%x] fl=%x xs=%p ",
	    command, drive, blkno, data, datasize, flags, xs);
#endif

	if (xs) {
		ccb = xs->io;
		/*
		 * The xs may have been restarted by the scsi layer, so
		 * ensure the ccb starts in the proper state.
		 */
		ccb->ccb_flags = 0;
	} else {
		/* Internal command. Need to get our own ccb. */
		ccb = scsi_io_get(&sc->sc_iopool, SCSI_POLL | SCSI_NOSLEEP);
		if (ccb == NULL)
			return (EBUSY);
	}

	if ((flags & (CAC_CCB_DATA_IN | CAC_CCB_DATA_OUT)) != 0) {
		bus_dmamap_load(sc->sc_dmat, ccb->ccb_dmamap_xfer,
		    (void *)data, datasize, NULL, BUS_DMA_NOWAIT);

		bus_dmamap_sync(sc->sc_dmat, ccb->ccb_dmamap_xfer, 0,
		    ccb->ccb_dmamap_xfer->dm_mapsize,
		    (flags & CAC_CCB_DATA_IN) != 0 ? BUS_DMASYNC_PREREAD :
		    BUS_DMASYNC_PREWRITE);

		sgb = ccb->ccb_seg;
		nsegs = ccb->ccb_dmamap_xfer->dm_nsegs;
		if (nsegs > CAC_SG_SIZE)
			panic("cac_cmd: nsegs botch");

		size = 0;
		for (i = 0; i < nsegs; i++, sgb++) {
			size += ccb->ccb_dmamap_xfer->dm_segs[i].ds_len;
			sgb->length =
			    htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_len);
			sgb->addr =
			    htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_addr);
		}
	} else {
		size = datasize;
		nsegs = 0;
	}

	ccb->ccb_hdr.drive = drive;
	ccb->ccb_hdr.priority = 0;
	ccb->ccb_hdr.size = htole16((sizeof(struct cac_req) +
	    sizeof(struct cac_sgb) * CAC_SG_SIZE) >> 2);

	ccb->ccb_req.next = 0;
	ccb->ccb_req.command = command;
	ccb->ccb_req.error = 0;
	ccb->ccb_req.blkno = htole32(blkno);
	ccb->ccb_req.bcount = htole16(howmany(size, DEV_BSIZE));
	ccb->ccb_req.sgcount = nsegs;
	ccb->ccb_req.reserved = 0;

	ccb->ccb_flags = flags;
	ccb->ccb_datasize = size;
	ccb->ccb_xs = xs;

	if (!xs || xs->flags & SCSI_POLL) {
		/* Synchronous commands musn't wait. */
		mtx_enter(&sc->sc_ccb_mtx);
		if ((*sc->sc_cl->cl_fifo_full)(sc)) {
			mtx_leave(&sc->sc_ccb_mtx);
			rv = EBUSY;
		} else {
			mtx_leave(&sc->sc_ccb_mtx);
			ccb->ccb_flags |= CAC_CCB_ACTIVE;
			(*sc->sc_cl->cl_submit)(sc, ccb);
			rv = cac_ccb_poll(sc, ccb, 2000);
		}
	} else
		rv = cac_ccb_start(sc, ccb);

	if (xs == NULL)
		scsi_io_put(&sc->sc_iopool, ccb);

	return (rv);
}

/*
 * Wait for the specified CCB to complete.  Must be called at splbio.
 */
int
cac_ccb_poll(struct cac_softc *sc, struct cac_ccb *wantccb, int timo)
{
	struct cac_ccb *ccb;
	int t;

	t = timo * 100;
	do {
		for (; t--; DELAY(10))
			if ((ccb = (*sc->sc_cl->cl_completed)(sc)) != NULL)
				break;
		if (t < 0) {
			printf("%s: timeout\n", sc->sc_dv.dv_xname);
			return (EBUSY);
		}
		cac_ccb_done(sc, ccb);
	} while (ccb != wantccb);

	return (0);
}

/*
 * Enqueue the specified command (if any) and attempt to start all enqueued
 * commands.
 */
int
cac_ccb_start(struct cac_softc *sc, struct cac_ccb *ccb)
{
	if (ccb != NULL) {
		mtx_enter(&sc->sc_ccb_mtx);
		SIMPLEQ_INSERT_TAIL(&sc->sc_ccb_queue, ccb, ccb_chain);
		mtx_leave(&sc->sc_ccb_mtx);
	}

	while (1) {
		mtx_enter(&sc->sc_ccb_mtx);
		if (SIMPLEQ_EMPTY(&sc->sc_ccb_queue) ||
		    (*sc->sc_cl->cl_fifo_full)(sc)) {
			mtx_leave(&sc->sc_ccb_mtx);
			break;
		}
		ccb = SIMPLEQ_FIRST(&sc->sc_ccb_queue);
		SIMPLEQ_REMOVE_HEAD(&sc->sc_ccb_queue, ccb_chain);
		mtx_leave(&sc->sc_ccb_mtx);

		ccb->ccb_flags |= CAC_CCB_ACTIVE;
		(*sc->sc_cl->cl_submit)(sc, ccb);
	}

	return (0);
}

/*
 * Process a finished CCB.
 */
void
cac_ccb_done(struct cac_softc *sc, struct cac_ccb *ccb)
{
	struct scsi_xfer *xs = ccb->ccb_xs;
	int error = 0;

	if ((ccb->ccb_flags & CAC_CCB_ACTIVE) == 0) {
		printf("%s: CCB not active, xs=%p\n", sc->sc_dv.dv_xname, xs);
		if (xs) {
			xs->error = XS_DRIVER_STUFFUP;
			scsi_done(xs);
		}
		return;
	}

	if ((ccb->ccb_flags & (CAC_CCB_DATA_IN | CAC_CCB_DATA_OUT)) != 0) {
		bus_dmamap_sync(sc->sc_dmat, ccb->ccb_dmamap_xfer, 0,
		    ccb->ccb_dmamap_xfer->dm_mapsize,
		    ccb->ccb_flags & CAC_CCB_DATA_IN ?
		    BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
		bus_dmamap_unload(sc->sc_dmat, ccb->ccb_dmamap_xfer);
	}

	if ((ccb->ccb_req.error & CAC_RET_SOFT_ERROR) != 0)
		printf("%s: soft error; corrected\n", sc->sc_dv.dv_xname);
	if ((ccb->ccb_req.error & CAC_RET_HARD_ERROR) != 0) {
		error = 1;
		printf("%s: hard error\n", sc->sc_dv.dv_xname);
	}
	if ((ccb->ccb_req.error & CAC_RET_CMD_REJECTED) != 0) {
		error = 1;
		printf("%s: invalid request\n", sc->sc_dv.dv_xname);
	}

	if (xs) {
		if (error)
			xs->error = XS_DRIVER_STUFFUP;
		else
			xs->resid = 0;

		scsi_done(xs);
	}
}

/*
 * Allocate a CCB.
 */
void *
cac_ccb_alloc(void *xsc)
{
	struct cac_softc *sc = xsc;
	struct cac_ccb *ccb = NULL;

	mtx_enter(&sc->sc_ccb_mtx);
	if (SIMPLEQ_EMPTY(&sc->sc_ccb_free)) {
#ifdef CAC_DEBUG
		printf("%s: unable to alloc CCB\n", sc->sc_dv.dv_xname);
#endif
	} else {
		ccb = SIMPLEQ_FIRST(&sc->sc_ccb_free);
		SIMPLEQ_REMOVE_HEAD(&sc->sc_ccb_free, ccb_chain);
	}
	mtx_leave(&sc->sc_ccb_mtx);

	return (ccb);
}

/*
 * Put a CCB onto the freelist.
 */
void
cac_ccb_free(void *xsc, void *xccb)
{
	struct cac_softc *sc = xsc;
	struct cac_ccb *ccb = xccb;

	ccb->ccb_flags = 0;

	mtx_enter(&sc->sc_ccb_mtx);
	SIMPLEQ_INSERT_HEAD(&sc->sc_ccb_free, ccb, ccb_chain);
	mtx_leave(&sc->sc_ccb_mtx);
}

int
cac_get_dinfo(sc, target)
	struct cac_softc *sc;
	int target;
{
	if (sc->sc_dinfos[target].ncylinders)
		return (0);

	if (cac_cmd(sc, CAC_CMD_GET_LOG_DRV_INFO, &sc->sc_dinfos[target],
	    sizeof(*sc->sc_dinfos), target, 0, CAC_CCB_DATA_IN, NULL)) {
		printf("%s: CMD_GET_LOG_DRV_INFO failed\n",
		    sc->sc_dv.dv_xname);
		return (-1);
	}

	return (0);
}

void
cacminphys(struct buf *bp, struct scsi_link *sl)
{
	if (bp->b_bcount > CAC_MAX_XFER)
		bp->b_bcount = CAC_MAX_XFER;
	minphys(bp);
}

void
cac_copy_internal_data(xs, v, size)
	struct scsi_xfer *xs;
	void *v;
	size_t size;
{
	size_t copy_cnt;

	if (!xs->datalen)
		printf("uio move is not yet supported\n");
	else {
		copy_cnt = MIN(size, xs->datalen);
		memcpy(xs->data, v, copy_cnt);
	}
}

void
cac_scsi_cmd(xs)
	struct scsi_xfer *xs;
{
	struct scsi_link *link = xs->sc_link;
	struct cac_softc *sc = link->adapter_softc;
	struct cac_drive_info *dinfo;
	struct scsi_inquiry_data inq;
	struct scsi_sense_data sd;
	struct scsi_read_cap_data rcd;
	u_int8_t target = link->target;
	u_int32_t blockno, blockcnt, size;
	struct scsi_rw *rw;
	struct scsi_rw_big *rwb;
	int op, flags, s, error;
	const char *p;

	if (target >= sc->sc_nunits || link->lun != 0) {
		xs->error = XS_DRIVER_STUFFUP;
		scsi_done(xs);
		return;
	}

	s = splbio();
	xs->error = XS_NOERROR;
	dinfo = &sc->sc_dinfos[target];

	switch (xs->cmd->opcode) {
	case TEST_UNIT_READY:
	case START_STOP:
#if 0
	case VERIFY:
#endif
		break;

	case REQUEST_SENSE:
		bzero(&sd, sizeof sd);
		sd.error_code = SSD_ERRCODE_CURRENT;
		sd.segment = 0;
		sd.flags = SKEY_NO_SENSE;
		*(u_int32_t*)sd.info = htole32(0);
		sd.extra_len = 0;
		cac_copy_internal_data(xs, &sd, sizeof sd);
		break;

	case INQUIRY:
		if (cac_get_dinfo(sc, target)) {
			xs->error = XS_DRIVER_STUFFUP;
			break;
		}
		bzero(&inq, sizeof inq);
		inq.device = T_DIRECT;
		inq.dev_qual2 = 0;
		inq.version = 2;
		inq.response_format = 2;
		inq.additional_length = 32;
		inq.flags |= SID_CmdQue;
		strlcpy(inq.vendor, "Compaq  ", sizeof inq.vendor);
		switch (CAC_GET1(dinfo->mirror)) {
		case 0: p = "RAID0";	break;
		case 1: p = "RAID4";	break;
		case 2: p = "RAID1";	break;
		case 3: p = "RAID5";	break;
		default:p = "<UNK>";	break;
		}
		snprintf(inq.product, sizeof inq.product, "%s vol  #%02d",
		    p, target);
		strlcpy(inq.revision, "   ", sizeof inq.revision);
		cac_copy_internal_data(xs, &inq, sizeof inq);
		break;

	case READ_CAPACITY:
		if (cac_get_dinfo(sc, target)) {
			xs->error = XS_DRIVER_STUFFUP;
			break;
		}
		bzero(&rcd, sizeof rcd);
		_lto4b( CAC_GET2(dinfo->ncylinders) * CAC_GET1(dinfo->nheads) *
		    CAC_GET1(dinfo->nsectors) - 1, rcd.addr);
		_lto4b(CAC_SECTOR_SIZE, rcd.length);
		cac_copy_internal_data(xs, &rcd, sizeof rcd);
		break;

	case PREVENT_ALLOW:
		break;

	case SYNCHRONIZE_CACHE:
		if (cac_flush(sc))
			xs->error = XS_DRIVER_STUFFUP;
		break;

	case READ_COMMAND:
	case READ_BIG:
	case WRITE_COMMAND:
	case WRITE_BIG:

		flags = 0;
		/* A read or write operation. */
		if (xs->cmdlen == 6) {
			rw = (struct scsi_rw *)xs->cmd;
			blockno = _3btol(rw->addr) &
			    (SRW_TOPADDR << 16 | 0xffff);
			blockcnt = rw->length ? rw->length : 0x100;
		} else {
			rwb = (struct scsi_rw_big *)xs->cmd;
			blockno = _4btol(rwb->addr);
			blockcnt = _2btol(rwb->length);
		}
		size = CAC_GET2(dinfo->ncylinders) *
		    CAC_GET1(dinfo->nheads) * CAC_GET1(dinfo->nsectors);
		if (blockno >= size || blockno + blockcnt > size) {
			printf("%s: out of bounds %u-%u >= %u\n",
			    sc->sc_dv.dv_xname, blockno, blockcnt, size);
			xs->error = XS_DRIVER_STUFFUP;
			break;
		}

		switch (xs->cmd->opcode) {
		case READ_COMMAND:
		case READ_BIG:
			op = CAC_CMD_READ;
			flags = CAC_CCB_DATA_IN;
			break;
		case WRITE_COMMAND:
		case WRITE_BIG:
			op = CAC_CMD_WRITE;
			flags = CAC_CCB_DATA_OUT;
			break;
		}

		if ((error = cac_cmd(sc, op, xs->data, blockcnt * DEV_BSIZE,
		    target, blockno, flags, xs))) {
			splx(s);
			if (error == EBUSY)
				xs->error = XS_BUSY;
			else
				xs->error = XS_DRIVER_STUFFUP;
			scsi_done(xs);
			return;
		}

		splx(s);
		return;

	default:
		SC_DEBUG(link, SDEV_DB1, ("unsupported scsi command %#x "
		    "tgt %d ", xs->cmd->opcode, target));
		xs->error = XS_DRIVER_STUFFUP;
	}

	splx(s);
	scsi_done(xs);
}

/*
 * Board specific linkage shared between multiple bus types.
 */

int
cac_l0_fifo_full(struct cac_softc *sc)
{

	return (cac_inl(sc, CAC_REG_CMD_FIFO) == 0);
}

void
cac_l0_submit(struct cac_softc *sc, struct cac_ccb *ccb)
{
#ifdef CAC_DEBUG
	printf("submit-%x ", ccb->ccb_paddr);
#endif
	bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 0,
	    sc->sc_dmamap->dm_mapsize,
	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
	cac_outl(sc, CAC_REG_CMD_FIFO, ccb->ccb_paddr);
}

struct cac_ccb *
cac_l0_completed(sc)
	struct cac_softc *sc;
{
	struct cac_ccb *ccb;
	paddr_t off, orig_off;

	if (!(off = cac_inl(sc, CAC_REG_DONE_FIFO)))
		return NULL;
#ifdef CAC_DEBUG
	printf("compl-%x ", off);
#endif
	orig_off = off;

	bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 0,
	    sc->sc_dmamap->dm_mapsize,
	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);

	off = (off & ~3) - sc->sc_ccbs_paddr;
	ccb = (struct cac_ccb *)(sc->sc_ccbs + off);

	if (orig_off & 3 && ccb->ccb_req.error == 0)
		ccb->ccb_req.error = CAC_RET_CMD_INVALID;

	return (ccb);
}

int
cac_l0_intr_pending(struct cac_softc *sc)
{

	return (cac_inl(sc, CAC_REG_INTR_PENDING));
}

void
cac_l0_intr_enable(struct cac_softc *sc, int state)
{

	cac_outl(sc, CAC_REG_INTR_MASK,
	    state ? CAC_INTR_ENABLE : CAC_INTR_DISABLE);
}

#if NBIO > 0
const int cac_level[] = { 0, 4, 1, 5, 51, 7 };
const int cac_stat[] = { BIOC_SVONLINE, BIOC_SVOFFLINE, BIOC_SVOFFLINE,
    BIOC_SVDEGRADED, BIOC_SVREBUILD, BIOC_SVREBUILD, BIOC_SVDEGRADED,
    BIOC_SVDEGRADED, BIOC_SVINVALID, BIOC_SVINVALID, BIOC_SVBUILDING,
    BIOC_SVOFFLINE, BIOC_SVBUILDING };

int
cac_ioctl(struct device *dev, u_long cmd, caddr_t addr)
{
	struct cac_softc *sc = (struct cac_softc *)dev;
	struct bioc_inq *bi;
	struct bioc_disk *bd;
	cac_lock_t lock;
	int error = 0;

	lock = CAC_LOCK(sc);
	switch (cmd) {
	case BIOCINQ:
		bi = (struct bioc_inq *)addr;
		strlcpy(bi->bi_dev, sc->sc_dv.dv_xname, sizeof(bi->bi_dev));
		bi->bi_novol = sc->sc_nunits;
		bi->bi_nodisk = 0;
		break;

	case BIOCVOL:
		error = cac_ioctl_vol(sc, (struct bioc_vol *)addr);
		break;

	case BIOCDISK:
		bd = (struct bioc_disk *)addr;
		if (bd->bd_volid > sc->sc_nunits) {
			error = EINVAL;
			break;
		}
		/* No disk information yet */
		break;

	case BIOCBLINK:
	case BIOCALARM:
	case BIOCSETSTATE:
	default:
		error = ENOTTY;
	}
	CAC_UNLOCK(sc, lock);

	return (error);
}

int
cac_ioctl_vol(struct cac_softc *sc, struct bioc_vol *bv)
{
	struct cac_drive_info dinfo;
	struct cac_drive_status dstatus;
	u_int32_t blks;

	if (bv->bv_volid > sc->sc_nunits)
		return (EINVAL);
	if (cac_cmd(sc, CAC_CMD_GET_LOG_DRV_INFO, &dinfo, sizeof(dinfo),
	    bv->bv_volid, 0, CAC_CCB_DATA_IN, NULL))
		return (EIO);
	if (cac_cmd(sc, CAC_CMD_SENSE_DRV_STATUS, &dstatus, sizeof(dstatus),
	    bv->bv_volid, 0, CAC_CCB_DATA_IN, NULL))
		return (EIO);
	bv->bv_status = BIOC_SVINVALID;
	blks = CAC_GET2(dinfo.ncylinders) * CAC_GET1(dinfo.nheads) *
	    CAC_GET1(dinfo.nsectors);
	bv->bv_size = (off_t)blks * CAC_GET2(dinfo.secsize);
	bv->bv_level = cac_level[CAC_GET1(dinfo.mirror)];	/*XXX limit check */
	bv->bv_nodisk = 0;		/* XXX */
	bv->bv_status = 0;		/* XXX */
	bv->bv_percent = -1;
	bv->bv_seconds = 0;
	if (dstatus.stat < nitems(cac_stat))
		bv->bv_status = cac_stat[dstatus.stat];
	if (bv->bv_status == BIOC_SVREBUILD ||
	    bv->bv_status == BIOC_SVBUILDING)
		bv->bv_percent = ((blks - CAC_GET4(dstatus.prog)) * 1000ULL) /
		    blks;

	return (0);
}

#ifndef SMALL_KERNEL
int
cac_create_sensors(struct cac_softc *sc)
{
	struct device *dev;
	struct scsibus_softc *ssc = NULL;
	struct scsi_link *link;
	int i;

	TAILQ_FOREACH(dev, &alldevs, dv_list) {
		if (dev->dv_parent != &sc->sc_dv)
			continue;

		/* check if this is the scsibus for the logical disks */
		ssc = (struct scsibus_softc *)dev;
		if (ssc->adapter_link == &sc->sc_link)
			break;
		ssc = NULL;
	}

	if (ssc == NULL)
		return (1);

	sc->sc_sensors = mallocarray(sc->sc_nunits,
	    sizeof(struct ksensor), M_DEVBUF, M_NOWAIT | M_ZERO);
	if (sc->sc_sensors == NULL)
		return (1);

	strlcpy(sc->sc_sensordev.xname, sc->sc_dv.dv_xname,
	    sizeof(sc->sc_sensordev.xname));

	for (i = 0; i < sc->sc_nunits; i++) {
		link = scsi_get_link(ssc, i, 0);
		if (link == NULL)
			goto bad;

		dev = link->device_softc;

		sc->sc_sensors[i].type = SENSOR_DRIVE;
		sc->sc_sensors[i].status = SENSOR_S_UNKNOWN;

		strlcpy(sc->sc_sensors[i].desc, dev->dv_xname,
		    sizeof(sc->sc_sensors[i].desc));

		sensor_attach(&sc->sc_sensordev, &sc->sc_sensors[i]);
	}

	if (sensor_task_register(sc, cac_sensor_refresh, 10) == NULL)
		goto bad;

	sensordev_install(&sc->sc_sensordev);

	return (0);

bad:
	free(sc->sc_sensors, M_DEVBUF, 0);

	return (1);
}

void
cac_sensor_refresh(void *arg)
{
	struct cac_softc *sc = arg;
	struct bioc_vol bv;
	int i, s;

	for (i = 0; i < sc->sc_nunits; i++) {
		bzero(&bv, sizeof(bv));
		bv.bv_volid = i;
		s = splbio();
		if (cac_ioctl_vol(sc, &bv)) {
			splx(s);
			return;
		}
		splx(s);

		switch (bv.bv_status) {
		case BIOC_SVOFFLINE:
			sc->sc_sensors[i].value = SENSOR_DRIVE_FAIL;
			sc->sc_sensors[i].status = SENSOR_S_CRIT;
			break;

		case BIOC_SVDEGRADED:
			sc->sc_sensors[i].value = SENSOR_DRIVE_PFAIL;
			sc->sc_sensors[i].status = SENSOR_S_WARN;
			break;

		case BIOC_SVSCRUB:
		case BIOC_SVONLINE:
			sc->sc_sensors[i].value = SENSOR_DRIVE_ONLINE;
			sc->sc_sensors[i].status = SENSOR_S_OK;
			break;

		case BIOC_SVREBUILD:
		case BIOC_SVBUILDING:
			sc->sc_sensors[i].value = SENSOR_DRIVE_REBUILD;
			sc->sc_sensors[i].status = SENSOR_S_OK;
			break;

		case BIOC_SVINVALID:
			/* FALLTRHOUGH */
		default:
			sc->sc_sensors[i].value = 0; /* unknown */
			sc->sc_sensors[i].status = SENSOR_S_UNKNOWN;
		}
	}
}
#endif /* SMALL_KERNEL */
#endif /* NBIO > 0 */


code:
/*	$OpenBSD: cacreg.h,v 1.6 2008/10/29 21:17:15 brad Exp $	*/
/*	$NetBSD: cacreg.h,v 1.5 2001/01/10 16:48:04 ad Exp $	*/

/*-
 * Copyright (c) 2000 The NetBSD Foundation, Inc.
 * All rights reserved.
 *
 * This code is derived from software contributed to The NetBSD Foundation
 * by Andrew Doran.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

/*-
 * Copyright (c) 1999 Jonathan Lemon
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */

#ifndef _IC_CACREG_H_
#define	_IC_CACREG_H_

/* Board register offsets */
#define	CAC_REG_CMD_FIFO		0x04
#define	CAC_REG_DONE_FIFO		0x08
#define	CAC_REG_INTR_MASK		0x0C
#define	CAC_REG_STATUS			0x10
#define	CAC_REG_INTR_PENDING		0x14

#define	CAC_42REG_CMD_FIFO		0x40
#define	CAC_42REG_DONE_FIFO		0x44
#define	CAC_42REG_INTR_MASK		0x34
#define	CAC_42REG_STATUS		0x30

#define	CAC_42_EXTINT			0x08

#define	CAC_EISAREG_INTR_MASK		0x01
#define	CAC_EISAREG_LOCAL_MASK		0x04
#define	CAC_EISAREG_LOCAL_DOORBELL	0x05
#define	CAC_EISAREG_SYSTEM_MASK		0x06
#define	CAC_EISAREG_SYSTEM_DOORBELL	0x07
#define	CAC_EISAREG_LIST_ADDR		0x08
#define	CAC_EISAREG_LIST_LEN		0x0c
#define	CAC_EISAREG_TAG			0x0f
#define	CAC_EISAREG_COMPLETE_ADDR	0x10
#define	CAC_EISAREG_LIST_STATUS		0x16

/* EISA channel control */
#define	CAC_EISA_CHANNEL_BUSY		0x01
#define	CAC_EISA_CHANNEL_CLEAR		0x02

/* Interrupt mask values */
#define	CAC_INTR_DISABLE		0x00
#define	CAC_INTR_ENABLE			0x01

/* Interrupt status masks */
#define	CAC_INTR_FIFO_NEMPTY		0x01

/* Command types */
#define	CAC_CMD_GET_LOG_DRV_INFO	0x10
#define	CAC_CMD_GET_CTRL_INFO		0x11
#define	CAC_CMD_SENSE_DRV_STATUS	0x12
#define	CAC_CMD_START_RECOVERY		0x13
#define	CAC_CMD_GET_PHYS_DRV_INFO	0x15
#define	CAC_CMD_BLINK_DRV_LEDS		0x16
#define	CAC_CMD_SENSE_DRV_LEDS		0x17
#define	CAC_CMD_GET_LOG_DRV_EXT		0x18
#define	CAC_CMD_GET_CTRL_INFO		0x11
#define	CAC_CMD_READ			0x20
#define	CAC_CMD_WRITE			0x30
#define	CAC_CMD_WRITE_MEDIA		0x31
#define	CAC_CMD_GET_CONFIG		0x50
#define	CAC_CMD_SET_CONFIG		0x51
#define	CAC_CMD_START_FIRMWARE		0x99
#define	CAC_CMD_FLUSH_CACHE		0xc2

/* Return status codes */
#define	CAC_RET_SOFT_ERROR		0x02
#define	CAC_RET_HARD_ERROR		0x04
#define	CAC_RET_CMD_INVALID		0x10
#define	CAC_RET_CMD_REJECTED		0x14

struct cac_drive_info {
	u_int16_t	secsize;
	u_int32_t	secperunit;
	u_int16_t	ncylinders;
	u_int8_t	nheads;
	u_int8_t	signature;
	u_int8_t	psectors;
	u_int16_t	wprecomp;
	u_int8_t	max_acc;
	u_int8_t	control;
	u_int16_t	pcylinders;
	u_int8_t	ptracks;
	u_int16_t	landing_zone;
	u_int8_t	nsectors;
	u_int8_t	checksum;
	u_int8_t	mirror;
} __packed;

struct cac_controller_info {
	u_int8_t	num_drvs;
	u_int32_t	signature;
	u_int8_t	firm_rev[4];
	u_int8_t	rom_rev[4];
	u_int8_t	hw_rev;
	u_int32_t	bb_rev;
	u_int32_t	drv_present_map;
	u_int32_t	ext_drv_map;
	u_int32_t	board_id;
	u_int8_t	cfg_error;
	u_int32_t	non_disk_bits;
	u_int8_t	bad_ram_addr;
	u_int8_t	cpu_rev;
	u_int8_t	pdpi_rev;
	u_int8_t	epic_rev;
	u_int8_t	wcxc_rev;
	u_int8_t	marketing_rev;
	u_int8_t	ctlr_flags;
	u_int8_t	host_flags;
	u_int8_t	expand_dis;
	u_int8_t	scsi_chips;
	u_int32_t	max_req_blocks;
	u_int32_t	ctlr_clock;
	u_int8_t	drvs_per_bus;
	u_int16_t	big_drv_present_map[8];
	u_int16_t	big_ext_drv_map[8];
	u_int16_t	big_non_disk_map[8];
	u_int16_t	task_flags;
	u_int8_t	icl_bus;
	u_int8_t	red_modes;
	u_int8_t	cur_red_mode;
	u_int8_t	red_ctlr_stat;
	u_int8_t	red_fail_reason;
	u_int8_t	reserved[403];
} __packed;

struct cac_drive_status {
	u_int8_t	stat;
#define	CAC_LD_OK	0
#define	CAC_LD_FAILED	1
#define	CAC_LD_UNCONF	2
#define	CAC_LD_DEGRAD	3
#define	CAC_LD_RBLDRD	4	/* ready for rebuild */
#define	CAC_LD_REBLD	5
#define	CAC_LD_PDINV	6	/* wrong phys drive replaced */
#define	CAC_LD_PDUNC	7	/* phys drive is not connected proper */
#define	CAC_LD_EXPND	10	/* expanding */
#define	CAC_LD_NORDY	11	/* volume is not ready */
#define	CAC_LD_QEXPND	12	/* queued for expansion */
	u_int8_t	failed[4];	/* failed map */
	u_int8_t	res0[416];
	u_int8_t	prog[4];	/* blocks left to rebuild/expand */
	u_int8_t	rebuild;	/* drive that is rebuilding */
	u_int16_t	remapcnt[32];	/* count of re3mapped blocks for pds */
	u_int8_t	replaced[4];	/* replaced drives map */
	u_int8_t	spare[4];	/* used spares map */
	u_int8_t	sparestat;	/* spare status */
#define	CAC_LD_CONF	0x01	/* spare configured */
#define	CAC_LD_RBLD	0x02	/* spare is used and rebuilding */
#define	CAC_LD_DONE	0x04	/* spare rebuild done */
#define	CAC_LD_FAIL	0x08	/* at least one spare drive has failed */
#define	CAC_LD_USED	0x10	/* at least one spare drive is used */
#define	CAC_LD_AVAIL	0x20	/* at least one spare is available */
	u_int8_t	sparemap[32];	/* spare->pd replacement map */
	u_int8_t	replok[4];	/* replaced failed map */
	u_int8_t	readyok;	/* ready to become ok */
	u_int8_t	memfail;	/* cache mem failure */
	u_int8_t	expfail;	/* expansion failure */
	u_int8_t	rebldfail;	/* rebuild failure */
#define	CAC_LD_RBLD_READ	0x01	/* read faild */
#define	CAC_LD_RBLD_WRITE	0x02	/* write fail */
	u_int8_t	bigfailed[16];	/* bigmap vers of same of the above */
	u_int8_t	bigremapcnt[256];
	u_int8_t	bigreplaced[16];
	u_int8_t	bigspare[16];
	u_int8_t	bigsparemap[128];
	u_int8_t	bigreplok[16];
	u_int8_t	bigrebuild;	/* big-number rebuilding driveno */
} __packed;

struct cac_blink {
	u_int32_t	duration;	/* x100ms */
	u_int32_t	elapsed;	/* only for sense */
	u_int8_t	pdtab[256];
#define	CAC_BLINK_ALL	1
#define	CAC_BLINK_TIMED 2
	u_int8_t	res[248];
} __packed;

struct cac_hdr {
	u_int8_t	drive;		/* logical drive */
	u_int8_t	priority;	/* block priority */
	u_int16_t	size;		/* size of request, in words */
} __packed;

struct cac_req {
	u_int16_t	next;		/* offset of next request */
	u_int8_t	command;	/* command */
	u_int8_t	error;		/* return error code */
	u_int32_t	blkno;		/* block number */
	u_int16_t	bcount;		/* block count */
	u_int8_t	sgcount;	/* number of scatter/gather entries */
	u_int8_t	reserved;	/* reserved */
} __packed;

struct cac_sgb {
	u_int32_t	length;		/* length of S/G segment */
	u_int32_t	addr;		/* physical address of block */
} __packed;

#endif	/* !_IC_CACREG_H_ */


code:
/*	$OpenBSD: cacvar.h,v 1.7 2013/05/30 16:15:02 deraadt Exp $	*/
/*	$NetBSD: cacvar.h,v 1.7 2000/10/19 14:28:47 ad Exp $	*/

/*-
 * Copyright (c) 2000 The NetBSD Foundation, Inc.
 * All rights reserved.
 *
 * This code is derived from software contributed to The NetBSD Foundation
 * by Andrew Doran.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef _IC_CACVAR_H_
#define	_IC_CACVAR_H_

#define	CAC_MAX_CCBS	128
#define	CAC_MAX_XFER	(0xffff * 512)
#define	CAC_SG_SIZE	32
#define	CAC_SECTOR_SIZE	512

#define	cac_inb(sc, port) \
	bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, port)
#define	cac_inw(sc, port) \
	bus_space_read_2((sc)->sc_iot, (sc)->sc_ioh, port)
#define	cac_inl(sc, port) \
	bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, port)
#define	cac_outb(sc, port, val) \
	bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, port, val)
#define	cac_outw(sc, port, val) \
	bus_space_write_2((sc)->sc_iot, (sc)->sc_ioh, port, val)
#define	cac_outl(sc, port, val) \
	bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, port, val)

/*
 * Stupid macros to deal with alignment/endianness issues.
 */

#define	CAC_GET1(x)							\
	(((u_char *)&(x))[0])
#define	CAC_GET2(x)							\
	(((u_char *)&(x))[0] | (((u_char *)&(x))[1] << 8))
#define	CAC_GET4(x)							\
	((((u_char *)&(x))[0] | (((u_char *)&(x))[1] << 8)) |		\
	(((u_char *)&(x))[2] << 16 | (((u_char *)&(x))[3] << 24)))

struct cac_ccb {
	/* Data the controller will touch - 276 bytes */
	struct cac_hdr	ccb_hdr;
	struct cac_req	ccb_req;
	struct cac_sgb	ccb_seg[CAC_SG_SIZE];

	/* Data the controller won't touch */
	int		ccb_flags;
	int		ccb_datasize;
	paddr_t		ccb_paddr;
	bus_dmamap_t	ccb_dmamap_xfer;
	SIMPLEQ_ENTRY(cac_ccb) ccb_chain;
	struct scsi_xfer *ccb_xs;
};

#define	CAC_CCB_DATA_IN		0x0001	/* Map describes inbound xfer */
#define	CAC_CCB_DATA_OUT	0x0002	/* Map describes outbound xfer */
#define	CAC_CCB_ACTIVE		0x0004	/* Command submitted to controller */

struct cac_softc;

struct cac_linkage {
	struct	cac_ccb *(*cl_completed)(struct cac_softc *);
	int	(*cl_fifo_full)(struct cac_softc *);
	void	(*cl_intr_enable)(struct cac_softc *, int);
	int	(*cl_intr_pending)(struct cac_softc *);
	void	(*cl_submit)(struct cac_softc *, struct cac_ccb *);
};

struct cac_softc {
	struct device		sc_dv;
	bus_space_tag_t		sc_iot;
	bus_space_handle_t	sc_ioh;
	bus_dma_tag_t		sc_dmat;
	bus_dmamap_t		sc_dmamap;
	int			sc_nunits;
	void			*sc_ih;
	struct scsi_link	sc_link;
	const struct cac_linkage	*sc_cl;
	caddr_t			sc_ccbs;
	paddr_t			sc_ccbs_paddr;
	SIMPLEQ_HEAD(, cac_ccb)	sc_ccb_free;
	SIMPLEQ_HEAD(, cac_ccb)	sc_ccb_queue;
	struct cac_drive_info	*sc_dinfos;
	int			(*sc_ioctl)(struct device *, u_long, caddr_t);
	struct ksensor		*sc_sensors;
	struct ksensordev	sc_sensordev;

	struct mutex		sc_ccb_mtx; /* ccb queue protection */
	struct scsi_iopool	sc_iopool;
};

/* XXX These have to become spinlocks in case of fine SMP */
#define	CAC_LOCK(sc) splbio()
#define	CAC_UNLOCK(sc, lock) splx(lock)
typedef	int cac_lock_t;

int	cac_init(struct cac_softc *, int);
int	cac_intr(void *);
int	cac_flush(struct cac_softc *);

extern const struct	cac_linkage cac_l0;

#endif	/* !_IC_CACVAR_H_ */


code:
/*	$OpenBSD: cd1190reg.h,v 1.4 2008/11/29 01:55:06 ray Exp $	*/

/*-
 * Copyright (c) 1998 Iain Hibbert.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/*
 * Definitions for Cirrus Logic CD1190 parallel chips.
 */

/* ACK Width Register */
#define CD1190_AWR		0x03

/* Controller Command Register */
#define CD1190_CCR		0x0b
#define CD1190_CCR_CGC		(1<<7)	/* Change Global Config Command */
#define CD1190_CCR_CGC_RESET	 (1<<0) /* CGC Reset Command */
#define CD1190_CCR_PAR		(1<<6)	/* Parallel Command */
#define CD1190_CCR_PAR_DISABLE	 (1<<2) /* PAR Parallel Disable */
#define CD1190_CCR_PAR_FLUSH	 (1<<1) /* PAR Flush FIFO */
#define CD1190_CCR_PAR_ENABLE	 (1<<0) /* PAR Parallel Enable */
#define CD1190_CCR_SIG		(1<<5)	/* Signal Command */
#define CD1190_CCR_SIG_SET_BUSY	 (1<<2) /* SIG Set Busy Output */
#define CD1190_CCR_SIG_ACK	 (1<<1) /* SIG Pulse ACK Output */
#define CD1190_CCR_SIG_CLR_BUSY	 (1<<0) /* SIG Clear Busy Output */
#define CD1190_CCR_TIM		(1<<4)	/* Timer Command */
#define CD1190_CCR_TIM_ENABLE	 (1<<3) /* Timer Enabled */

/* Data Time-0ut Register */
#define CD1190_DTR		0x09

/* End Of Service Request Register */
#define CD1190_ESR		0x10

/* FIFO Count Register */
#define CD1190_FCR		0x0e

/* FIFO Data Register */
#define CD1190_FDR		0x12

/* Firmware Revision Register */
#define CD1190_FRR		0x0f

/* FIFO Threshold Register */
#define CD1190_FTR		0x08

/* Global Config Register */
#define CD1190_GCR		0x0a
#define CD1190_GCR_NOACK	(1<<2) /* NO-ACK handshaking */
#define CD1190_GCR_MODE		(1<<1) /* Peripheral/Controller Mode */
#define CD1190_GCR_DIR		(1<<0) /* Input/Output Direction */

/* defines for variable CD1190_IO */
#define CD1190_CO		0x00
#define CD1190_CI		0x01
#define CD1190_PO		0x02
#define CD1190_PI		0x03

/* Interrupt Config Register */
#define CD1190_ICR		0x01
#define CD1190_ICR_ENABLE	(1<<7) /* Enable Interrupts */
#define CD1190_ICR_ACK		(1<<3) /* Enable: Unsolicited ACK */
#define CD1190_ICR_FIFO		(1<<2) /* Enable: FIFO Thresh/Time */
#define CD1190_ICR_SIGNAL	(1<<1) /* Enable: Signal Status */
#define CD1190_ICR_TIMER	(1<<0) /* Enable: Timer Expired */

/* Interrupt Status Register */
#define CD1190_ISR		0x0c
#define CD1190_ISR_INTERRUPT	(1<<7) /* Interrupt Has Occurred */
#define CD1190_ISR_ACK		(1<<3) /* Unsolicited ACK */
#define CD1190_ISR_FIFO		(1<<2) /* FIFO Thresh/Time */
#define CD1190_ISR_SIGNAL	(1<<1) /* Signal Status */
#define CD1190_ISR_TIMER	(1<<0) /* Timer Expired */

/* Interrupt Vector Register */
#define CD1190_IVR		0x00

/* Parallel Status Register */
#define CD1190_PSR		0x1c
#define CD1190_PSR_ENP		(1<<7) /* Parallel Enabled */
#define CD1190_PSR_BUSY		(1<<6) /* Parallel Busy */
#define CD1190_PSR_ACK		(1<<5) /* Parallel Acknowledge */
#define CD1190_PSR_STATUS	(CD1190_PSR_ENP | CD1190_PSR_BUSY)
#define CD1190_PSR_NORMAL	CD1190_PSR_ENP

/* Signal Control Register */
#define CD1190_SCR		0x1e
#define CD1190_SCR_WRRD		(1<<7) /* Read Only: Write/Read */
#define CD1190_SCR_IP3		(1<<6) /* Read Only: Input Line 3 */
#define CD1190_SCR_IP2		(1<<5) /* Read Only: Input Line 2 */
#define CD1190_SCR_IP1		(1<<4) /* Read Only: Input Line 1 */
#define CD1190_SCR_WR_WRRD	(1<<3) /* Write/Read */
#define CD1190_SCR_OP3		(1<<2) /* Output Line 3 */
#define CD1190_SCR_OP2		(1<<1) /* Output Line 2 */
#define CD1190_SCR_OP1		(1<<0) /* Output Line 1 */

/* Input signals
 *
 *	IP3 	-	*ERROR
 *	IP2 	-	PAPER EMPTY / FAULT
 *	IP1 	-	SELECT
 *	WRRD	-	AFD
 *	OP3 	-	SLIN
 *	OP2 	-	*INIT / *RESET
 *	OP1 	-	N/A
 */
#define CD1190_SCR_NOERROR	CD1190_SCR_IP3 /* Printer Error (active low) */
#define CD1190_SCR_PE		CD1190_SCR_IP2 /* Paper Empty */
#define CD1190_SCR_SELECT	CD1190_SCR_IP1 /* Printer Select */

#define CD1190_SCR_STATUS	(CD1190_SCR_IP3 | CD1190_SCR_IP2 | CD1190_SCR_IP1)

/* Outout signals - Active High?
 *
 *	IP3 	-	SLIN
 *	IP2 	-	*INIT / *RESET
 *	IP1 	-	N/A
 *	WRRD	-	AFD
 *	OP3 	-	*ERROR
 *	OP2 	-	SELECT
 *	OP1 	-	PAPER EMPTY / FAULT
 */
#define CD1190_SCR_RESET	CD1190_SCR_OP2
#define CD1190_SCR_SEL_IN	CD1190_SCR_OP3

/* Specification Register ZEROes */
#define CD1190_SR0		0x06
#define CD1190_SR0_WRRD		(1<<7) /* WR/RD 1 to 0 Change */
#define CD1190_SR0_IP3		(1<<6) /* IP3 1 to 0 Change */
#define CD1190_SR0_IP2		(1<<5) /* IP2 1 to 0 Change */
#define CD1190_SR0_IP1		(1<<4) /* IP1 1 to 0 Change */

/* Specification Register ONEs */
#define CD1190_SR1		0x07
#define CD1190_SR1_WRRD		(1<<7) /* WR/RD 0 to 1 Change */
#define CD1190_SR1_IP3		(1<<6) /* IP3 0 to 1 Change */
#define CD1190_SR1_IP2		(1<<5) /* IP2 0 to 1 Change */
#define CD1190_SR1_IP1		(1<<4) /* IP1 0 to 1 Change */

/* Signal Status Register */
#define CD1190_SSR		0x0d
#define CD1190_SSR_WRRD		(1<<7) /* WR/RD Change */
#define CD1190_SSR_IP3		(1<<6) /* IP3 Change */
#define CD1190_SSR_IP2		(1<<5) /* IP2 Change */
#define CD1190_SSR_IP1		(1<<4) /* IP1 Change */

/* Strobe Width Register */
#define CD1190_SWR		0x02

/* Timer Multipler Register */
#define CD1190_TMR		0x05

/* Timer Prescale Register */
#define CD1190_TPR		0x04


code:
/*	$OpenBSD: cd1400reg.h,v 1.4 1998/05/20 19:29:23 deraadt Exp $	*/
/*	$NetBSD: cd1400reg.h,v 1.3 1996/09/24 18:02:33 christos Exp $	*/

/*-
 * cyclades cyclom-y serial driver
 *	Andrew Herbert <andrew@werple.apana.org.au>, 17 August 1993
 *
 * Copyright (c) 1993 Andrew Herbert.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. The name Andrew Herbert may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY ``AS IS'' AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 * NO EVENT SHALL I BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/*
 * Definitions for Cirrus Logic CD1400 serial/parallel chips.
 */

#define	CD1400_NO_OF_CHANNELS	4	/* 4 serial channels per chip */
#define	CD1400_RX_FIFO_SIZE	12
#define	CD1400_TX_FIFO_SIZE	12
#define	CD1400_PAR_FIFO_SIZE	30

/*
 * Global registers.
 */
#define	CD1400_GFRCR		0x40	/* global firmware revision code */
#define	CD1400_CAR		0x68	/* channel access */
#define	CD1400_CAR_CHAN			(3<<0)	/* channel select */
#define	CD1400_GCR		0x4B	/* global configuration */
#define	CD1400_GCR_PARALLEL		(1<<7)	/* channel 0 is parallel */
#define	CD1400_SVRR		0x67	/* service request */
#define	CD1400_SVRR_MDMCH		(1<<2)
#define	CD1400_SVRR_TXRDY		(1<<1)
#define	CD1400_SVRR_RXRDY		(1<<0)
#define	CD1400_RICR		0x44	/* receive interrupting channel */
#define	CD1400_TICR		0x45	/* transmit interrupting channel */
#define	CD1400_MICR		0x46	/* modem interrupting channel */
#define	CD1400_RIR		0x6B	/* receive interrupt status */
#define	CD1400_RIR_RDIREQ		(1<<7)	/* rx service required */
#define	CD1400_RIR_RBUSY		(1<<6)	/* rx service in progress */
#define	CD1400_RIR_CHAN			(3<<0)	/* channel select */
#define	CD1400_TIR		0x6A	/* transmit interrupt status */
#define	CD1400_TIR_RDIREQ		(1<<7)	/* tx service required */
#define	CD1400_TIR_RBUSY		(1<<6)	/* tx service in progress */
#define	CD1400_TIR_CHAN			(3<<0)	/* channel select */
#define	CD1400_MIR		0x69	/* modem interrupt status */
#define	CD1400_MIR_RDIREQ		(1<<7)	/* modem service required */
#define	CD1400_MIR_RBUSY		(1<<6)	/* modem service in progress */
#define	CD1400_MIR_CHAN			(3<<0)	/* channel select */
#define	CD1400_PPR		0x7E	/* prescaler period */
#define	CD1400_PPR_PRESCALER		512

/*
 * Virtual registers.
 */
#define	CD1400_RIVR		0x43	/* receive interrupt vector */
#define	CD1400_RIVR_EXCEPTION		(1<<2)	/* receive exception bit */
#define	CD1400_TIVR		0x42	/* transmit interrupt vector */
#define	CD1400_MIVR		0x41	/* modem interrupt vector */
#define	CD1400_TDR		0x63	/* transmit data */
#define	CD1400_RDSR		0x62	/* receive data/status */
#define	CD1400_RDSR_TIMEOUT		(1<<7)	/* rx timeout */
#define	CD1400_RDSR_SPECIAL_SHIFT	4	/* rx special char shift */
#define	CD1400_RDSR_SPECIAL		(7<<4)	/* rx special char */
#define	CD1400_RDSR_BREAK		(1<<3)	/* rx break */
#define	CD1400_RDSR_PE			(1<<2)	/* rx parity error */
#define	CD1400_RDSR_FE			(1<<1)	/* rx framing error */
#define	CD1400_RDSR_OE			(1<<0)	/* rx overrun error */
#define	CD1400_MISR		0x4C	/* modem interrupt status */
#define	CD1400_MISR_DSRd		(1<<7)	/* DSR delta */
#define	CD1400_MISR_CTSd		(1<<6)	/* CTS delta */
#define	CD1400_MISR_RId			(1<<5)	/* RI delta */
#define	CD1400_MISR_CDd			(1<<4)	/* CD delta */
#define	CD1400_EOSRR		0x60	/* end of service request */

/*
 * Channel registers.
 */
#define	CD1400_LIVR		0x18	/* local interrupt vector */
#define	CD1400_CCR		0x05	/* channel control */
#define	CD1400_CCR_CMDRESET		(1<<7)	/* enables following: */
#define	CD1400_CCR_FTF				(1<<1)	/* flush tx fifo */
#define	CD1400_CCR_FULLRESET			(1<<0)	/* full reset */
#define	CD1400_CCR_CMDCORCHG		(1<<6)	/* enables following: */
#define	CD1400_CCR_COR3				(1<<3)	/* COR3 changed */
#define	CD1400_CCR_COR2				(1<<2)	/* COR2 changed */
#define	CD1400_CCR_COR1				(1<<1)	/* COR1 changed */
#define	CD1400_CCR_CMDSENDSC		(1<<5)	/* enables following: */
#define	CD1400_CCR_SC				(7<<0)	/* special char 1-4 */
#define	CD1400_CCR_CMDCHANCTL		(1<<4)	/* enables following: */
#define	CD1400_CCR_XMTEN			(1<<3)	/* tx enable */
#define	CD1400_CCR_XMTDIS			(1<<2)	/* tx disable */
#define	CD1400_CCR_RCVEN			(1<<1)	/* rx enable */
#define	CD1400_CCR_RCVDIS			(1<<0)	/* rx disable */
#define	CD1400_SRER		0x06	/* service request enable */
#define	CD1400_SRER_MDMCH		(1<<7)	/* modem change */
#define	CD1400_SRER_RXDATA		(1<<4)	/* rx data */
#define	CD1400_SRER_TXRDY		(1<<2)	/* tx fifo empty */
#define	CD1400_SRER_TXMPTY		(1<<1)	/* tx shift reg empty */
#define	CD1400_SRER_NNDT		(1<<0)	/* no new data */
#define	CD1400_COR1		0x08	/* channel option 1 */
#define	CD1400_COR1_PARODD		(1<<7)
#define	CD1400_COR1_PARNORMAL		(2<<5)
#define	CD1400_COR1_PARFORCE		(1<<5)	/* odd/even = force 1/0 */
#define	CD1400_COR1_PARNONE		(0<<5)
#define	CD1400_COR1_NOINPCK		(1<<4)
#define	CD1400_COR1_STOP2		(2<<2)
#define	CD1400_COR1_STOP15		(1<<2)	/* 1.5 stop bits */
#define	CD1400_COR1_STOP1		(0<<2)
#define	CD1400_COR1_CS8			(3<<0)
#define	CD1400_COR1_CS7			(2<<0)
#define	CD1400_COR1_CS6			(1<<0)
#define	CD1400_COR1_CS5			(0<<0)
#define	CD1400_COR2		0x09	/* channel option 2 */
#define	CD1400_COR2_IXANY		(1<<7)	/* implied XON mode */
#define	CD1400_COR2_IXOFF		(1<<6)	/* in-band tx flow control */
#define	CD1400_COR2_ETC			(1<<5)	/* embedded tx command */
#define	CD1400_COR2_LLM			(1<<4)	/* local loopback mode */
#define	CD1400_COR2_RLM			(1<<3)	/* remote loopback mode */
#define	CD1400_COR2_RTSAO		(1<<2)	/* RTS auto output */
#define	CD1400_COR2_CCTS_OFLOW		(1<<1)	/* CTS auto enable */
#define	CD1400_COR2_CDSR_OFLOW		(1<<0)	/* DSR auto enable */
#define	CD1400_COR3		0x0A	/* channel option 3 */
#define	CD1400_COR3_SCDRNG		(1<<7)	/* special char detect range */
#define	CD1400_COR3_SCD34		(1<<6)	/* special char detect 3-4 */
#define	CD1400_COR3_FTC			(1<<5)	/* flow control transparency */
#define	CD1400_COR3_SCD12		(1<<4)	/* special char detect 1-2 */
#define	CD1400_COR3_RXTH		(15<<0)	/* rx fifo threshold */
#define	CD1400_COR4		0x1E	/* channel option 4 */
#define	CD1400_COR4_IGNCR		(1<<7)
#define	CD1400_COR4_ICRNL		(1<<6)
#define	CD1400_COR4_INLCR		(1<<5)
#define	CD1400_COR4_IGNBRK		(1<<4)
#define	CD1400_COR4_NOBRKINT		(1<<3)
#define	CD1400_COR4_PFO_ESC		(4<<0)	/* parity/framing/overrun... */
#define	CD1400_COR4_PFO_NUL		(3<<0)
#define	CD1400_COR4_PFO_DISCARD		(2<<0)
#define	CD1400_COR4_PFO_GOOD		(1<<0)
#define	CD1400_COR4_PFO_EXCEPTION	(0<<0)
#define	CD1400_COR5		0x1F	/* channel option 5 */
#define	CD1400_COR5_ISTRIP		(1<<7)
#define	CD1400_COR5_LNEXT		(1<<6)
#define	CD1400_COR5_CMOE		(1<<5)	/* char matching on error */
#define	CD1400_COR5_EBD			(1<<2)	/* end of break detected */
#define	CD1400_COR5_ONLCR		(1<<1)
#define	CD1400_COR5_OCRNL		(1<<0)
#define	CD1400_CCSR		0x0B	/* channel control status */
#define	CD1400_RDCR		0x0E	/* received data count */
#define	CD1400_SCHR1		0x1A	/* special character 1 */
#define	CD1400_SCHR2		0x1B	/* special character 2 */
#define	CD1400_SCHR3		0x1C	/* special character 3 */
#define	CD1400_SCHR4		0x1D	/* special character 4 */
#define	CD1400_SCRL		0x22	/* special character range, low */
#define	CD1400_SCRH		0x23	/* special character range, high */
#define	CD1400_LNC		0x24	/* lnext character */
#define	CD1400_MCOR1		0x15	/* modem change option 1 */
#define	CD1400_MCOR1_DSRzd		(1<<7)	/* DSR one-to-zero delta */
#define	CD1400_MCOR1_CTSzd		(1<<6)
#define	CD1400_MCOR1_RIzd		(1<<5)
#define	CD1400_MCOR1_CDzd		(1<<4)
#define	CD1400_MCOR1_DTRth		(15<<0)	/* dtrflow threshold */
#define	CD1400_MCOR2		0x16	/* modem change option 2 */
#define	CD1400_MCOR2_DSRod		(1<<7)	/* DSR zero-to-one delta */
#define	CD1400_MCOR2_CTSod		(1<<6)
#define	CD1400_MCOR2_RIod		(1<<5)
#define	CD1400_MCOR2_CDod		(1<<4)
#define	CD1400_RTPR		0x21	/* receive timeout period */
#define	CD1400_MSVR1		0x6C	/* modem signal value 1 */
#define	CD1400_MSVR1_RTS		(1<<0)	/* RTS line (r/w) */
#define	CD1400_MSVR2		0x6D	/* modem signal value 2 */
#define	CD1400_MSVR2_DSR		(1<<7)	/* !DSR line (r) */
#define	CD1400_MSVR2_CTS		(1<<6)	/* !CTS line (r) */
#define	CD1400_MSVR2_RI			(1<<5)	/* !RI line (r) */
#define	CD1400_MSVR2_CD			(1<<4)	/* !CD line (r) */
#define	CD1400_MSVR2_DTR		(1<<1)	/* DTR line (r/w) */
#define	CD1400_PSVR		0x6F	/* printer signal value */
#define	CD1400_RBPR		0x78	/* receive baud rate period */
#define	CD1400_RCOR		0x7C	/* receive clock option */
#define	CD1400_TBPR		0x72	/* transmit baud rate period */
#define	CD1400_TCOR		0x76	/* transmit clock option */