code:
/*	$OpenBSD: arcbios.h,v 1.25 2015/02/06 22:11:49 miod Exp $	*/
/*-
 * Copyright (c) 1996 M. Warner Losh.  All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of the University nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */

#include <sys/types.h>

typedef struct arc_sid
{
	char vendor[8];
	char prodid[8];
} arc_sid_t;

typedef enum arc_config_class
{
	arc_SystemClass,
	arc_ProcessorClass,
	arc_CacheClass,
#ifdef __sgi__
	arc_MemoryClass,
#endif
	arc_AdapterClass,
	arc_ControllerClass,
	arc_PeripheralClass,
#ifdef __arc__
	arc_MemoryClass
#endif
} arc_config_class_t;

typedef enum arc_config_type
{
	arc_System,

	arc_CentralProcessor,
	arc_FloatingPointProcessor,

	arc_PrimaryIcache,
	arc_PrimaryDcache,
	arc_SecondaryIcache,
	arc_SecondaryDcache,
	arc_SecondaryCache,

#ifdef __sgi__
	arc_SystemMemory,
#endif

	arc_EisaAdapter,		/* Eisa adapter         */
	arc_TcAdapter,			/* Turbochannel adapter */
	arc_ScsiAdapter,		/* SCSI adapter         */
	arc_DtiAdapter,			/* AccessBus adapter    */
	arc_MultiFunctionAdapter,

	arc_DiskController,
	arc_TapeController,
	arc_CdromController,
	arc_WormController,
	arc_SerialController,
	arc_NetworkController,
	arc_DisplayController,
	arc_ParallelController,
	arc_PointerController,
	arc_KeyboardController,
	arc_AudioController,
	arc_OtherController,		/* denotes a controller not otherwise defined */

	arc_DiskPeripheral,
	arc_FloppyDiskPeripheral,
	arc_TapePeripheral,
	arc_ModemPeripheral,
	arc_MonitorPeripheral,
	arc_PrinterPeripheral,
	arc_PointerPeripheral,
	arc_KeyboardPeripheral,
	arc_TerminalPeripheral,
#ifdef __arc__
	arc_OtherPeripheral,		/* denotes a peripheral not otherwise defined   */
#endif
	arc_LinePeripheral,
	arc_NetworkPeripheral,
#ifdef __arc__
	arc_SystemMemory,
#endif
#ifdef __sgi__
	arc_OtherPeripheral,		/* denotes a peripheral not otherwise defined   */
#endif
} arc_config_type_t;

typedef u_int32_t arc_dev_flags_t;

#define	ARCBIOS_DEVFLAGS_FAILED		0x01
#define	ARCBIOS_DEVFLAGS_READONLY	0x02
#define	ARCBIOS_DEVFLAGS_REMOVABLE	0x04
#define	ARCBIOS_DEVFLAGS_CONSOLE_INPUT	0x08
#define	ARCBIOS_DEVFLAGS_CONSOLE_OUTPUT	0x10
#define	ARCBIOS_DEVFLAGS_INPUT		0x20
#define	ARCBIOS_DEVFLAGS_OUTPUT		0x40

typedef struct arc_config
{
	arc_config_class_t	class;
	arc_config_type_t	type;
	arc_dev_flags_t		flags;
	u_int16_t		version;
	u_int16_t		revision;
	u_int32_t		key;
	u_int32_t		affinity_mask;
	u_int32_t		config_data_len;
	u_int32_t		id_len;
	int32_t			id;
} arc_config_t;

typedef struct arc_config64
{
	arc_config_class_t	class;
	arc_config_type_t	type;
	arc_dev_flags_t		flags;
	u_int16_t		version;
	u_int16_t		revision;
	u_int64_t		key;
	u_int64_t		affinity_mask;
	u_int64_t		config_data_len;
	u_int64_t		id_len;
	int64_t			id;
} arc_config64_t;

typedef enum arc_status
{
	arc_ESUCCESS,			/* Success                   */
	arc_E2BIG,			/* Arg list too long         */
	arc_EACCES,			/* No such file or directory */
	arc_EAGAIN,			/* Try again                 */
	arc_EBADF,			/* Bad file number           */
	arc_EBUSY,			/* Device or resource busy   */
	arc_EFAULT,			/* Bad address               */
	arc_EINVAL,			/* Invalid argument          */
	arc_EIO,			/* I/O error                 */
	arc_EISDIR,			/* Is a directory            */
	arc_EMFILE,			/* Too many open files       */
	arc_EMLINK,			/* Too many links            */
	arc_ENAMETOOLONG,		/* File name too long        */
	arc_ENODEV,			/* No such device            */
	arc_ENOENT,			/* No such file or directory */
	arc_ENOEXEC,			/* Exec format error         */
	arc_ENOMEM,			/* Out of memory             */
	arc_ENOSPC,			/* No space left on device   */
	arc_ENOTDIR,			/* Not a directory           */
	arc_ENOTTY,			/* Not a typewriter          */
	arc_ENXIO,			/* No such device or address */
	arc_EROFS,			/* Read-only file system     */
} arc_status_t;

/*
 *	Oops! Arc systems and SGI's have different order of types.
 */
#ifdef __arc__
typedef enum {
	ExceptionBlock,		SystemParameterBlock,	FreeMemory,
	BadMemory,		LoadedProgram,		FirmwareTemporary,
	FirmwarePermanent,	FreeContigous
} MEMORYTYPE;
#endif

#ifdef __sgi__
typedef enum {
	ExceptionBlock,		SystemParameterBlock,	FreeContigous,
	FreeMemory,		BadMemory,		LoadedProgram,
	FirmwareTemporary,	FirmwarePermanent,
} MEMORYTYPE;
#endif

typedef struct arc_mem {
	MEMORYTYPE	Type;		/* Memory chunk type */
	u_int32_t	BasePage;	/* Page no, first page */
	u_int32_t	PageCount;	/* Number of pages */
} arc_mem_t;

typedef struct arc_mem64 {
	MEMORYTYPE	Type;		/* Memory chunk type */
	u_int64_t	BasePage;	/* Page no, first page */
	u_int64_t	PageCount;	/* Number of pages */
} arc_mem64_t;

typedef struct arc_time {
	u_int16_t	Year;
	u_int16_t	Month;
	u_int16_t	Day;
	u_int16_t	Hour;
	u_int16_t	Minutes;
	u_int16_t	Seconds;
	u_int16_t	Milliseconds;
} arc_time_t;

typedef struct arc_dsp_stat {
	u_int16_t	CursorXPosition;
	u_int16_t	CursorYPosition;
	u_int16_t	CursorMaxXPosition;
	u_int16_t	CursorMaxYPosition;
	u_char		ForegroundColor;
	u_char		BackgroundColor;
	u_char		HighIntensity;
	u_char		Underscored;
	u_char		ReverseVideo;
} arc_dsp_stat_t;

typedef caddr_t arc_dirent_t; /* XXX */
typedef u_int32_t arc_open_mode_t; /* XXX */
typedef u_int32_t arc_seek_mode_t; /* XXX */
typedef u_int32_t arc_mount_t; /* XXX */

typedef struct arc_quad {
#ifdef __MIPSEB__
	long	hi;
	u_long	lo;
#else
	u_long	lo;
	long	hi;
#endif
} arc_quad_t;

typedef struct arc_calls
{
	arc_status_t (*load)(		/* Load 1 */
		char *,			/* Image to load */
		u_long,			/* top address */
		u_long *,		/* Entry address */
		u_long *);		/* Low address */

	arc_status_t (*invoke)(		/* Invoke 2 */
		u_long,			/* Entry Address */
		u_long,			/* Stack Address */
		u_long,			/* Argc */
		char **,		/* argv */
		char **);		/* envp */

	arc_status_t (*execute)(	/* Execute 3 */
		char *,			/* Image path */
		u_long,			/* Argc */
		char **,		/* argv */
		char **);		/* envp */

	__dead void (*halt)(void);	/* Halt 4 */

	__dead void (*power_down)(void); /* PowerDown 5 */

	__dead void (*restart)(void);	/* Restart 6 */

	__dead void (*reboot)(void);	/* Reboot 7 */

	__dead void (*enter_interactive_mode)(void); /* EnterInteractiveMode 8 */

	__dead void (*return_from_main)(void); /* ReturnFromMain 9 */

	arc_config_t *(*get_peer)(	/* GetPeer 10 */
		arc_config_t *);	/* Component */

	arc_config_t *(*get_child)(	/* GetChild 11 */
		arc_config_t *);	/* Component */

	arc_config_t *(*get_parent)(	/* GetParent 12 */
		arc_config_t *);	/* Component */

	arc_status_t (*get_config_data)( /* GetConfigurationData 13 */
		caddr_t,		/* Configuration Data */
		arc_config_t *);	/* Component */

	arc_config_t *(*add_child)(	/* AddChild 14 */
		arc_config_t *,		/* Component */
		arc_config_t *);	/* New Component */

	arc_status_t (*delete_component)( /* DeleteComponent 15 */
		arc_config_t *);	/* Component */

	arc_config_t *(*get_component)( /* GetComponent 16 */
		char *);		/* Path */

	arc_status_t (*save_config)(void); /* SaveConfiguration 17 */

	arc_sid_t *(*get_system_id)(void); /* GetSystemId 18 */

	arc_mem_t *(*get_memory_descriptor)( /* GetMemoryDescriptor 19 */
		arc_mem_t *);		/* MemoryDescriptor */

#ifdef __arc__
	void (*signal)(			/* Signal 20 */
		u_int32_t,		/* Signal number */
/**/		caddr_t);		/* Handler */
#else
	void *unused;
#endif

	arc_time_t *(*get_time)(void);	/* GetTime 21 */

	u_long (*get_relative_time)(void); /* GetRelativeTime 22 */

	arc_status_t (*get_dir_entry)(	/* GetDirectoryEntry 23 */
		u_long,			/* FileId */
		arc_dirent_t *,		/* Directory entry */
		u_long,			/* Length */
		u_long *);		/* Count */

	arc_status_t (*open)(		/* Open 24 */
		char *,			/* Path */
		arc_open_mode_t,	/* Open mode */
		u_long *);		/* FileId */

	arc_status_t (*close)(		/* Close 25 */
		u_long);		/* FileId */

	arc_status_t (*read)(		/* Read 26 */
		u_long,			/* FileId */
		caddr_t,		/* Buffer */
		u_long,			/* Length */
		u_long *);		/* Count */

	arc_status_t (*get_read_status)( /* GetReadStatus 27 */
		u_long);		/* FileId */

	arc_status_t (*write)(		/* Write 28 */
		u_long,			/* FileId */
		caddr_t,		/* Buffer */
		u_long,			/* Length */
		u_long *);		/* Count */

	arc_status_t (*seek)(		/* Seek 29 */
		u_long,			/* FileId */
		arc_quad_t *,		/* Offset */
		arc_seek_mode_t);	/* Mode */

	arc_status_t (*mount)(		/* Mount 30 */
		char *,			/* Path */
		arc_mount_t);		/* Operation */

	char *(*getenv)(			/* GetEnvironmentVariable 31 */
		char *);		/* Variable */

	arc_status_t (*putenv)(		/* SetEnvironmentVariable 32 */
		char *,			/* Variable */
		char *);		/* Value */

	arc_status_t (*get_file_info)(void);	/* GetFileInformation 33 */

	arc_status_t (*set_file_info)(void);	/* SetFileInformation 34 */

	void (*flush_all_caches)(void);	/* FlushAllCaches 35 */

#ifdef __arc__
	arc_status_t (*test_unicode)(	/* TestUnicodeCharacter 36 */
		u_int32_t,		/* FileId */
		u_int16_t);		/* UnicodeCharacter */

	arc_dsp_stat_t *(*get_display_status)( /* GetDisplayStatus 37 */
		u_int32_t);		/* FileId */
#endif
} arc_calls_t;

#define ARC_PARAM_BLK_MAGIC	0x53435241
#define ARC_PARAM_BLK_MAGIC_BUG	0x41524353	/* This is wrong... but req */

typedef struct arc_param_blk_32
{
	u_int32_t	magic;		/* Magic Number */
	u_int32_t	length;		/* Length of parameter block */
	u_int16_t	version;	/* ?? */
	u_int16_t	revision;	/* ?? */
	int32_t		restart_block;	/* ?? */
	int32_t		debug_block;	/* Debugging info -- unused */
	int32_t		general_exp_vect; /* ?? */
	int32_t		tlb_miss_exp_vect; /* ?? */
	u_int32_t	firmware_length; /* Size of Firmware jumptable in bytes */
	int32_t		firmware_vect;	/* Firmware jumptable */
	int32_t		vendor_length;	/* Size of Vendor specific jumptable */
	u_int32_t	vendor_vect;	/* Vendor specific jumptable */
	u_int32_t	adapter_count;	/* ?? */
	u_int32_t	adapter0_type;	/* ?? */
	u_int32_t	adapter0_length; /* ?? */
	int32_t		adapter0_vect;	/* ?? */
} arc_param_blk_32_t;

typedef struct arc_param_blk_64
{
	u_int64_t	magic;		/* Magic Number */
	u_int64_t	length;		/* Length of parameter block */
	u_int16_t	version;	/* ?? */
	u_int16_t	revision;	/* ?? */
	int64_t		restart_block;	/* ?? */
	int64_t		debug_block;	/* Debugging info -- unused */
	int64_t		general_exp_vect; /* ?? */
	int64_t		tlb_miss_exp_vect; /* ?? */
	u_int64_t	firmware_length; /* Size of Firmware jumptable in bytes */
	int64_t		firmware_vect;	/* Firmware jumptable */
	u_int64_t	vendor_length;	/* Size of Vendor specific jumptable */
	int64_t		vendor_vect;	/* Vendor specific jumptable */
	u_int64_t	adapter_count;	/* ?? */
	u_int64_t	adapter0_type;	/* ?? */
	u_int64_t	adapter0_length; /* ?? */
	int64_t		adapter0_vect;	/* ?? */
} arc_param_blk_64_t;

#define	ARCBIOS_BASE	0x0000001000	/* physical */
extern void *bios_base;
#define	ArcBiosBase32	((arc_param_blk_32_t *)bios_base)
#define	ArcBiosBase64	((arc_param_blk_64_t *)bios_base)

#define	ARCBIOS_PAGE_SIZE	4096

extern int bios_is_32bit;
extern int bios_consrate;
extern char bios_enaddr[20];
extern char bios_console[30];
extern char bios_graphics[6];
extern char bios_keyboard[6];

extern void (*bios_halt)(void);
extern void (*bios_powerdown)(void);
extern void (*bios_restart)(void);
extern void (*bios_reboot)(void);
extern void (*bios_eim)(void);

int  bios_getchar(void);
void bios_putchar(char);
void bios_putstring(char *);
void bios_printf(const char *, ...)
    __attribute__((__format__(__kprintf__,1,2)));
void bios_ident(void);
void bios_display_info(int *, int *, int *, int *);

/*
 * Direct ARC-BIOS calls.
 */
long Bios_Load(char *, u_long, u_long, u_long *);
long Bios_Invoke(u_long, u_long, u_long, char **, char **);
long Bios_Execute(char *, u_long, char **, char **);
void Bios_Halt(void);
void Bios_PowerDown(void);
void Bios_Restart(void);
void Bios_Reboot(void);
void Bios_EnterInteractiveMode(void);
long Bios_GetPeer(void *);
arc_config_t *Bios_GetChild(void *);
long Bios_GetParent(void *);
long Bios_GetConfigurationData(void *, void *);
long Bios_AddChild(void *, void *);
long Bios_DeleteComponent(void *);
long Bios_GetComponent(char *);
long Bios_SaveConfiguration(void);
arc_sid_t *Bios_GetSystemId(void);
arc_mem_t *Bios_GetMemoryDescriptor(void *);
arc_time_t *Bios_GetTime(void);
long Bios_GetRelativeTime(void);
long Bios_GetDirectoryEntry(u_long, void *, u_long, u_long *);
long Bios_Open(char *, int, long *);
long Bios_Close(long);
long Bios_Read(long, char *, long, long *);
long Bios_GetReadStatus(u_long);
long Bios_Write(long, char *, long, long *);
long Bios_Seek(long, arc_quad_t *, int);
long Bios_Mount(char *, void *);
char *Bios_GetEnvironmentVariable(const char *);
long Bios_SetEnvironmentVariable(char *, char *);
long Bios_GetFileInformation(u_long, u_long, u_long);
long Bios_SetFileInformation(u_long, u_long, u_long);
void Bios_FlushAllCaches(void);
long Bios_TestUnicodeCharacter(u_long, u_int16_t);
arc_dsp_stat_t *Bios_GetDisplayStatus(u_long);


code:
/*	$OpenBSD: archtype.h,v 1.16 2012/10/03 21:44:51 miod Exp $	*/
/*
 * Copyright (c) 1997-2004 Opsycon AB, Sweden (www.opsycon.se)
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 */

#ifndef _MIPS64_ARCHTYPE_H_
#define _MIPS64_ARCHTYPE_H_
/*
 * Define architectural identities for the different Mips machines.
 */
#define	ACER_PICA_61		0x0001	/* Acer Labs Pica 61 */
#define	MAGNUM			0x0002	/* Mips MAGNUM R4000 */
#define	DESKSTATION_RPC44	0x0003	/* Deskstation rPC44 */
#define	DESKSTATION_TYNE	0x0004	/* Deskstation Tyne */
#define	NKK_AQUARIUS		0x0005	/* NKK R4{67}00 PC */
#define NEC_R94			0x0006	/* NEC Magnum class */
#define	SNI_RM200		0x0007	/* Siemens Nixdorf RM200 */

#define	SGI_IP17		0x0011	/* Crimson */
#define	SGI_IP19		0x0012	/* Onyx (!S model Challenge) */
#define	SGI_IP20		0x0013	/* Indigo */
#define	SGI_IP21		0x0014	/* POWER Challenge, POWER Onyx */
#define	SGI_IP22		0x0015	/* Indy, Indigo2, Challenge S */
#define	SGI_IP25		0x0016	/* POWER Challenge R10k */
#define	SGI_IP26		0x0017	/* POWER Indigo2 R8k */
#define	SGI_IP27		0x0018	/* IP27 Origin200/2000 */
#define	SGI_IP28		0x0019	/* POWER Indigo2 R10k */
#define	SGI_OCTANE		0x001a	/* IP30 Octane */
#define	SGI_O2			0x001b	/* IP32 O2  */
#define	SGI_IP35		0x001c	/* IP35 Origin3x0/3x00/Fuel/Tezro */

#define	ALGOR_P4032		0x0021	/* ALGORITHMICS P-4032 */
#define	ALGOR_P5064		0x0022	/* ALGORITHMICS P-5064 */

#define	GALILEO_G9		0x0031	/* Galileo GT-64011 Eval board */
#define GALILEO_EV64240		0x0032	/* Galileo EV64240 Eval board */
#define GALILEO_EV64340		0x0033	/* Galileo EV64340 Eval board */

#define	MOMENTUM_CP7000		0x0041	/* Momentum Ocelot */
#define	MOMENTUM_CP7000G	0x0042	/* Momentum Ocelot-G */
#define	MOMENTUM_JAGUAR		0x0043	/* Momentum Jaguar ATX */

#define	WG4308			0x0052	/* Willowglen 4308 LMD */
#define	WG4309			0x0053	/* Willowglen 4309 LMD */
#define	WG4409			0x0054	/* Willowglen 4409 LMD */
#define	WG8138			0x0055	/* Willowglen 8138 523x VME card */
#define	WG8168			0x0056	/* Willowglen 8168 5231 VME card */
#define	WG6000			0x0057	/* Willowglen CPU-6000 */
#define	WG7000			0x0058	/* Willowglen CPU-7000 */
#define	WG8200			0x0059	/* Willowglen CPU-8200 */
#define	WG8232			0x005a	/* Willowglen CPU-8232 */

#define	LAGUNA			0x00f1	/* Heurikon Laguna VME board */

#endif /* !_MIPS64_ARCHTYPE_H_ */

license: unknown


code:
/*	$OpenBSD: asm.h,v 1.21 2014/03/14 16:57:21 miod Exp $ */

/*
 * Copyright (c) 2001-2002 Opsycon AB  (www.opsycon.se / www.opsycon.com)
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 */
#ifndef _MIPS64_ASM_H_
#define _MIPS64_ASM_H_

#include <machine/regdef.h>

#define	_MIPS_ISA_MIPS1	1	/* R2000/R3000 */
#define	_MIPS_ISA_MIPS2	2	/* R4000/R6000 */
#define	_MIPS_ISA_MIPS3	3	/* R4000 */
#define	_MIPS_ISA_MIPS4	4	/* TFP (R1x000) */

#if !defined(ABICALLS) && !defined(_NO_ABICALLS)
#define	ABICALLS	.abicalls
#endif

#if defined(ABICALLS) && !defined(_KERNEL)
	ABICALLS
#endif

#define _C_LABEL(x) x		/* XXX Obsolete but keep for a while */

#if !defined(__MIPSEL__) && !defined(__MIPSEB__)
#error "__MIPSEL__ or __MIPSEB__ must be defined"
#endif
/*
 * Define how to access unaligned data word
 */
#if defined(__MIPSEL__)
#define LWLO    lwl
#define LWHI    lwr
#define	SWLO	swl
#define	SWHI	swr
#define LDLO    ldl
#define LDHI    ldr
#define	SDLO	sdl
#define	SDHI	sdr
#endif
#if defined(__MIPSEB__)
#define LWLO    lwr
#define LWHI    lwl
#define	SWLO	swr
#define	SWHI	swl
#define LDLO    ldr
#define LDHI    ldl
#define	SDLO	sdr
#define	SDHI	sdl
#endif

/*
 *  Define programming environment for ABI.
 */
#if defined(ABICALLS) && !defined(_KERNEL) && !defined(_STANDALONE)

#ifndef _MIPS_SIM
#define _MIPS_SIM 1
#define _ABIO32	1
#endif
#ifndef _MIPS_ISA
#define _MIPS_ISA 2
#define _MIPS_ISA_MIPS2 2
#endif

#if (_MIPS_SIM == _ABIO32) || (_MIPS_SIM == _ABI32)
#define NARGSAVE	4

#define	SETUP_GP		\
	.set	noreorder;	\
	.cpload	t9;		\
	.set	reorder;

#define	SAVE_GP(x)		\
	.cprestore x

#define	SETUP_GP64(gpoff, name)
#define	RESTORE_GP64
#endif

#if (_MIPS_SIM == _ABI64) || (_MIPS_SIM == _ABIN32)
#define NARGSAVE	0

#define	SETUP_GP
#define	SAVE_GP(x)
#define	SETUP_GP64(gpoff, name)	\
	.cpsetup t9, gpoff, name
#define	RESTORE_GP64		\
	.cpreturn
#endif

#define	MKFSIZ(narg,locals) (((narg+locals)*REGSZ+31)&(~31))

#else /* defined(ABICALLS) && !defined(_KERNEL) */

#define	NARGSAVE	4
#define	SETUP_GP
#define	SAVE_GP(x)

#define	ALIGNSZ		16	/* Stack layout alignment */
#define	FRAMESZ(sz)	(((sz) + (ALIGNSZ-1)) & ~(ALIGNSZ-1))

#endif

/*
 *  Basic register operations based on selected ISA
 */
#if (_MIPS_ISA == _MIPS_ISA_MIPS1 || _MIPS_ISA == _MIPS_ISA_MIPS2)
#define REGSZ		4	/* 32 bit mode register size */
#define LOGREGSZ	2	/* log rsize */
#define	REG_S	sw
#define	REG_L	lw
#define	CF_SZ		24	/* Call frame size */
#define	CF_ARGSZ	16	/* Call frame arg size */
#define	CF_RA_OFFS	20	/* Call ra save offset */
#endif

#if (_MIPS_ISA == _MIPS_ISA_MIPS3 || _MIPS_ISA == _MIPS_ISA_MIPS4)
#define REGSZ		8	/* 64 bit mode register size */
#define LOGREGSZ	3	/* log rsize */
#define	REG_S	sd
#define	REG_L	ld
#define	CF_SZ		48	/* Call frame size (multiple of ALIGNSZ) */
#define	CF_ARGSZ	32	/* Call frame arg size */
#define	CF_RA_OFFS	40	/* Call ra save offset */
#endif

#ifndef __LP64__
#define	PTR_L		lw
#define	PTR_S		sw
#define	PTR_SUB		sub
#define	PTR_ADD		add
#define	PTR_SUBU	subu
#define	PTR_ADDU	addu
#define LI		li
#define	LA		la
#define	PTR_SLL		sll
#define	PTR_SRL		srl
#define	PTR_VAL		.word
#else
#define	PTR_L		ld
#define	PTR_S		sd
#define	PTR_ADD		dadd
#define	PTR_SUB		dsub
#define	PTR_SUBU	dsubu
#define	PTR_ADDU	daddu
#define LI		dli
#define LA		dla
#define	PTR_SLL		dsll
#define	PTR_SRL		dsrl
#define	PTR_VAL		.dword
#endif

/*
 * The following macros are here to benefit the R8000 processor:
 * - all coprocessor 0 control registers are 64-bit
 * - the regular nop (sll zero, zero, 0) has the drawback of using the
 *   shifter, potentially breaking instruction dispatch if occuring after
 *   another instruction using the shifter.
 */
#ifdef CPU_R8000
#define	SSNOP	sll zero, zero, 1		/* ``ssnop'' */
#define	NOP	PTR_ADDU zero, zero, zero	/* real nop for R8000 */
#define	DMFC0	SSNOP; dmfc0
#define	DMTC0	SSNOP; dmtc0
#define	MFC0	SSNOP; dmfc0
#define	MTC0	SSNOP; dmtc0
#define	ERET	eret; mul k0, k0; mflo k0
#else
#define	NOP	nop
#define	DMFC0	dmfc0
#define	DMTC0	dmtc0
#define	MFC0	mfc0
#define	MTC0	mtc0
#define	ERET	sync; eret
#endif

/*
 * Define -pg profile entry code.
 */
#if defined(XGPROF) || defined(XPROF)
#define	MCOUNT			\
	PTR_SUBU sp, sp, 64;	\
	SAVE_GP(16);		\
	sd	ra, 56(sp);	\
	sd	gp, 48(sp);	\
	.set	noat;		\
	.set	noreorder;	\
	move	AT, ra;		\
	jal	_mcount;	\
	PTR_SUBU sp, sp, 16;	\
	ld	ra, 56(sp);	\
	PTR_ADDU sp, sp, 64;	\
	.set reorder;		\
	.set	at;
#else
#define	MCOUNT
#endif

/*
 * LEAF(x, fsize)
 *
 *	Declare a leaf routine.
 */
#define LEAF(x, fsize)		\
	.align	3;		\
	.globl x;		\
	.ent x, 0;		\
x: ;				\
	.frame sp, fsize, ra;	\
	SETUP_GP		\
	MCOUNT

#define	ALEAF(x)		\
	.globl	x;		\
x:

/*
 * NLEAF(x)
 *
 *	Declare a non-profiled leaf routine.
 */
#define NLEAF(x, fsize)		\
	.align	3;		\
	.globl x;		\
	.ent x, 0;		\
x: ;				\
	.frame sp, fsize, ra;	\
	SETUP_GP

/*
 * NON_LEAF(x)
 *
 *	Declare a non-leaf routine (a routine that makes other C calls).
 */
#define NON_LEAF(x, fsize, retpc) \
	.align	3;		\
	.globl x;		\
	.ent x, 0;		\
x: ;				\
	.frame sp, fsize, retpc; \
	SETUP_GP		\
	MCOUNT

/*
 * NNON_LEAF(x)
 *
 *	Declare a non-profiled non-leaf routine
 *	(a routine that makes other C calls).
 */
#define NNON_LEAF(x, fsize, retpc) \
	.align	3;		\
	.globl x;		\
	.ent x, 0;		\
x: ;				\
	.frame sp, fsize, retpc	\
	SETUP_GP

/*
 * END(x)
 *
 *	Mark end of a procedure.
 */
#define END(x) \
	.end x

/*
 * STRONG_ALIAS, WEAK_ALIAS
 *	Create a strong or weak alias.
 */
#define STRONG_ALIAS(alias,sym) \
	.global alias; alias = sym
#define WEAK_ALIAS(alias,sym) \
	.weak alias; alias = sym

/*
 * Macros to panic and printf from assembly language.
 */
#define PANIC(msg) \
	LA	a0, 9f; \
	jal	panic;	\
	nop	;	\
	MSG(msg)

#define	PRINTF(msg) \
	LA	a0, 9f; \
	jal	printf; \
	nop	;	\
	MSG(msg)

#define	MSG(msg) \
	.rdata; \
9:	.asciiz	msg; \
	.text

#define ASMSTR(str) \
	.asciiz str; \
	.align	3

#define	LOAD_XKPHYS(reg, cca) \
	li	reg, cca | 0x10; \
	dsll	reg, reg, 59

#ifdef MULTIPROCESSOR
#define GET_CPU_INFO(ci, tmp)	HW_GET_CPU_INFO(ci, tmp)
#else  /* MULTIPROCESSOR */
#define GET_CPU_INFO(ci, tmp)		\
	LA	ci, cpu_info_primary
#endif /* MULTIPROCESSOR */

/*
 * Hazards
 */

#ifdef CPU_RM7000
/*
 * Due to a flaw in RM7000 1.x processors a pipeline 'drain' is
 * required after some mtc0 instructions.
 * Ten nops in sequence does the trick.
 */
#define	MTC0_HAZARD		NOP;NOP;NOP;NOP;NOP;NOP;NOP;NOP;NOP;NOP
#define	MTC0_SR_IE_HAZARD	MTC0_HAZARD
/*
 * The RM7000 needs twice as much nops around tlb* instructions.
 */
#define	TLB_HAZARD		NOP; NOP; NOP; NOP
#endif

#ifdef CPU_R8000
/*
 * The R8000 needs a lot of care inserting proper superscalar dispatch breaks
 * to prevent unwanted side-effects or avoid collisions on the internal MiscBus
 * and the E and W stages of the pipelines.
 *
 * The following settings are a bit pessimistic, but better run safely than
 * not at all.
 */
#define	PRE_MFC0_ADDR_HAZARD	.align 5; SSNOP
#define	MFC0_HAZARD		SSNOP
#define	MTC0_HAZARD		SSNOP; SSNOP; SSNOP
#define	MTC0_SR_IE_HAZARD	MTC0_HAZARD; SSNOP
#define	MTC0_SR_CU_HAZARD	MTC0_HAZARD; SSNOP
#endif

/* Hazard between {d,}mfc0 of COP_0_VADDR */
#ifndef	PRE_MFC0_ADDR_HAZARD
#define	PRE_MFC0_ADDR_HAZARD	/* nothing */
#endif

/* Hazard after {d,}mfc0 from any register */
#ifndef	MFC0_HAZARD
#define	MFC0_HAZARD     	/* nothing */
#endif
/* Hazard after {d,}mtc0 to any register */
#ifndef	MTC0_HAZARD
#define	MTC0_HAZARD     	NOP; NOP; NOP; NOP
#endif
/* Hazard after {d,}mtc0 to COP_0_SR affecting the state of interrupts */
#ifndef	MTC0_SR_IE_HAZARD
#define	MTC0_SR_IE_HAZARD	MTC0_HAZARD
#endif
/* Hazard after {d,}mtc0 to COP_0_SR affecting the state of coprocessors */
#ifndef	MTC0_SR_CU_HAZARD
#define	MTC0_SR_CU_HAZARD	NOP; NOP
#endif

/* Hazard before and after a tlbp, tlbr, tlbwi or tlbwr instruction */
#ifndef	TLB_HAZARD
#define	TLB_HAZARD		NOP; NOP
#endif

#endif /* !_MIPS64_ASM_H_ */


code:
/*	$OpenBSD: atomic.h,v 1.10 2015/02/10 23:54:09 dlg Exp $	*/

/* Public Domain */

#ifndef _MIPS64_ATOMIC_H_
#define _MIPS64_ATOMIC_H_

#if defined(_KERNEL)

/* wait until the bits to set are clear, and set them */
static __inline void
atomic_wait_and_setbits_int(volatile unsigned int *uip, unsigned int v)
{
	unsigned int tmp0, tmp1;

	__asm__ volatile (
	"1:	ll	%0,	0(%2)\n"
	"	and	%1,	%0,	%3\n"
	"	bnez	%1,	1b\n"
	"	or	%0,	%3,	%0\n"
	"	sc	%0,	0(%2)\n"
	"	beqz	%0,	1b\n"
	"	 nop\n" :
		"=&r"(tmp0), "=&r"(tmp1) :
		"r"(uip), "r"(v) : "memory");
}

static __inline void
atomic_setbits_int(volatile unsigned int *uip, unsigned int v)
{
	unsigned int tmp;

	__asm__ volatile (
	"1:	ll	%0,	0(%1)\n"
	"	or	%0,	%2,	%0\n"
	"	sc	%0,	0(%1)\n"
	"	beqz	%0,	1b\n"
	"	 nop\n" :
		"=&r"(tmp) :
		"r"(uip), "r"(v) : "memory");
}

static __inline void
atomic_clearbits_int(volatile unsigned int *uip, unsigned int v)
{
	unsigned int tmp;

	__asm__ volatile (
	"1:	ll	%0,	0(%1)\n"
	"	and	%0,	%2,	%0\n"
	"	sc	%0,	0(%1)\n"
	"	beqz	%0,	1b\n"
	"	 nop\n" :
		"=&r"(tmp) :
		"r"(uip), "r"(~v) : "memory");
}

static inline unsigned int
_atomic_cas_uint(volatile unsigned int *p, unsigned int o, unsigned int n)
{
	unsigned int rv, wv;

	__asm__ volatile (
	"1:	ll	%0,	%1\n"
	"	bne	%0,	%4,	2f\n"
	"	move	%2,	%3\n"
	"	sc	%2,	%1\n"
	"	beqz	%2,	1b\n"
	"2:	nop\n"
	    : "=&r" (rv), "+m" (*p), "=&r" (wv)
	    : "r" (n), "Ir" (o));

	return (rv);
}
#define atomic_cas_uint(_p, _o, _n) _atomic_cas_uint((_p), (_o), (_n))

static inline unsigned long
_atomic_cas_ulong(volatile unsigned long *p, unsigned long o, unsigned long n)
{
	unsigned long rv, wv;

	__asm__ volatile (
	"1:	lld	%0,	%1\n"
	"	bne	%0,	%4,	2f\n"
	"	move	%2,	%3\n"
	"	scd	%2,	%1\n"
	"	beqz	%2,	1b\n"
	"2:	nop\n"
	    : "=&r" (rv), "+m" (*p), "=&r" (wv)
	    : "r" (n), "Ir" (o));

	return (rv);
}
#define atomic_cas_ulong(_p, _o, _n) _atomic_cas_ulong((_p), (_o), (_n))

static inline void *
_atomic_cas_ptr(volatile void *pp, void *o, void *n)
{
	void * volatile *p = pp;
	void *rv, *wv;

	__asm__ volatile (
	"1:	lld	%0,	%1\n"
	"	bne	%0,	%4,	2f\n"
	"	move	%2,	%3\n"
	"	scd	%2,	%1\n"
	"	beqz	%2,	1b\n"
	"2:	nop\n"
	    : "=&r" (rv), "+m" (*p), "=&r" (wv)
	    : "r" (n), "Ir" (o));

	return (rv);
}
#define atomic_cas_ptr(_p, _o, _n) _atomic_cas_ptr((_p), (_o), (_n))

static inline unsigned int
_atomic_swap_uint(volatile unsigned int *uip, unsigned int v)
{
	unsigned int o, t;

	__asm__ volatile (
	"1:	ll	%0,	%1\n"
	"	move	%2,	%3\n"
	"	sc	%2,	%1\n"
	"	beqz	%2,	1b\n"
	"	nop\n"
	    : "=&r" (o), "+m" (*uip), "=&r" (t)
	    : "r" (v));

	return (o);
}
#define atomic_swap_uint(_p, _v) _atomic_swap_uint((_p), (_v))

static inline unsigned long
_atomic_swap_ulong(volatile unsigned long *uip, unsigned long v)
{
	unsigned long o, t;

	__asm__ volatile (
	"1:	lld	%0,	%1\n"
	"	move	%2,	%3\n"
	"	scd	%2,	%1\n"
	"	beqz	%2,	1b\n"
	"	nop\n"
	    : "=&r" (o), "+m" (*uip), "=&r" (t)
	    : "r" (v));

	return (o);
}
#define atomic_swap_ulong(_p, _v) _atomic_swap_ulong((_p), (_v))

static inline void *
_atomic_swap_ptr(volatile void *uipp, void *n)
{
	void * volatile *uip = uipp;
	void *o, *t;

	__asm__ volatile (
	"1:	lld	%0,	%1\n"
	"	move	%2,	%3\n"
	"	scd	%2,	%1\n"
	"	beqz	%2,	1b\n"
	"	nop\n"
	    : "=&r" (o), "+m" (*uip), "=&r" (t)
	    : "r" (n));

	return (o);
}
#define atomic_swap_ptr(_p, _n) _atomic_swap_ptr((_p), (_n))

static inline unsigned int
_atomic_add_int_nv(volatile unsigned int *uip, unsigned int v)
{
	unsigned int rv, nv;

	__asm__ volatile (
	"1:	ll	%0,	%1\n"
	"	addu	%2,	%0,	%3\n"
	"	sc	%2,	%1\n"
	"	beqz	%2,	1b\n"
	"	nop\n"
	    : "=&r" (rv), "+m" (*uip), "=&r" (nv)
	    : "Ir" (v));

	return (rv + v);
}
#define atomic_add_int_nv(_uip, _v) _atomic_add_int_nv((_uip), (_v))
#define atomic_sub_int_nv(_uip, _v) _atomic_add_int_nv((_uip), 0 - (_v))

static inline unsigned long
_atomic_add_long_nv(volatile unsigned long *uip, unsigned long v)
{
	unsigned long rv, nv;

	__asm__ volatile (
	"1:	lld	%0,	%1\n"
	"	daddu	%2,	%0,	%3\n"
	"	scd	%2,	%1\n"
	"	beqz	%2,	1b\n"
	"	nop\n"
	    : "=&r" (rv), "+m" (*uip), "=&r" (nv)
	    : "Ir" (v));

	return (rv + v);
}
#define atomic_add_long_nv(_uip, _v) _atomic_add_long_nv((_uip), (_v))
#define atomic_sub_long_nv(_uip, _v) _atomic_add_long_nv((_uip), 0 - (_v))

#endif /* defined(_KERNEL) */
#endif /* _MIPS64_ATOMIC_H_ */


code:
/*	$OpenBSD: autoconf.h,v 1.1 2010/01/09 20:33:16 miod Exp $	*/

/*
 * Copyright (c) 2010 Miodrag Vallat.
 *
 * Permission to use, copy, modify, and distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

/*
 * Common defines used by autoconf on all mips64-based platforms.
 */

#ifndef	_MIPS64_AUTOCONF_H_
#define	_MIPS64_AUTOCONF_H_

#include <machine/cpu.h>		/* for struct cpu_hwinfo */

struct cpu_attach_args {
	struct mainbus_attach_args	 caa_maa;
	struct cpu_hwinfo		*caa_hw;
};

extern struct cpu_hwinfo bootcpu_hwinfo;

#endif /* _MIPS64_AUTOCONF_H_ */


code:
/*	$OpenBSD: cache.h,v 1.6 2014/03/31 20:21:19 miod Exp $	*/

/*
 * Copyright (c) 2012 Miodrag Vallat.
 *
 * Permission to use, copy, modify, and distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#ifndef	_MIPS64_CACHE_H_
#define	_MIPS64_CACHE_H_

/*
 * Declare canonical cache functions for a given processor.
 *
 * The following assumptions are made:
 * - only L1 has split instruction and data caches.
 * - L1 I$ is virtually indexed.
 *
 * Processor-specific routines will make extra assumptions.
 */

#define CACHE_PROTOS(chip) \
/* Figure out cache configuration */ \
void	chip##_ConfigCache(struct cpu_info *); \
/* Writeback and invalidate all caches */ \
void  	chip##_SyncCache(struct cpu_info *); \
/* Invalidate all I$ for the given range */ \
void	chip##_InvalidateICache(struct cpu_info *, vaddr_t, size_t); \
/* Register a given page for I$ invalidation */ \
void	chip##_InvalidateICachePage(struct cpu_info *, vaddr_t); \
/* Perform postponed I$ invalidation */ \
void	chip##_SyncICache(struct cpu_info *); \
/* Writeback all D$ for the given page */ \
void	chip##_SyncDCachePage(struct cpu_info *, vaddr_t, paddr_t); \
/* Writeback all D$ for the given range */ \
void	chip##_HitSyncDCache(struct cpu_info *, vaddr_t, size_t); \
/* Invalidate all D$ for the given range */ \
void	chip##_HitInvalidateDCache(struct cpu_info *, vaddr_t, size_t); \
/* Enforce coherency of the given range */ \
void	chip##_IOSyncDCache(struct cpu_info *, vaddr_t, size_t, int);

/*
 * Cavium Octeon.
 */
CACHE_PROTOS(Octeon)

/*
 * STC Loongson 2E and 2F.
 */
CACHE_PROTOS(Loongson2)

/*
 * MIPS R4000 and R4400.
 */
CACHE_PROTOS(Mips4k)

/*
 * IDT/QED/PMC-Sierra R4600, R4700, R5000, RM52xx, RM7xxx, RM9xxx.
 */
CACHE_PROTOS(Mips5k)

/*
 * MIPS (SGI, really) R8000.
 */
CACHE_PROTOS(tfp)

/*
 * MIPS/NEC R10000/R120000/R140000/R16000.
 */
CACHE_PROTOS(Mips10k)

/*
 * Values used by the IOSyncDCache routine [which acts as the backend of
 * bus_dmamap_sync()].
 */
#define	CACHE_SYNC_R	0	/* WB invalidate, WT invalidate */
#define	CACHE_SYNC_W	1	/* WB writeback, WT unaffected */
#define	CACHE_SYNC_X	2	/* WB writeback + invalidate, WT invalidate */

extern vaddr_t cache_valias_mask;

#endif	/* _MIPS64_CACHE_H_ */


code:
/*	$OpenBSD: cdefs.h,v 1.6 2013/03/28 17:30:45 martynas Exp $	*/

/*
 * Copyright (c) 2002-2003 Opsycon AB  (www.opsycon.se / www.opsycon.com)
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 */

#ifndef _MIPS64_CDEFS_H_
#define	_MIPS64_CDEFS_H_

#define __strong_alias(alias,sym)			\
	__asm__(".global " __STRING(alias) " ; "	\
	    __STRING(alias) " = " __STRING(sym))
#define __weak_alias(alias,sym)				\
	__asm__(".weak " __STRING(alias) " ; "		\
	    __STRING(alias) " = " __STRING(sym))
#define	__warn_references(sym,msg)			\
	__asm__(".section .gnu.warning." __STRING(sym)	\
	    " ; .ascii \"" msg "\" ; .text")
#define	__indr_references(sym,msg)	/* nothing */

#endif /* !_MIPS64_CDEFS_H_ */


code:
/*	$OpenBSD: cpu.h,v 1.105 2015/07/02 01:33:59 dlg Exp $	*/

/*-
 * Copyright (c) 1992, 1993
 *	The Regents of the University of California.  All rights reserved.
 *
 * This code is derived from software contributed to Berkeley by
 * Ralph Campbell and Rick Macklem.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of the University nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 *	Copyright (C) 1989 Digital Equipment Corporation.
 *	Permission to use, copy, modify, and distribute this software and
 *	its documentation for any purpose and without fee is hereby granted,
 *	provided that the above copyright notice appears in all copies.
 *	Digital Equipment Corporation makes no representations about the
 *	suitability of this software for any purpose.  It is provided "as is"
 *	without express or implied warranty.
 *
 *	from: @(#)cpu.h	8.4 (Berkeley) 1/4/94
 */

#ifndef _MIPS64_CPU_H_
#define	_MIPS64_CPU_H_

#ifndef _LOCORE

/*
 * MIPS32-style segment definitions.
 * They only cover the first 512MB of physical addresses.
 */
#define	CKSEG0_BASE		0xffffffff80000000UL
#define	CKSEG1_BASE		0xffffffffa0000000UL
#define	CKSSEG_BASE		0xffffffffc0000000UL
#define	CKSEG3_BASE		0xffffffffe0000000UL
#define	CKSEG_SIZE		0x0000000020000000UL

#define	CKSEG0_TO_PHYS(x)	((u_long)(x) & (CKSEG_SIZE - 1))
#define	CKSEG1_TO_PHYS(x)	((u_long)(x) & (CKSEG_SIZE - 1))
#define	PHYS_TO_CKSEG0(x)	((u_long)(x) | CKSEG0_BASE)
#define	PHYS_TO_CKSEG1(x)	((u_long)(x) | CKSEG1_BASE)

/*
 * MIPS64-style segment definitions.
 * These allow for 36 bits of addressable physical memory, thus 64GB.
 */

/*
 * Cache Coherency Attributes.
 */
/* r8k only */
#define	CCA_NC_COPROCESSOR	0UL	/* uncached, coprocessor ordered */
/* common to r4, r5k, r8k and r1xk */
#define	CCA_NC			2UL	/* uncached, write-around */
#define	CCA_NONCOHERENT		3UL	/* cached, non-coherent, write-back */
/* r8k, r1xk only */
#define	CCA_COHERENT_EXCL	4UL	/* cached, coherent, exclusive */
#define	CCA_COHERENT_EXCLWRITE	5UL	/* cached, coherent, exclusive write */
/* r4k only */
#define	CCA_COHERENT_UPDWRITE	6UL	/* cached, coherent, update on write */
/* r1xk only */
#define	CCA_NC_ACCELERATED	7UL	/* uncached accelerated */

#ifdef TGT_COHERENT
#define	CCA_CACHED		CCA_COHERENT_EXCLWRITE
#else
#define	CCA_CACHED		CCA_NONCOHERENT
#endif

/*
 * Uncached spaces.
 * R1x000 processors use bits 58:57 of uncached virtual addresses (CCA_NC)
 * to select different spaces. Unfortunately, other processors need these
 * bits to be zero, so uncached address have to be decided at runtime.
 */
#define	SP_HUB			0UL	/* Hub space */
#define	SP_IO			1UL	/* I/O space */
#define	SP_SPECIAL		2UL	/* Memory Special space */
#define	SP_NC			3UL	/* Memory Uncached space */

#define	XKSSSEG_BASE		0x4000000000000000UL
#define	XKPHYS_BASE		0x8000000000000000UL
#define	XKSSEG_BASE		0xc000000000000000UL

#define	XKPHYS_TO_PHYS(x)	((paddr_t)(x) & 0x0000000fffffffffUL)
#define	PHYS_TO_XKPHYS(x,c)	((paddr_t)(x) | XKPHYS_BASE | ((c) << 59))
#define	PHYS_TO_XKPHYS_UNCACHED(x,s) \
	(PHYS_TO_XKPHYS(x, CCA_NC) | ((s) << 57))
#define	IS_XKPHYS(va)		(((va) >> 62) == 2)
#define	XKPHYS_TO_CCA(x)	(((x) >> 59) & 0x07)
#define	XKPHYS_TO_SP(x)		(((x) >> 57) & 0x03)

#endif	/* _LOCORE */

/*
 * Exported definitions unique to mips cpu support.
 */

#if defined(_KERNEL) && !defined(_LOCORE)

#include <sys/device.h>
#include <machine/intr.h>
#include <sys/sched.h>

struct cpu_hwinfo {
	uint32_t	c0prid;
	uint32_t	c1prid;
	uint32_t	clock;	/* Hz */
	uint32_t	tlbsize;
	uint		type;
	uint32_t	l2size;
};

/*
 * Cache memory configuration. One struct per cache.
 */
struct cache_info {
	uint		size;		/* total cache size */
	uint		linesize;	/* line size */
	uint		setsize;	/* set size */
	uint		sets;		/* number of sets */
};

struct cpu_info {
	struct device	*ci_dev;	/* our device */
	struct cpu_info	*ci_self;	/* pointer to this structure */
	struct cpu_info	*ci_next;	/* next cpu */
	struct proc	*ci_curproc;
	struct user	*ci_curprocpaddr;
	struct proc	*ci_fpuproc;	/* pointer to last proc to use FP */
	uint32_t	 ci_delayconst;
	struct cpu_hwinfo
			ci_hw;

#if defined(MULTIPROCESSOR)
	struct srp_hazard ci_srp_hazards[SRP_HAZARD_NUM];
#endif

	/* cache information and pending flush state */
	uint		ci_cacheconfiguration;
	uint64_t	ci_cachepending_l1i;
	struct cache_info
			ci_l1inst,
			ci_l1data,
			ci_l2,
			ci_l3;

	/* function pointers for the cache handling routines */
	void		(*ci_SyncCache)(struct cpu_info *);
	void		(*ci_InvalidateICache)(struct cpu_info *, vaddr_t,
			    size_t);
	void		(*ci_InvalidateICachePage)(struct cpu_info *, vaddr_t);
	void		(*ci_SyncICache)(struct cpu_info *);
	void		(*ci_SyncDCachePage)(struct cpu_info *, vaddr_t,
			    paddr_t);
	void		(*ci_HitSyncDCache)(struct cpu_info *, vaddr_t, size_t);
	void		(*ci_HitInvalidateDCache)(struct cpu_info *, vaddr_t,
			    size_t);
	void		(*ci_IOSyncDCache)(struct cpu_info *, vaddr_t, size_t,
			    int);

	struct schedstate_percpu
			ci_schedstate;
	int		ci_want_resched;	/* need_resched() invoked */
	cpuid_t		ci_cpuid;		/* our CPU ID */
	uint32_t	ci_randseed;		/* per cpu random seed */
	int		ci_ipl;			/* software IPL */
	uint32_t	ci_softpending;		/* pending soft interrupts */
	int		ci_clock_started;
	u_int32_t	ci_cpu_counter_last;	/* last compare value loaded */
	u_int32_t	ci_cpu_counter_interval; /* # of counter ticks/tick */

	u_int32_t	ci_pendingticks;
	struct pmap	*ci_curpmap;
	uint		ci_intrdepth;		/* interrupt depth */
#ifdef MULTIPROCESSOR
	u_long		ci_flags;		/* flags; see below */
	struct intrhand	ci_ipiih;
#endif
	volatile int    ci_ddb;
#define	CI_DDB_RUNNING		0
#define	CI_DDB_SHOULDSTOP	1
#define	CI_DDB_STOPPED		2
#define	CI_DDB_ENTERDDB		3
#define	CI_DDB_INDDB		4

#ifdef DIAGNOSTIC
	int	ci_mutex_level;
#endif
#ifdef GPROF
	struct gmonparam *ci_gmon;
#endif
};

#define	CPUF_PRIMARY	0x01		/* CPU is primary CPU */
#define	CPUF_PRESENT	0x02		/* CPU is present */
#define	CPUF_RUNNING	0x04		/* CPU is running */

extern struct cpu_info cpu_info_primary;
extern struct cpu_info *cpu_info_list;
#define CPU_INFO_ITERATOR		int
#define	CPU_INFO_FOREACH(cii, ci)	for (cii = 0, ci = cpu_info_list; \
					    ci != NULL; ci = ci->ci_next)

#define CPU_INFO_UNIT(ci)               ((ci)->ci_dev ? (ci)->ci_dev->dv_unit : 0)

#ifdef MULTIPROCESSOR
#define MAXCPUS				4
#define getcurcpu()			hw_getcurcpu()
#define setcurcpu(ci)			hw_setcurcpu(ci)
extern struct cpu_info *get_cpu_info(int);
#define curcpu() getcurcpu()
#define	CPU_IS_PRIMARY(ci)		((ci)->ci_flags & CPUF_PRIMARY)
#define cpu_number()			(curcpu()->ci_cpuid)

extern struct cpuset cpus_running;
void cpu_unidle(struct cpu_info *);
void cpu_boot_secondary_processors(void);
#define cpu_boot_secondary(ci)          hw_cpu_boot_secondary(ci)
#define cpu_hatch(ci)                   hw_cpu_hatch(ci)

vaddr_t alloc_contiguous_pages(size_t);

#define MIPS64_IPI_NOP		0x00000001
#define MIPS64_IPI_RENDEZVOUS	0x00000002
#define MIPS64_IPI_DDB		0x00000004
#define MIPS64_NIPIS		3	/* must not exceed 32 */

void	mips64_ipi_init(void);
void	mips64_send_ipi(unsigned int, unsigned int);
void	smp_rendezvous_cpus(unsigned long, void (*)(void *), void *arg);

#include <sys/mplock.h>
#else
#define MAXCPUS				1
#define curcpu()			(&cpu_info_primary)
#define	CPU_IS_PRIMARY(ci)		1
#define cpu_number()			0
#define cpu_unidle(ci)
#define get_cpu_info(i)			(&cpu_info_primary)
#endif

#define CPU_BUSY_CYCLE()	do {} while (0)

extern void (*md_startclock)(struct cpu_info *);
void	cp0_calibrate(struct cpu_info *);

#include <machine/frame.h>

/*
 * Arguments to hardclock encapsulate the previous machine state in
 * an opaque clockframe.
 */
#define	clockframe trap_frame	/* Use normal trap frame */

#define	SR_KSU_USER		0x00000010
#define	CLKF_USERMODE(framep)	((framep)->sr & SR_KSU_USER)
#define	CLKF_PC(framep)		((framep)->pc)
#define	CLKF_INTR(framep)	(curcpu()->ci_intrdepth > 1)	/* XXX */

/*
 * This is used during profiling to integrate system time.
 */
#define	PROC_PC(p)	((p)->p_md.md_regs->pc)
#define	PROC_STACK(p)	((p)->p_md.md_regs->sp)

/*
 * Preempt the current process if in interrupt from user mode,
 * or after the current trap/syscall if in system mode.
 */
#define	need_resched(ci) \
	do { \
		(ci)->ci_want_resched = 1; \
		if ((ci)->ci_curproc != NULL) \
			aston((ci)->ci_curproc); \
	} while(0)
#define	clear_resched(ci) 	(ci)->ci_want_resched = 0

/*
 * Give a profiling tick to the current process when the user profiling
 * buffer pages are invalid.  On the PICA, request an ast to send us
 * through trap, marking the proc as needing a profiling tick.
 */
#define	need_proftick(p)	aston(p)

/*
 * Notify the current process (p) that it has a signal pending,
 * process as soon as possible.
 */
#ifdef MULTIPROCESSOR
#define	signotify(p)		(aston(p), cpu_unidle(p->p_cpu))
#else
#define	signotify(p)		aston(p)
#endif

#define	aston(p)		p->p_md.md_astpending = 1

#ifdef CPU_R8000
#define	mips_sync()		__asm__ volatile ("lw $0, 0(%0)" :: \
				    "r" (PHYS_TO_XKPHYS(0, CCA_NC)) : "memory")
#else
#define	mips_sync()		__asm__ volatile ("sync" ::: "memory")
#endif

#endif /* _KERNEL && !_LOCORE */

#ifdef _KERNEL
/*
 * Values for the code field in a break instruction.
 */
#define	BREAK_INSTR		0x0000000d
#define	BREAK_VAL_MASK		0x03ff0000
#define	BREAK_VAL_SHIFT		16
#define	BREAK_KDB_VAL		512
#define	BREAK_SSTEP_VAL		513
#define	BREAK_BRKPT_VAL		514
#define	BREAK_SOVER_VAL		515
#define	BREAK_DDB_VAL		516
#define	BREAK_FPUEMUL_VAL	517
#define	BREAK_KDB	(BREAK_INSTR | (BREAK_KDB_VAL << BREAK_VAL_SHIFT))
#define	BREAK_SSTEP	(BREAK_INSTR | (BREAK_SSTEP_VAL << BREAK_VAL_SHIFT))
#define	BREAK_BRKPT	(BREAK_INSTR | (BREAK_BRKPT_VAL << BREAK_VAL_SHIFT))
#define	BREAK_SOVER	(BREAK_INSTR | (BREAK_SOVER_VAL << BREAK_VAL_SHIFT))
#define	BREAK_DDB	(BREAK_INSTR | (BREAK_DDB_VAL << BREAK_VAL_SHIFT))
#define	BREAK_FPUEMUL	(BREAK_INSTR | (BREAK_FPUEMUL_VAL << BREAK_VAL_SHIFT))

#endif /* _KERNEL */

/*
 * CTL_MACHDEP definitions.
 */
#define	CPU_ALLOWAPERTURE	1	/* allow mmap of /dev/xf86 */
		/*		2	   formerly: keyboard reset */
#define	CPU_MAXID		3	/* number of valid machdep ids */

#define	CTL_MACHDEP_NAMES {			\
	{ 0, 0 },				\
	{ "allowaperture", CTLTYPE_INT },	\
	{ 0, 0 },				\
}

/*
 * MIPS CPU types (cp_imp).
 */
#define	MIPS_R2000	0x01	/* MIPS R2000 CPU		ISA I   */
#define	MIPS_R3000	0x02	/* MIPS R3000 CPU		ISA I   */
#define	MIPS_R6000	0x03	/* MIPS R6000 CPU		ISA II	*/
#define	MIPS_R4000	0x04	/* MIPS R4000/4400 CPU		ISA III	*/
#define	MIPS_R3LSI	0x05	/* LSI Logic R3000 derivate	ISA I	*/
#define	MIPS_R6000A	0x06	/* MIPS R6000A CPU		ISA II	*/
#define MIPS_OCTEON	0x06	/* Cavium OCTEON		MIPS64R2*/
#define	MIPS_R3IDT	0x07	/* IDT R3000 derivate		ISA I	*/
#define	MIPS_R10000	0x09	/* MIPS R10000/T5 CPU		ISA IV  */
#define	MIPS_R4200	0x0a	/* MIPS R4200 CPU (ICE)		ISA III */
#define	MIPS_R4300	0x0b	/* NEC VR4300 CPU		ISA III */
#define	MIPS_R4100	0x0c	/* NEC VR41xx CPU MIPS-16	ISA III */
#define	MIPS_R12000	0x0e	/* MIPS R12000			ISA IV  */
#define	MIPS_R14000	0x0f	/* MIPS R14000			ISA IV  */
#define	MIPS_R8000	0x10	/* MIPS R8000 Blackbird/TFP	ISA IV  */
#define	MIPS_R4600	0x20	/* PMCS R4600 Orion		ISA III */
#define	MIPS_R4700	0x21	/* PMCS R4700 Orion		ISA III */
#define	MIPS_R3TOSH	0x22	/* Toshiba R3000 based CPU	ISA I	*/
#define	MIPS_R5000	0x23	/* MIPS R5000 CPU		ISA IV  */
#define	MIPS_RM7000	0x27	/* PMCS RM7000 CPU		ISA IV  */
#define	MIPS_RM52X0	0x28	/* PMCS RM52X0 CPU		ISA IV  */
#define	MIPS_RM9000	0x34	/* PMCS RM9000 CPU		ISA IV  */
#define	MIPS_LOONGSON	0x42	/* STC LoongSon CPU		ISA III */
#define	MIPS_VR5400	0x54	/* NEC Vr5400 CPU		ISA IV+ */
#define	MIPS_LOONGSON2	0x63	/* STC LoongSon2/3 CPU		ISA III+ */
#define MIPS_OCTEON2	0x93	/* Cavium OCTEON II		MIPS64R2 */

/*
 * MIPS FPU types. Only soft, rest is the same as cpu type.
 */
#define	MIPS_SOFT	0x00	/* Software emulation		ISA I   */

#if defined(_KERNEL) && !defined(_LOCORE)

extern register_t protosr;

struct exec_package;
struct user;

void	tlb_asid_wrap(struct cpu_info *);
void	tlb_flush(int);
void	tlb_flush_addr(vaddr_t);
void	tlb_init(unsigned int);
int64_t	tlb_probe(vaddr_t);
void	tlb_set_gbase(vaddr_t, vsize_t);
void	tlb_set_page_mask(uint32_t);
void	tlb_set_pid(u_int);
void	tlb_set_wired(uint32_t);
int	tlb_update(vaddr_t, register_t);
void	tlb_update_indexed(vaddr_t, register_t, register_t, uint);

void	build_trampoline(vaddr_t, vaddr_t);
void	cpu_switchto_asm(struct proc *, struct proc *);
int	exec_md_map(struct proc *, struct exec_package *);
void	savectx(struct user *, int);

void	enable_fpu(struct proc *);
void	save_fpu(void);
int	fpe_branch_emulate(struct proc *, struct trap_frame *, uint32_t,
	    vaddr_t);
void	MipsSaveCurFPState(struct proc *);
void	MipsSaveCurFPState16(struct proc *);
void	MipsSwitchFPState(struct proc *, struct trap_frame *);
void	MipsSwitchFPState16(struct proc *, struct trap_frame *);

int	guarded_read_1(paddr_t, uint8_t *);
int	guarded_read_2(paddr_t, uint16_t *);
int	guarded_read_4(paddr_t, uint32_t *);
int	guarded_write_4(paddr_t, uint32_t);

void	MipsFPTrap(struct trap_frame *);
register_t MipsEmulateBranch(struct trap_frame *, vaddr_t, uint32_t, uint32_t);

int	classify_insn(uint32_t);
#define	INSNCLASS_NEUTRAL	0
#define	INSNCLASS_CALL		1
#define	INSNCLASS_BRANCH	2

/*
 * R4000 end-of-page errata workaround routines
 */

extern int r4000_errata;
u_int	eop_page_check(paddr_t);
void	eop_tlb_flush_addr(struct pmap *, vaddr_t, u_long);
int	eop_tlb_miss_handler(struct trap_frame *, struct cpu_info *,
	    struct proc *);
void	eop_cleanup(struct trap_frame *, struct proc *);

/*
 * Low level access routines to CPU registers
 */

void	setsoftintr0(void);
void	clearsoftintr0(void);
void	setsoftintr1(void);
void	clearsoftintr1(void);
register_t enableintr(void);
register_t disableintr(void);
register_t getsr(void);
register_t setsr(register_t);

u_int	cp0_get_count(void);
register_t cp0_get_config(void);
uint32_t cp0_get_config_1(void);
uint32_t cp0_get_config_2(void);
uint32_t cp0_get_config_3(void);
register_t cp0_get_prid(void);
void	cp0_reset_cause(register_t);
void	cp0_set_compare(u_int);
void	cp0_set_config(register_t);
void	cp0_set_trapbase(register_t);
u_int	cp1_get_prid(void);

/*
 * Cache routines (may be overridden)
 */

#ifndef	Mips_SyncCache
#define	Mips_SyncCache(ci) \
	((ci)->ci_SyncCache)(ci)
#endif
#ifndef	Mips_InvalidateICache
#define	Mips_InvalidateICache(ci, va, l) \
	((ci)->ci_InvalidateICache)(ci, va, l)
#endif
#ifndef	Mips_InvalidateICachePage
#define	Mips_InvalidateICachePage(ci, va) \
	((ci)->ci_InvalidateICachePage)(ci, va)
#endif
#ifndef	Mips_SyncICache
#define	Mips_SyncICache(ci) \
	((ci)->ci_SyncICache)(ci)
#endif
#ifndef	Mips_SyncDCachePage
#define	Mips_SyncDCachePage(ci, va, pa) \
	((ci)->ci_SyncDCachePage)(ci, va, pa)
#endif
#ifndef	Mips_HitSyncDCache
#define	Mips_HitSyncDCache(ci, va, l) \
	((ci)->ci_HitSyncDCache)(ci, va, l)
#endif
#ifndef	Mips_HitInvalidateDCache
#define	Mips_HitInvalidateDCache(ci, va, l) \
	((ci)->ci_HitInvalidateDCache)(ci, va, l)
#endif
#ifndef	Mips_IOSyncDCache
#define	Mips_IOSyncDCache(ci, va, l, h) \
	((ci)->ci_IOSyncDCache)(ci, va, l, h)
#endif

#endif /* _KERNEL && !_LOCORE */
#endif /* !_MIPS64_CPU_H_ */


code:
/*	$OpenBSD: cpustate.h,v 1.10 2014/07/09 12:58:08 miod Exp $ */

/*
 * Copyright (c) 2002-2003 Opsycon AB  (www.opsycon.se / www.opsycon.com)
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 */

#define	KERN_REG_SIZE		(NUMSAVEREGS * REGSZ)
#define	KERN_EXC_FRAME_SIZE	(CF_SZ + KERN_REG_SIZE + 16)

#define	SAVE_REG(reg, offs, base, bo) \
	REG_S	reg, bo + (REGSZ * offs) (base)

#define	RESTORE_REG(reg, offs, base, bo) \
	REG_L	reg, bo + (REGSZ * offs) (base)

/*
 *  This macro saves the 'scratch' cpu state on stack.
 *  Macros are generic so no 'special' instructions!
 *  a0 will have a pointer to the 'frame' on return.
 *  a1 will have saved STATUS_REG on return.
 *  a3 will have the exception pc on 'return'.
 *  No traps, no interrupts if frame = k1 or k0!
 *  Temp regs are saved with their register number so
 *  branch emulation etc works properly.
 */
#define	SAVE_CPU(frame, bo)			 \
	SAVE_REG(AT, AST, frame, bo)		;\
	SAVE_REG(v0, V0, frame, bo)		;\
	SAVE_REG(v1, V1, frame, bo)		;\
	SAVE_REG(a0, A0, frame, bo)		;\
	SAVE_REG(a1, A1, frame, bo)		;\
	SAVE_REG(a2, A2, frame, bo)		;\
	SAVE_REG(a3, A3, frame, bo)		;\
	MFC0	a0, COP_0_CAUSE_REG		;\
	SAVE_REG(a4, A4, frame, bo)		;\
	SAVE_REG(a5, A5, frame, bo)		;\
	MFC0	a1, COP_0_STATUS_REG		;\
	SAVE_REG(a6, A6, frame, bo)		;\
	SAVE_REG(a7, A7, frame, bo)		;\
	PRE_MFC0_ADDR_HAZARD			;\
	DMFC0	a2, COP_0_BAD_VADDR		;\
	SAVE_REG(t0, T0, frame, bo)		;\
	SAVE_REG(t1, T1, frame, bo)		;\
	DMFC0	a3, COP_0_EXC_PC		;\
	SAVE_REG(t2, T2, frame, bo)		;\
	SAVE_REG(t3, T3, frame, bo)		;\
	SAVE_REG(t8, T8, frame, bo)		;\
	SAVE_REG(t9, T9, frame, bo)		;\
	SAVE_REG(gp, GP, frame, bo)		;\
	SAVE_REG(ra, RA, frame, bo)		;\
	mflo	v0				;\
	mfhi	v1				;\
	SAVE_REG(v0, MULLO, frame, bo)		;\
	SAVE_REG(v1, MULHI, frame, bo)		;\
	SAVE_REG(a0, CAUSE, frame, bo)		;\
	SAVE_REG(a1, SR, frame, bo)		;\
	SAVE_REG(a2, BADVADDR, frame, bo)	;\
	SAVE_REG(a3, PC, frame, bo)		;\
	SAVE_REG(sp, SP, frame, bo)		;\
	PTR_ADDU a0, frame, bo			;\
	GET_CPU_INFO(v0, v1)			;\
	lw	a2, CI_IPL(v0)			;\
	SAVE_REG(a2, CPL, frame, bo)

/*
 *  Save 'callee save' registers in frame to aid DDB.
 */
#define	SAVE_CPU_SREG(frame, bo)		 \
	SAVE_REG(s0, S0, frame, bo)		;\
	SAVE_REG(s1, S1, frame, bo)		;\
	SAVE_REG(s2, S2, frame, bo)		;\
	SAVE_REG(s3, S3, frame, bo)		;\
	SAVE_REG(s4, S4, frame, bo)		;\
	SAVE_REG(s5, S5, frame, bo)		;\
	SAVE_REG(s6, S6, frame, bo)		;\
	SAVE_REG(s7, S7, frame, bo)		;\
	SAVE_REG(s8, S8, frame, bo)

/*
 *  Restore cpu state. When called a0 = EXC_PC.
 */
#define	RESTORE_CPU(frame, bo)			 \
	RESTORE_REG(t1, SR, frame, bo)		;\
	RESTORE_REG(t2, MULLO, frame, bo)	;\
	RESTORE_REG(t3, MULHI, frame, bo)	;\
	MTC0	t1, COP_0_STATUS_REG		;\
	MTC0_SR_IE_HAZARD			;\
	mtlo	t2				;\
	mthi	t3				;\
	DMTC0	a0, COP_0_EXC_PC		;\
	MTC0_HAZARD				;\
	RESTORE_REG(AT, AST, frame, bo)		;\
	RESTORE_REG(v0, V0, frame, bo)		;\
	RESTORE_REG(v1, V1, frame, bo)		;\
	RESTORE_REG(a0, A0, frame, bo)		;\
	RESTORE_REG(a1, A1, frame, bo)		;\
	RESTORE_REG(a2, A2, frame, bo)		;\
	RESTORE_REG(a3, A3, frame, bo)		;\
	RESTORE_REG(a4, A4, frame, bo)		;\
	RESTORE_REG(a5, A5, frame, bo)		;\
	RESTORE_REG(a6, A6, frame, bo)		;\
	RESTORE_REG(a7, A7, frame, bo)		;\
	RESTORE_REG(t0, T0, frame, bo)		;\
	RESTORE_REG(t1, T1, frame, bo)		;\
	RESTORE_REG(t2, T2, frame, bo)		;\
	RESTORE_REG(t3, T3, frame, bo)		;\
	RESTORE_REG(t8, T8, frame, bo)		;\
	RESTORE_REG(t9, T9, frame, bo)		;\
	RESTORE_REG(gp, GP, frame, bo)		;\
	RESTORE_REG(ra, RA, frame, bo)

/*
 *  Restore 'callee save' registers
 */
#define	RESTORE_CPU_SREG(frame, bo)		 \
	RESTORE_REG(s0, S0, frame, bo)		;\
	RESTORE_REG(s1, S1, frame, bo)		;\
	RESTORE_REG(s2, S2, frame, bo)		;\
	RESTORE_REG(s3, S3, frame, bo)		;\
	RESTORE_REG(s4, S4, frame, bo)		;\
	RESTORE_REG(s5, S5, frame, bo)		;\
	RESTORE_REG(s6, S6, frame, bo)		;\
	RESTORE_REG(s7, S7, frame, bo)		;\
	RESTORE_REG(s8, S8, frame, bo)


code:
/*	$OpenBSD: db_machdep.h,v 1.15 2014/03/21 23:05:41 miod Exp $ */

/*
 * Copyright (c) 1998-2003 Opsycon AB (www.opsycon.se)
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 */

#ifndef	_MIPS64_DB_MACHDEP_H_
#define	_MIPS64_DB_MACHDEP_H_

#include <machine/frame.h>
#include <machine/trap.h>
#include <uvm/uvm_param.h>

#define DB_MACHINE_COMMANDS	/* We have machine specific commands */

typedef struct trap_frame db_regs_t;
extern db_regs_t	ddb_regs;

typedef	long		db_expr_t;
typedef vaddr_t		db_addr_t;

#define	SOFTWARE_SSTEP		/* Need software single step */
#define	SOFTWARE_SSTEP_EMUL	/* next_instr_address() emulates 100% */
db_addr_t	next_instr_address(db_addr_t, boolean_t);
#define	BKPT_SIZE   (4)
#define	BKPT_SET(ins)	(BREAK_DDB)
#define	DB_VALID_BREAKPOINT(addr)	(((addr) & 3) == 0)

#define	IS_BREAKPOINT_TRAP(type, code)	((type) == T_BREAK)
#define IS_WATCHPOINT_TRAP(type, code)	(0)	/* XXX mips3 watchpoint */

#define	PC_REGS(regs)	((db_addr_t)(regs)->pc)
#define	SET_PC_REGS(regs, value)	(regs)->pc = (register_t)(value)
#define DDB_REGS	(&ddb_regs)

/*
 *  Test of instructions to see class.
 */
#define	inst_branch(i)		(classify_insn(i) == INSNCLASS_BRANCH)
#define	inst_trap_return(i)	((i) & 0)
#define	inst_call(i)		(classify_insn(i) == INSNCLASS_CALL)
#define	inst_return(i)		((i) == 0x03e00008)

void db_machine_init(void);

int db_enter_ddb(void);
void db_startcpu(int);
void db_stopcpu(int);

int	dbmd_print_insn(uint32_t, db_addr_t, int (*)(const char *, ...));

extern struct mutex ddb_mp_mutex;

#define DDB_STATE_NOT_RUNNING	0
#define DDB_STATE_RUNNING	1
#define DDB_STATE_EXITING	2

#endif	/* !_MIPS64_DB_MACHDEP_H_ */


code:
/*	$OpenBSD: endian.h,v 1.9 2014/07/12 16:25:08 guenther Exp $ */

/*
 * Copyright (c) 2001-2002 Opsycon AB  (www.opsycon.se / www.opsycon.com)
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 */

#ifndef _MIPS64_ENDIAN_H_
#define _MIPS64_ENDIAN_H_

#if defined(__MIPSEL__)
#define _BYTE_ORDER _LITTLE_ENDIAN
#endif
#if defined(__MIPSEB__)
#define _BYTE_ORDER _BIG_ENDIAN
#endif

#if !defined(_BYTE_ORDER)
#error "__MIPSEL__ or __MIPSEB__ must be defined to define BYTE_ORDER!!!"
#endif

#define	__STRICT_ALIGNMENT

#ifndef __FROM_SYS__ENDIAN
#include <sys/endian.h>
#endif

#endif /* _MIPS64_ENDIAN_H_ */


code:
/*	$OpenBSD: exec.h,v 1.6 2013/02/09 19:25:13 miod Exp $	*/

/*
 * Copyright (c) 1996-2004 Per Fogelstrom, Opsycon AB
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 */

#ifndef _MIPS64_EXEC_H_
#define _MIPS64_EXEC_H_

#define	__LDPGSZ	16384

#define	ARCH_ELFSIZE 64
#define ELF_TARG_CLASS  ELFCLASS64

#if defined(__MIPSEB__)
#define ELF_TARG_DATA		ELFDATA2MSB
#else
#define ELF_TARG_DATA		ELFDATA2LSB
#endif
#define ELF_TARG_MACH		EM_MIPS

#define _NLIST_DO_ELF

#define _KERN_DO_ELF64

/* Information taken from MIPS ABI supplement */

/* Architecture dependent Segment types - p_type */
#define PT_MIPS_REGINFO 0x70000000      /* Register usage information */

/* Architecture dependent d_tag field for Elf32_Dyn.  */
#define DT_MIPS_RLD_VERSION  0x70000001 /* Runtime Linker Interface ID */
#define DT_MIPS_TIME_STAMP   0x70000002 /* Timestamp */
#define DT_MIPS_ICHECKSUM    0x70000003 /* Cksum of ext. str. and com. sizes */
#define DT_MIPS_IVERSION     0x70000004 /* Version string (string tbl index) */
#define DT_MIPS_FLAGS        0x70000005 /* Flags */
#define DT_MIPS_BASE_ADDRESS 0x70000006 /* Segment base address */
#define DT_MIPS_CONFLICT     0x70000008 /* Adr of .conflict section */
#define DT_MIPS_LIBLIST      0x70000009 /* Address of .liblist section */
#define DT_MIPS_LOCAL_GOTNO  0x7000000a /* Number of local .GOT entries */
#define DT_MIPS_CONFLICTNO   0x7000000b /* Number of .conflict entries */
#define DT_MIPS_LIBLISTNO    0x70000010 /* Number of .liblist entries */
#define DT_MIPS_SYMTABNO     0x70000011 /* Number of .dynsym entries */
#define DT_MIPS_UNREFEXTNO   0x70000012 /* First external DYNSYM */
#define DT_MIPS_GOTSYM       0x70000013 /* First GOT entry in .dynsym */
#define DT_MIPS_HIPAGENO     0x70000014 /* Number of GOT page table entries */
#define DT_MIPS_RLD_MAP      0x70000016 /* Address of debug map pointer */

#define DT_PROCNUM (DT_MIPS_RLD_MAP - DT_LOPROC + 1)

/*
 * Legal values for e_flags field of Elf32_Ehdr.
 */
#define EF_MIPS_NOREORDER	0x00000001	/* .noreorder was used */
#define EF_MIPS_PIC		0x00000002	/* Contains PIC code */
#define EF_MIPS_CPIC		0x00000004	/* Uses PIC calling sequence */
#define	EF_MIPS_ABI2		0x00000020	/* -n32 on Irix 6 */
#define	EF_MIPS_32BITMODE	0x00000100	/* 64 bit in 32 bit mode... */
#define EF_MIPS_ARCH		0xf0000000	/* MIPS architecture level */
#define	E_MIPS_ARCH_1		0x00000000
#define	E_MIPS_ARCH_2		0x10000000
#define	E_MIPS_ARCH_3		0x20000000
#define	E_MIPS_ARCH_4		0x30000000
#define	EF_MIPS_ABI		0x0000f000	/* ABI level */
#define	E_MIPS_ABI_NONE		0x00000000	/* ABI level not set */
#define	E_MIPS_ABI_O32		0x00001000
#define	E_MIPS_ABI_O64		0x00002000
#define	E_MIPS_ABI_EABI32	0x00004000
#define	E_MIPS_ABI_EABI64	0x00004000

/*
 * Mips special sections.
 */
#define	SHN_MIPS_ACOMMON	0xff00		/* Allocated common symbols */
#define	SHN_MIPS_SCOMMON	0xff03		/* Small common symbols */
#define	SHN_MIPS_SUNDEFINED	0xff04		/* Small undefined symbols */

/*
 * Legal values for sh_type field of Elf32_Shdr.
 */
#define	SHT_MIPS_LIBLIST  0x70000000	/* Shared objects used in link */
#define	SHT_MIPS_CONFLICT 0x70000002	/* Conflicting symbols */
#define	SHT_MIPS_GPTAB    0x70000003	/* Global data area sizes */
#define	SHT_MIPS_UCODE    0x70000004	/* Reserved for SGI/MIPS compilers */
#define	SHT_MIPS_DEBUG    0x70000005	/* MIPS ECOFF debugging information */
#define	SHT_MIPS_REGINFO  0x70000006	/* Register usage information */

/*
 * Legal values for sh_flags field of Elf32_Shdr.
 */
#define	SHF_MIPS_GPREL	0x10000000	/* Must be part of global data area */

#if 0
/*
 * Entries found in sections of type SHT_MIPS_GPTAB.
 */
typedef union {
	struct {
		Elf32_Word gt_current_g_value;	/* -G val used in compilation */
		Elf32_Word gt_unused;	/* Not used */
	} gt_header;			/* First entry in section */
	struct {
		Elf32_Word gt_g_value;	/* If this val were used for -G */
		Elf32_Word gt_bytes;	/* This many bytes would be used */
	} gt_entry;			/* Subsequent entries in section */
} Elf32_gptab;

/*
 * Entry found in sections of type SHT_MIPS_REGINFO.
 */
typedef struct {
	Elf32_Word	ri_gprmask;	/* General registers used */
	Elf32_Word	ri_cprmask[4];	/* Coprocessor registers used */
	Elf32_Sword	ri_gp_value;	/* $gp register value */
} Elf32_RegInfo;
#endif

/*
 * Mips relocations.
 */

#define	R_MIPS_NONE	0	/* No reloc */
#define	R_MIPS_16	1	/* Direct 16 bit */
#define	R_MIPS_32	2	/* Direct 32 bit */
#define	R_MIPS_REL32	3	/* PC relative 32 bit */
#define	R_MIPS_26	4	/* Direct 26 bit shifted */
#define	R_MIPS_HI16	5	/* High 16 bit */
#define	R_MIPS_LO16	6	/* Low 16 bit */
#define	R_MIPS_GPREL16	7	/* GP relative 16 bit */
#define	R_MIPS_LITERAL	8	/* 16 bit literal entry */
#define	R_MIPS_GOT16	9	/* 16 bit GOT entry */
#define	R_MIPS_PC16	10	/* PC relative 16 bit */
#define	R_MIPS_CALL16	11	/* 16 bit GOT entry for function */
#define	R_MIPS_GPREL32	12	/* GP relative 32 bit */

#define	R_MIPS_64	18

#define	R_MIPS_REL32_64	((R_MIPS_64 << 8) | R_MIPS_REL32)

#endif	/* !_MIPS64_EXEC_H_ */


code:
/*	$OpenBSD: fenv.h,v 1.3 2011/05/25 21:46:49 martynas Exp $	*/

/*
 * Copyright (c) 2011 Martynas Venckus <martynas@openbsd.org>
 *
 * Permission to use, copy, modify, and distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#ifndef	_MIPS64_FENV_H_
#define	_MIPS64_FENV_H_

/*
 * Each symbol representing a floating point exception expands to an integer
 * constant expression with values, such that bitwise-inclusive ORs of _all
 * combinations_ of the constants result in distinct values.
 *
 * We use such values that allow direct bitwise operations on FPU registers.
 */
#define	FE_INEXACT		0x04
#define	FE_UNDERFLOW		0x08
#define	FE_OVERFLOW		0x10
#define	FE_DIVBYZERO		0x20
#define	FE_INVALID		0x40

/*
 * The following symbol is simply the bitwise-inclusive OR of all floating-point
 * exception constants defined above.
 */
#define	FE_ALL_EXCEPT		(FE_INEXACT | FE_UNDERFLOW | FE_OVERFLOW | \
				 FE_DIVBYZERO | FE_INVALID)
#define	_MASK_SHIFT		5

/*
 * Each symbol representing the rounding direction, expands to an integer
 * constant expression whose value is distinct non-negative value.
 *
 * We use such values that allow direct bitwise operations on FPU registers.
 */
#define	FE_TONEAREST		0x0
#define	FE_TOWARDZERO		0x1
#define	FE_UPWARD		0x2
#define	FE_DOWNWARD		0x3

/*
 * The following symbol is simply the bitwise-inclusive OR of all floating-point
 * rounding direction constants defined above.
 */
#define	_ROUND_MASK		(FE_TONEAREST | FE_TOWARDZERO | FE_UPWARD | \
				 FE_DOWNWARD)

/*
 * fenv_t represents the entire floating-point environment.
 */
typedef	unsigned int fenv_t;

/*
 * The following constant represents the default floating-point environment
 * (that is, the one installed at program startup) and has type pointer to
 * const-qualified fenv_t.
 *
 * It can be used as an argument to the functions within the <fenv.h> header
 * that manage the floating-point environment, namely fesetenv() and
 * feupdateenv().
 */
__BEGIN_DECLS
extern	fenv_t			__fe_dfl_env;
__END_DECLS
#define	FE_DFL_ENV		((const fenv_t *)&__fe_dfl_env)

/*
 * fexcept_t represents the floating-point status flags collectively, including
 * any status the implementation associates with the flags.
 *
 * A floating-point status flag is a system variable whose value is set (but
 * never cleared) when a floating-point exception is raised, which occurs as a
 * side effect of exceptional floating-point arithmetic to provide auxiliary
 * information.
 *
 * A floating-point control mode is a system variable whose value may be set by
 * the user to affect the subsequent behavior of floating-point arithmetic.
 */
typedef	unsigned int		fexcept_t;

#endif	/* !_MIPS64_FENV_H_ */


code:
/*	$OpenBSD: fpu.h,v 1.2 2012/12/04 05:00:40 deraadt Exp $	*/

/*
 * Copyright (c) 2010 Miodrag Vallat.
 *
 * Permission to use, copy, modify, and distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

/*
 * Layout of the floating-point control/status register (FCR31)
 */

/* flush denormalized results to zero instead of causing FPCSR_C_E */
#define	FPCSR_FS	0x01000000

/* compare condition bits: one bit for MIPS I/II/III, eight bits for MIPS IV */
#define	FPCSR_CONDBIT(c)	((c) == 0 ? 23 : 24 + (c))
#define	FPCSR_CONDVAL(c)	(1U << FPCSR_CONDBIT(c))

/* cause bits */
#define	FPCSR_C_E	0x00020000	/* unimplemented operation */
#define	FPCSR_C_V	0x00010000	/* invalid operation */
#define	FPCSR_C_Z	0x00008000	/* division by zero */
#define	FPCSR_C_O	0x00004000	/* overflow */
#define	FPCSR_C_U	0x00002000	/* underflow */
#define	FPCSR_C_I	0x00001000	/* inexact */

/* enable bits */
#define	FPCSR_E_V	0x00000800	/* invalid operation */
#define	FPCSR_E_Z	0x00000400	/* division by zero */
#define	FPCSR_E_O	0x00000200	/* overflow */
#define	FPCSR_E_U	0x00000100	/* underflow */
#define	FPCSR_E_I	0x00000080	/* inexact */

/* flags bits */
#define	FPCSR_F_V	0x00000040	/* invalid operation */
#define	FPCSR_F_Z	0x00000020	/* division by zero */
#define	FPCSR_F_O	0x00000010	/* overflow */
#define	FPCSR_F_U	0x00000008	/* underflow */
#define	FPCSR_F_I	0x00000004	/* inexact */

#define	FPCSR_C_MASK	0x0003f000
#define	FPCSR_C_SHIFT		12
#define	FPCSR_E_MASK	0x00000f80
#define	FPCSR_E_SHIFT		7
#define	FPCSR_F_MASK	0x0000007c
#define	FPCSR_F_SHIFT		2
#define	FPCSR_RM_MASK	0x00000003	/* rounding mode */

#ifndef _KERNEL

/*
 * IRIX-compatible interfaces allowing userland to control the state
 * of the floating-point control/status register.  These are intended
 * to let userland control the state of the FS bit.
 */
#include <sys/cdefs.h>

__BEGIN_DECLS
int	get_fpc_csr(void);
int	set_fpc_csr(int);
__END_DECLS
#endif	/* _KERNEL */


code:
/*	$OpenBSD: frame.h,v 1.6 2014/07/09 12:58:08 miod Exp $ */

/*
 * Copyright (c) 1998-2003 Opsycon AB (www.opsycon.se)
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 */
#ifndef _MIPS64_FRAME_H_
#define	_MIPS64_FRAME_H_

/*
 *  The layout of this *must* match with regnum.h or bad things
 *  will happen. libc setjmp/longjmp depends on this as well.
 */
struct trap_frame {
	register_t	zero;
	register_t	ast;
	register_t	v0;
	register_t	v1;
	register_t	a0;
	register_t	a1;
	register_t	a2;
	register_t	a3;
	register_t	a4; /* ta0 */
	register_t	a5; /* ta1 */
	register_t	a6; /* ta2 */
	register_t	a7; /* ta3 */
	register_t	t0;
	register_t	t1;
	register_t	t2;
	register_t	t3;
	register_t	s0;
	register_t	s1;
	register_t	s2;
	register_t	s3;
	register_t	s4;
	register_t	s5;
	register_t	s6;
	register_t	s7;
	register_t	t8;
	register_t	t9;
	register_t	k0;
	register_t	k1;
	register_t	gp;
	register_t	sp;
	register_t	s8;
	register_t	ra;
	register_t	sr;
	register_t	mullo;
	register_t	mulhi;
	register_t	badvaddr;
	register_t	cause;
	register_t	pc;
	register_t	ic;
	register_t	ipl;

/* From here and on, only saved user processes. */

	f_register_t	f0;
	f_register_t	f1;
	f_register_t	f2;
	f_register_t	f3;
	f_register_t	f4;
	f_register_t	f5;
	f_register_t	f6;
	f_register_t	f7;
	f_register_t	f8;
	f_register_t	f9;
	f_register_t	f10;
	f_register_t	f11;
	f_register_t	f12;
	f_register_t	f13;
	f_register_t	f14;
	f_register_t	f15;
	f_register_t	f16;
	f_register_t	f17;
	f_register_t	f18;
	f_register_t	f19;
	f_register_t	f20;
	f_register_t	f21;
	f_register_t	f22;
	f_register_t	f23;
	f_register_t	f24;
	f_register_t	f25;
	f_register_t	f26;
	f_register_t	f27;
	f_register_t	f28;
	f_register_t	f29;
	f_register_t	f30;
	f_register_t	f31;
	register_t	fsr;
};

#endif	/* !_MIPS64_FRAME_H_ */


code:
/*	$OpenBSD: ieee.h,v 1.4 2010/01/23 19:11:21 miod Exp $	*/

/*
 * Copyright (c) 1992, 1993
 *	The Regents of the University of California.  All rights reserved.
 *
 * This software was developed by the Computer Systems Engineering group
 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
 * contributed to Berkeley.
 *
 * All advertising materials mentioning features or use of this software
 * must display the following acknowledgement:
 *	This product includes software developed by the University of
 *	California, Lawrence Berkeley Laboratory.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of the University nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 *	@(#)ieee.h	8.1 (Berkeley) 6/11/93
 */

/*
 * ieee.h defines the machine-dependent layout of the machine's IEEE
 * floating point.  It does *not* define (yet?) any of the rounding
 * mode bits, exceptions, and so forth.
 */

/*
 * Define the number of bits in each fraction and exponent.
 *
 *		     k	         k+1
 * Note that  1.0 x 2  == 0.1 x 2      and that denorms are represented
 *
 *					  (-exp_bias+1)
 * as fractions that look like 0.fffff x 2             .  This means that
 *
 *			 -126
 * the number 0.10000 x 2    , for instance, is the same as the normalized
 *
 *		-127			   -128
 * float 1.0 x 2    .  Thus, to represent 2    , we need one leading zero
 *
 *				  -129
 * in the fraction; to represent 2    , we need two, and so on.  This
 *
 *						     (-exp_bias-fracbits+1)
 * implies that the smallest denormalized number is 2
 *
 * for whichever format we are talking about: for single precision, for
 *
 *						-126		-149
 * instance, we get .00000000000000000000001 x 2    , or 1.0 x 2    , and
 *
 * -149 == -127 - 23 + 1.
 */
#define	SNG_EXPBITS	8
#define	SNG_FRACBITS	23

#define	DBL_EXPBITS	11
#define	DBL_FRACHBITS	20
#define	DBL_FRACLBITS	32
#define	DBL_FRACBITS	52

#define	EXT_EXPBITS	15
#define	EXT_FRACHBITS	16
#define	EXT_FRACHMBITS	32
#define	EXT_FRACLMBITS	32
#define	EXT_FRACLBITS	32
#define	EXT_FRACBITS	112

#define	EXT_IMPLICIT_NBIT

#define	EXT_TO_ARRAY32(p, a) do {		\
	(a)[0] = (uint32_t)(p)->ext_fracl;	\
	(a)[1] = (uint32_t)(p)->ext_fraclm;	\
	(a)[2] = (uint32_t)(p)->ext_frachm;	\
	(a)[3] = (uint32_t)(p)->ext_frach;	\
} while(0)

struct ieee_single {
#ifdef __MIPSEB__
	u_int	sng_sign:1;
	u_int	sng_exp:8;
	u_int	sng_frac:23;
#else
	u_int	sng_frac:23;
	u_int	sng_exp:8;
	u_int	sng_sign:1;
#endif
};

struct ieee_double {
#ifdef __MIPSEB__
	u_int	dbl_sign:1;
	u_int	dbl_exp:11;
	u_int	dbl_frach:20;
	u_int	dbl_fracl;
#else
	u_int	dbl_fracl;
	u_int	dbl_frach:20;
	u_int	dbl_exp:11;
	u_int	dbl_sign:1;
#endif
};

struct ieee_ext {
#ifdef __MIPSEB__
	u_int	ext_sign:1;
	u_int	ext_exp:15;
	u_int	ext_frach:16;
	u_int	ext_frachm;
	u_int	ext_fraclm;
	u_int	ext_fracl;
#else
	u_int	ext_fracl;
	u_int	ext_fraclm;
	u_int	ext_frachm;
	u_int	ext_frach:16;
	u_int	ext_exp:15;
	u_int	ext_sign:1;
#endif
};

/*
 * Floats whose exponent is in [1..INFNAN) (of whatever type) are
 * `normal'.  Floats whose exponent is INFNAN are either Inf or NaN.
 * Floats whose exponent is zero are either zero (iff all fraction
 * bits are zero) or subnormal values.
 *
 * A NaN is a `signalling NaN' if its QUIETNAN bit is clear in its
 * high fraction; if the bit is set, it is a `quiet NaN'.
 */
#define	SNG_EXP_INFNAN	255
#define	DBL_EXP_INFNAN	2047
#define	EXT_EXP_INFNAN	32767

#if 0
#define	SNG_QUIETNAN	(1 << 22)
#define	DBL_QUIETNAN	(1 << 19)
#define	EXT_QUIETNAN	(1 << 15)
#endif

/*
 * Exponent biases.
 */
#define	SNG_EXP_BIAS	127
#define	DBL_EXP_BIAS	1023
#define	EXT_EXP_BIAS	16383


code:
/*	$OpenBSD: ieeefp.h,v 1.4 2011/03/23 16:54:36 pirofti Exp $	*/

/*
 * Written by J.T. Conklin, Apr 11, 1995
 * Public domain.
 */

#ifndef _MIPS64_IEEEFP_H_
#define _MIPS64_IEEEFP_H_

typedef int fp_except;
#define FP_X_IMP	0x01	/* imprecise (loss of precision) */
#define FP_X_UFL	0x02	/* underflow exception */
#define FP_X_OFL	0x04	/* overflow exception */
#define FP_X_DZ		0x08	/* divide-by-zero exception */
#define FP_X_INV	0x10	/* invalid operation exception */

typedef enum {
    FP_RN=0,			/* round to nearest representable number */
    FP_RZ=1,			/* round to zero (truncate) */
    FP_RP=2,			/* round toward positive infinity */
    FP_RM=3			/* round toward negative infinity */
} fp_rnd;

#ifdef _KERNEL

/*
 * Defines for the floating-point completion/emulation code.
 */

#include <sys/param.h>
#include <sys/systm.h>
#include <sys/proc.h>
#include <machine/fpu.h>

#define	float_raise(bits) \
	do { curproc->p_md.md_regs->fsr |= (bits) << FPCSR_C_SHIFT; } while (0)
#define	float_set_inexact()	float_raise(FP_X_IMP)
#define	float_set_invalid()	float_raise(FP_X_INV)

#define	float_get_round(csr)	(csr & FPCSR_RM_MASK)
#define	fpgetround()		float_get_round(curproc->p_md.md_regs->fsr)

#endif

#endif /* !_MIPS64_IEEEFP_H_ */


code:
/*	$OpenBSD: kcore.h,v 1.2 2011/03/23 16:54:36 pirofti Exp $	*/
/*	$NetBSD: kcore.h,v 1.1 1996/03/10 21:55:18 leo Exp $	*/

/*
 * Copyright (c) 1996 Leo Weppelman.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *      This product includes software developed by Leo Weppelman.
 * 4. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef _MIPS64_KCORE_H_
#define	_MIPS64_KCORE_H_

#define	NPHYS_RAM_SEGS	8

typedef struct cpu_kcore_hdr {
	paddr_t		kernel_pa;	/* Phys. address of kernel VA 0	*/
	int		mmutype;
	phys_ram_seg_t  ram_segs[NPHYS_RAM_SEGS];
} cpu_kcore_hdr_t;

#endif /* !_MIPS64_KCORE_H_ */


code:
/*	$OpenBSD: limits.h,v 1.8 2015/04/30 13:42:08 millert Exp $	*/

/*
 * Copyright (c) 1988, 1993
 *	The Regents of the University of California.  All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of the University nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 *	@(#)limits.h	8.3 (Berkeley) 1/4/94
 */

#ifndef _MIPS64_LIMITS_H_
#define _MIPS64_LIMITS_H_

#include <sys/cdefs.h>

#if __POSIX_VISIBLE || __XPG_VISIBLE
#define	SSIZE_MAX	LONG_MAX	/* max value for a ssize_t */
#endif

#if __BSD_VISIBLE
#define	SIZE_T_MAX	ULONG_MAX	/* max value for a size_t (historic) */

/* Quads and longs are the same on mips64 */
#define	UQUAD_MAX	(ULONG_MAX)	/* max value for a uquad_t */
#define	QUAD_MAX	(LONG_MAX)	/* max value for a quad_t */
#define	QUAD_MIN	(LONG_MIN)	/* min value for a quad_t */

#endif /* __BSD_VISIBLE */

#endif /* !_MIPS64_LIMITS_H_ */


code:
/*	$OpenBSD: lock.h,v 1.7 2015/02/11 00:14:11 dlg Exp $	*/

/* public domain */

#ifndef	_MIPS64_LOCK_H_
#define	_MIPS64_LOCK_H_

#include <sys/atomic.h>

static __inline int
__cpu_cas(volatile unsigned long *addr, unsigned long old, unsigned long new)
{
	return (atomic_cas_ulong(addr, old, new) != old);
}

#endif	/* _MIPS64_LOCK_H_ */


code:
/*	$OpenBSD: loongson2.h,v 1.4 2013/01/16 20:28:06 miod Exp $	*/

/*
 * Copyright (c) 2009 Miodrag Vallat.
 *
 * Permission to use, copy, modify, and distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#ifndef	_MIPS64_LOONGSON2_H_
#define	_MIPS64_LOONGSON2_H_

/*
 * Loongson 2E/2F specific defines
 */

/*
 * Address Window registers physical addresses
 *
 * The Loongson 2F processor has an AXI crossbar with four possible bus
 * masters, each one having four programmable address windows.
 *
 * Each window is defined with three 64-bit registers:
 * - a base address register, defining the address in the master address
 *   space (base register).
 * - an address mask register, defining which address bits are valid in this
 *   window.  A given address matches a window if (addr & mask) == base.
 * - the location of the window base in the target, as well at the target
 *   number itself (mmap register). The lower 20 bits of the address are
 *   forced as zeroes regardless of their value in this register.
 *   The translated address is thus (addr & ~mask) | (mmap & ~0xfffff).
 */

#define	LOONGSON_AWR_BASE_ADDRESS	0x3ff00000

#define	LOONGSON_AWR_BASE(master, window) \
	(LOONGSON_AWR_BASE_ADDRESS + (window) * 0x08 + (master) * 0x60 + 0x00)
#define	LOONGSON_AWR_SIZE(master, window) \
	(LOONGSON_AWR_BASE_ADDRESS + (window) * 0x08 + (master) * 0x60 + 0x20)
#define	LOONGSON_AWR_MMAP(master, window) \
	(LOONGSON_AWR_BASE_ADDRESS + (window) * 0x08 + (master) * 0x60 + 0x40)

/*
 * Bits in the diagnostic register
 */

#define	COP_0_DIAG_ITLB_CLEAR		0x04
#define	COP_0_DIAG_BTB_CLEAR		0x02
#define	COP_0_DIAG_RAS_DISABLE		0x01

#if defined(_KERNEL) && !defined(_LOCORE)
int	loongson2f_cpuspeed(int *);
void	loongson2f_setperf(int);
#endif

#endif	/* _MIPS64_LOONGSON2_H_ */


code:
/*	$OpenBSD: memconf.h,v 1.7 2011/05/30 22:25:21 oga Exp $	*/

/*
 * Copyright (c) 1996 Per Fogelstrom
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/*
 * Memory config list used by pmap_bootstrap.
 */

#ifndef _MIPS64_MEMCONF_H_
#define _MIPS64_MEMCONF_H_

struct phys_mem_desc {
	uint64_t	mem_first_page;
	uint64_t	mem_last_page;
};

#ifdef _KERNEL
#ifndef	MAXMEMSEGS
#define	MAXMEMSEGS	16
#endif
extern struct phys_mem_desc mem_layout[];
int	memrange_register(uint64_t, uint64_t, uint64_t);
#endif

#endif /* !_MIPS64_MEMCONF_H_ */