code:
/*
 * THIS FILE IS AUTOMATICALLY GENERATED
 * DONT EDIT THIS FILE
 */

/*	$OpenBSD: cn30xxnpireg.h,v 1.1 2011/06/16 11:22:30 syuu Exp $	*/

/*
 * Copyright (c) 2007 Internet Initiative Japan, Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */

/*
 * Cavium Networks OCTEON CN30XX Hardware Reference Manual
 * CN30XX-HM-1.0
 * 9.15 NPI Registers
 */

#ifndef _CN30XXNPIREG_H_
#define _CN30XXNPIREG_H_

#define	MPI_CFG					0x0001070000001000ULL

#define	NPI_RSL_INT_BLOCKS			0x00011f0000000000ULL
#define	NPI_DBG_SELECT				0x00011f0000000008ULL
#define	NPI_CTL_STATUS				0x00011f0000000010ULL
#define	NPI_INT_SUM				0x00011f0000000018ULL
#define	NPI_INT_ENB				0x00011f0000000020ULL
#define	NPI_MEM_ACCESS_SUBID3			0x00011f0000000028ULL
#define	NPI_MEM_ACCESS_SUBID4			0x00011f0000000030ULL
#define	NPI_MEM_ACCESS_SUBID5			0x00011f0000000038ULL
#define	NPI_MEM_ACCESS_SUBID6			0x00011f0000000040ULL
#define	NPI_PCI_READ_CMD			0x00011f0000000048ULL
#define	NPI_NUM_DESC_OUTPUT0			0x00011f0000000050ULL
#define	NPI_BASE_ADDR_INPUT0			0x00011f0000000070ULL
#define	NPI_SIZE_INPUT0				0x00011f0000000078ULL
#define	PCI_READ_TIMEOUT			0x00011f00000000b0ULL
#define	NPI_BASE_ADDR_OUTPUT0			0x00011f00000000b8ULL
#define	NPI_PCI_BURST_SIZE			0x00011f00000000d8ULL
#define	NPI_BUFF_SIZE_OUTPUT0			0x00011f00000000e0ULL
#define	NPI_OUTPUT_CONTROL			0x00011f0000000100ULL
#define	NPI_LOWP_IBUFF_SADDR			0x00011f0000000108ULL
#define	NPI_HIGHP_IBUFF_SADDR			0x00011f0000000110ULL
#define	NPI_LOWP_DBELL				0x00011f0000000118ULL
#define	NPI_HIGHP_DBELL				0x00011f0000000120ULL
#define	NPI_DMA_CONTROL				0x00011f0000000128ULL
#define	NPI_PCI_INT_ARB_CFG			0x00011f0000000130ULL
#define	NPI_INPUT_CONTROL			0x00011f0000000138ULL
#define	NPI_DMA_LOWP_COUNTS			0x00011f0000000140ULL
#define	NPI_DMA_HIGHP_COUNTS			0x00011f0000000148ULL
#define	NPI_DMA_LOWP_NADDR			0x00011f0000000150ULL
#define	NPI_DMA_HIGHP_NADDR			0x00011f0000000158ULL
#define	NPI_P0_PAIR_CNTS			0x00011f0000000160ULL
#define	NPI_P0_DBPAIR_ADDR			0x00011f0000000180ULL
#define	NPI_P0_INSTR_CNTS			0x00011f00000001a0ULL
#define	NPI_P0_INSTR_ADDR			0x00011f00000001c0ULL
#define	NPI_WIN_READ_TO				0x00011f00000001e0ULL
#define	DBG_DATA				0x00011f00000001e8ULL
#define	NPI_PORT_BP_CONTROL			0x00011f00000001f0ULL
#define	NPI_PORT32_INSTR_HDR			0x00011f00000001f8ULL
#define	NPI_BIST_STATUS				0x00011f00000003f8ULL

#define	NPI_MSI_RCV				0x00011f0000001190ULL

#define	NPI_RSL_INT_BLOCKS_XXX_63_31		0xffffffff80000000ULL
#define	NPI_RSL_INT_BLOCKS_IOB			0x0000000040000000ULL
#define	NPI_RSL_INT_BLOCKS_XXX_29_23		0x000000003f800000ULL
#define	NPI_RSL_INT_BLOCKS_ASX0			0x0000000000400000ULL
#define	NPI_RSL_INT_BLOCKS_XXX_21		0x0000000000200000ULL
#define	NPI_RSL_INT_BLOCKS_PIP			0x0000000000100000ULL
#define	NPI_RSL_INT_BLOCKS_XXX_19_18		0x00000000000c0000ULL
#define	NPI_RSL_INT_BLOCKS_LMC			0x0000000000020000ULL
#define	NPI_RSL_INT_BLOCKS_L2C			0x0000000000010000ULL
#define	NPI_RSL_INT_BLOCKS_XXX_15_13		0x000000000000e000ULL
#define	NPI_RSL_INT_BLOCKS_POW			0x0000000000001000ULL
#define	NPI_RSL_INT_BLOCKS_TIM			0x0000000000000800ULL
#define	NPI_RSL_INT_BLOCKS_PKO			0x0000000000000400ULL
#define	NPI_RSL_INT_BLOCKS_IPD			0x0000000000000200ULL
#define	NPI_RSL_INT_BLOCKS_XXX_8_6		0x00000000000001c0ULL
#define	NPI_RSL_INT_BLOCKS_FPA			0x0000000000000020ULL
#define	NPI_RSL_INT_BLOCKS_XXX_4		0x0000000000000010ULL
#define	NPI_RSL_INT_BLOCKS_NPI			0x0000000000000008ULL
#define	NPI_RSL_INT_BLOCKS_GMX1			0x0000000000000004ULL
#define	NPI_RSL_INT_BLOCKS_GMX0			0x0000000000000002ULL
#define	NPI_RSL_INT_BLOCKS_MIO			0x0000000000000001ULL

#define	NPI_DBG_SELECT_XXX_63_16		0xffffffffffff0000ULL
#define	NPI_DBG_SELECT_DBG_SEL			0x000000000000ffffULL

#define	NPI_CTL_STATUS_XXX_63			0x8000000000000000ULL
#define	NPI_DBG_SELECT_DBG_SEL			0x000000000000ffffULL

#define	NPI_CTL_STATUS_XXX_63			0x8000000000000000ULL
#define	NPI_CTL_STATUS_CHIP_REV			0x7f80000000000000ULL
#define	NPI_CTL_STATUS_DIS_PNIW			0x0040000000000000ULL
#define	NPI_CTL_STATUS_SPR5			0x0020000000000000ULL
#define	NPI_CTL_STATUS_SPR4			0x0010000000000000ULL
#define	NPI_CTL_STATUS_SPR8			0x0008000000000000ULL
#define	NPI_CTL_STATUS_OUT0_ENB			0x0004000000000000ULL
#define	NPI_CTL_STATUS_SPR3			0x0002000000000000ULL
#define	NPI_CTL_STATUS_SPR2			0x0001000000000000ULL
#define	NPI_CTL_STATUS_SPR7			0x0000800000000000ULL
#define	NPI_CTL_STATUS_INS0_ENB			0x0000400000000000ULL
#define	NPI_CTL_STATUS_SPR1			0x0000200000000000ULL
#define	NPI_CTL_STATUS_SPR0			0x0000100000000000ULL
#define	NPI_CTL_STATUS_SPR6			0x0000080000000000ULL
#define	NPI_CTL_STATUS_INS0_64B			0x0000040000000000ULL
#define	NPI_CTL_STATUS_PCI_WDIS			0x0000020000000000ULL
#define	NPI_CTL_STATUS_WAIT_COM			0x0000010000000000ULL
#define	NPI_CTL_STATUS_SPARES1			0x000000e000000000ULL
#define	NPI_CTL_STATUS_MAX_WORD			0x0000001f00000000ULL
#define	NPI_CTL_STATUS_SPARES0			0x00000000fffffc00ULL
#define	NPI_CTL_STATUS_TIMER			0x00000000000003ffULL

#define	NPI_INT_SUM_XXX_63_62			0xc000000000000000ULL
#define	NPI_INT_SUM_Q1_A_F			0x2000000000000000ULL
#define	NPI_INT_SUM_Q1_S_E			0x1000000000000000ULL
#define	NPI_INT_SUM_PDF_P_F			0x0800000000000000ULL
#define	NPI_INT_SUM_PDF_P_E			0x0400000000000000ULL
#define	NPI_INT_SUM_PCF_P_F			0x0200000000000000ULL
#define	NPI_INT_SUM_PCF_P_E			0x0100000000000000ULL
#define	NPI_INT_SUM_RDX_S_E			0x0080000000000000ULL
#define	NPI_INT_SUM_RWX_S_E			0x0040000000000000ULL
#define	NPI_INT_SUM_PNC_A_F			0x0020000000000000ULL
#define	NPI_INT_SUM_PNC_S_F			0x0010000000000000ULL
#define	NPI_INT_SUM_COM_A_F			0x0008000000000000ULL
#define	NPI_INT_SUM_COM_S_E			0x0004000000000000ULL
#define	NPI_INT_SUM_Q3_A_F			0x0002000000000000ULL
#define	NPI_INT_SUM_Q3_S_E			0x0001000000000000ULL
#define	NPI_INT_SUM_Q2_A_F			0x0000800000000000ULL
#define	NPI_INT_SUM_Q2_S_E			0x0000400000000000ULL
#define	NPI_INT_SUM_PCR_A_F			0x0000200000000000ULL
#define	NPI_INT_SUM_PCR_S_E			0x0000100000000000ULL
#define	NPI_INT_SUM_FCR_A_F			0x0000080000000000ULL
#define	NPI_INT_SUM_FCR_S_E			0x0000040000000000ULL
#define	NPI_INT_SUM_IOBDMA			0x0000020000000000ULL
#define	NPI_INT_SUM_P_DPERR			0x0000010000000000ULL
#define	NPI_INT_SUM_WIN_RTO			0x0000008000000000ULL
#define	NPI_INT_SUM_SPR17			0x0000004000000000ULL
#define	NPI_INT_SUM_SPR16			0x0000002000000000ULL
#define	NPI_INT_SUM_SPR26			0x0000001000000000ULL
#define	NPI_INT_SUM_IO_PPERR			0x0000000800000000ULL
#define	NPI_INT_SUM_SPR15			0x0000000400000000ULL
#define	NPI_INT_SUM_SPR14			0x0000000200000000ULL
#define	NPI_INT_SUM_SPR25			0x0000000100000000ULL
#define	NPI_INT_SUM_P0_PTOUT			0x0000000080000000ULL
#define	NPI_INT_SUM_SPR13			0x0000000040000000ULL
#define	NPI_INT_SUM_SPR12			0x0000000020000000ULL
#define	NPI_INT_SUM_SPR24			0x0000000010000000ULL
#define	NPI_INT_SUM_P0_PPERR			0x0000000008000000ULL
#define	NPI_INT_SUM_SPR11			0x0000000004000000ULL
#define	NPI_INT_SUM_SPR10			0x0000000002000000ULL
#define	NPI_INT_SUM_SPR23			0x0000000001000000ULL
#define	NPI_INT_SUM_G0_RTOUT			0x0000000000800000ULL
#define	NPI_INT_SUM_SPR9			0x0000000000400000ULL
#define	NPI_INT_SUM_SPR8			0x0000000000200000ULL
#define	NPI_INT_SUM_SPR22			0x0000000000100000ULL
#define	NPI_INT_SUM_P0_PERR			0x0000000000080000ULL
#define	NPI_INT_SUM_SPR7			0x0000000000040000ULL
#define	NPI_INT_SUM_SPR6			0x0000000000020000ULL
#define	NPI_INT_SUM_SPR21			0x0000000000010000ULL
#define	NPI_INT_SUM_P0_RTOUT			0x0000000000008000ULL
#define	NPI_INT_SUM_SPR5			0x0000000000004000ULL
#define	NPI_INT_SUM_SPR4			0x0000000000002000ULL
#define	NPI_INT_SUM_SPR20			0x0000000000001000ULL
#define	NPI_INT_SUM_IO_OVERF			0x0000000000000800ULL
#define	NPI_INT_SUM_SPR3			0x0000000000000400ULL
#define	NPI_INT_SUM_SPR2			0x0000000000000200ULL
#define	NPI_INT_SUM_SPR19			0x0000000000000100ULL
#define	NPI_INT_SUM_IO_RTOUT			0x0000000000000080ULL
#define	NPI_INT_SUM_SPR1			0x0000000000000040ULL
#define	NPI_INT_SUM_SPR0			0x0000000000000020ULL
#define	NPI_INT_SUM_SPR18			0x0000000000000010ULL
#define	NPI_INT_SUM_PO0_2SML			0x0000000000000008ULL
#define	NPI_INT_SUM_PCI_RSL			0x0000000000000004ULL
#define	NPI_INT_SUM_RML_TWO			0x0000000000000002ULL
#define	NPI_INT_SUM_RML_RTO			0x0000000000000001ULL

#define	NPI_INT_ENB_XXX_63_62			0xc000000000000000ULL
#define	NPI_INT_ENB_Q1_A_F			0x2000000000000000ULL
#define	NPI_INT_ENB_Q1_S_E			0x1000000000000000ULL
#define	NPI_INT_ENB_PDF_P_F			0x0800000000000000ULL
#define	NPI_INT_ENB_PDF_P_E			0x0400000000000000ULL
#define	NPI_INT_ENB_PCF_P_F			0x0200000000000000ULL
#define	NPI_INT_ENB_PCF_P_E			0x0100000000000000ULL
#define	NPI_INT_ENB_RDX_S_E			0x0080000000000000ULL
#define	NPI_INT_ENB_RWX_S_E			0x0040000000000000ULL
#define	NPI_INT_ENB_PNC_A_F			0x0020000000000000ULL
#define	NPI_INT_ENB_PNC_S_F			0x0010000000000000ULL
#define	NPI_INT_ENB_COM_A_F			0x0008000000000000ULL
#define	NPI_INT_ENB_COM_S_E			0x0004000000000000ULL
#define	NPI_INT_ENB_Q3_A_F			0x0002000000000000ULL
#define	NPI_INT_ENB_Q3_S_E			0x0001000000000000ULL
#define	NPI_INT_ENB_Q2_A_F			0x0000800000000000ULL
#define	NPI_INT_ENB_Q2_S_E			0x0000400000000000ULL
#define	NPI_INT_ENB_PCR_A_F			0x0000200000000000ULL
#define	NPI_INT_ENB_PCR_S_E			0x0000100000000000ULL
#define	NPI_INT_ENB_FCR_A_F			0x0000080000000000ULL
#define	NPI_INT_ENB_FCR_S_E			0x0000040000000000ULL
#define	NPI_INT_ENB_IOBDMA			0x0000020000000000ULL
#define	NPI_INT_ENB_P_DPERR			0x0000010000000000ULL
#define	NPI_INT_ENB_WIN_RTO			0x0000008000000000ULL
#define	NPI_INT_ENB_SPR17			0x0000004000000000ULL
#define	NPI_INT_ENB_SPR16			0x0000002000000000ULL
#define	NPI_INT_ENB_SPR26			0x0000001000000000ULL
#define	NPI_INT_ENB_IO_PPERR			0x0000000800000000ULL
#define	NPI_INT_ENB_SPR15			0x0000000400000000ULL
#define	NPI_INT_ENB_SPR14			0x0000000200000000ULL
#define	NPI_INT_ENB_SPR25			0x0000000100000000ULL
#define	NPI_INT_ENB_P0_PTOUT			0x0000000080000000ULL
#define	NPI_INT_ENB_SPR13			0x0000000040000000ULL
#define	NPI_INT_ENB_SPR12			0x0000000020000000ULL
#define	NPI_INT_ENB_SPR24			0x0000000010000000ULL
#define	NPI_INT_ENB_P0_PPERR			0x0000000008000000ULL
#define	NPI_INT_ENB_SPR11			0x0000000004000000ULL
#define	NPI_INT_ENB_SPR10			0x0000000002000000ULL
#define	NPI_INT_ENB_SPR23			0x0000000001000000ULL
#define	NPI_INT_ENB_G0_RTOUT			0x0000000000800000ULL
#define	NPI_INT_ENB_SPR9			0x0000000000400000ULL
#define	NPI_INT_ENB_SPR8			0x0000000000200000ULL
#define	NPI_INT_ENB_SPR22			0x0000000000100000ULL
#define	NPI_INT_ENB_P0_PERR			0x0000000000080000ULL
#define	NPI_INT_ENB_SPR7			0x0000000000040000ULL
#define	NPI_INT_ENB_SPR6			0x0000000000020000ULL
#define	NPI_INT_ENB_SPR21			0x0000000000010000ULL
#define	NPI_INT_ENB_P0_RTOUT			0x0000000000008000ULL
#define	NPI_INT_ENB_SPR5			0x0000000000004000ULL
#define	NPI_INT_ENB_SPR4			0x0000000000002000ULL
#define	NPI_INT_ENB_SPR20			0x0000000000001000ULL
#define	NPI_INT_ENB_IO_OVERF			0x0000000000000800ULL
#define	NPI_INT_ENB_SPR3			0x0000000000000400ULL
#define	NPI_INT_ENB_SPR2			0x0000000000000200ULL
#define	NPI_INT_ENB_SPR19			0x0000000000000100ULL
#define	NPI_INT_ENB_IO_RTOUT			0x0000000000000080ULL
#define	NPI_INT_ENB_SPR1			0x0000000000000040ULL
#define	NPI_INT_ENB_SPR0			0x0000000000000020ULL
#define	NPI_INT_ENB_SPR18			0x0000000000000010ULL
#define	NPI_INT_ENB_PO0_2SML			0x0000000000000008ULL
#define	NPI_INT_ENB_PCI_RSL			0x0000000000000004ULL
#define	NPI_INT_ENB_RML_TWO			0x0000000000000002ULL
#define	NPI_INT_ENB_RML_RTO			0x0000000000000001ULL

#define	NPI_MEM_ACCESS_SUBIDX_XXX_63_38		0xffffffc000000000ULL
#define	NPI_MEM_ACCESS_SUBIDX_SHORT		0x0000002000000000ULL
#define	NPI_MEM_ACCESS_SUBIDX_NMERGE		0x0000001000000000ULL
#define	NPI_MEM_ACCESS_SUBIDX_ESR		0x0000000c00000000ULL
#define	NPI_MEM_ACCESS_SUBIDX_ESW		0x0000000300000000ULL
#define	NPI_MEM_ACCESS_SUBIDX_NSR		0x0000000080000000ULL
#define	NPI_MEM_ACCESS_SUBIDX_NSW		0x0000000040000000ULL
#define	NPI_MEM_ACCESS_SUBIDX_ROR		0x0000000020000000ULL
#define	NPI_MEM_ACCESS_SUBIDX_ROW		0x0000000010000000ULL
#define	NPI_MEM_ACCESS_SUBIDX_BA		0x000000000fffffffULL

#define	NPI_PCI_READ_CMD_XXX_63_11		0xfffffffffffff800ULL
#define	NPI_PCI_READ_CMD_CMD_SIZE		0x00000000000007ffULL

#define	NPI_NUM_DESC_OUTPUT0_XXX_63_32		0xffffffff00000000ULL
#define	NPI_NUM_DESC_OUTPUT0_SIZE		0x00000000ffffffffULL

#define	NPI_BASE_ADDR_INPUT0_BADDR		0xfffffffffffffff8ULL
#define	NPI_BASE_ADDR_INPUT0_XXX_2_0		0x0000000000000007ULL

#define	NPI_SIZE_INPUT0_XXX_63_32		0xffffffff00000000ULL
#define	NPI_SIZE_INPUT0_SIZE			0x00000000ffffffffULL

#define	PCI_READ_TIMEOUT_XXX_63_32		0xffffffff00000000ULL
#define	PCI_READ_TIMEOUT_ENB			0x0000000080000000ULL
#define	PCI_READ_TIMEOUT_CNT			0x000000007fffffffULL

#define	NPI_BASE_ADDR_OUTPUT0_BADDR		0xfffffffffffffff8ULL
#define	NPI_BASE_ADDR_OUTPUT0_XXX_2_0		0x0000000000000007ULL

#define	NPI_PCI_BURST_SIZE_XXX_63_14		0xffffffffffffc000ULL
#define	NPI_PCI_BURST_SIZE_WR_BRST		0x0000000000003f80ULL
#define	NPI_PCI_BURST_SIZE_RD_BRST		0x000000000000007fULL

#define	NPI_BUFF_SIZE_OUTPUT0_XXX_63_23		0xffffffffff800000ULL
#define	NPI_BUFF_SIZE_OUTPUT0_ISIZE		0x00000000007f0000ULL
#define	NPI_BUFF_SIZE_OUTPUT0_BSIZE		0x000000000000ffffULL

#define	NPI_OUTPUT_CONTROL_XXX_63_48		0xffff000000000000ULL
#define	NPI_OUTPUT_CONTROL_SPR5			0x0000e00000000000ULL
#define	NPI_OUTPUT_CONTROL_P0_BMODE		0x0000100000000000ULL
#define	NPI_OUTPUT_CONTROL_SPR4			0x00000fff00000000ULL
#define	NPI_OUTPUT_CONTROL_O0_ES		0x00000000c0000000ULL
#define	NPI_OUTPUT_CONTROL_O0_NS		0x0000000020000000ULL
#define	NPI_OUTPUT_CONTROL_O0_RO		0x0000000010000000ULL
#define	NPI_OUTPUT_CONTROL_SPR3			0x000000000e000000ULL
#define	NPI_OUTPUT_CONTROL_O0_CSRM		0x0000000001000000ULL
#define	NPI_OUTPUT_CONTROL_SPR2			0x0000000000f00000ULL
#define	NPI_OUTPUT_CONTROL_SPR1			0x00000000000e0000ULL
#define	NPI_OUTPUT_CONTROL_IPTR_O0		0x0000000000010000ULL
#define	NPI_OUTPUT_CONTROL_SPR0			0x000000000000fff0ULL
#define	NPI_OUTPUT_CONTROL_ESR_SL0		0x000000000000000cULL
#define	NPI_OUTPUT_CONTROL_NSR_SL0		0x0000000000000002ULL
#define	NPI_OUTPUT_CONTROL_ROR_SL0		0x0000000000000001ULL

#define	NPI_LOWP_IBUFF_SADDR_XXX_63_36		0xfffffff000000000ULL
#define	NPI_LOWP_IBUFF_SADDR_SADDR		0x0000000fffffffffULL

#define	NPI_HIGHP_IBUFF_SADDR_XXX_63_36		0xfffffff000000000ULL
#define	NPI_HIGHP_IBUFF_SADDR_SADDR		0x0000000fffffffffULL

#define	NPI_LOWP_DBELL_XXX_63_16		0xffffffffffff0000ULL
#define	NPI_LOWP_DBELL_DBELL			0x000000000000ffffULL

#define	NPI_HIGHP_DBELL_XXX_63_16		0xffffffffffff0000ULL
#define	NPI_HIGHP_DBELL_DBELL			0x000000000000ffffULL

#define	NPI_DMA_CONTROL_XXX_63_36		0xfffffff000000000ULL
#define	NPI_DMA_CONTROL_B0_LEND			0x0000000800000000ULL
#define	NPI_DMA_CONTROL_DWB_DENB		0x0000000400000000ULL
#define	NPI_DMA_CONTROL_DWB_ICHK		0x00000003fe000000ULL
#define	NPI_DMA_CONTROL_FPA_QUE			0x0000000001c00000ULL
#define	NPI_DMA_CONTROL_O_ADD1			0x0000000000200000ULL
#define	NPI_DMA_CONTROL_O_RO			0x0000000000100000ULL
#define	NPI_DMA_CONTROL_O_NS			0x0000000000080000ULL
#define	NPI_DMA_CONTROL_O_ES			0x0000000000060000ULL
#define	NPI_DMA_CONTROL_O_MODE			0x0000000000010000ULL
#define	NPI_DMA_CONTROL_HP_ENB			0x0000000000008000ULL
#define	NPI_DMA_CONTROL_LP_ENB			0x0000000000004000ULL
#define	NPI_DMA_CONTROL_CSIZE			0x0000000000003fffULL

#define	NPI_PCI_INT_ARB_CFG_XXX_63_5		0xffffffffffffffe0ULL
#define	NPI_PCI_INT_ARB_CFG_EN			0x0000000000000010ULL
#define	NPI_PCI_INT_ARB_CFG_PARK_MOD		0x0000000000000008ULL
#define	NPI_PCI_INT_ARB_CFG_PARK_DEV		0x0000000000000007ULL

#define	NPI_INPUT_CONTROL_XXX_63_22		0xffffffffffc00000ULL
#define	NPI_INPUT_CONTROL_PBP_DHI		0x00000000003ffe00ULL
#define	NPI_INPUT_CONTROL_D_NSR			0x0000000000000100ULL
#define	NPI_INPUT_CONTROL_D_ESR			0x00000000000000c0ULL
#define	NPI_INPUT_CONTROL_D_ROR			0x0000000000000020ULL
#define	NPI_INPUT_CONTROL_USE_CSR		0x0000000000000010ULL
#define	NPI_INPUT_CONTROL_NSR			0x0000000000000008ULL
#define	NPI_INPUT_CONTROL_ESR			0x0000000000000006ULL
#define	NPI_INPUT_CONTROL_ROR			0x0000000000000001ULL

#define	NPI_DMA_LOWP_COUNTS_XXX_63_39		0xffffff8000000000ULL
#define	NPI_DMA_LOWP_COUNTS_FCNT		0x0000007f00000000ULL
#define	NPI_DMA_LOWP_COUNTS_DBELL		0x00000000ffffffffULL

#define	NPI_DMA_HIGHP_COUNTS_XXX_63_39		0xffffff8000000000ULL
#define	NPI_DMA_HIGHP_COUNTS_FCNT		0x0000007f00000000ULL
#define	NPI_DMA_HIGHP_COUNTS_DBELL		0x00000000ffffffffULL

#define	NPI_DMA_LOWP_NADDR_XXX_63_40		0xffffff0000000000ULL
#define	NPI_DMA_LOWP_NADDR_STATE		0x000000f000000000ULL
#define	NPI_DMA_LOWP_NADDR_ADDR			0x0000000fffffffffULL

#define	NPI_DMA_HIGHP_NADDR_XXX_63_40		0xffffff0000000000ULL
#define	NPI_DMA_HIGHP_NADDR_STATE		0x000000f000000000ULL
#define	NPI_DMA_HIGHP_NADDR_ADDR		0x0000000fffffffffULL

#define	NPI_P0_PAIR_CNTS_XXX_63_37		0xffffffe000000000ULL
#define	NPI_P0_PAIR_CNTS_FCNT			0xffffffff00000000ULL
#define	NPI_P0_PAIR_CNTS_AVAIL			0x00000000c0000000ULL

#define	NPI_P0_DBPAIR_ADDR_XXX_63		0x8000000000000000ULL
#define	NPI_P0_DBPAIR_ADDR_STATE		0x6000000000000000ULL
#define	NPI_P0_DBPAIR_ADDR_NADDR		0x1fffffffffffffffULL

#define	NPI_P0_INSTR_CNTS_XXX_63_38		0xffffffc000000000ULL
#define	NPI_P0_INSTR_CNTS_FCNT			0x0000003f00000000ULL
#define	NPI_P0_INSTR_CNTS_AVAIL			0x00000000ffffffffULL

#define	NPI_P0_INSTR_ADDR_STATE			0xe000000000000000ULL
#define	NPI_P0_INSTR_ADDR_NADDR			0x1fffffffffffffffULL

#define	NPI_WIN_READ_TO_XXX_63_32		0xffffffff00000000ULL
#define	NPI_WIN_READ_TO_TIME			0x00000000ffffffffULL

#define	DBG_DATA_XXX_63_31			0xffffffff80000000ULL
#define	DBG_DATA_PLL_MUL			0x0000000070000000ULL
#define	DBG_DATA_XXX_27_23			0x000000000f800000ULL
#define	DBG_DATA_C_MUL				0x00000000007c0000ULL
#define	DBG_DATA_DSEL_EXT			0x0000000000020000ULL
#define	DBG_DATA_DATA				0x000000000001ffffULL

#define	NPI_PORT_BP_CONTROL_XXX_63_5		0xffffffffffffffe0ULL
#define	NPI_PORT_BP_CONTROL_BP_ON		0x0000000000000010ULL
#define	NPI_PORT_BP_CONTROL_ENB			0x000000000000000fULL

#define	NPI_PORT32_INSTR_HDR_XXX_63_44		0xfffff00000000000ULL
#define	NPI_PORT32_INSTR_HDR_PBP		0x0000080000000000ULL
#define	NPI_PORT32_INSTR_HDR_XXX_42_38		0x000007c000000000ULL
#define	NPI_PORT32_INSTR_HDR_RPARMODE		0x0000003000000000ULL
#define	NPI_PORT32_INSTR_HDR_XXX_35		0x0000000800000000ULL
#define	NPI_PORT32_INSTR_HDR_RSKP_LEN		0x00000007f0000000ULL
#define	NPI_PORT32_INSTR_HDR_XXX_27_22		0x000000000fc00000ULL
#define	NPI_PORT32_INSTR_HDR_USE_IHDR		0x0000000000200000ULL
#define	NPI_PORT32_INSTR_HDR_XXX_20_16		0x00000000001f0000ULL
#define	NPI_PORT32_INSTR_HDR_PAR_MODE		0x000000000000c000ULL
#define	NPI_PORT32_INSTR_HDR_XXX_13		0x0000000000002000ULL
#define	NPI_PORT32_INSTR_HDR_SKP_LEN		0x0000000000001fc0ULL
#define	NPI_PORT32_INSTR_HDR_XXX_5_0		0x000000000000003fULL

#define	NPI_BIST_STATUS_XXX_63_20		0xfffffffffff00000ULL
#define	NPI_BIST_STATUS_CSR_BS			0x0000000000080000ULL
#define	NPI_BIST_STATUS_DIF_BS			0x0000000000040000ULL
#define	NPI_BIST_STATUS_RDP_BS			0x0000000000020000ULL
#define	NPI_BIST_STATUS_PCNC_BS			0x0000000000010000ULL
#define	NPI_BIST_STATUS_PCN_BS			0x0000000000008000ULL
#define	NPI_BIST_STATUS_RDN_BS			0x0000000000004000ULL
#define	NPI_BIST_STATUS_PCAC_BS			0x0000000000002000ULL
#define	NPI_BIST_STATUS_PCAD_BS			0x0000000000001000ULL
#define	NPI_BIST_STATUS_RDNL_BS			0x0000000000000800ULL
#define	NPI_BIST_STATUS_PGF_BS			0x0000000000000400ULL
#define	NPI_BIST_STATUS_PIG_BS			0x0000000000000200ULL
#define	NPI_BIST_STATUS_POF0_BS			0x0000000000000100ULL
#define	NPI_BIST_STATUS_POF1_BS			0x0000000000000080ULL
#define	NPI_BIST_STATUS_POF2_BS			0x0000000000000040ULL
#define	NPI_BIST_STATUS_POF3_BS			0x0000000000000020ULL
#define	NPI_BIST_STATUS_POS_BS			0x0000000000000010ULL
#define	NPI_BIST_STATUS_NUS_BS			0x0000000000000008ULL
#define	NPI_BIST_STATUS_DOB_BS			0x0000000000000004ULL
#define	NPI_BIST_STATUS_PDF_BS			0x0000000000000002ULL
#define	NPI_BIST_STATUS_DPI_BS			0x0000000000000001ULL

#endif /* _CN30XXNPIREG_H_ */


code:
/*	$OpenBSD: cn30xxpip.c,v 1.4 2014/12/05 15:50:03 mpi Exp $	*/

/*
 * Copyright (c) 2007 Internet Initiative Japan, Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */

#include <sys/param.h>
#include <sys/systm.h>
#include <sys/malloc.h>
#include <sys/socket.h>
#include <sys/syslog.h>
#include <sys/time.h>
#include <net/if.h>
#include <net/if_var.h>

#include <machine/octeonvar.h>

#include <octeon/dev/cn30xxpipreg.h>
#include <octeon/dev/cn30xxpipvar.h>

#ifdef OCTEON_ETH_DEBUG
struct cn30xxpip_softc *__cn30xxpip_softc;

void	cn30xxpip_intr_rml(void *);

void	cn30xxpip_dump(void);
void	cn30xxpip_int_enable(struct cn30xxpip_softc *, int);
#endif

/*
 * register definitions
 */
#define	_ENTRY(x)	{ #x, x##_OFFSET }
#define	_ENTRY_0_3(x) \
	_ENTRY(x## 0), _ENTRY(x## 1), _ENTRY(x## 2), _ENTRY(x## 3)
#define	_ENTRY_0_7(x) \
	_ENTRY(x## 0), _ENTRY(x## 1), _ENTRY(x## 2), _ENTRY(x## 3), \
	_ENTRY(x## 4), _ENTRY(x## 5), _ENTRY(x## 6), _ENTRY(x## 7)
#define	_ENTRY_0_1_2_32(x) \
	_ENTRY(x## 0), _ENTRY(x## 1), _ENTRY(x## 2), _ENTRY(x##32)

struct cn30xxpip_dump_reg_ {
	const char *name;
	size_t	offset;
};

const struct cn30xxpip_dump_reg_ cn30xxpip_dump_stats_[] = {
/* PIP_QOS_DIFF[0-63] */
	_ENTRY_0_1_2_32	(PIP_STAT0_PRT),
	_ENTRY_0_1_2_32	(PIP_STAT1_PRT),
	_ENTRY_0_1_2_32	(PIP_STAT2_PRT),
	_ENTRY_0_1_2_32	(PIP_STAT3_PRT),
	_ENTRY_0_1_2_32	(PIP_STAT4_PRT),
	_ENTRY_0_1_2_32	(PIP_STAT5_PRT),
	_ENTRY_0_1_2_32	(PIP_STAT6_PRT),
	_ENTRY_0_1_2_32	(PIP_STAT7_PRT),
	_ENTRY_0_1_2_32	(PIP_STAT8_PRT),
	_ENTRY_0_1_2_32	(PIP_STAT9_PRT),
/* PIP_TAG_INC[0-63] */
	_ENTRY_0_1_2_32	(PIP_STAT_INB_PKTS),
	_ENTRY_0_1_2_32	(PIP_STAT_INB_OCTS),
	_ENTRY_0_1_2_32	(PIP_STAT_INB_ERRS),
};

const struct cn30xxpip_dump_reg_ cn30xxpip_dump_regs_[] = {
	_ENTRY		(PIP_BIST_STATUS),
	_ENTRY		(PIP_INT_REG),
	_ENTRY		(PIP_INT_EN),
	_ENTRY		(PIP_STAT_CTL),
	_ENTRY		(PIP_GBL_CTL),
	_ENTRY		(PIP_GBL_CFG),
	_ENTRY		(PIP_SOFT_RST),
	_ENTRY		(PIP_IP_OFFSET),
	_ENTRY		(PIP_TAG_SECRET),
	_ENTRY		(PIP_TAG_MASK),
	_ENTRY_0_3	(PIP_DEC_IPSEC),
	_ENTRY		(PIP_RAW_WORD),
	_ENTRY_0_7	(PIP_QOS_VLAN),
	_ENTRY_0_3	(PIP_QOS_WATCH),
	_ENTRY_0_1_2_32	(PIP_PRT_CFG),
	_ENTRY_0_1_2_32	(PIP_PRT_TAG),
};
#undef	_ENTRY
#undef	_ENTRY_0_3
#undef	_ENTRY_0_7
#undef	_ENTRY_0_1_2_32

/* XXX */
void
cn30xxpip_init(struct cn30xxpip_attach_args *aa,
    struct cn30xxpip_softc **rsc)
{
	struct cn30xxpip_softc *sc;
	int status;

	sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
	if (sc == NULL)
		panic("can't allocate memory: %s", __func__);

	sc->sc_port = aa->aa_port;
	sc->sc_regt = aa->aa_regt;
	sc->sc_tag_type = aa->aa_tag_type;
	sc->sc_receive_group = aa->aa_receive_group;
	sc->sc_ip_offset = aa->aa_ip_offset;

	status = bus_space_map(sc->sc_regt, PIP_BASE, PIP_SIZE, 0,
	    &sc->sc_regh);
	if (status != 0)
		panic("can't map %s space", "pip register");

	*rsc = sc;

#ifdef OCTEON_ETH_DEBUG
	cn30xxpip_int_enable(sc, 1);
	__cn30xxpip_softc = sc;
	printf("PIP Code initialized.\n");
#endif
}

#define	_PIP_RD8(sc, off) \
	bus_space_read_8((sc)->sc_regt, (sc)->sc_regh, (off))
#define	_PIP_WR8(sc, off, v) \
	bus_space_write_8((sc)->sc_regt, (sc)->sc_regh, (off), (v))

int
cn30xxpip_port_config(struct cn30xxpip_softc *sc)
{
	uint64_t prt_cfg;
	uint64_t prt_tag;
	uint64_t ip_offset;

	/*
	 * Process the headers and place the IP header in the work queue
	 */
	prt_cfg = 0;
	/* RAWDRP=0; don't allow raw packet drop */
	/* TAGINC=0 */
	SET(prt_cfg, PIP_PRT_CFGN_DYN_RS);
	/* INST_HDR=0 */
	/* GRP_WAT=0 */
	SET(prt_cfg, (sc->sc_port << 24) & PIP_PRT_CFGN_QOS);
	/* QOS_WAT=0 */
	/* SPARE=0 */
	/* QOS_DIFF=0 */
	/* QOS_VLAN=0 */
	SET(prt_cfg, PIP_PRT_CFGN_CRC_EN);
	SET(prt_cfg, (PIP_PORT_CFG_MODE_L2) & PIP_PRT_CFGN_MODE);
	/* SKIP=0 */

	prt_tag = 0;
	SET(prt_tag, PIP_PRT_TAGN_INC_PRT);
	CLR(prt_tag, PIP_PRT_TAGN_IP6_DPRT);
	CLR(prt_tag, PIP_PRT_TAGN_IP4_DPRT);
	CLR(prt_tag, PIP_PRT_TAGN_IP6_SPRT);
	CLR(prt_tag, PIP_PRT_TAGN_IP4_SPRT);
	CLR(prt_tag, PIP_PRT_TAGN_IP6_NXTH);
	CLR(prt_tag, PIP_PRT_TAGN_IP4_PCTL);
	CLR(prt_tag, PIP_PRT_TAGN_IP6_DST);
	CLR(prt_tag, PIP_PRT_TAGN_IP4_SRC);
	CLR(prt_tag, PIP_PRT_TAGN_IP6_SRC);
	CLR(prt_tag, PIP_PRT_TAGN_IP4_DST);
	SET(prt_tag, PIP_PRT_TAGN_TCP6_TAG_ORDERED);
	SET(prt_tag, PIP_PRT_TAGN_TCP4_TAG_ORDERED);
	SET(prt_tag, PIP_PRT_TAGN_IP6_TAG_ORDERED);
	SET(prt_tag, PIP_PRT_TAGN_IP4_TAG_ORDERED);
	SET(prt_tag, PIP_PRT_TAGN_NON_TAG_ORDERED);
	SET(prt_tag, sc->sc_receive_group & PIP_PRT_TAGN_GRP);

	ip_offset = 0;
	SET(ip_offset, (sc->sc_ip_offset / 8) & PIP_IP_OFFSET_MASK_OFFSET);

	_PIP_WR8(sc, PIP_PRT_CFG0_OFFSET + (8 * sc->sc_port), prt_cfg);
	_PIP_WR8(sc, PIP_PRT_TAG0_OFFSET + (8 * sc->sc_port), prt_tag);
	_PIP_WR8(sc, PIP_IP_OFFSET_OFFSET, ip_offset);

	return 0;
}

void
cn30xxpip_prt_cfg_enable(struct cn30xxpip_softc *sc, uint64_t prt_cfg,
    int enable)
{
	uint64_t tmp;

	tmp = _PIP_RD8(sc, PIP_PRT_CFG0_OFFSET + (8 * sc->sc_port));
	if (enable)
		tmp |= prt_cfg;
	else
		tmp &= ~prt_cfg;
	_PIP_WR8(sc, PIP_PRT_CFG0_OFFSET + (8 * sc->sc_port), tmp);
}

void
cn30xxpip_stats(struct cn30xxpip_softc *sc, struct ifnet *ifp, int gmx_port)
{
	const struct cn30xxpip_dump_reg_ *reg;
	uint64_t tmp, pkts, octs;
	uint64_t pip_stat_ctl;

	if (sc == NULL || ifp == NULL)
		panic("%s: invalid argument. sc=%p, ifp=%p\n", __func__,
			sc, ifp);

	if (gmx_port < 0 || gmx_port > 2) {
		printf("%s: invalid gmx_port %d\n", __func__, gmx_port);
		return;
	}

	pip_stat_ctl = _PIP_RD8(sc, PIP_STAT_CTL_OFFSET);
	_PIP_WR8(sc, PIP_STAT_CTL_OFFSET, pip_stat_ctl | PIP_STAT_CTL_RDCLR);
	reg = &cn30xxpip_dump_stats_[gmx_port];
	tmp = _PIP_RD8(sc, reg->offset);
	octs = (tmp & 0x00000000ffffffffULL); /* XXX: no counter in ifp?? */
	pkts = (tmp & 0xffffffff00000000ULL) >> 32;
	ifp->if_iqdrops += pkts;

	_PIP_WR8(sc, PIP_STAT_CTL_OFFSET, pip_stat_ctl);
}

#ifdef OCTEON_ETH_DEBUG
int	cn30xxpip_intr_rml_verbose;

void
cn30xxpip_intr_rml(void *arg)
{
	struct cn30xxpip_softc *sc;
	uint64_t reg;

	sc = __cn30xxpip_softc;
	KASSERT(sc != NULL);
	reg = cn30xxpip_int_summary(sc);
	if (cn30xxpip_intr_rml_verbose)
		printf("%s: PIP_INT_REG=0x%016llx\n", __func__, reg);
}

void	cn30xxpip_dump_regs(void);
void	cn30xxpip_dump_stats(void);

void
cn30xxpip_dump(void)
{
	cn30xxpip_dump_regs();
	cn30xxpip_dump_stats();
}

void
cn30xxpip_dump_regs(void)
{
	struct cn30xxpip_softc *sc = __cn30xxpip_softc;
	const struct cn30xxpip_dump_reg_ *reg;
	uint64_t tmp;
	int i;

	for (i = 0; i < (int)nitems(cn30xxpip_dump_regs_); i++) {
		reg = &cn30xxpip_dump_regs_[i];
		tmp = _PIP_RD8(sc, reg->offset);
		printf("\t%-24s: %16llx\n", reg->name, tmp);
	}
}

void
cn30xxpip_dump_stats(void)
{
	struct cn30xxpip_softc *sc = __cn30xxpip_softc;
	const struct cn30xxpip_dump_reg_ *reg;
	uint64_t tmp;
	int i;
	uint64_t pip_stat_ctl;

	pip_stat_ctl = _PIP_RD8(sc, PIP_STAT_CTL_OFFSET);
	_PIP_WR8(sc, PIP_STAT_CTL_OFFSET, pip_stat_ctl & ~PIP_STAT_CTL_RDCLR);
	for (i = 0; i < (int)nitems(cn30xxpip_dump_stats_); i++) {
		reg = &cn30xxpip_dump_stats_[i];
		tmp = _PIP_RD8(sc, reg->offset);
		printf("\t%-24s: %16llx\n", reg->name, tmp);
	}
	printf("\t%-24s:\n", "PIP_QOS_DIFF[0-63]");
	for (i = 0; i < 64; i++) {
		tmp = _PIP_RD8(sc, PIP_QOS_DIFF0_OFFSET + sizeof(uint64_t) * i);
		printf("%s\t%16llx%s",
		    ((i % 4) == 0) ? "\t" : "",
		    tmp,
		    ((i % 4) == 3) ? "\n" : "");
	}
	printf("\t%-24s:\n", "PIP_TAG_INC[0-63]");
	for (i = 0; i < 64; i++) {
		tmp = _PIP_RD8(sc, PIP_TAG_INC0_OFFSET + sizeof(uint64_t) * i);
		printf("%s\t%16llx%s",
		    ((i % 4) == 0) ? "\t" : "",
		    tmp,
		    ((i % 4) == 3) ? "\n" : "");
	}
	_PIP_WR8(sc, PIP_STAT_CTL_OFFSET, pip_stat_ctl);
}

void
cn30xxpip_int_enable(struct cn30xxpip_softc *sc, int enable)
{
	uint64_t pip_int_xxx = 0;

	SET(pip_int_xxx,
	    PIP_INT_EN_BEPERR |
	    PIP_INT_EN_FEPERR |
	    PIP_INT_EN_SKPRUNT |
	    PIP_INT_EN_BADTAG |
	    PIP_INT_EN_PRTNXA |
	    PIP_INT_EN_PKTDRP);
	_PIP_WR8(sc, PIP_INT_REG_OFFSET, pip_int_xxx);
	_PIP_WR8(sc, PIP_INT_EN_OFFSET, enable ? pip_int_xxx : 0);
}
uint64_t
cn30xxpip_int_summary(struct cn30xxpip_softc *sc)
{
	uint64_t summary;

	summary = _PIP_RD8(sc, PIP_INT_REG_OFFSET);
	_PIP_WR8(sc, PIP_INT_REG_OFFSET, summary);
	return summary;
}
#endif /* OCTEON_ETH_DEBUG */

license: unknown


code:
/*
 * THIS FILE IS AUTOMATICALLY GENERATED
 * DONT EDIT THIS FILE
 */

/*	$OpenBSD: cn30xxpipreg.h,v 1.2 2014/08/11 18:29:56 miod Exp $	*/

/*
 * Copyright (c) 2007 Internet Initiative Japan, Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */

/*
 * Cavium Networks OCTEON CN30XX Hardware Reference Manual
 * CN30XX-HM-1.0
 * 7.8 PIP Registers
 */

#ifndef _CN30XXPIPREG_H_
#define _CN30XXPIPREG_H_

#define	PIP_BIST_STATUS				0x00011800a0000000ULL
#define	PIP_INT_REG				0x00011800a0000008ULL
#define	PIP_INT_EN				0x00011800a0000010ULL
#define	PIP_STAT_CTL				0x00011800a0000018ULL
#define	PIP_GBL_CTL				0x00011800a0000020ULL
#define	PIP_GBL_CFG				0x00011800a0000028ULL
#define	PIP_SOFT_RST				0x00011800a0000030ULL
#define	PIP_IP_OFFSET				0x00011800a0000060ULL
#define	PIP_TAG_SECRET				0x00011800a0000068ULL
#define	PIP_TAG_MASK				0x00011800a0000070ULL
#define	PIP_DEC_IPSEC0				0x00011800a0000080ULL
#define	PIP_DEC_IPSEC1				0x00011800a0000088ULL
#define	PIP_DEC_IPSEC2				0x00011800a0000090ULL
#define	PIP_DEC_IPSEC3				0x00011800a0000098ULL
#define	PIP_RAW_WORD				0x00011800a00000b0ULL
#define	PIP_QOS_VLAN0				0x00011800a00000c0ULL
#define	PIP_QOS_VLAN1				0x00011800a00000c8ULL
#define	PIP_QOS_VLAN2				0x00011800a00000d0ULL
#define	PIP_QOS_VLAN3				0x00011800a00000d8ULL
#define	PIP_QOS_VLAN4				0x00011800a00000e0ULL
#define	PIP_QOS_VLAN5				0x00011800a00000e8ULL
#define	PIP_QOS_VLAN6				0x00011800a00000f0ULL
#define	PIP_QOS_VLAN7				0x00011800a00000f8ULL
#define	PIP_QOS_WATCH0				0x00011800a0000100ULL
#define	PIP_QOS_WATCH1				0x00011800a0000108ULL
#define	PIP_QOS_WATCH2				0x00011800a0000110ULL
#define	PIP_QOS_WATCH3				0x00011800a0000118ULL
#define	PIP_PRT_CFG0				0x00011800a0000200ULL
#define	PIP_PRT_CFG1				0x00011800a0000208ULL
#define	PIP_PRT_CFG2				0x00011800a0000210ULL
#define	PIP_PRT_CFG32				0x00011800a0000300ULL
#define	PIP_PRT_TAG0				0x00011800a0000400ULL
#define	PIP_PRT_TAG1				0x00011800a0000408ULL
#define	PIP_PRT_TAG2				0x00011800a0000410ULL
#define	PIP_PRT_TAG32				0x00011800a0000500ULL
#define	PIP_QOS_DIFF0				0x00011800a0000600ULL
/* PIP_QOS_DIFF[1-63] */
/* PIP_STAT[0-9]_PRT{0,1,2,32} */
#define	PIP_STAT0_PRT0				0x00011800a0000800ULL
#define	PIP_STAT0_PRT1				0x00011800a0000850ULL
#define	PIP_STAT0_PRT2				0x00011800a00008a0ULL
#define	PIP_STAT0_PRT32				0x00011800a0001200ULL
#define	PIP_TAG_INC0				0x00011800a0001800ULL
/* PIP_TAG_INC[1-63] */
#define	PIP_STAT_INB_PKTS0			0x00011800a0001a00ULL
#define	PIP_STAT_INB_PKTS1			0x00011800a0001a20ULL
#define	PIP_STAT_INB_PKTS2			0x00011800a0001a40ULL
#define	PIP_STAT_INB_PKTS32			0x00011800a0001e00ULL
#define	PIP_STAT_INB_OCTS0			0x00011800a0001a08ULL
#define	PIP_STAT_INB_OCTS1			0x00011800a0001a28ULL
#define	PIP_STAT_INB_OCTS2			0x00011800a0001a48ULL
#define	PIP_STAT_INB_OCTS32			0x00011800a0001e08ULL
#define	PIP_STAT_INB_ERRS0			0x00011800a0001a10ULL
#define	PIP_STAT_INB_ERRS1			0x00011800a0001a30ULL
#define	PIP_STAT_INB_ERRS2			0x00011800a0001a50ULL
#define	PIP_STAT_INB_ERRS32			0x00011800a0001e10ULL

#define PIP_BASE 0x00011800a0000000ULL
#define PIP_SIZE 0x1e50ULL

#define	PIP_BIST_STATUS_OFFSET				0x0ULL
#define	PIP_INT_REG_OFFSET				0x8ULL
#define	PIP_INT_EN_OFFSET				0x10ULL
#define	PIP_STAT_CTL_OFFSET				0x18ULL
#define	PIP_GBL_CTL_OFFSET				0x20ULL
#define	PIP_GBL_CFG_OFFSET				0x28ULL
#define	PIP_SOFT_RST_OFFSET				0x30ULL
#define	PIP_IP_OFFSET_OFFSET				0x60ULL
#define	PIP_TAG_SECRET_OFFSET				0x68ULL
#define	PIP_TAG_MASK_OFFSET				0x70ULL
#define	PIP_DEC_IPSEC0_OFFSET				0x80ULL
#define	PIP_DEC_IPSEC1_OFFSET				0x88ULL
#define	PIP_DEC_IPSEC2_OFFSET				0x90ULL
#define	PIP_DEC_IPSEC3_OFFSET				0x98ULL
#define	PIP_RAW_WORD_OFFSET				0xb0ULL
#define	PIP_QOS_VLAN0_OFFSET				0xc0ULL
#define	PIP_QOS_VLAN1_OFFSET				0xc8ULL
#define	PIP_QOS_VLAN2_OFFSET				0xd0ULL
#define	PIP_QOS_VLAN3_OFFSET				0xd8ULL
#define	PIP_QOS_VLAN4_OFFSET				0xe0ULL
#define	PIP_QOS_VLAN5_OFFSET				0xe8ULL
#define	PIP_QOS_VLAN6_OFFSET				0xf0ULL
#define	PIP_QOS_VLAN7_OFFSET				0xf8ULL
#define	PIP_QOS_WATCH0_OFFSET				0x100ULL
#define	PIP_QOS_WATCH1_OFFSET				0x108ULL
#define	PIP_QOS_WATCH2_OFFSET				0x110ULL
#define	PIP_QOS_WATCH3_OFFSET				0x118ULL
#define	PIP_PRT_CFG0_OFFSET				0x200ULL
#define	PIP_PRT_CFG1_OFFSET				0x208ULL
#define	PIP_PRT_CFG2_OFFSET				0x210ULL
#define	PIP_PRT_CFG32_OFFSET				0x300ULL
#define	PIP_PRT_TAG0_OFFSET				0x400ULL
#define	PIP_PRT_TAG1_OFFSET				0x408ULL
#define	PIP_PRT_TAG2_OFFSET				0x410ULL
#define	PIP_PRT_TAG32_OFFSET				0x500ULL
#define	PIP_QOS_DIFF0_OFFSET				0x600ULL
/* PIP_QOS_DIFF[1-63] */
#define	PIP_STAT0_PRT0_OFFSET				0x800ULL
#define	PIP_STAT0_PRT1_OFFSET				0x850ULL
#define	PIP_STAT0_PRT2_OFFSET				0x8a0ULL
#define	PIP_STAT0_PRT32_OFFSET				0x1200ULL
#define	PIP_STAT0_PRT33_OFFSET				0x1250ULL
#define	PIP_STAT1_PRT0_OFFSET				0x800ULL
#define	PIP_STAT1_PRT1_OFFSET				0x850ULL
#define	PIP_STAT1_PRT2_OFFSET				0x8a0ULL
#define	PIP_STAT1_PRT32_OFFSET				0x1200ULL
#define	PIP_STAT1_PRT33_OFFSET				0x1250ULL
#define	PIP_STAT2_PRT0_OFFSET				0x810ULL
#define	PIP_STAT2_PRT1_OFFSET				0x860ULL
#define	PIP_STAT2_PRT2_OFFSET				0x8b0ULL
#define	PIP_STAT2_PRT32_OFFSET				0x1210ULL
#define	PIP_STAT2_PRT33_OFFSET				0x1260ULL
#define	PIP_STAT3_PRT0_OFFSET				0x818ULL
#define	PIP_STAT3_PRT1_OFFSET				0x868ULL
#define	PIP_STAT3_PRT2_OFFSET				0x8b8ULL
#define	PIP_STAT3_PRT32_OFFSET				0x1218ULL
#define	PIP_STAT3_PRT33_OFFSET				0x1268ULL
#define	PIP_STAT4_PRT0_OFFSET				0x820ULL
#define	PIP_STAT4_PRT1_OFFSET				0x870ULL
#define	PIP_STAT4_PRT2_OFFSET				0x8c0ULL
#define	PIP_STAT4_PRT32_OFFSET				0x1220ULL
#define	PIP_STAT4_PRT33_OFFSET				0x1270ULL
#define	PIP_STAT5_PRT0_OFFSET				0x828ULL
#define	PIP_STAT5_PRT1_OFFSET				0x878ULL
#define	PIP_STAT5_PRT2_OFFSET				0x8c8ULL
#define	PIP_STAT5_PRT32_OFFSET				0x1228ULL
#define	PIP_STAT5_PRT33_OFFSET				0x1278ULL
#define	PIP_STAT6_PRT0_OFFSET				0x830ULL
#define	PIP_STAT6_PRT1_OFFSET				0x880ULL
#define	PIP_STAT6_PRT2_OFFSET				0x8d0ULL
#define	PIP_STAT6_PRT32_OFFSET				0x1238ULL
#define	PIP_STAT6_PRT33_OFFSET				0x1288ULL
#define	PIP_STAT7_PRT0_OFFSET				0x838ULL
#define	PIP_STAT7_PRT1_OFFSET				0x888ULL
#define	PIP_STAT7_PRT2_OFFSET				0x8d8ULL
#define	PIP_STAT7_PRT32_OFFSET				0x1238ULL
#define	PIP_STAT7_PRT33_OFFSET				0x1288ULL
#define	PIP_STAT8_PRT0_OFFSET				0x840ULL
#define	PIP_STAT8_PRT1_OFFSET				0x890ULL
#define	PIP_STAT8_PRT2_OFFSET				0x8e0ULL
#define	PIP_STAT8_PRT32_OFFSET				0x1240ULL
#define	PIP_STAT8_PRT33_OFFSET				0x1290ULL
#define	PIP_STAT9_PRT0_OFFSET				0x848ULL
#define	PIP_STAT9_PRT1_OFFSET				0x898ULL
#define	PIP_STAT9_PRT2_OFFSET				0x8e8ULL
#define	PIP_STAT9_PRT32_OFFSET				0x1248ULL
#define	PIP_STAT9_PRT33_OFFSET				0x1298ULL
#define	PIP_TAG_INC0_OFFSET				0x1800ULL
/* PIP_TAG_INC[1-63] */
#define	PIP_STAT_INB_PKTS0_OFFSET			0x1a00ULL
#define	PIP_STAT_INB_PKTS1_OFFSET			0x1a20ULL
#define	PIP_STAT_INB_PKTS2_OFFSET			0x1a40ULL
#define	PIP_STAT_INB_PKTS32_OFFSET			0x1e00ULL
#define	PIP_STAT_INB_OCTS0_OFFSET			0x1a08ULL
#define	PIP_STAT_INB_OCTS1_OFFSET			0x1a28ULL
#define	PIP_STAT_INB_OCTS2_OFFSET			0x1a48ULL
#define	PIP_STAT_INB_OCTS32_OFFSET			0x1e08ULL
#define	PIP_STAT_INB_ERRS0_OFFSET			0x1a10ULL
#define	PIP_STAT_INB_ERRS1_OFFSET			0x1a30ULL
#define	PIP_STAT_INB_ERRS2_OFFSET			0x1a50ULL
#define	PIP_STAT_INB_ERRS32_OFFSET			0x1e10ULL
#define	PIP_STAT_INB_ERRS33_OFFSET			0x1e30ULL

/*
 * PIP_BIST_STATUS
 */
#define	PIP_BIST_STATUS_63_13			0xfffffffffffc0000ULL
#define	PIP_BIST_STATUS_BIST			0x000000000003ffffULL

/*
 * PIP_INT_REG
 */
#define	PIP_INT_REG_63_9			0xfffffffffffffe00ULL
#define	PIP_INT_REG_BEPERR			0x0000000000000100ULL
#define	PIP_INT_REG_FEPERR			0x0000000000000080ULL
#define	PIP_INT_REG_6				0x0000000000000040ULL
#define	PIP_INT_REG_SKPRUNT			0x0000000000000020ULL
#define	PIP_INT_REG_BADTAG			0x0000000000000010ULL
#define	PIP_INT_REG_PRTNXA			0x0000000000000008ULL
#define	PIP_INT_REG_2_1				0x00000006
#define	PIP_INT_REG_PKTDRP			0x00000001

/*
 * PIP_INT_EN
 */
#define	PIP_INT_EN_63_9				0xfffffffffffffe00ULL
#define	PIP_INT_EN_BEPERR			0x0000000000000100ULL
#define	PIP_INT_EN_FEPERR			0x0000000000000080ULL
#define	PIP_INT_EN_6				0x0000000000000040ULL
#define	PIP_INT_EN_SKPRUNT			0x0000000000000020ULL
#define	PIP_INT_EN_BADTAG			0x0000000000000010ULL
#define	PIP_INT_EN_PRTNXA			0x0000000000000008ULL
#define	PIP_INT_EN_2_1				0x00000006
#define	PIP_INT_EN_PKTDRP			0x00000001

/*
 * PIP_STAT_CTL
 */
#define	PIP_STAT_CTL_63_1			0xfffffffffffffffeULL
#define	PIP_STAT_CTL_RDCLR			0x0000000000000001ULL

/*
 * PIP_GBL_CTL
 */
#define	PIP_GBL_CTL_63_17			0xfffffffffffe0000ULL
#define	PIP_GBL_CTL_IGNRS			0x0000000000010000ULL
#define	PIP_GBL_CTL_VS_WQE			0x0000000000008000ULL
#define	PIP_GBL_CTL_VS_QOS			0x0000000000004000ULL
#define	PIP_GBL_CTL_L2MAL			0x0000000000002000ULL
#define	PIP_GBL_CTL_TCP_FLAG			0x0000000000001000ULL
#define	PIP_GBL_CTL_L4_LEN			0x0000000000000800ULL
#define	PIP_GBL_CTL_L4_CHK			0x0000000000000400ULL
#define	PIP_GBL_CTL_L4_PRT			0x0000000000000200ULL
#define	PIP_GBL_CTL_L4_MAL			0x0000000000000100ULL
#define	PIP_GBL_CTL_7_6				0x00000000000000c0ULL
#define	PIP_GBL_CTL_IP6_EEXT			0x0000000000000030ULL
#define	PIP_GBL_CTL_IP4_OPTS			0x0000000000000008ULL
#define	PIP_GBL_CTL_IP_HOP			0x0000000000000004ULL
#define	PIP_GBL_CTL_IP_MAL			0x0000000000000002ULL
#define	PIP_GBL_CTL_IP_CHK			0x0000000000000001ULL

/*
 * PIP_GBL_CFG
 */
/* XXX CN30XX-HM-1.0 says 63_17 is reserved */
#define	PIP_GBL_CFG_63_19			0xfffffffffff80000ULL
#define	PIP_GBL_CFG_TAG_SYN			0x0000000000040000ULL
#define	PIP_GBL_CFG_IP6_UDP			0x0000000000020000ULL
#define	PIP_GBL_CFG_MAX_L2			0x0000000000010000ULL
#define	PIP_GBL_CFG_15_11			0x000000000000f800ULL
#define	PIP_GBL_CFG_RAW_SHF			0x0000000000000700ULL
#define	PIP_GBL_CFG_7_3				0x00000000000000f8ULL
#define	PIP_GBL_CFG_NIP_SHF			0x0000000000000007ULL

/*
 * PIP_SFT_RST
 */
#define	PIP_SFT_RST_63_17			0xfffffffffffffffeULL
#define	PIP_SFT_RST_RST				0x0000000000000001ULL

/*
 * PIP_IP_OFFSET
 */
#define	PIP_IP_OFFSET_63_3			0xfffffffffffffff8ULL
/* PIP_IP_OFFSET_OFFSET is defined above - conflict! */
#define	PIP_IP_OFFSET_MASK_OFFSET		0x0000000000000007ULL

/*
 * PIP_TAG_SECRET
 */
#define	PIP_TAG_SECRET_63_3			0xffffffff00000000ULL
#define	PIP_TAG_SECRET_DST			0x00000000ffff0000ULL
#define	PIP_TAG_SECRET_SRC			0x000000000000ffffULL

/*
 * PIP_TAG_MASK
 */
#define	PIP_TAG_MASK_63_16			0xffffffffffff0000ULL
#define	PIP_TAG_MASK_MASK			0x000000000000ffffULL

/*
 * PIP_DEC_IPSECN
 */
#define	PIP_DEC_IPSECN_63_18			0xfffffffffffc0000ULL
#define	PIP_DEC_IPSECN_TCP			0x0000000000020000ULL
#define	PIP_DEC_IPSECN_UDP			0x0000000000010000ULL
#define	PIP_DEC_IPSECN_DPRT			0x000000000000ffffULL

/*
 * PIP_RAW_WORD
 */
#define	PIP_RAW_WORD_63_56			0xff00000000000000ULL
#define	PIP_RAW_WORD_WORD			0x00ffffffffffffffULL

/*
 * PIP_QOS_VLAN
 */
#define	PIP_QOS_VLAN_63_3			0xfffffffffffffff8ULL
#define	PIP_QOS_VLAN_QOS			0x0000000000000007ULL

/*
 * PIP_QOS_WATCHN
 */
#define	PIP_QOS_WATCHN_63_48			0xffff000000000000ULL
#define	PIP_QOS_WATCHN_MASK			0x0000ffff00000000ULL
#define	PIP_QOS_WATCHN_31_28			0x00000000f0000000ULL
#define	PIP_QOS_WATCHN_GRP			0x000000000f000000ULL
#define	PIP_QOS_WATCHN_23			0x0000000000800000ULL
#define	PIP_QOS_WATCHN_WATCHER			0x0000000000700000ULL
#define	PIP_QOS_WATCHN_19_18			0x00000000000c0000ULL
#define	PIP_QOS_WATCHN_TYPE			0x0000000000030000ULL
#define	PIP_QOS_WATCHN_15_0			0x000000000000ffffULL

/*
 * PIP_PRT_CFGN
 */
#define	PIP_PRT_CFGN_63_37			0xffffffe000000000ULL
#define	PIP_PRT_CFGN_RAWDRP			0x0000001000000000ULL
#define	PIP_PRT_CFGN_TAG_INC			0x0000000c00000000ULL
#define	PIP_PRT_CFGN_DYN_RS			0x0000000200000000ULL
#define	PIP_PRT_CFGN_INST_HDR			0x0000000100000000ULL
#define	PIP_PRT_CFGN_GRP_WAT			0x00000000f0000000ULL
#define	PIP_PRT_CFGN_27				0x0000000008000000ULL
#define	PIP_PRT_CFGN_QOS			0x0000000007000000ULL
#define	PIP_PRT_CFGN_QOS_WAT			0x0000000000f00000ULL
#define	PIP_PRT_CFGN_19				0x0000000000080000ULL
#define	PIP_PRT_CFGN_SPARE			0x0000000000040000ULL
#define	PIP_PRT_CFGN_QOS_DIFF			0x0000000000020000ULL
#define	PIP_PRT_CFGN_QOS_VLAN			0x0000000000010000ULL
#define	PIP_PRT_CFGN_15_13			0x000000000000e000ULL
#define	PIP_PRT_CFGN_CRC_EN			0x0000000000001000ULL
#define	PIP_PRT_CFGN_11_10			0x0000000000000c00ULL
#define	PIP_PRT_CFGN_MODE			0x0000000000000300ULL
#define	 PIP_PRT_CFGN_MODE_SHIFT		8
#define   PIP_PORT_CFG_MODE_NONE		(0ULL << PIP_PRT_CFGN_MODE_SHIFT)
#define   PIP_PORT_CFG_MODE_L2			(1ULL << PIP_PRT_CFGN_MODE_SHIFT)
#define   PIP_PORT_CFG_MODE_IP			(2ULL << PIP_PRT_CFGN_MODE_SHIFT)
#define   PIP_PORT_CFG_MODE_PCI			(3ULL << PIP_PRT_CFGN_MODE_SHIFT)
#define	PIP_PRT_CFGN_7				0x0000000000000080ULL
#define	PIP_PRT_CFGN_SKIP			0x000000000000007fULL

/*
 * PIP_PRT_TAGN
 */
#define	PIP_PRT_TAGN_63_40			0xffffff0000000000ULL
#define	PIP_PRT_TAGN_GRPTAGBASE			0x000000f000000000ULL
#define	PIP_PRT_TAGN_GRPTAGMASK			0x0000000f00000000ULL
#define	PIP_PRT_TAGN_GRPTAG			0x0000000080000000ULL
#define	PIP_PRT_TAGN_SPARE			0x0000000040000000ULL
#define	PIP_PRT_TAGN_TAG_MODE			0x0000000030000000ULL
#define	PIP_PRT_TAGN_INC_VS			0x000000000c000000ULL
#define	PIP_PRT_TAGN_INC_VLAN			0x0000000002000000ULL
#define	PIP_PRT_TAGN_INC_PRT			0x0000000001000000ULL
#define	PIP_PRT_TAGN_IP6_DPRT			0x0000000000800000ULL
#define	PIP_PRT_TAGN_IP4_DPRT			0x0000000000400000ULL
#define	PIP_PRT_TAGN_IP6_SPRT			0x0000000000200000ULL
#define	PIP_PRT_TAGN_IP4_SPRT			0x0000000000100000ULL
#define	PIP_PRT_TAGN_IP6_NXTH			0x0000000000080000ULL
#define	PIP_PRT_TAGN_IP4_PCTL			0x0000000000040000ULL
#define	PIP_PRT_TAGN_IP6_DST			0x0000000000020000ULL
#define	PIP_PRT_TAGN_IP4_SRC			0x0000000000010000ULL
#define	PIP_PRT_TAGN_IP6_SRC			0x0000000000008000ULL
#define	PIP_PRT_TAGN_IP4_DST			0x0000000000004000ULL
#define	PIP_PRT_TAGN_TCP6_TAG			0x0000000000003000ULL
#define	 PIP_PRT_TAGN_TCP6_TAG			0x0000000000003000ULL
#define	  PIP_PRT_TAGN_TCP6_TAG_SHIFT		12
#define	   PIP_PRT_TAGN_TCP6_TAG_ORDERED	(0ULL << PIP_PRT_TAGN_TCP6_TAG_SHIFT)
#define	   PIP_PRT_TAGN_TCP6_TAG_ATOMIC		(1ULL << PIP_PRT_TAGN_TCP6_TAG_SHIFT)
#define	   PIP_PRT_TAGN_TCP6_TAG_NULL		(2ULL << PIP_PRT_TAGN_TCP6_TAG_SHIFT)
#define	   PIP_PRT_TAGN_TCP6_TAG_XXX_3		(3ULL << PIP_PRT_TAGN_TCP6_TAG_SHIFT)
#define	PIP_PRT_TAGN_TCP4_TAG			0x0000000000000c00ULL
#define	  PIP_PRT_TAGN_TCP4_TAG_SHIFT		10
#define	   PIP_PRT_TAGN_TCP4_TAG_ORDERED	(0ULL << PIP_PRT_TAGN_TCP4_TAG_SHIFT)
#define	   PIP_PRT_TAGN_TCP4_TAG_ATOMIC		(1ULL << PIP_PRT_TAGN_TCP4_TAG_SHIFT)
#define	   PIP_PRT_TAGN_TCP4_TAG_NULL		(2ULL << PIP_PRT_TAGN_TCP4_TAG_SHIFT)
#define	   PIP_PRT_TAGN_TCP4_TAG_XXX_3		(3ULL << PIP_PRT_TAGN_TCP4_TAG_SHIFT)
#define	PIP_PRT_TAGN_IP6_TAG			0x0000000000000300ULL
#define	  PIP_PRT_TAGN_IP6_TAG_SHIFT		8
#define	   PIP_PRT_TAGN_IP6_TAG_ORDERED		(0ULL << PIP_PRT_TAGN_IP6_TAG_SHIFT)
#define	   PIP_PRT_TAGN_IP6_TAG_ATOMIC		(1ULL << PIP_PRT_TAGN_IP6_TAG_SHIFT)
#define	   PIP_PRT_TAGN_IP6_TAG_NULL		(2ULL << PIP_PRT_TAGN_IP6_TAG_SHIFT)
#define	   PIP_PRT_TAGN_IP6_TAG_XXX_3		(3ULL << PIP_PRT_TAGN_IP6_TAG_SHIFT)
#define	PIP_PRT_TAGN_IP4_TAG			0x00000000000000c0ULL
#define	  PIP_PRT_TAGN_IP4_TAG_SHIFT		6
#define	   PIP_PRT_TAGN_IP4_TAG_ORDERED		(0ULL << PIP_PRT_TAGN_IP4_TAG_SHIFT)
#define	   PIP_PRT_TAGN_IP4_TAG_ATOMIC		(1ULL << PIP_PRT_TAGN_IP4_TAG_SHIFT)
#define	   PIP_PRT_TAGN_IP4_TAG_NULL		(2ULL << PIP_PRT_TAGN_IP4_TAG_SHIFT)
#define	   PIP_PRT_TAGN_IP4_TAG_XXX_3		(3ULL << PIP_PRT_TAGN_IP4_TAG_SHIFT)
#define	PIP_PRT_TAGN_NON_TAG			0x0000000000000030ULL
#define	  PIP_PRT_TAGN_NON_TAG_SHIFT		4
#define	   PIP_PRT_TAGN_NON_TAG_ORDERED		(0ULL << PIP_PRT_TAGN_NON_TAG_SHIFT)
#define	   PIP_PRT_TAGN_NON_TAG_ATOMIC		(1ULL << PIP_PRT_TAGN_NON_TAG_SHIFT)
#define	   PIP_PRT_TAGN_NON_TAG_NULL		(2ULL << PIP_PRT_TAGN_NON_TAG_SHIFT)
#define	   PIP_PRT_TAGN_NON_TAG_XXX_3		(3ULL << PIP_PRT_TAGN_NON_TAG_SHIFT)
#define	PIP_PRT_TAGN_GRP			0x000000000000000fULL

/*
 * PIP_QOS_DIFFN
 */
#define	PIP_QOS_DIFF_63_3			0xfffffffffffffff8ULL
#define	PIP_QOS_DIFF_QOS			0x0000000000000007ULL

/*
 * PIP_TAG_INCN
 */
#define	PIP_TAG_INCN_63_8			0xffffffffffffff00ULL
#define	PIP_TAG_INCN_EN				0x00000000000000ffULL

/*
 * PIP_STAT0_PRTN
 */
#define	PIP_STAT0_PRTN_DRP_PKTS			0xffffffff00000000ULL
#define	PIP_STAT0_PRTN_DRP_OCTS			0x00000000ffffffffULL

/*
 * PIP_STAT1_PRTN
 */
#define	PIP_STAT1_PRTN_63_48			0xffff000000000000ULL
#define	PIP_STAT1_PRTN_OCTS			0x0000ffffffffffffULL

/*
 * PIP_STAT2_PRTN
 */
#define	PIP_STAT2_PRTN_PKTS			0xffffffff00000000ULL
#define	PIP_STAT2_PRTN_RAW			0x00000000ffffffffULL

/*
 * PIP_STAT3_PRTN
 */
#define	PIP_STAT3_PRTN_BCST			0xffffffff00000000ULL
#define	PIP_STAT3_PRTN_MCST			0x00000000ffffffffULL

/*
 * PIP_STAT4_PRTN
 */
#define	PIP_STAT4_PRTN_H65TO127			0xffffffff00000000ULL
#define	PIP_STAT4_PRTN_H64			0x00000000ffffffffULL

/*
 * PIP_STAT5_PRTN
 */
#define	PIP_STAT5_PRTN_H256TO511		0xffffffff00000000ULL
#define	PIP_STAT5_PRTN_H128TO255		0x00000000ffffffffULL

/*
 * PIP_STAT6_PRTN
 */
#define	PIP_STAT6_PRTN_H1024TO1518		0xffffffff00000000ULL
#define	PIP_STAT6_PRTN_H512TO1023		0x00000000ffffffffULL

/*
 * PIP_STAT7_PRTN
 */
#define	PIP_STAT7_PRTN_FCS			0xffffffff00000000ULL
#define	PIP_STAT7_PRTN_H1519			0x00000000ffffffffULL

/*
 * PIP_STAT8_PRTN
 */
#define	PIP_STAT8_PRTN_FRAG			0xffffffff00000000ULL
#define	PIP_STAT8_PRTN_UNDERSZ			0x00000000ffffffffULL

/*
 * PIP_STAT9_PRTN
 */
#define	PIP_STAT9_PRTN_JABBER			0xffffffff00000000ULL
#define	PIP_STAT9_PRTN_OVERSZ			0x00000000ffffffffULL

/*
 * PIP_STAT_INB_PKTN
 */
#define	PIP_STAT_INB_PKTSN			0xffffffff00000000ULL
#define	PIP_STAT_INB_PKTSN_PKTS			0x00000000ffffffffULL

/*
 * PIP_STAT_INB_OCTSN
 */
#define	PIP_STAT_INB_OCTSN			0xffff000000000000ULL
#define	PIP_STAT_INB_OCTSN_OCTS			0x0000ffffffffffffULL

/*
 * PIP_STAT_INB_ERRS
 */
#define	PIP_STAT_INB_ERRSN			0xffffffffffff0000ULL
#define	PIP_STAT_INB_ERRSN_OCTS			0x000000000000ffffULL

/*
 * Work-Queue Entry Format
 */
/* WORD0 */
#define PIP_WQE_WORD0_HW_CSUM			0xffff000000000000ULL
#define PIP_WQE_WORD0_47_40			0x0000ff0000000000ULL
#define PIP_WQE_WORD0_POW_NEXT_PTR		0x000000ffffffffffULL

/* WORD 1 */
#define PIP_WQE_WORD1_LEN			0xffff000000000000ULL
#define PIP_WQE_WORD1_IPRT			0x0000fc0000000000ULL
#define PIP_WQE_WORD1_QOS			0x0000038000000000ULL
#define PIP_WQE_WORD1_GRP			0x0000007800000000ULL
#define PIP_WQE_WORD1_TT			0x0000000700000000ULL
#define PIP_WQE_WORD1_TAG			0x00000000ffffffffULL

/* WORD 2 */
#define PIP_WQE_WORD2_RAWFULL_BUFS		0xff00000000000000ULL
#define PIP_WQE_WORD2_RAWFULL_PIP_RAW_WORD	0x00ffffffffffffffULL

#define PIP_WQE_WORD2_IP_BUFS			0xff00000000000000ULL
#define PIP_WQE_WORD2_IP_OFFSET			0x00ff000000000000ULL
#define   PIP_WQE_WORD2_IP_OFFSET_SHIFT		48
#define PIP_WQE_WORD2_IP_VV			0x0000800000000000ULL
#define PIP_WQE_WORD2_IP_VS			0x0000400000000000ULL
#define PIP_WQE_WORD2_IP_45			0x0000200000000000ULL
#define PIP_WQE_WORD2_IP_VC			0x0000100000000000ULL
#define PIP_WQE_WORD2_IP_VLAN_ID		0x00000fff00000000ULL
#define PIP_WQE_WORD2_IP_31_20			0x00000000fff00000ULL
#define PIP_WQE_WORD2_IP_CO			0x0000000000080000ULL
#define PIP_WQE_WORD2_IP_TU			0x0000000000040000ULL
#define PIP_WQE_WORD2_IP_SE			0x0000000000020000ULL
#define PIP_WQE_WORD2_IP_V6			0x0000000000010000ULL
#define PIP_WQE_WORD2_IP_15			0x0000000000008000ULL
#define PIP_WQE_WORD2_IP_LE			0x0000000000004000ULL
#define PIP_WQE_WORD2_IP_FR			0x0000000000002000ULL
#define PIP_WQE_WORD2_IP_IE			0x0000000000001000ULL
#define PIP_WQE_WORD2_IP_B			0x0000000000000800ULL
#define PIP_WQE_WORD2_IP_M			0x0000000000000400ULL
#define PIP_WQE_WORD2_IP_NI			0x0000000000000200ULL
#define PIP_WQE_WORD2_IP_RE			0x0000000000000100ULL
#define PIP_WQE_WORD2_IP_OPECODE		0x00000000000000ffULL

#define PIP_WQE_WORD2_NOIP_BUFS			0xff00000000000000ULL
#define PIP_WQE_WORD2_NOIP_55_48		0x00ff000000000000ULL
#define PIP_WQE_WORD2_NOIP_VV			0x0000800000000000ULL
#define PIP_WQE_WORD2_NOIP_VS			0x0000400000000000ULL
#define PIP_WQE_WORD2_NOIP_45			0x0000200000000000ULL
#define PIP_WQE_WORD2_NOIP_VC			0x0000100000000000ULL
#define PIP_WQE_WORD2_NOIP_VLAN_ID		0x00000fff00000000ULL
#define PIP_WQE_WORD2_NOIP_31_14		0x00000000ffffc000ULL
#define PIP_WQE_WORD2_NOIP_IR			0x0000000000002000ULL
#define PIP_WQE_WORD2_NOIP_IA			0x0000000000001000ULL
#define PIP_WQE_WORD2_NOIP_B			0x0000000000000800ULL
#define PIP_WQE_WORD2_NOIP_M			0x0000000000000400ULL
#define PIP_WQE_WORD2_NOIP_NI			0x0000000000000200ULL
#define PIP_WQE_WORD2_NOIP_RE			0x0000000000000100ULL
#define PIP_WQE_WORD2_NOIP_OPECODE		0x00000000000000ffULL

/* WORD 3 */
#define PIP_WQE_WORD3_63			0x8000000000000000ULL
#define PIP_WQE_WORD3_BACK			0x7800000000000000ULL
#define PIP_WQE_WORD3_58_56			0x0700000000000000ULL
#define PIP_WQE_WORD3_SIZE			0x00ffff0000000000ULL
#define PIP_WQE_WORD3_ADDR			0x000000ffffffffffULL

/* opcode for WORD2[LE] */
#define PIP_WQE_WORD2_LE_OPCODE_MAL		1ULL
#define PIP_WQE_WORD2_LE_OPCODE_CSUM		2ULL
#define PIP_WQE_WORD2_LE_OPCODE_UDPLEN		3ULL
#define PIP_WQE_WORD2_LE_OPCODE_PORT		4ULL
#define PIP_WQE_WORD2_LE_OPCODE_XXX_5		5ULL
#define PIP_WQE_WORD2_LE_OPCODE_XXX_6		6ULL
#define PIP_WQE_WORD2_LE_OPCODE_XXX_7		7ULL
#define PIP_WQE_WORD2_LE_OPCODE_FINO		8ULL
#define PIP_WQE_WORD2_LE_OPCODE_NOFL		9ULL
#define PIP_WQE_WORD2_LE_OPCODE_FINRST		10ULL
#define PIP_WQE_WORD2_LE_OPCODE_SYNURG		11ULL
#define PIP_WQE_WORD2_LE_OPCODE_SYNRST		12ULL
#define PIP_WQE_WORD2_LE_OPCODE_SYNFIN		13ULL

/* opcode for WORD2[IE] */
#define PIP_WQE_WORD2_IE_OPCODE_NOTIP		1ULL
#define PIP_WQE_WORD2_IE_OPCODE_CSUM		2ULL
#define PIP_WQE_WORD2_IE_OPCODE_MALHDR		3ULL
#define PIP_WQE_WORD2_IE_OPCODE_MAL		4ULL
#define PIP_WQE_WORD2_IE_OPCODE_TTL		5ULL
#define PIP_WQE_WORD2_IE_OPCODE_OPT		6ULL

/* opcode for WORD2[RE] */
#define PIP_WQE_WORD2_RE_OPCODE_PARTIAL		1ULL
#define PIP_WQE_WORD2_RE_OPCODE_JABBER		2ULL
#define PIP_WQE_WORD2_RE_OPCODE_OVRRUN		3ULL
#define PIP_WQE_WORD2_RE_OPCODE_OVRSZ		4ULL
#define PIP_WQE_WORD2_RE_OPCODE_ALIGN		5ULL
#define PIP_WQE_WORD2_RE_OPCODE_FRAG		6ULL
#define PIP_WQE_WORD2_RE_OPCODE_GMXFCS		7ULL
#define PIP_WQE_WORD2_RE_OPCODE_UDRSZ		8ULL
#define PIP_WQE_WORD2_RE_OPCODE_EXTEND		9ULL
#define PIP_WQE_WORD2_RE_OPCODE_LENGTH		10ULL
#define PIP_WQE_WORD2_RE_OPCODE_MIIRX		11ULL
#define PIP_WQE_WORD2_RE_OPCODE_MIISKIP		12ULL
#define PIP_WQE_WORD2_RE_OPCODE_MIINBL		13ULL
#define PIP_WQE_WORD2_RE_OPCODE_XXX_14		14ULL
#define PIP_WQE_WORD2_RE_OPCODE_XXX_15		15ULL
#define PIP_WQE_WORD2_RE_OPCODE_XXX_16		16ULL
#define PIP_WQE_WORD2_RE_OPCODE_SKIP		17ULL
#define PIP_WQE_WORD2_RE_OPCODE_L2MAL		18ULL

/* XXX backward compatibility */
#define	PIP_OVER_ERR		PIP_WQE_WORD2_RE_OPCODE_OVRRUN
#define	PIP_GMX_FCS_ERR		PIP_WQE_WORD2_RE_OPCODE_GMXFCS
#define	PIP_ALIGN_ERR		PIP_WQE_WORD2_RE_OPCODE_ALIGN

#endif /* _CN30XXPIPREG_H_ */


code:
/*	$OpenBSD: cn30xxpipvar.h,v 1.2 2014/08/11 18:29:56 miod Exp $	*/

/*
 * Copyright (c) 2007 Internet Initiative Japan, Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */

#ifndef _CN30XXPIPVAR_H_
#define _CN30XXPIPVAR_H_

/* XXX */
struct cn30xxpip_softc {
	int			sc_port;
	bus_space_tag_t		sc_regt;
	bus_space_handle_t	sc_regh;
	int			sc_tag_type;
	int			sc_receive_group;
	size_t			sc_ip_offset;
};

/* XXX */
struct cn30xxpip_attach_args {
	int			aa_port;
	bus_space_tag_t		aa_regt;
	int			aa_tag_type;
	int			aa_receive_group;
	size_t			aa_ip_offset;
};

void			cn30xxpip_init(struct cn30xxpip_attach_args *,
			    struct cn30xxpip_softc **);
void			cn30xxpip_gbl_ctl_debug(struct cn30xxpip_softc *);
int			cn30xxpip_port_config(struct cn30xxpip_softc *);
void			cn30xxpip_prt_cfg_enable(struct cn30xxpip_softc *,
			    uint64_t, int);
void			cn30xxpip_stats(struct cn30xxpip_softc *,
			    struct ifnet *, int);
#ifdef OCTEON_ETH_DEBUG
void	cn30xxpip_int_enable(struct cn30xxpip_softc *, int);
void	cn30xxpip_dump(void);
void	cn30xxpip_dump_regs(void);
void	cn30xxpip_dump_stats(void);

void	cn30xxpip_int_enable(struct cn30xxpip_softc *, int);
uint64_t cn30xxpip_int_summary(struct cn30xxpip_softc *);
#endif /* OCTEON_ETH_DEBUG */

#endif


code:
/*	$OpenBSD: cn30xxpko.c,v 1.4 2014/08/11 18:29:56 miod Exp $	*/

/*
 * Copyright (c) 2007 Internet Initiative Japan, Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */

#include <sys/param.h>
#include <sys/systm.h>
#include <sys/malloc.h>

#include <machine/octeonvar.h>

#include <octeon/dev/cn30xxfaureg.h>
#include <octeon/dev/cn30xxfpavar.h>
#include <octeon/dev/cn30xxpkoreg.h>
#include <octeon/dev/cn30xxpkovar.h>

static inline void	cn30xxpko_op_store(uint64_t, uint64_t);

#ifdef OCTEON_ETH_DEBUG
void	cn30xxpko_intr_rml(void *);
#endif

#define	_PKO_RD8(sc, off) \
	bus_space_read_8((sc)->sc_regt, (sc)->sc_regh, (off))
#define	_PKO_WR8(sc, off, v) \
	bus_space_write_8((sc)->sc_regt, (sc)->sc_regh, (off), (v))

#ifdef OCTEON_ETH_DEBUG
struct cn30xxpko_softc	*__cn30xxpko_softc;
#endif

/* ----- gloal functions */

/* XXX */
void
cn30xxpko_init(struct cn30xxpko_attach_args *aa,
    struct cn30xxpko_softc **rsc)
{
	struct cn30xxpko_softc *sc;
	int status;

	sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
	if (sc == NULL)
		panic("can't allocate memory: %s", __func__);

	sc->sc_port = aa->aa_port;
	sc->sc_regt = aa->aa_regt;
	sc->sc_cmdptr = aa->aa_cmdptr;
	sc->sc_cmd_buf_pool = aa->aa_cmd_buf_pool;
	sc->sc_cmd_buf_size = aa->aa_cmd_buf_size;

	status = bus_space_map(sc->sc_regt, PKO_BASE, PKO_SIZE, 0,
	    &sc->sc_regh);
	if (status != 0)
		panic("can't map %s space", "pko register");

	*rsc = sc;

#ifdef OCTEON_ETH_DEBUG
	__cn30xxpko_softc = sc;
#endif
}

int
cn30xxpko_enable(struct cn30xxpko_softc *sc)
{
	uint64_t reg_flags;

	reg_flags = _PKO_RD8(sc, PKO_REG_FLAGS_OFFSET);
	/* PKO_REG_FLAGS_RESET=0 */
	/* PKO_REG_FLAGS_STORE_BE=0 */
	SET(reg_flags, PKO_REG_FLAGS_ENA_DWB);
	SET(reg_flags, PKO_REG_FLAGS_ENA_PKO);
	/* XXX */
	mips_sync();
	_PKO_WR8(sc, PKO_REG_FLAGS_OFFSET, reg_flags);

	return 0;
}

#if 0
void
cn30xxpko_reset(cn30xxpko_softc *sc)
{
	uint64_t reg_flags;

	reg_flags = _PKO_RD8(sc, PKO_REG_FLAGS_OFFSET);
	SET(reg_flags, PKO_REG_FLAGS_RESET);
	_PKO_WR8(sc, PKO_REG_FLAGS_OFFSET, reg_flags);
}
#endif

void
cn30xxpko_config(struct cn30xxpko_softc *sc)
{
	uint64_t reg_cmd_buf = 0;

	SET(reg_cmd_buf, (sc->sc_cmd_buf_pool << 20) & PKO_REG_CMD_BUF_POOL);
	SET(reg_cmd_buf, sc->sc_cmd_buf_size & PKO_REG_CMD_BUF_SIZE);
	_PKO_WR8(sc, PKO_REG_CMD_BUF_OFFSET, reg_cmd_buf);

#ifdef OCTEON_ETH_DEBUG
	cn30xxpko_int_enable(sc, 1);
#endif
}

int
cn30xxpko_port_enable(struct cn30xxpko_softc *sc, int enable)
{
	uint64_t reg_read_idx;
	uint64_t mem_queue_qos;

	reg_read_idx = 0;
	SET(reg_read_idx, sc->sc_port & PKO_REG_READ_IDX_IDX);

	/* XXX assume one queue maped one port */
	/* Enable packet output by enabling all queues for this port */
	mem_queue_qos = 0;
	SET(mem_queue_qos, ((uint64_t)sc->sc_port << 7) & PKO_MEM_QUEUE_QOS_PID);
	SET(mem_queue_qos, sc->sc_port & PKO_MEM_QUEUE_QOS_QID);
	SET(mem_queue_qos, ((enable ? 0xffULL : 0x00ULL) << 53) &
	    PKO_MEM_QUEUE_QOS_QOS_MASK);

	_PKO_WR8(sc, PKO_REG_READ_IDX_OFFSET, reg_read_idx);
	_PKO_WR8(sc, PKO_MEM_QUEUE_QOS_OFFSET, mem_queue_qos);

	return 0;
}

int pko_queue_map_init[32];

int
cn30xxpko_port_config(struct cn30xxpko_softc *sc)
{
	paddr_t buf_ptr = 0;
	uint64_t mem_queue_ptrs;

	KASSERT(sc->sc_port < 32);

	buf_ptr = cn30xxfpa_load(FPA_COMMAND_BUFFER_POOL);
	if (buf_ptr == 0)
		return 1;

	KASSERT(buf_ptr != 0);

	/* assume one queue maped one port */
	mem_queue_ptrs = 0;
	SET(mem_queue_ptrs, PKO_MEM_QUEUE_PTRS_TAIL);
	SET(mem_queue_ptrs, ((uint64_t)0 << 13) & PKO_MEM_QUEUE_PTRS_IDX);
	SET(mem_queue_ptrs, ((uint64_t)sc->sc_port << 7) & PKO_MEM_QUEUE_PTRS_PID);
	SET(mem_queue_ptrs, sc->sc_port & PKO_MEM_QUEUE_PTRS_QID);
	SET(mem_queue_ptrs, ((uint64_t)0xff << 53) & PKO_MEM_QUEUE_PTRS_QOS_MASK);
	SET(mem_queue_ptrs, ((uint64_t)buf_ptr << 17) & PKO_MEM_QUEUE_PTRS_BUF_PTR);
	mips_sync();
	_PKO_WR8(sc, PKO_MEM_QUEUE_PTRS_OFFSET, mem_queue_ptrs);

	/*
	 * Set initial command buffer address and index
	 * for queue.
	 */
	sc->sc_cmdptr->cmdptr = (uint64_t)buf_ptr;
	sc->sc_cmdptr->cmdptr_idx = 0;

	pko_queue_map_init[sc->sc_port] = 1;

	return 0;
}

#ifdef OCTEON_ETH_DEBUG
int	cn30xxpko_intr_rml_verbose;

void
cn30xxpko_intr_rml(void *arg)
{
	struct cn30xxpko_softc *sc;
	uint64_t reg;

	sc = __cn30xxpko_softc;
	KASSERT(sc != NULL);
	reg = cn30xxpko_int_summary(sc);
	if (cn30xxpko_intr_rml_verbose)
		printf("%s: PKO_REG_ERROR=0x%016llx\n", __func__, reg);
}

void
cn30xxpko_int_enable(struct cn30xxpko_softc *sc, int enable)
{
	uint64_t pko_int_xxx = 0;

	pko_int_xxx = PKO_REG_ERROR_DOORBELL | PKO_REG_ERROR_PARITY;
	_PKO_WR8(sc, PKO_REG_ERROR_OFFSET, pko_int_xxx);
	_PKO_WR8(sc, PKO_REG_INT_MASK_OFFSET, enable ? pko_int_xxx : 0);
}

uint64_t
cn30xxpko_int_summary(struct cn30xxpko_softc *sc)
{
	uint64_t summary;

	summary = _PKO_RD8(sc, PKO_REG_ERROR_OFFSET);
	_PKO_WR8(sc, PKO_REG_ERROR_OFFSET, summary);
	return summary;
}
#endif


code:
/*
 * THIS FILE IS AUTOMATICALLY GENERATED
 * DONT EDIT THIS FILE
 */

/*	$OpenBSD: cn30xxpkoreg.h,v 1.1 2011/06/16 11:22:30 syuu Exp $	*/

/*
 * Copyright (c) 2007 Internet Initiative Japan, Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */

/*
 * Cavium Networks OCTEON CN30XX Hardware Reference Manual
 * CN30XX-HM-1.0
 * 8.9 PKO Registers
 */

#ifndef _CN30XXPKOREG_H_
#define _CN30XXPKOREG_H_

#define	PKO_REG_FLAGS				0x0001180050000000ULL
#define	PKO_REG_READ_IDX			0x0001180050000008ULL
#define	PKO_REG_CMD_BUF				0x0001180050000010ULL
#define	PKO_REG_GMX_PORT_MODE			0x0001180050000018ULL
#define	PKO_REG_QUEUE_MODE			0x0001180050000048ULL
#define	PKO_REG_BIST_RESULT			0x0001180050000050ULL
#define	PKO_REG_ERROR				0x0001180050000058ULL
#define	PKO_REG_INT_MASK			0x0001180050000090ULL
#define	PKO_REG_DEBUG0				0x0001180050000098ULL
#define	PKO_MEM_QUEUE_PTRS			0x0001180050001000ULL
#define	PKO_MEM_QUEUE_QOS			0x0001180050001008ULL
#define	PKO_MEM_COUNT0				0x0001180050001080ULL
#define	PKO_MEM_COUNT1				0x0001180050001088ULL
#define	PKO_DEBUG0				0x0001180050001100ULL
#define	PKO_DEBUG1				0x0001180050001108ULL
#define	PKO_DEBUG2				0x0001180050001110ULL
#define	PKO_DEBUG3				0x0001180050001118ULL
#define	PKO_DEBUG4				0x0001180050001120ULL
#define	PKO_DEBUG5				0x0001180050001128ULL
#define	PKO_DEBUG6				0x0001180050001130ULL
#define	PKO_DEBUG7				0x0001180050001138ULL
#define	PKO_DEBUG8				0x0001180050001140ULL
#define	PKO_DEBUG9				0x0001180050001148ULL
#define	PKO_DEBUG10				0x0001180050001150ULL
#define	PKO_DEBUG11				0x0001180050001158ULL
#define	PKO_DEBUG12				0x0001180050001160ULL
#define	PKO_DEBUG13				0x0001180050001168ULL
#define	PKO_DEBUG14				0x0001180050001170ULL

#define PKO_BASE				0x0001180050000000ULL
#define	PKO_SIZE				0x01178ULL

#define PKO_REG_FLAGS_OFFSET			0x00000ULL
#define PKO_REG_READ_IDX_OFFSET			0x00008ULL
#define	PKO_REG_CMD_BUF_OFFSET			0x00010ULL
#define	PKO_REG_GMX_PORT_MODE_OFFSET		0x00018ULL
#define	PKO_REG_QUEUE_MODE_OFFSET		0x00048ULL
#define	PKO_REG_BIST_RESULT_OFFSET		0x00080ULL
#define	PKO_REG_ERROR_OFFSET			0x00088ULL
#define	PKO_REG_INT_MASK_OFFSET			0x00090ULL
#define	PKO_REG_DEBUG0_OFFSET			0x00098ULL
#define	PKO_MEM_QUEUE_PTRS_OFFSET		0x01000ULL
#define	PKO_MEM_QUEUE_QOS_OFFSET		0x01008ULL
#define	PKO_MEM_COUNT0_OFFSET			0x01080ULL
#define	PKO_MEM_COUNT1_OFFSET			0x01088ULL
#define	PKO_MEM_DEBUG0_OFFSET			0x01100ULL
#define	PKO_MEM_DEBUG1_OFFSET			0x01108ULL
#define	PKO_MEM_DEBUG2_OFFSET			0x01110ULL
#define	PKO_MEM_DEBUG3_OFFSET			0x01118ULL
#define	PKO_MEM_DEBUG4_OFFSET			0x01120ULL
#define	PKO_MEM_DEBUG5_OFFSET			0x01128ULL
#define	PKO_MEM_DEBUG6_OFFSET			0x01130ULL
#define	PKO_MEM_DEBUG7_OFFSET			0x01138ULL
#define	PKO_MEM_DEBUG8_OFFSET			0x01140ULL
#define	PKO_MEM_DEBUG9_OFFSET			0x01148ULL
#define	PKO_MEM_DEBUG10_OFFSET			0x01150ULL
#define	PKO_MEM_DEBUG11_OFFSET			0x01158ULL
#define	PKO_MEM_DEBUG12_OFFSET			0x01160ULL
#define	PKO_MEM_DEBUG13_OFFSET			0x01168ULL
#define	PKO_MEM_DEBUG14_OFFSET			0x01170ULL

/*
 * PKO_REG_FLAGS
 */
#define PKO_REG_FLAGS_63_7		0xfffffffffffffff0ULL
#define PKO_REG_FLAGS_RESET		0x0000000000000008ULL
#define PKO_REG_FLAGS_STORE_BE		0x0000000000000004ULL
#define PKO_REG_FLAGS_ENA_DWB		0x0000000000000002ULL
#define PKO_REG_FLAGS_ENA_PKO		0x0000000000000001ULL

/*
 * PKO_REG_READ_IDX
 */
#define PKO_REG_READ_IDX_63_16		0xffffffffffff0000ULL
#define PKO_REG_READ_IDX_INC		0x000000000000ff00ULL
#define PKO_REG_READ_IDX_IDX		0x00000000000000ffULL

/*
 * PKO_REG_CMD_BUF
 */
#define PKO_REG_CMD_BUF_63_23		0xffffffffff800000ULL
#define PKO_REG_CMD_BUF_POOL		0x0000000000700000ULL
#define PKO_REG_CMD_BUF_19_13		0x00000000000fe000ULL
#define PKO_REG_CMD_BUF_SIZE		0x0000000000001fffULL

/*
 * PKO_REG_GMX_PORT_MODE
 */
#define PKO_REG_GMX_PORT_MODE_63_6	0xffffffffffffffc0ULL
#define PKO_REG_GMX_PORT_MODE_MODE1	0x0000000000000038ULL
#define PKO_REG_GMX_PORT_MODE_MODE0	0x0000000000000007ULL

/*
 * PKO_REG_QUEUE_MODE
 */
#define PKO_REG_QUEUE_MODE_63_6		0xfffffffffffffffcULL
#define PKO_REG_QUEUE_MODE_MODE		0x000000000000000eULL

/*
 * PKO_REG_BIST_RESULT
 */
#define PKO_REG_BIST_RESULT_63_27	0xfffffffff8000000ULL
#define PKO_REG_BIST_RESULT_PSB2	0x0000000007c00000ULL
#define PKO_REG_BIST_RESULT_COUNT	0x0000000000200000ULL
#define PKO_REG_BIST_RESULT_RIF		0x0000000000100000ULL
#define PKO_REG_BIST_RESULT_WIF		0x0000000000080000ULL
#define PKO_REG_BIST_RESULT_NCB		0x0000000000040000ULL
#define PKO_REG_BIST_RESULT_OUT		0x0000000000020000ULL
#define PKO_REG_BIST_RESULT_CRC		0x0000000000010000ULL
#define PKO_REG_BIST_RESULT_CHK		0x0000000000008000ULL
#define PKO_REG_BIST_RESULT_QSB		0x0000000000006000ULL
#define PKO_REG_BIST_RESULT_QCB		0x0000000000001800ULL
#define PKO_REG_BIST_RESULT_PDB		0x0000000000000780ULL
#define PKO_REG_BIST_RESULT_PSB		0x000000000000007fULL

/*
 * PKO_REG_ERROR
 */
#define PKO_REG_ERROR_63_2		0xfffffffffffffffcULL
#define PKO_REG_ERROR_DOORBELL		0x0000000000000002ULL
#define PKO_REG_ERROR_PARITY		0x0000000000000001ULL

/*
 * PKO_REG_INT_MASK
 */
#define PKO_REG_INT_MASK_63_2		0xfffffffffffffffcULL
#define PKO_REG_INT_MASK_DOORBELL	0x0000000000000002ULL
#define PKO_REG_INT_MASK_PARITY		0x0000000000000001ULL

/*
 * PKO_REG_DEBUG0
 */
#define PKO_REG_DEBUG0_63_17		0xfffffffffffe0000ULL
#define PKO_REG_DEBUG0_ASSERTS		0x000000000001ffffULL

/*
 * PKO_MEM_QUEUE_PTRS
 */
#define PKO_MEM_QUEUE_PTRS_S_TAIL	0x8000000000000000ULL
#define PKO_MEM_QUEUE_PTRS_STATIC_P	0x4000000000000000ULL
#define PKO_MEM_QUEUE_PTRS_STATIC_Q	0x2000000000000000ULL
#define PKO_MEM_QUEUE_PTRS_QOS_MASK	0x1fe0000000000000ULL
#define PKO_MEM_QUEUE_PTRS_BUF_PTR	0x001ffffffffe0000ULL
#define PKO_MEM_QUEUE_PTRS_TAIL		0x0000000000010000ULL
#define PKO_MEM_QUEUE_PTRS_IDX		0x000000000000e000ULL
#define PKO_MEM_QUEUE_PTRS_PID		0x0000000000001f80ULL
#define PKO_MEM_QUEUE_PTRS_QID		0x000000000000007fULL

/*
 * PKO_MEM_QUEUE_QOS
 */
#define PKO_MEM_QUEUE_QOS_63_61		0xe000000000000000ULL
#define PKO_MEM_QUEUE_QOS_QOS_MASK	0x1fe0000000000000ULL
#define PKO_MEM_QUEUE_QOS_52_13		0x001fffffffffe000ULL
#define PKO_MEM_QUEUE_QOS_PID		0x0000000000001f80ULL
#define PKO_MEM_QUEUE_QOS_QID		0x000000000000007fULL

/*
 * PKO_MEM_COUNT0
 */
#define PKO_MEM_COUNT0_63_32		0xffffffff00000000ULL
#define PKO_MEM_COUNT0_COUNT		0x00000000ffffffffULL

/*
 * PKO_MEM_COUNT1
 */
#define PKO_MEM_COUNT1_63_48		0xffff000000000000ULL
#define PKO_MEM_COUNT1_COUNT		0x0000ffffffffffffULL

/*
 * PKO_MEM_DEBUG0
 */
#define PKO_MEM_DEBUG0_FAU		0xfffffff000000000ULL
#define PKO_MEM_DEBUG0_CMD		0x0000000fffc00000ULL
#define PKO_MEM_DEBUG0_SEGS		0x00000000003f0000ULL
#define PKO_MEM_DEBUG0_SIZE		0x000000000000ffffULL

/*
 * PKO_MEM_DEBUG1
 */
#define PKO_MEM_DEBUG1_I		0x8000000000000000ULL
#define PKO_MEM_DEBUG1_BACK		0x7800000000000000ULL
#define PKO_MEM_DEBUG1_POOL		0x0700000000000000ULL
#define PKO_MEM_DEBUG1_SIZE		0x00ffff0000000000ULL
#define PKO_MEM_DEBUG1_PTR		0x000000ffffffffffULL

/*
 * PKO_MEM_DEBUG2
 */
#define PKO_MEM_DEBUG2_I		0x8000000000000000ULL
#define PKO_MEM_DEBUG2_BACK		0x7800000000000000ULL
#define PKO_MEM_DEBUG2_POOL		0x0700000000000000ULL
#define PKO_MEM_DEBUG2_SIZE		0x00ffff0000000000ULL
#define PKO_MEM_DEBUG2_PTR		0x000000ffffffffffULL

/*
 * PKO_MEM_DEBUG3
 */
#define PKO_MEM_DEBUG3_I		0x8000000000000000ULL
#define PKO_MEM_DEBUG3_BACK		0x7800000000000000ULL
#define PKO_MEM_DEBUG3_POOL		0x0700000000000000ULL
#define PKO_MEM_DEBUG3_SIZE		0x00ffff0000000000ULL
#define PKO_MEM_DEBUG3_PTR		0x000000ffffffffffULL

/*
 * PKO_MEM_DEBUG4
 */
#define PKO_MEM_DEBUG4_DATA		0xffffffffffffffffULL

/*
 * PKO_MEM_DEBUG5
 */
#define PKO_MEM_DEBUG5_DWRI_MOD			0x8000000000000000ULL
#define PKO_MEM_DEBUG5_DWRI_SOP			0x4000000000000000ULL
#define PKO_MEM_DEBUG5_DWRI_LEN			0x2000000000000000ULL
#define PKO_MEM_DEBUG5_DWRI_CNT			0x1fff000000000000ULL
#define PKO_MEM_DEBUG5_CMND_SIZ			0x0000ffff00000000ULL
#define PKO_MEM_DEBUG5_UID			0x0000000080000000ULL
#define PKO_MEM_DEBUG5_XFER_WOR			0x0000000040000000ULL
#define PKO_MEM_DEBUG5_XFER_DWR			0x0000000020000000ULL
#define PKO_MEM_DEBUG5_CBUF_FRE			0x0000000010000000ULL
#define PKO_MEM_DEBUG5_27			0x0000000008000000ULL
#define PKO_MEM_DEBUG5_CHK_MODE			0x0000000004000000ULL
#define PKO_MEM_DEBUG5_ACTIVE			0x0000000002000000ULL
#define PKO_MEM_DEBUG5_QOS			0x0000000001c00000ULL
#define PKO_MEM_DEBUG5_QCB_RIDX			0x00000000003e0000ULL
#define PKO_MEM_DEBUG5_QID_OFF			0x000000000001c000ULL
#define PKO_MEM_DEBUG5_QID_BASE			0x0000000000003f80ULL
#define PKO_MEM_DEBUG5_WAIT			0x0000000000000040ULL
#define PKO_MEM_DEBUG5_MINOR			0x0000000000000030ULL
#define PKO_MEM_DEBUG5_MAJOR			0x000000000000000fULL

/*
 * PKO_MEM_DEBUG6
 */
#define PKO_MEM_DEBUG6_63_11		0xfffffffffffff800ULL
#define PKO_MEM_DEBUG6_QID_OFFM		0x0000000000000700ULL
#define PKO_MEM_DEBUG6_STATIC_P		0x0000000000000080ULL
#define PKO_MEM_DEBUG6_WORK_MIN		0x0000000000000070ULL
#define PKO_MEM_DEBUG6_DWRI_CHK		0x0000000000000008ULL
#define PKO_MEM_DEBUG6_DWRI_UID		0x0000000000000004ULL
#define PKO_MEM_DEBUG6_DWRI_MOD		0x0000000000000003ULL

/*
 * PKO_MEM_DEBUG7
 */
#define PKO_MEM_DEBUG7_63_58		0xfc00000000000000ULL
#define PKO_MEM_DEBUG7_DWB		0x03fe000000000000ULL
#define PKO_MEM_DEBUG7_START		0x0001ffffffff0000ULL
#define PKO_MEM_DEBUG7_SIZE		0x000000000000ffffULL

/*
 * PKO_MEM_DEBUG8
 */
#define PKO_MEM_DEBUG8_QOS		0xf800000000000000ULL
#define PKO_MEM_DEBUG8_TAIL		0x0400000000000000ULL
#define PKO_MEM_DEBUG8_BUF_SIZ		0x03ffe00000000000ULL
#define PKO_MEM_DEBUG8_BUF_PTR		0x00001ffffffff000ULL
#define PKO_MEM_DEBUG8_QCB_WIDX		0x0000000000000fc0ULL
#define PKO_MEM_DEBUG8_QCB_RIDX		0x000000000000003fULL

/*
 * PKO_MEM_DEBUG9
 */
#define PKO_MEM_DEBUG9_63_28		0xfffffffff0000000ULL
#define PKO_MEM_DEBUG9_DOORBELL		0x000000000fffff00ULL
#define PKO_MEM_DEBUG9_7_5		0x00000000000000e0ULL
#define PKO_MEM_DEBUG9_S_TAIL		0x0000000000000010ULL
#define PKO_MEM_DEBUG9_STATIC_Q		0x0000000000000008ULL
#define PKO_MEM_DEBUG9_QOOS		0x0000000000000007ULL

/*
 * PKO_MEM_DEBUG10
 */
#define PKO_MEM_DEBUG10_FAU		0xfffffff000000000ULL
#define PKO_MEM_DEBUG10_CMD		0x0000000fffc00000ULL
#define PKO_MEM_DEBUG10_SEGS		0x00000000003f0000ULL
#define PKO_MEM_DEBUG10_SIZE		0x000000000000ffffULL

/*
 * PKO_MEM_DEBUG11
 */
#define PKO_MEM_DEBUG11_I		0x8000000000000000ULL
#define PKO_MEM_DEBUG11_BACK		0x7800000000000000ULL
#define PKO_MEM_DEBUG11_POOL		0x0700000000000000ULL
#define PKO_MEM_DEBUG11_SIZE		0x00ffff0000000000ULL
#define PKO_MEM_DEBUG11_PTR		0x000000ffffffffffULL

/*
 * PKO_MEM_DEBUG12
 */
#define PKO_MEM_DEBUG12_DATA		0xffffffffffffffffULL

/*
 * PKO_MEM_DEBUG13
 */
#define PKO_MEM_DEBUG13_63_51		0xfff8000000000000ULL
#define PKO_MEM_DEBUG13_WIDX		0x0007fffc00000000ULL
#define PKO_MEM_DEBUG13_RIDX2		0x00000003fffe0000ULL
#define PKO_MEM_DEBUG13_WIDX2		0x000000000001ffffULL

/*
 * PKO_MEM_DEBUG14
 */
#define PKO_MEM_DEBUG13_63_17		0xfffffffffffe0000ULL
#define PKO_MEM_DEBUG13_RIDX		0x000000000001ffffULL

/*
 * PKO_CMD_WORD0
 */
#define PKO_CMD_WORD0_SZ1		0xc000000000000000ULL
#define PKO_CMD_WORD0_SZ0		0x3000000000000000ULL
#define PKO_CMD_WORD0_S1		0x0800000000000000ULL
#define PKO_CMD_WORD0_REG1		0x07ff000000000000ULL
#define PKO_CMD_WORD0_S0		0x0000800000000000ULL
#define PKO_CMD_WORD0_REG0		0x00007ff000000000ULL
#define PKO_CMD_WORD0_LE		0x0000000800000000ULL
#define PKO_CMD_WORD0_N2		0x0000000400000000ULL
#define PKO_CMD_WORD0_Q			0x0000000200000000ULL
#define PKO_CMD_WORD0_R			0x0000000100000000ULL
#define PKO_CMD_WORD0_G			0x0000000080000000ULL
#define PKO_CMD_WORD0_IPOFFP1		0x000000007f000000ULL
#define PKO_CMD_WORD0_II		0x0000000000800000ULL
#define PKO_CMD_WORD0_DF		0x0000000000400000ULL
#define PKO_CMD_WORD0_SEGS		0x00000000003f0000ULL
#define PKO_CMD_WORD0_TOTALBYTES	0x000000000000ffffULL

/*
 * PKO_CMD_WORD1
 */
#define PKO_CMD_WORD1_I			0x8000000000000000ULL
#define PKO_CMD_WORD1_BACK		0x7800000000000000ULL
#define PKO_CMD_WORD1_POOL		0x0700000000000000ULL
#define PKO_CMD_WORD1_SIZE		0x00ffff0000000000ULL
#define PKO_CMD_WORD1_ADDR		0x000000ffffffffffULL

/*
 * PKO_CMD_WORD2
 */
#define PKO_CMD_WORD2_63_36		0xfffffff000000000ULL
#define PKO_CMD_WORD2_PTR		0x0000000fffffffffULL

/*
 *  DOORBELL_WRITE
 */
#define PKO_DOORBELL_WRITE_IO_BIT	0x0001000000000000ULL
#define PKO_DOORBELL_WRITE_MAJOR_DID	0x0000f80000000000ULL
#define PKO_DOORBELL_WRITE_SUB_DID	0x0000070000000000ULL
#define PKO_DOORBELL_WRITE_39_16	0x000000ffffff0000ULL
#define PKO_DOORBELL_WRITE_PID		0x000000000003f000ULL
#define PKO_DOORBELL_WRITE_QID		0x0000000000000ff8ULL
#define PKO_DOORBELL_WRITE_2_0		0x0000000000000007ULL

#define PKO_DOORBELL_WRITE_WDC		0x00000000000fffffULL

/* ---- operations */

#define	CN30XXPKO_MAJORDID	0x0a
#define	CN30XXPKO_SUBDID	0x02

#endif /* _CN30XXPKOREG_H_ */


code:
/*	$OpenBSD: cn30xxpkovar.h,v 1.5 2014/08/11 18:29:56 miod Exp $	*/

/*
 * Copyright (c) 2007 Internet Initiative Japan, Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */

/*
 * Cavium Networks OCTEON CN30XX Hardware Reference Manual
 * CN30XX-HM-1.0
 * 8.9 PKO Registers
 */

#ifndef _CN30XXPKOVAR_H_
#define _CN30XXPKOVAR_H_

#include <octeon/dev/cn30xxfauvar.h>
#include <octeon/dev/cn30xxpkoreg.h>

#define FAU_OP_SIZE_8	0
#define FAU_OP_SIZE_16	1
#define FAU_OP_SIZE_32	2
#define FAU_OP_SIZE_64	3

#define PKO_OUTPUT_PORTS_NUM		5
#define PKO_OUTPUT_PORTS_PKTIF_NUM	3
#define PKO_OUTPUT_PORTS_PCIIF_NUM	2
#define	PKO_MEM_QUEUE_PTRS_ILLEGAL_PID	63

/* XXX */
struct cn30xxpko_cmdptr_desc {
	uint64_t	cmdptr;
	uint64_t	cmdptr_idx;
};

/* XXX */
struct cn30xxpko_softc {
	int			sc_port;
	bus_space_tag_t		sc_regt;
	bus_space_handle_t	sc_regh;
	struct cn30xxpko_cmdptr_desc
				*sc_cmdptr;
	int			sc_cmd_buf_pool;
	size_t			sc_cmd_buf_size;
};

/* XXX */
struct cn30xxpko_attach_args {
	int				aa_port;
	bus_space_tag_t			aa_regt;
	struct cn30xxpko_cmdptr_desc	*aa_cmdptr;
	int				aa_cmd_buf_pool;
	size_t				aa_cmd_buf_size;
};

/* XXX */
void			cn30xxpko_init(struct cn30xxpko_attach_args *,
			    struct cn30xxpko_softc **);
int			cn30xxpko_enable(struct cn30xxpko_softc *);
int			cn30xxpko_reset(struct cn30xxpko_softc *);
void			cn30xxpko_config(struct cn30xxpko_softc *);
int			cn30xxpko_port_enable(struct cn30xxpko_softc *, int);
int			cn30xxpko_port_config(struct cn30xxpko_softc *);
void			cn30xxpko_int_enable(struct cn30xxpko_softc *, int);
uint64_t		cn30xxpko_int_summary(struct cn30xxpko_softc *);
static inline uint64_t	cn30xxpko_cmd_word0(int, int, int, int, int, int,
			    int, int, int, int, int, int, int, int, int, int);
static inline uint64_t	cn30xxpko_cmd_word1(int, int, int, int, paddr_t);

static inline uint64_t
cn30xxpko_cmd_word0(int sz1, int sz0, int s1, int reg1, int s0, int reg0,
    int le, int n2, int q, int r, int g, int ipoffp1, int ii, int df, int segs,
    int totalbytes)
{
	uint64_t cmd = 0;

	SET(cmd, (((uint64_t)sz1 << 62) & PKO_CMD_WORD0_SZ1)
 	    | (((uint64_t)sz0 << 60) & PKO_CMD_WORD0_SZ0)
	    | (((uint64_t)s1 << 59) & PKO_CMD_WORD0_S1)
	    | (((uint64_t)reg1 << 48) & PKO_CMD_WORD0_REG1)
	    | (((uint64_t)s0 << 47) & PKO_CMD_WORD0_S0)
	    | (((uint64_t)reg0 << 36) & PKO_CMD_WORD0_REG0)
	    | (((uint64_t)le << 35) & PKO_CMD_WORD0_LE)
	    | (((uint64_t)n2 << 34) & PKO_CMD_WORD0_N2)
	    | (((uint64_t)q << 33) & PKO_CMD_WORD0_Q)
	    | (((uint64_t)r << 32) & PKO_CMD_WORD0_R)
	    | (((uint64_t)g << 31) & PKO_CMD_WORD0_G)
	    | (((uint64_t)ipoffp1 << 24) & PKO_CMD_WORD0_IPOFFP1)
	    | (((uint64_t)ii << 23) & PKO_CMD_WORD0_II)
	    | (((uint64_t)df << 22) & PKO_CMD_WORD0_DF)
	    | (((uint64_t)segs << 16) & PKO_CMD_WORD0_SEGS)
	    | (((uint64_t)totalbytes << 0) & PKO_CMD_WORD0_TOTALBYTES));
	return cmd;
}

static inline uint64_t
cn30xxpko_cmd_word1(int i, int back, int pool, int size, paddr_t addr)
{
	uint64_t cmd = 0;

	SET(cmd, (((uint64_t)i << 63) & PKO_CMD_WORD1_I)
	    | (((uint64_t)back << 59) & PKO_CMD_WORD1_BACK)
	    | (((uint64_t)pool << 56) & PKO_CMD_WORD1_POOL)
	    | (((uint64_t)size << 40) & PKO_CMD_WORD1_SIZE)
	    | (((uint64_t)addr << 0) & PKO_CMD_WORD1_ADDR));
	return cmd;
}

/* ---- operation primitives */

/* 8.8.1 Store Operations */

static inline void
cn30xxpko_op_store(uint64_t args, uint64_t value)
{
	paddr_t addr;

	addr =
	    ((uint64_t)1 << 48) |
	    ((uint64_t)(CN30XXPKO_MAJORDID & 0x1f) << 43) |
	    ((uint64_t)(CN30XXPKO_SUBDID & 0x7) << 40) |
	    ((uint64_t)args);
	/* XXX */
	mips_sync();
	octeon_xkphys_write_8(addr, value);
}

static inline void
cn30xxpko_op_doorbell_write(int pid, int qid, int wdc)
{
	uint64_t args, value;

	args =
	    ((uint64_t)(pid & 0x3f) << 12) |
	    ((uint64_t)(qid & 0x1ff) << 3);
	value = wdc & 0xfffff;
	cn30xxpko_op_store(args, value);
}

#endif