code:
/*	$OpenBSD: gbe.c,v 1.21 2013/10/21 10:36:16 miod Exp $ */

/*
 * Copyright (c) 2007, 2008, 2009 Joel Sing <jsing@openbsd.org>
 *
 * Permission to use, copy, modify, and distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

/*
 * Graphics Back End (GBE) Framebuffer for SGI O2.
 */

#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <sys/malloc.h>

#include <uvm/uvm_extern.h>

#include <machine/autoconf.h>
#include <machine/bus.h>

#include <mips64/arcbios.h>

#include <sgi/dev/gl.h>
#include <sgi/localbus/crimebus.h>
#include <sgi/localbus/macebusvar.h>

#include <dev/wscons/wsconsio.h>
#include <dev/wscons/wsdisplayvar.h>
#include <dev/rasops/rasops.h>

#include "gbereg.h"

/* Amount of memory to allocate for framebuffer. */
#define GBE_FB_SIZE	8 * 1 << 20

/*
 * Colourmap data.
 */
struct  gbe_cmap {
	u_int8_t cm_red[256];
	u_int8_t cm_green[256];
	u_int8_t cm_blue[256];
};

/*
 * Screen data.
 */
struct gbe_screen {
	struct device *sc;		/* Back pointer. */

	struct rasops_info ri;		/* Screen raster display info. */
	struct rasops_info ri_tile;	/* Raster info for rasops tile. */
	struct gbe_cmap cmap;		/* Display colour map. */

	int fb_size;			/* Size of framebuffer memory. */
	int tm_size;			/* Size of tilemap memory. */

	caddr_t tm;			/* Address of tilemap memory. */
	paddr_t tm_phys;		/* Physical address of tilemap. */
	caddr_t fb;			/* Address of framebuffer memory. */
	paddr_t fb_phys;		/* Physical address of framebuffer. */
	caddr_t ro;			/* Address of rasops tile. */
	paddr_t ro_phys;		/* Physical address of rasops tile. */

	int width;			/* Width in pixels. */
	int height;			/* Height in pixels. */
	int depth;			/* Colour depth in bits. */
	int mode;			/* Display mode. */
	int bufmode;			/* Rendering engine buffer mode. */
	int linebytes;			/* Bytes per line. */
	int ro_curpos;			/* Current position in rasops tile. */
};

/*
 * GBE device data.
 */
struct gbe_softc {
	struct device sc_dev;

	bus_space_tag_t iot;
	bus_space_handle_t ioh;		/* GBE registers. */
	bus_space_handle_t re_ioh;	/* Rendering engine registers. */
	bus_dma_tag_t dmat;

	int rev;			/* Hardware revision. */
	int console;			/* Is this the console? */
	int screens;			/* No of screens allocated. */

	struct gbe_screen *curscr;	/* Current screen. */
};

/*
 * Hardware and device related functions.
 */
void	gbe_init_screen(struct gbe_screen *);
void	gbe_enable(struct gbe_softc *);
void	gbe_disable(struct gbe_softc *);
void	gbe_setup(struct gbe_softc *);
void	gbe_setcolour(struct gbe_softc *, u_int, u_int8_t, u_int8_t, u_int8_t);
void	gbe_wait_re_idle(struct gbe_softc *);

/*
 * Colour map handling for indexed modes.
 */
int	gbe_getcmap(struct gbe_cmap *, struct wsdisplay_cmap *);
int	gbe_putcmap(struct gbe_cmap *, struct wsdisplay_cmap *);
void	gbe_loadcmap(struct gbe_screen *, u_int, u_int);

/*
 * Interfaces for wscons.
 */
int 	gbe_ioctl(void *, u_long, caddr_t, int, struct proc *);
paddr_t gbe_mmap(void *, off_t, int);
int	gbe_alloc_screen(void *, const struct wsscreen_descr *, void **,
	    int *, int *, long *);
void	gbe_free_screen(void *, void *);
int	gbe_show_screen(void *, void *, int, void (*)(void *, int, int),
	    void *);
int	gbe_load_font(void *, void *, struct wsdisplay_font *);
int	gbe_list_font(void *, struct wsdisplay_font *);

/*
 * Hardware acceleration for rasops.
 */
void	gbe_rop(struct gbe_softc *, int, int, int, int, int);
void	gbe_copyrect(struct gbe_softc *, int, int, int, int, int, int, int);
void	gbe_fillrect(struct gbe_softc *, int, int, int, int, int);
int	gbe_do_cursor(struct rasops_info *);
int	gbe_putchar(void *, int, int, u_int, long);
int	gbe_copycols(void *, int, int, int, int);
int	gbe_erasecols(void *, int, int, int, long);
int	gbe_copyrows(void *, int, int, int);
int	gbe_eraserows(void *, int, int, long);

static struct gbe_screen gbe_consdata;
static int gbe_console;

struct wsscreen_descr gbe_stdscreen = {
	"std",		/* Screen name. */
};

struct wsdisplay_accessops gbe_accessops = {
	.ioctl = gbe_ioctl,
	.mmap = gbe_mmap,
	.alloc_screen = gbe_alloc_screen,
	.free_screen = gbe_free_screen,
	.show_screen = gbe_show_screen,
	.load_font = gbe_load_font,
	.list_font = gbe_list_font
};

const struct wsscreen_descr *gbe_scrlist[] = {
	&gbe_stdscreen
};

struct wsscreen_list gbe_screenlist = {
	sizeof(gbe_scrlist) / sizeof(struct wsscreen_descr *), gbe_scrlist
};

int	gbe_match(struct device *, void *, void *);
void	gbe_attach(struct device *, struct device *, void *);
int	gbe_activate(struct device *, int);

struct cfattach gbe_ca = {
	sizeof (struct gbe_softc), gbe_match, gbe_attach,
	NULL, gbe_activate
};

struct cfdriver gbe_cd = {
	NULL, "gbe", DV_DULL
};

int
gbe_match(struct device *parent, void *cf, void *aux)
{
	struct mainbus_attach_args *maa = aux;

	if (strcmp(maa->maa_name, gbe_cd.cd_name) != 0)
		return 0;

	return 1;
}

void
gbe_attach(struct device *parent, struct device *self, void *aux)
{
	struct gbe_softc *gsc = (void*)self;
	struct gbe_screen *screen;
	struct wsemuldisplaydev_attach_args waa;
	bus_dma_segment_t tm_segs[1];
	bus_dma_segment_t fb_segs[1];
	bus_dma_segment_t ro_segs[1];
	bus_dmamap_t tm_dmamap;
	bus_dmamap_t fb_dmamap;
	bus_dmamap_t ro_dmamap;
	int tm_nsegs;
	int fb_nsegs;
	int ro_nsegs;
	uint32_t val;
	long attr;

	printf(": ");

	/* GBE isn't strictly on the crimebus, but use this for now... */
	gsc->iot = &crimebus_tag;
	gsc->dmat = &mace_bus_dma_tag;
	gsc->console = gbe_console;
	gsc->screens = 0;

	if (gsc->console == 1) {

		/*
		 * We've already been setup via gbe_cnattach().
		 */

		gsc->ioh = PHYS_TO_XKPHYS(GBE_BASE, CCA_NC);
		gsc->re_ioh = PHYS_TO_XKPHYS(RE_BASE, CCA_NC);

		gsc->rev = bus_space_read_4(gsc->iot, gsc->ioh, GBE_CTRL_STAT)
		    & 0xf;

		gsc->curscr = &gbe_consdata;
		gbe_consdata.sc = (void*)self;

		printf("rev %u, %iMB, %dx%d at %d bits\n", gsc->rev,
		    gbe_consdata.fb_size >> 20, gbe_consdata.width,
		    gbe_consdata.height, gbe_consdata.depth);

		waa.console = gsc->console;
		waa.scrdata = &gbe_screenlist;
		waa.accessops = &gbe_accessops;
		waa.accesscookie = &gbe_consdata;
		waa.defaultscreens = 0;
		config_found(self, &waa, wsemuldisplaydevprint);

		return;
	}

	/*
	 * Setup screen data.
	 */
	gsc->curscr = malloc(sizeof(struct gbe_screen), M_DEVBUF, M_NOWAIT);
	if (gsc->curscr == NULL) {
		printf("failed to allocate screen memory!\n");
		return;
	}
	gsc->curscr->sc = (void *)gsc;
	screen = gsc->curscr;

	/*
	 * Setup bus space mappings.
	 */
	if (bus_space_map(gsc->iot, GBE_BASE - CRIMEBUS_BASE, GBE_REG_SIZE,
	    BUS_SPACE_MAP_LINEAR, &gsc->ioh)) {
		printf("failed to map framebuffer bus space!\n");
		return;
	}

	if (bus_space_map(gsc->iot, RE_BASE - CRIMEBUS_BASE, RE_REG_SIZE,
	    BUS_SPACE_MAP_LINEAR, &gsc->re_ioh)) {
		printf("failed to map rendering engine bus space!\n");
		goto fail0;
	}

	/* Determine GBE revision. */
	gsc->rev = bus_space_read_4(gsc->iot, gsc->ioh, GBE_CTRL_STAT) & 0xf;

	/* Determine resolution configured by firmware. */
	val = bus_space_read_4(gsc->iot, gsc->ioh, GBE_VT_HCMAP);
	screen->width = (val >> GBE_VT_HCMAP_ON_SHIFT) & 0xfff;
	val = bus_space_read_4(gsc->iot, gsc->ioh, GBE_VT_VCMAP);
	screen->height = (val >> GBE_VT_VCMAP_ON_SHIFT) & 0xfff;

	if (screen->width == 0 || screen->height == 0) {
		printf("device has not been setup by firmware!\n");
		goto fail1;
	}

	/* Setup screen defaults. */
	screen->fb_size = GBE_FB_SIZE;
	screen->tm_size = GBE_TLB_SIZE * sizeof(uint16_t);
	screen->depth = 8;
	screen->linebytes = screen->width * screen->depth / 8;

	/*
	 * Setup DMA for tilemap.
	 */
	if (bus_dmamap_create(gsc->dmat, screen->tm_size, 1, screen->tm_size,
	    0, BUS_DMA_NOWAIT, &tm_dmamap)) {
		printf("failed to create DMA map for tilemap!\n");
		goto fail1;
	}

	if (bus_dmamem_alloc(gsc->dmat, screen->tm_size, 65536, 0, tm_segs, 1,
	    &tm_nsegs, BUS_DMA_NOWAIT)) {
		printf("failed to allocate DMA memory for tilemap!\n");
		goto fail2;
	}

	if (bus_dmamem_map(gsc->dmat, tm_segs, tm_nsegs, screen->tm_size,
	    &screen->tm, BUS_DMA_COHERENT)) {
		printf("failed to map DMA memory for tilemap!\n");
		goto fail3;
	}

	if (bus_dmamap_load(gsc->dmat, tm_dmamap, screen->tm, screen->tm_size,
	    NULL, BUS_DMA_NOWAIT)){
		printf("failed to load DMA map for tilemap\n");
		goto fail4;
	}

	/*
	 * Setup DMA for framebuffer.
	 */
	if (bus_dmamap_create(gsc->dmat, screen->fb_size, 1, screen->fb_size,
	    0, BUS_DMA_NOWAIT, &fb_dmamap)) {
		printf("failed to create DMA map for framebuffer!\n");
		goto fail5;
	}

	if (bus_dmamem_alloc(gsc->dmat, screen->fb_size, 65536, 0, fb_segs,
	    1, &fb_nsegs, BUS_DMA_NOWAIT)) {
		printf("failed to allocate DMA memory for framebuffer!\n");
		goto fail6;
	}

	if (bus_dmamem_map(gsc->dmat, fb_segs, fb_nsegs, screen->fb_size,
	    &screen->fb, BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) {
		printf("failed to map DMA memory for framebuffer!\n");
		goto fail7;
	}

	if (bus_dmamap_load(gsc->dmat, fb_dmamap, screen->fb, screen->fb_size,
	    NULL, BUS_DMA_NOWAIT)) {
		printf("failed to load DMA map for framebuffer\n");
		goto fail8;
	}

	/*
	 * Setup DMA for rasops tile.
	 */
	if (bus_dmamap_create(gsc->dmat, GBE_TILE_SIZE, 1, GBE_TILE_SIZE,
	    0, BUS_DMA_NOWAIT, &ro_dmamap)) {
		printf("failed to create DMA map for rasops tile!\n");
		goto fail9;
	}

	if (bus_dmamem_alloc(gsc->dmat, GBE_TILE_SIZE, 65536, 0, ro_segs,
	    1, &ro_nsegs, BUS_DMA_NOWAIT)) {
		printf("failed to allocate DMA memory for rasops tile!\n");
		goto fail10;
	}

	if (bus_dmamem_map(gsc->dmat, ro_segs, ro_nsegs, GBE_TILE_SIZE,
	    &screen->ro, BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) {
		printf("failed to map DMA memory for rasops tile!\n");
		goto fail11;
	}

	if (bus_dmamap_load(gsc->dmat, ro_dmamap, screen->ro, GBE_TILE_SIZE,
	    NULL, BUS_DMA_NOWAIT)) {
		printf("failed to load DMA map for rasops tile\n");
		goto fail12;
	}

	screen->tm_phys = tm_dmamap->dm_segs[0].ds_addr;
	screen->fb_phys = fb_dmamap->dm_segs[0].ds_addr;
	screen->ro_phys = ro_dmamap->dm_segs[0].ds_addr;

	gbe_init_screen(screen);
	gbe_disable(gsc);
	gbe_setup(gsc);
	gbe_enable(gsc);

	/* Load colourmap if required. */
	if (screen->depth == 8)
		gbe_loadcmap(screen, 0, 255);

	/* Clear framebuffer. */
	gbe_fillrect(gsc, 0, 0, screen->width, screen->height, 0);

	printf("rev %u, %iMB, %dx%d at %d bits\n", gsc->rev,
	    screen->fb_size >> 20, screen->width, screen->height,
	    screen->depth);

	/*
	 * Attach wsdisplay.
	 */

	/* Attach as console if necessary. */
	if (strncmp(bios_console, "video", 5) == 0) {
		screen->ri.ri_ops.alloc_attr(&screen->ri, 0, 0, 0, &attr);
		wsdisplay_cnattach(&gbe_stdscreen, &screen->ri, 0, 0, attr);
		gsc->console = 1;
	}

	waa.console = gsc->console;
	waa.scrdata = &gbe_screenlist;
	waa.accessops = &gbe_accessops;
	waa.accesscookie = screen;
	waa.defaultscreens = 0;
	config_found(self, &waa, wsemuldisplaydevprint);

	return;

fail12:
	bus_dmamem_unmap(gsc->dmat, screen->ro, GBE_TILE_SIZE);
fail11:
	bus_dmamem_free(gsc->dmat, ro_segs, ro_nsegs);
fail10:
	bus_dmamap_destroy(gsc->dmat, ro_dmamap);
fail9:
	bus_dmamap_unload(gsc->dmat, fb_dmamap);
fail8:
	bus_dmamem_unmap(gsc->dmat, screen->fb, screen->fb_size);
fail7:
	bus_dmamem_free(gsc->dmat, fb_segs, fb_nsegs);
fail6:
	bus_dmamap_destroy(gsc->dmat, fb_dmamap);
fail5:
	bus_dmamap_unload(gsc->dmat, tm_dmamap);
fail4:
	bus_dmamem_unmap(gsc->dmat, screen->tm, screen->tm_size);
fail3:
	bus_dmamem_free(gsc->dmat, tm_segs, tm_nsegs);
fail2:
	bus_dmamap_destroy(gsc->dmat, tm_dmamap);
fail1:
	bus_space_unmap(gsc->iot, gsc->re_ioh, RE_REG_SIZE);
fail0:
	bus_space_unmap(gsc->iot, gsc->ioh, GBE_REG_SIZE);
}

int
gbe_activate(struct device *self, int act)
{
	struct gbe_softc *gsc = (struct gbe_softc *)self;
	int ret = 0;

	switch (act) {
	case DVACT_POWERDOWN:
		gbe_disable(gsc);
		break;
	}

	return (ret);
}

/*
 * GBE hardware specific functions.
 */

void
gbe_init_screen(struct gbe_screen *screen)
{
	uint16_t *tm;
	int i;

	/*
	 * Initialise screen.
	 */
	screen->mode = WSDISPLAYIO_MODE_EMUL;

	/* Initialise rasops. */
	memset(&screen->ri, 0, sizeof(struct rasops_info));

	screen->ri.ri_flg = RI_CENTER;
	screen->ri.ri_depth = screen->depth;
	screen->ri.ri_width = screen->width;
	screen->ri.ri_height = screen->height;
	screen->ri.ri_bits = (void *)screen->fb;
	screen->ri.ri_stride = screen->linebytes;

	if (screen->depth == 32) {
		screen->ri.ri_rpos = 24;
		screen->ri.ri_rnum = 8;
		screen->ri.ri_gpos = 16;
		screen->ri.ri_gnum = 8;
		screen->ri.ri_bpos = 8;
		screen->ri.ri_bnum = 8;
	} else if (screen->depth == 16) {
		screen->ri.ri_rpos = 10;
		screen->ri.ri_rnum = 5;
		screen->ri.ri_gpos = 5;
		screen->ri.ri_gnum = 5;
		screen->ri.ri_bpos = 0;
		screen->ri.ri_bnum = 5;
	}

	rasops_init(&screen->ri, screen->height / 8, screen->width / 8);

	/* Create a rasops instance that can draw into a single tile. */
	memcpy(&screen->ri_tile, &screen->ri, sizeof(struct rasops_info));
	screen->ri_tile.ri_flg = 0;
	screen->ri_tile.ri_width = GBE_TILE_WIDTH >> (screen->depth >> 4);
	screen->ri_tile.ri_height = GBE_TILE_HEIGHT;
	screen->ri_tile.ri_stride = screen->ri_tile.ri_width *
	    screen->depth / 8;
	screen->ri_tile.ri_xorigin = 0;
	screen->ri_tile.ri_yorigin = 0;
	screen->ri_tile.ri_bits = screen->ro;
	screen->ri_tile.ri_origbits = screen->ro;
	screen->ro_curpos = 0;

	screen->ri.ri_hw = screen->sc;

	screen->ri.ri_do_cursor = gbe_do_cursor;
	screen->ri.ri_ops.putchar = gbe_putchar;
	screen->ri.ri_ops.copyrows = gbe_copyrows;
	screen->ri.ri_ops.copycols = gbe_copycols;
	screen->ri.ri_ops.eraserows = gbe_eraserows;
	screen->ri.ri_ops.erasecols = gbe_erasecols;

	gbe_stdscreen.ncols = screen->ri.ri_cols;
	gbe_stdscreen.nrows = screen->ri.ri_rows;
	gbe_stdscreen.textops = &screen->ri.ri_ops;
	gbe_stdscreen.fontwidth = screen->ri.ri_font->fontwidth;
	gbe_stdscreen.fontheight = screen->ri.ri_font->fontheight;
	gbe_stdscreen.capabilities = screen->ri.ri_caps;

	/*
	 * Map framebuffer into tilemap. Each entry in the tilemap is 16 bits
	 * wide. Each tile is 64KB or 2^16 bits, hence the last 16 bits of the
	 * address will range from 0x0000 to 0xffff. As a result we simply
	 * discard the lower 16 bits and store bits 17 through 32 as an entry
	 * in the tilemap.
	 */
	tm = (void *)screen->tm;
	for (i = 0; i < (screen->fb_size >> GBE_TILE_SHIFT) &&
	    i < GBE_TLB_SIZE; i++)
		tm[i] = (screen->fb_phys >> GBE_TILE_SHIFT) + i;
}

void
gbe_enable(struct gbe_softc *gsc)
{
	struct gbe_screen *screen = gsc->curscr;
	uint32_t val;
	int i;

	/* Enable dot clock. */
	val = bus_space_read_4(gsc->iot, gsc->ioh, GBE_DOTCLOCK);
	bus_space_write_4(gsc->iot, gsc->ioh, GBE_DOTCLOCK,
	    val | GBE_DOTCLOCK_RUN);
	for (i = 0; i < 10000; i++) {
		val = bus_space_read_4(gsc->iot, gsc->ioh, GBE_DOTCLOCK);
		if ((val & GBE_DOTCLOCK_RUN) == GBE_DOTCLOCK_RUN)
			break;
		delay(10);
	}
	if (i == 10000)
		printf("timeout enabling dot clock!\n");

	/* Unfreeze pixel counter. */
	bus_space_write_4(gsc->iot, gsc->ioh, GBE_VT_XY, 0);
	for (i = 0; i < 10000; i++) {
		val = bus_space_read_4(gsc->iot, gsc->ioh, GBE_VT_XY);
		if ((val & GBE_VT_XY_FREEZE) == 0)
			break;
		delay(10);
	}
	if (i == 10000)
		printf("timeout unfreezing pixel counter!\n");

	/* Disable sync-on-green. */
	if (strcmp(osloadoptions, "nosog") == 0)
		bus_space_write_4(gsc->iot, gsc->ioh, GBE_VT_FLAGS,
		    GBE_VT_SYNC_LOW);

	/* Provide GBE with address of tilemap and enable DMA. */
	bus_space_write_4(gsc->iot, gsc->ioh, GBE_FB_CTRL,
	    ((screen->tm_phys >> 9) <<
	    GBE_FB_CTRL_TILE_PTR_SHIFT) | GBE_FB_CTRL_DMA_ENABLE);
}

void
gbe_disable(struct gbe_softc *gsc)
{
	uint32_t val;
	int i;

	/* Nothing to do if the pixel counter is frozen! */
	val = bus_space_read_4(gsc->iot, gsc->ioh, GBE_VT_XY);
	if ((val & GBE_VT_XY_FREEZE) == GBE_VT_XY_FREEZE)
		return;

	/* Enable sync-on-green. */
	bus_space_write_4(gsc->iot, gsc->ioh, GBE_VT_FLAGS, 0);

	val = bus_space_read_4(gsc->iot, gsc->ioh, GBE_DOTCLOCK);
	if ((val & GBE_DOTCLOCK_RUN) == 0)
		return;

	/* Disable overlay and turn off hardware cursor. */
	bus_space_write_4(gsc->iot, gsc->ioh, GBE_OVERLAY_TILE, 0);
	bus_space_write_4(gsc->iot, gsc->ioh, GBE_CURSOR_CTRL, 0);
	bus_space_write_4(gsc->iot, gsc->ioh, GBE_DID_CTRL, 0);

	/* Disable DMA. */
	val = bus_space_read_4(gsc->iot, gsc->ioh, GBE_OVERLAY_CTRL);
	bus_space_write_4(gsc->iot, gsc->ioh, GBE_OVERLAY_CTRL,
	    val & ~GBE_OVERLAY_CTRL_DMA_ENABLE);
	val = bus_space_read_4(gsc->iot, gsc->ioh, GBE_FB_CTRL);
	bus_space_write_4(gsc->iot, gsc->ioh, GBE_FB_CTRL,
	    val & ~GBE_FB_CTRL_DMA_ENABLE);
	bus_space_write_4(gsc->iot, gsc->ioh, GBE_DID_CTRL, 0);
	for (i = 0; i < 100000; i++) {
		if ((bus_space_read_4(gsc->iot, gsc->ioh, GBE_OVERLAY_HW_CTRL)
		    & GBE_OVERLAY_CTRL_DMA_ENABLE) == 0 &&
		    (bus_space_read_4(gsc->iot, gsc->ioh, GBE_FB_HW_CTRL)
		    & GBE_FB_CTRL_DMA_ENABLE) == 0 &&
		    bus_space_read_4(gsc->iot, gsc->ioh, GBE_DID_HW_CTRL) == 0)
			break;
		delay(10);
	}
	if (i == 100000)
		printf("timeout disabling DMA!\n");

	/* Wait for the end of pixel refresh. */
	val = bus_space_read_4(gsc->iot, gsc->ioh, GBE_VT_VPIX)
	    & GBE_VT_VPIX_OFF_MASK;
	for (i = 0; i < 100000; i++) {
		if (((bus_space_read_4(gsc->iot, gsc->ioh, GBE_VT_XY)
		    & GBE_VT_XY_Y_MASK) >> GBE_VT_XY_Y_SHIFT) < val)
			break;
		delay(1);
	}
	if (i == 100000)
		printf("timeout waiting for pixel refresh!\n");
	for (i = 0; i < 100000; i++) {
		if (((bus_space_read_4(gsc->iot, gsc->ioh, GBE_VT_XY)
		    & GBE_VT_XY_Y_MASK) >> GBE_VT_XY_Y_SHIFT) > val)
			break;
		delay(1);
	}
	if (i == 100000)
		printf("timeout waiting for pixel refresh!\n");

	/* Freeze pixel counter. */
	bus_space_write_4(gsc->iot, gsc->ioh, GBE_VT_XY, GBE_VT_XY_FREEZE);
	for (i = 0; i < 100000; i++) {
		val = bus_space_read_4(gsc->iot, gsc->ioh, GBE_VT_XY);
		if ((val & GBE_VT_XY_FREEZE) == GBE_VT_XY_FREEZE)
			break;
		delay(10);
	}
	if (i == 100000)
		printf("timeout freezing pixel counter!\n");

	/* Disable dot clock. */
	val = bus_space_read_4(gsc->iot, gsc->ioh, GBE_DOTCLOCK);
	bus_space_write_4(gsc->iot, gsc->ioh, GBE_DOTCLOCK,
	    val & ~GBE_DOTCLOCK_RUN);
	for (i = 0; i < 100000; i++) {
		val = bus_space_read_4(gsc->iot, gsc->ioh, GBE_DOTCLOCK);
		if ((val & GBE_DOTCLOCK_RUN) == 0)
			break;
		delay(10);
	}
	if (i == 100000)
		printf("timeout disabling dot clock!\n");

	/* Reset DMA fifo. */
	val = bus_space_read_4(gsc->iot, gsc->ioh, GBE_FB_SIZE_TILE);
	val &= ~(1 << GBE_FB_SIZE_TILE_FIFO_RESET_SHIFT);
	bus_space_write_4(gsc->iot, gsc->ioh, GBE_FB_SIZE_TILE,
	    val | (1 << GBE_FB_SIZE_TILE_FIFO_RESET_SHIFT));
	bus_space_write_4(gsc->iot, gsc->ioh, GBE_FB_SIZE_TILE, val);
}

void
gbe_setup(struct gbe_softc *gsc)
{
	struct gbe_screen *screen = gsc->curscr;
	int i, t, cmode, tile_width, tiles_x, tiles_y;
	u_char *colour;
	uint16_t *tm;
	uint32_t val;
	uint64_t reg;

	/*
	 * Setup framebuffer.
	 */
	switch (screen->depth) {
	case 32:
		cmode = GBE_CMODE_RGB8;
		screen->bufmode = COLOUR_DEPTH_32 << BUFMODE_BUFDEPTH_SHIFT |
		    PIXEL_TYPE_RGB << BUFMODE_PIXTYPE_SHIFT |
		    COLOUR_DEPTH_32 << BUFMODE_PIXDEPTH_SHIFT;
		break;
	case 16:
		cmode = GBE_CMODE_ARGB5;
		screen->bufmode = COLOUR_DEPTH_16 << BUFMODE_BUFDEPTH_SHIFT |
		    PIXEL_TYPE_RGBA << BUFMODE_PIXTYPE_SHIFT |
		    COLOUR_DEPTH_16 << BUFMODE_PIXDEPTH_SHIFT;
		break;
	case 8:
	default:
		cmode = GBE_CMODE_I8;
		screen->bufmode = COLOUR_DEPTH_8 << BUFMODE_BUFDEPTH_SHIFT |
		    PIXEL_TYPE_CI << BUFMODE_PIXTYPE_SHIFT |
		    COLOUR_DEPTH_8 << BUFMODE_PIXDEPTH_SHIFT;
		break;
	}

	/* Calculate tile width in bytes and screen size in tiles. */
	tile_width = GBE_TILE_WIDTH >> (screen->depth >> 4);
	tiles_x = (screen->width + tile_width - 1) >>
	    (GBE_TILE_WIDTH_SHIFT - (screen->depth >> 4));
	tiles_y = (screen->height + GBE_TILE_HEIGHT - 1) >>
	    GBE_TILE_HEIGHT_SHIFT;

	if (screen->mode != WSDISPLAYIO_MODE_EMUL) {

		/*
		 * Setup the framebuffer in "linear" mode. We trick the
		 * framebuffer into linear mode by telling it that it is one
		 * tile wide and specifying an adjusted framebuffer height.
		 */

		bus_space_write_4(gsc->iot, gsc->ioh, GBE_FB_SIZE_TILE,
		    ((screen->depth >> 4) << GBE_FB_SIZE_TILE_DEPTH_SHIFT) |
		    (1 << GBE_FB_SIZE_TILE_WIDTH_SHIFT));

		bus_space_write_4(gsc->iot, gsc->ioh, GBE_FB_SIZE_PIXEL,
		    (screen->width * screen->height / tile_width) <<
		        GBE_FB_SIZE_PIXEL_HEIGHT_SHIFT);

	} else {

		/*
		 * Setup the framebuffer in tiled mode. Provide the tile
		 * colour depth, screen width in whole and partial tiles,
		 * and the framebuffer height in pixels.
		 */

		bus_space_write_4(gsc->iot, gsc->ioh, GBE_FB_SIZE_TILE,
		    ((screen->depth >> 4) << GBE_FB_SIZE_TILE_DEPTH_SHIFT) |
		    ((screen->width / tile_width) <<
		        GBE_FB_SIZE_TILE_WIDTH_SHIFT) |
		    (((screen->width % tile_width) >> (screen->depth >> 4)) /
		        32));

		bus_space_write_4(gsc->iot, gsc->ioh, GBE_FB_SIZE_PIXEL,
		    screen->height << GBE_FB_SIZE_PIXEL_HEIGHT_SHIFT);

	}

	/* Set colour mode registers. */
	val = (cmode << GBE_WID_MODE_SHIFT) | GBE_BMODE_BOTH;
	for (i = 0; i < (32 * 4); i += 4)
		bus_space_write_4(gsc->iot, gsc->ioh, GBE_MODE + i, val);

	/*
	 * Initialise colourmap if required.
	 */
	if (screen->depth == 8) {
		for (i = 0; i < 16; i++) {
			colour = (u_char *)&rasops_cmap[i * 3];
			screen->cmap.cm_red[i] = colour[0];
			screen->cmap.cm_green[i] = colour[1];
			screen->cmap.cm_blue[i] = colour[2];
		}
		for (i = 240; i < 256; i++) {
			colour = (u_char *)&rasops_cmap[i * 3];
			screen->cmap.cm_red[i] = colour[0];
			screen->cmap.cm_green[i] = colour[1];
			screen->cmap.cm_blue[i] = colour[2];
		}
	}

	/*
	 * Setup an alpha ramp.
	 */
	for (i = 0; i < GBE_GMAP_ENTRIES; i++)
		bus_space_write_4(gsc->iot, gsc->ioh,
		    GBE_GMAP + i * sizeof(u_int32_t),
		    (i << 24) | (i << 16) | (i << 8));

	/*
	 * Initialise the rendering engine.
	 */
	val = screen->mode | BUF_TYPE_TLB_A << BUFMODE_BUFTYPE_SHIFT;
	bus_space_write_4(gsc->iot, gsc->re_ioh, RE_PP_BUFMODE_SRC, val);
	bus_space_write_4(gsc->iot, gsc->re_ioh, RE_PP_BUFMODE_DST, val);
	bus_space_write_4(gsc->iot, gsc->re_ioh, RE_PP_CLIPMODE, 0);
	bus_space_write_4(gsc->iot, gsc->re_ioh, RE_PP_COLOUR_MASK, 0xffffffff);
	bus_space_write_4(gsc->iot, gsc->re_ioh, RE_PP_PIXEL_XFER_X_STEP, 1);
	bus_space_write_4(gsc->iot, gsc->re_ioh, RE_PP_PIXEL_XFER_Y_STEP, 1);
	bus_space_write_4(gsc->iot, gsc->re_ioh, RE_PP_WINOFFSET_DST, 0);
	bus_space_write_4(gsc->iot, gsc->re_ioh, RE_PP_WINOFFSET_SRC, 0);

	/*
	 * Load framebuffer tiles into TLB A. Each TLB consists of a 16x16
	 * tile array representing 2048x2048 pixels. Each entry in the TLB
	 * consists of four 16-bit entries which represent bits 17:32 of the
	 * 64KB tile address. As a result, we can make use of the tilemap
	 * which already stores tile entries in the same format.
	 */
	tm = (void *)screen->tm;
	for (i = 0, t = 0; i < GBE_TLB_SIZE; i++) {
		reg <<= 16;
		if (i % 16 < tiles_x)
			reg |= (tm[t++] | 0x8000);
		if (i % 4 == 3)
			bus_space_write_8(gsc->iot, gsc->re_ioh,
			    RE_TLB_A + (i >> 2) * 8, reg);
	}

	/* Load single tile into TLB B for rasops. */
	bus_space_write_8(gsc->iot, gsc->re_ioh,
	    RE_TLB_B, (screen->ro_phys >> 16 | 0x8000) << 48);
}

void
gbe_wait_re_idle(struct gbe_softc *gsc)
{
	int i;

	/* Wait until rendering engine is idle. */
	for (i = 0; i < 100000; i++) {
		if (bus_space_read_4(gsc->iot, gsc->re_ioh, RE_PP_STATUS) &
		    RE_PP_STATUS_IDLE)
			break;
		delay(1);
	}
	if (i == 100000)
		printf("%s: rendering engine did not become idle!\n",
		    gsc->sc_dev.dv_xname);
}

/*
 * Interfaces for wscons.
 */

int
gbe_ioctl(void *v, u_long cmd, caddr_t data, int flags, struct proc *p)
{
	struct gbe_screen *screen = (struct gbe_screen *)v;
	int rc, mode;

	switch (cmd) {
	case WSDISPLAYIO_GTYPE:
		*(u_int *)data = WSDISPLAY_TYPE_GBE;
		break;

	case WSDISPLAYIO_GINFO:
	{
		struct wsdisplay_fbinfo *fb = (struct wsdisplay_fbinfo *)data;

		fb->height = screen->height;
		fb->width = screen->width;
		fb->depth = screen->depth;
		fb->cmsize = screen->depth == 8 ? 256 : 0;
	}
		break;

	case WSDISPLAYIO_LINEBYTES:
		*(u_int *)data = screen->linebytes;
		break;

	case WSDISPLAYIO_GETCMAP:
		if (screen->depth == 8) {
			struct wsdisplay_cmap *cm =
			    (struct wsdisplay_cmap *)data;

			rc = gbe_getcmap(&screen->cmap, cm);
			if (rc != 0)
				return (rc);
		}
		break;

	case WSDISPLAYIO_PUTCMAP:
		if (screen->depth == 8) {
			struct wsdisplay_cmap *cm =
			    (struct wsdisplay_cmap *)data;

			rc = gbe_putcmap(&screen->cmap, cm);
			if (rc != 0)
				return (rc);
			gbe_loadcmap(screen, cm->index, cm->index + cm->count);
		}
		break;

	case WSDISPLAYIO_GMODE:
		*(u_int *)data = screen->mode;
		break;

	case WSDISPLAYIO_SMODE:
		mode = *(u_int *)data;
		if (mode == WSDISPLAYIO_MODE_EMUL ||
		    mode == WSDISPLAYIO_MODE_MAPPED ||
		    mode == WSDISPLAYIO_MODE_DUMBFB) {

			screen->mode = mode;

			gbe_disable((struct gbe_softc *)screen->sc);
			gbe_setup((struct gbe_softc *)screen->sc);
			gbe_enable((struct gbe_softc *)screen->sc);

			/* Clear framebuffer if entering emulated mode. */
			if (screen->mode == WSDISPLAYIO_MODE_EMUL)
				gbe_fillrect((struct gbe_softc *)screen->sc,
				    0, 0, screen->width, screen->height, 0);
		}
		break;

	case WSDISPLAYIO_GVIDEO:
	case WSDISPLAYIO_SVIDEO:
		/* Handled by the upper layer. */
		break;

	default:
		return (-1);
	}

	return (0);
}

paddr_t
gbe_mmap(void *v, off_t offset, int protection)
{
	struct gbe_screen *screen = (void *)v;
	paddr_t pa;

	if (offset >= 0 && offset < screen->fb_size)
		pa = screen->fb_phys + offset;
	else
		pa = -1;

	return (pa);
}

int
gbe_alloc_screen(void *v, const struct wsscreen_descr *type, void **cookiep,
    int *curxp, int *curyp, long *attrp)
{
	struct gbe_screen *screen = (struct gbe_screen *)v;
	struct gbe_softc *gsc = (struct gbe_softc *)screen->sc;

	/* We do not allow multiple consoles at the moment. */
	if (gsc->screens > 0)
		return (ENOMEM);

	gsc->screens++;

	/* Return rasops_info via cookie. */
	*cookiep = &screen->ri;

	/* Move cursor to top left of screen. */
	*curxp = 0;
	*curyp = 0;

	/* Correct screen attributes. */
	screen->ri.ri_ops.alloc_attr(&screen->ri, 0, 0, 0, attrp);

	return (0);
}

void
gbe_free_screen(void *v, void *cookie)
{
	/* We do not allow multiple consoles at the moment. */
}

int
gbe_show_screen(void *v, void *cookie, int waitok, void (*cb)(void *, int, int),
    void *cbarg)
{
	/* We do not allow multiple consoles at the moment. */
	return (0);
}

int
gbe_load_font(void *v, void *emulcookie, struct wsdisplay_font *font)
{
	struct gbe_screen *screen = (struct gbe_screen *)v;

	return rasops_load_font(&screen->ri, emulcookie, font);
}

int
gbe_list_font(void *v, struct wsdisplay_font *font)
{
	struct gbe_screen *screen = (struct gbe_screen *)v;

	return rasops_list_font(&screen->ri, font);
}

/*
 * Colour map handling for indexed modes.
 */

void
gbe_setcolour(struct gbe_softc *gsc, u_int index, u_int8_t r, u_int8_t g,
    u_int8_t b)
{
	int i;

	/* Wait until the colourmap FIFO has free space. */
	for (i = 0; i < 10000; i++) {
		if (bus_space_read_4(gsc->iot, gsc->ioh, GBE_CMAP_FIFO)
		    < GBE_CMAP_FIFO_ENTRIES)
			break;
		delay(10);
	}
	if (i == 10000)
		printf("colourmap FIFO has no free space!\n");

	bus_space_write_4(gsc->iot, gsc->ioh,
	    GBE_CMAP + index * sizeof(u_int32_t),
	    ((u_int)r << 24) | ((u_int)g << 16) | ((u_int)b << 8));
}

int
gbe_getcmap(struct gbe_cmap *cm, struct wsdisplay_cmap *rcm)
{
	u_int index = rcm->index, count = rcm->count;
	int rc;

	if (index >= 256 || count > 256 - index)
		return (EINVAL);

	if ((rc = copyout(&cm->cm_red[index], rcm->red, count)) != 0)
		return (rc);
	if ((rc = copyout(&cm->cm_green[index], rcm->green, count)) != 0)
		return (rc);
	if ((rc = copyout(&cm->cm_blue[index], rcm->blue, count)) != 0)
		return (rc);

	return (0);
}

int
gbe_putcmap(struct gbe_cmap *cm, struct wsdisplay_cmap *rcm)
{
	u_int index = rcm->index, count = rcm->count;
	int rc;

	if (index >= 256 || count > 256 - index)
		return (EINVAL);

	if ((rc = copyin(rcm->red, &cm->cm_red[index], count)) != 0)
		return (rc);
	if ((rc = copyin(rcm->green, &cm->cm_green[index], count)) != 0)
		return (rc);
	if ((rc = copyin(rcm->blue, &cm->cm_blue[index], count)) != 0)
		return (rc);

	return (0);
}

void
gbe_loadcmap(struct gbe_screen *screen, u_int start, u_int end)
{
	struct gbe_softc *gsc = (void *)screen->sc;
	struct gbe_cmap *cm = &screen->cmap;

	for (; start <= end; start++)
		gbe_setcolour(gsc, start,
		    cm->cm_red[start], cm->cm_green[start], cm->cm_blue[start]);
}

/*
 * Hardware accelerated functions for rasops.
 */

void
gbe_rop(struct gbe_softc *gsc, int x, int y, int w, int h, int op)
{
	gbe_wait_re_idle(gsc);

	bus_space_write_4(gsc->iot, gsc->re_ioh, RE_PP_PRIMITIVE,
	    PRIMITIVE_RECTANGLE | PRIMITIVE_LRTB);
	bus_space_write_4(gsc->iot, gsc->re_ioh, RE_PP_DRAWMODE,
	    DRAWMODE_BITMASK | DRAWMODE_BYTEMASK | DRAWMODE_PIXEL_XFER |
	    DRAWMODE_LOGIC_OP);
	bus_space_write_4(gsc->iot, gsc->re_ioh, RE_PP_LOGIC_OP, op);
	bus_space_write_4(gsc->iot, gsc->re_ioh, RE_PP_PIXEL_XFER_SRC,
	    (x << 16) | (y & 0xffff));
	bus_space_write_4(gsc->iot, gsc->re_ioh, RE_PP_VERTEX_X_0,
	    (x << 16) | (y & 0xffff));
	bus_space_write_4(gsc->iot, gsc->re_ioh, RE_PP_VERTEX_X_1 | RE_START,
	    ((x + w - 1) << 16) | ((y + h - 1) & 0xffff));
}

void
gbe_copyrect(struct gbe_softc *gsc, int src, int sx, int sy, int dx, int dy,
    int w, int h)
{
	int direction, x0, y0, x1, y1;

	if (sx >= dx && sy >= dy) {
		direction = PRIMITIVE_LRTB;
		x0 = dx;
		y0 = dy;
		x1 = dx + w - 1;
		y1 = dy + h - 1;
	} else if (sx >= dx && sy < dy) {
		direction = PRIMITIVE_LRBT;
		sy = sy + h - 1;
		x0 = dx;
		y0 = dy + h - 1;
		x1 = dx + w - 1;
		y1 = dy;
	} else if (sx < dx && sy >= dy) {
		direction = PRIMITIVE_RLTB;
		sx = sx + w - 1;
		x0 = dx + w - 1;
		y0 = dy;
		x1 = dx;
		y1 = dy + h - 1;
	} else if (sx < dx && sy < dy) {
		direction = PRIMITIVE_RLBT;
		sy = sy + h - 1;
		sx = sx + w - 1;
		x0 = dx + w - 1;
		y0 = dy + h - 1;
		x1 = dx;
		y1 = dy;
	}

	gbe_wait_re_idle(gsc);

	if (src != BUF_TYPE_TLB_A)
		bus_space_write_4(gsc->iot, gsc->re_ioh, RE_PP_BUFMODE_SRC,
		    gsc->curscr->bufmode | (src << BUFMODE_BUFTYPE_SHIFT));

	bus_space_write_4(gsc->iot, gsc->re_ioh, RE_PP_PRIMITIVE,
	    PRIMITIVE_RECTANGLE | direction);
	bus_space_write_4(gsc->iot, gsc->re_ioh, RE_PP_DRAWMODE,
	    DRAWMODE_BITMASK | DRAWMODE_BYTEMASK | DRAWMODE_PIXEL_XFER);
	bus_space_write_4(gsc->iot, gsc->re_ioh, RE_PP_PIXEL_XFER_SRC,
	    (sx << 16) | (sy & 0xffff));
	bus_space_write_4(gsc->iot, gsc->re_ioh, RE_PP_VERTEX_X_0,
	    (x0 << 16) | (y0 & 0xffff));
	bus_space_write_4(gsc->iot, gsc->re_ioh, RE_PP_VERTEX_X_1 | RE_START,
	    (x1 << 16) | (y1 & 0xffff));

	if (src != BUF_TYPE_TLB_A) {
		gbe_wait_re_idle(gsc);
		bus_space_write_4(gsc->iot, gsc->re_ioh, RE_PP_BUFMODE_SRC,
		    gsc->curscr->bufmode |
		    (BUF_TYPE_TLB_A << BUFMODE_BUFTYPE_SHIFT));
	}
}

void
gbe_fillrect(struct gbe_softc *gsc, int x, int y, int w, int h, int bg)
{

	gbe_wait_re_idle(gsc);

	bus_space_write_4(gsc->iot, gsc->re_ioh, RE_PP_PRIMITIVE,
	    PRIMITIVE_RECTANGLE | PRIMITIVE_LRTB);
	bus_space_write_4(gsc->iot, gsc->re_ioh, RE_PP_DRAWMODE,
	    DRAWMODE_BITMASK | DRAWMODE_BYTEMASK);
	bus_space_write_4(gsc->iot, gsc->re_ioh, RE_PP_SHADE_FG_COLOUR, bg);
	bus_space_write_4(gsc->iot, gsc->re_ioh, RE_PP_VERTEX_X_0,
	    (x << 16) | (y & 0xffff));
	bus_space_write_4(gsc->iot, gsc->re_ioh, RE_PP_VERTEX_X_1 | RE_START,
	    ((x + w - 1) << 16) | ((y + h - 1) & 0xffff));
}

int
gbe_do_cursor(struct rasops_info *ri)
{
	struct gbe_softc *sc = ri->ri_hw;
	int y, x, w, h;

	w = ri->ri_font->fontwidth;
	h = ri->ri_font->fontheight;
	x = ri->ri_xorigin + ri->ri_ccol * w;
	y = ri->ri_yorigin + ri->ri_crow * h;

	gbe_rop(sc, x, y, w, h, OPENGL_LOGIC_OP_COPY_INVERTED);

	return 0;
}

int
gbe_putchar(void *cookie, int row, int col, u_int uc, long attr)
{
	struct rasops_info *ri = cookie;
	struct gbe_softc *gsc = ri->ri_hw;
	struct gbe_screen *screen = gsc->curscr;
	struct rasops_info *ri_tile = &screen->ri_tile;
	int x, y, w, h;

	w = ri->ri_font->fontwidth;
	h = ri->ri_font->fontheight;
	x = ri->ri_xorigin + col * w;
	y = ri->ri_yorigin + row * h;

	ri_tile->ri_ops.putchar(ri_tile, 0, screen->ro_curpos, uc, attr);

	gbe_copyrect(gsc, BUF_TYPE_TLB_B, screen->ro_curpos * w, 0, x, y, w, h);

	screen->ro_curpos++;
	if ((screen->ro_curpos + 1) * w > screen->ri_tile.ri_width)
		screen->ro_curpos = 0;

	return 0;
}

int
gbe_copycols(void *cookie, int row, int src, int dst, int num)
{
	struct rasops_info *ri = cookie;
	struct gbe_softc *sc = ri->ri_hw;

	num *= ri->ri_font->fontwidth;
	src *= ri->ri_font->fontwidth;
	dst *= ri->ri_font->fontwidth;
	row *= ri->ri_font->fontheight;

	gbe_copyrect(sc, BUF_TYPE_TLB_A, ri->ri_xorigin + src,
	    ri->ri_yorigin + row, ri->ri_xorigin + dst, ri->ri_yorigin + row,
	    num, ri->ri_font->fontheight);

	return 0;
}

int
gbe_erasecols(void *cookie, int row, int col, int num, long attr)
{
	struct rasops_info *ri = cookie;
	struct gbe_softc *sc = ri->ri_hw;
	int bg, fg;

	ri->ri_ops.unpack_attr(cookie, attr, &fg, &bg, NULL);

	row *= ri->ri_font->fontheight;
	col *= ri->ri_font->fontwidth;
	num *= ri->ri_font->fontwidth;

	gbe_fillrect(sc, ri->ri_xorigin + col, ri->ri_yorigin + row,
	    num, ri->ri_font->fontheight, ri->ri_devcmap[bg]);

	return 0;
}

int
gbe_copyrows(void *cookie, int src, int dst, int num)
{
	struct rasops_info *ri = cookie;
	struct gbe_softc *sc = ri->ri_hw;

	num *= ri->ri_font->fontheight;
	src *= ri->ri_font->fontheight;
	dst *= ri->ri_font->fontheight;

	gbe_copyrect(sc, BUF_TYPE_TLB_A, ri->ri_xorigin, ri->ri_yorigin + src,
	    ri->ri_xorigin, ri->ri_yorigin + dst, ri->ri_emuwidth, num);

	return 0;
}

int
gbe_eraserows(void *cookie, int row, int num, long attr)
{
	struct rasops_info *ri = cookie;
	struct gbe_softc *sc = ri->ri_hw;
	int x, y, w, bg, fg;

	ri->ri_ops.unpack_attr(cookie, attr, &fg, &bg, NULL);

	if ((num == ri->ri_rows) && ISSET(ri->ri_flg, RI_FULLCLEAR)) {
		num = ri->ri_height;
		x = y = 0;
		w = ri->ri_width;
	} else {
		num *= ri->ri_font->fontheight;
		x = ri->ri_xorigin;
		y = ri->ri_yorigin + row * ri->ri_font->fontheight;
		w = ri->ri_emuwidth;
	}

	gbe_fillrect(sc, x, y, w, num, ri->ri_devcmap[bg]);

	return 0;
}

/*
 * Console functions for early display.
 */

int
gbe_cnprobe(bus_space_tag_t iot, bus_addr_t addr)
{
	bus_space_handle_t ioh;
	int val, width, height;

	/* Setup bus space mapping. */
	ioh = PHYS_TO_XKPHYS(addr, CCA_NC);

	/* Determine resolution configured by firmware. */
	val = bus_space_read_4(iot, ioh, GBE_VT_HCMAP);
	width = (val >> GBE_VT_HCMAP_ON_SHIFT) & 0xfff;
	val = bus_space_read_4(iot, ioh, GBE_VT_VCMAP);
	height = (val >> GBE_VT_VCMAP_ON_SHIFT) & 0xfff;

	/* Ensure that the firmware has setup the device. */
	if (width != 0 && height != 0)
		return (1);
	else
		return (0);
}

int
gbe_cnattach(bus_space_tag_t iot, bus_addr_t addr)
{
	struct gbe_softc *gsc;
	uint32_t val;
	paddr_t pa;
	vaddr_t va;
	long attr;

	/*
	 * Setup GBE for use as early console.
	 */
	va = pmap_steal_memory(sizeof(struct gbe_softc), NULL, NULL);
	gsc = (struct gbe_softc *)va;
	gsc->curscr = &gbe_consdata;
	gbe_consdata.sc = (struct device *)gsc;

	/* Setup bus space mapping. */
	gsc->iot = iot;
	gsc->ioh = PHYS_TO_XKPHYS(addr, CCA_NC);
	gsc->re_ioh = PHYS_TO_XKPHYS(RE_BASE, CCA_NC);

	/* Determine GBE revision. */
	gsc->rev = bus_space_read_4(gsc->iot, gsc->ioh, GBE_CTRL_STAT) & 0xf;

	/* Determine resolution configured by firmware. */
	val = bus_space_read_4(gsc->iot, gsc->ioh, GBE_VT_HCMAP);
	gbe_consdata.width = (val >> GBE_VT_HCMAP_ON_SHIFT) & 0xfff;
	val = bus_space_read_4(gsc->iot, gsc->ioh, GBE_VT_VCMAP);
	gbe_consdata.height = (val >> GBE_VT_VCMAP_ON_SHIFT) & 0xfff;

	/* Ensure that the firmware has setup the device. */
	if (gbe_consdata.width == 0 || gbe_consdata.height == 0)
		return (ENXIO);

	/* Setup screen defaults. */
	gbe_consdata.fb_size = GBE_FB_SIZE;
	gbe_consdata.tm_size = GBE_TLB_SIZE * sizeof(uint16_t);
	gbe_consdata.depth = 8;
	gbe_consdata.linebytes = gbe_consdata.width * gbe_consdata.depth / 8;

	/*
	 * Steal memory for tilemap - 64KB aligned and coherent.
	 */
	va = pmap_steal_memory(gbe_consdata.tm_size + 65536, NULL, NULL);
	pmap_extract(pmap_kernel(), va, &pa);
	gbe_consdata.tm_phys = ((pa >> 16) + 1) << 16;
	gbe_consdata.tm = (caddr_t)PHYS_TO_XKPHYS(gbe_consdata.tm_phys, CCA_NC);

	/*
	 * Steal memory for framebuffer - 64KB aligned and coherent.
	 */
	va = pmap_steal_memory(gbe_consdata.fb_size + 65536, NULL, NULL);
	pmap_extract(pmap_kernel(), va, &pa);
	gbe_consdata.fb_phys = ((pa >> 16) + 1) << 16;
	gbe_consdata.fb = (caddr_t)PHYS_TO_XKPHYS(gbe_consdata.fb_phys, CCA_NC);

	/*
	 * Steal memory for rasops tile - 64KB aligned and coherent.
	 */
	va = pmap_steal_memory(GBE_TILE_SIZE + 65536, NULL, NULL);
	pmap_extract(pmap_kernel(), va, &pa);
	gbe_consdata.ro_phys = ((pa >> 16) + 1) << 16;
	gbe_consdata.ro = (caddr_t)PHYS_TO_XKPHYS(gbe_consdata.ro_phys, CCA_NC);

	/*
	 * Setup GBE hardware.
	 */
	gbe_init_screen(&gbe_consdata);
	gbe_disable(gsc);
	gbe_setup(gsc);
	gbe_enable(gsc);

	/* Load colourmap if required. */
	if (gbe_consdata.depth == 8)
		gbe_loadcmap(&gbe_consdata, 0, 255);

	/* Clear framebuffer. */
	gbe_fillrect(gsc, 0, 0, gbe_consdata.width, gbe_consdata.height, 0);

	/*
	 * Attach wsdisplay.
	 */
	gbe_consdata.ri.ri_ops.alloc_attr(&gbe_consdata.ri, 0, 0, 0, &attr);
	wsdisplay_cnattach(&gbe_stdscreen, &gbe_consdata.ri, 0, 0, attr);
	gbe_console = 1;

	return (0);
}


code:
/*	$OpenBSD: gbereg.h,v 1.6 2012/05/29 17:37:09 mikeb Exp $ */

/*
 * Copyright (c) 2007, Joel Sing <jsing@openbsd.org>
 *
 * Permission to use, copy, modify, and distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

/*
 * GBE Framebuffer for SGI O2.
 */

#define GBE_BASE		0x16000000
#define GBE_REG_SIZE		0x100000
#define GBE_TLB_SIZE		128

#define GBE_TILE_SHIFT		16
#define GBE_TILE_SIZE		(1 << GBE_TILE_SHIFT)

#define GBE_TILE_WIDTH		512		/* Width of tile in bytes. */
#define GBE_TILE_WIDTH_SHIFT	9
#define GBE_TILE_HEIGHT		128		/* Height of tile in bytes. */
#define GBE_TILE_HEIGHT_SHIFT	7

/*
 * GBE Registers.
 */

#define GBE_CTRL_STAT		0x00000000	/* General control/status */
#define	GBE_CURSOR_ON		0x00000001
#define GBE_DOTCLOCK		0x00000004	/* Dotclock */
#define   GBE_DOTCLOCK_RUN	0x00100000	/* Enable dotclock */
#define GBE_VT_XY		0x00010000	/* Current dot coordinates */
#define   GBE_VT_XY_X_SHIFT	0
#define   GBE_VT_XY_X_MASK	0x00000fff
#define   GBE_VT_XY_Y_SHIFT	12
#define   GBE_VT_XY_Y_MASK	0x00fff000
#define   GBE_VT_XY_FREEZE	0x80000000	/* Freeze pixel counter */
#define GBE_VT_MAXXY		0x00010004	/* */
#define GBE_VT_VSYNC		0x00010008	/* Vertical sync on/off */
#define GBE_VT_HSYNC		0x0001000c	/* Horizontal sync on/off */
#define GBE_VT_VBLANK		0x00010010	/* Vertical blanking */
#define GBE_VT_HBLANK		0x00010014	/* Horizontal blanking */
#define GBE_VT_FLAGS		0x00010018	/* Video timing flags */
#define   GBE_VT_SYNC_LOW	0x00000020	/* Sync on green */
#define GBE_VT_HPIX		0x00010034	/* Horizontal pixel on/off */
#define GBE_VT_VPIX		0x00010038	/* Vertical pixel on/off */
#define   GBE_VT_VPIX_OFF_MASK	0x00000fff
#define   GBE_VT_VPIX_OFF_SHIFT	0
#define   GBE_VT_VPIX_ON_MASK	0x00fff000
#define   GBE_VT_VPIX_ON_SHIFT	12
#define GBE_VT_HCMAP		0x0001003c	/* Horizontal cmap write */
#define   GBE_VT_HCMAP_ON_SHIFT	12
#define GBE_VT_VCMAP		0x00010040	/* Vertical cmap write */
#define   GBE_VT_VCMAP_ON_SHIFT	12
#define GBE_VT_DIDSTARTXY	0x00010044	/* DID reset at x/y */
#define GBE_VT_CRSSTARTXY	0x00010048	/* CRS reset at x/y */
#define GBE_VT_VCSTARTXY	0x0001004c	/* VC reset at x/y */
#define GBE_OVERLAY_TILE	0x00020000	/* Overlay plane - tile width */
#define GBE_OVERLAY_HW_CTRL	0x00020004	/* Overlay plane - h/w control */
#define GBE_OVERLAY_CTRL	0x00020008	/* Overlay plane - control */
#define   GBE_OVERLAY_CTRL_DMA_ENABLE	0x00000001
#define GBE_FB_SIZE_TILE	0x00030000	/* Framebuffer - tile size */
#define   GBE_FB_SIZE_TILE_WIDTH_SHIFT		5
#define   GBE_FB_SIZE_TILE_DEPTH_SHIFT		13
#define   GBE_FB_SIZE_TILE_FIFO_RESET_SHIFT	15
#define GBE_FB_SIZE_PIXEL	0x00030004	/* Framebuffer - pixel size */
#define   GBE_FB_SIZE_PIXEL_HEIGHT_SHIFT	16
#define GBE_FB_HW_CTRL		0x00030008	/* Framebuffer - hardware control */
#define GBE_FB_CTRL		0x0003000c	/* Framebuffer - control */
#define   GBE_FB_CTRL_TILE_PTR_SHIFT	9
#define   GBE_FB_CTRL_DMA_ENABLE	0x00000001
#define GBE_DID_HW_CTRL		0x00040000	/* DID hardware control */
#define GBE_DID_CTRL		0x00040004	/* DID control */
#define GBE_MODE		0x00048000	/* Colour mode */
#define   GBE_WID_MODE_SHIFT	2
#define GBE_CMAP		0x050000	/* Colourmap */
#define   GBE_CMAP_ENTRIES	6144
#define GBE_CMAP_FIFO		0x058000	/* Colourmap FIFO status */
#define   GBE_CMAP_FIFO_ENTRIES	63
#define GBE_GMAP		0x060000	/* Gammamap */
#define   GBE_GMAP_ENTRIES	256
#define GBE_CURSOR_POS		0x00070000	/* Cursor position */
#define GBE_CURSOR_CTRL		0x00070004	/* Cursor control */

/*
 * GBE Constants.
 */

#define GBE_FB_DEPTH_8		0
#define GBE_FB_DEPTH_16		1
#define GBE_FB_DEPTH_32		2

#define GBE_CMODE_I8		0	/* 8 bit indexed */
#define GBE_CMODE_I12		1	/* 12 bit indexed */
#define GBE_CMODE_RG3B2		2	/* 3:3:2 direct */
#define GBE_CMODE_RGB4		3	/* 4:4:4 direct */
#define GBE_CMODE_ARGB5		4	/* 1:5:5:5 direct */
#define GBE_CMODE_RGB8		5	/* 8:8:8 direct */
#define GBE_CMODE_RGBA5		6	/* 5:5:5:5 direct */
#define GBE_CMODE_RGB10		7	/* 10:10:10 direct */

#define GBE_BMODE_BOTH		3

/*
 * Rendering Engine Registers.
 */

#define RE_BASE			0x15000000
#define RE_REG_SIZE		0x5000
#define RE_START		0x00000800	/* Start rendering operation. */

/* TLB Registers. */
#define RE_TLB_A		0x00001000	/* 256 16-bit tile entries. */
#define	RE_TLB_B		0x00001200
#define	RE_TLB_C		0x00001400
#define	RE_TLB_TEX		0x00001600
#define	RE_TLB_CLIP_ID		0x000016e0
#define	RE_TLB_LINEAR_A		0x00001700
#define	RE_TLB_LINEAR_B		0x00001780

/* Pixel Pipeline Registers. */
#define RE_PP_BUFMODE_SRC	0x00002000
#define RE_PP_BUFMODE_DST	0x00002008
#define RE_PP_CLIPMODE		0x00002010
#define RE_PP_DRAWMODE		0x00002018
#define   DRAWMODE_STENCIL	0x1 << 0
#define   DRAWMODE_DEPTH_MASK	0x1 << 1
#define   DRAWMODE_DEPTH_TEST   0x1 << 2
#define   DRAWMODE_BYTEMASK	0xf << 3
#define   DRAWMODE_BITMASK	0x1 << 7
#define   DRAWMODE_DITHER	0x1 << 8
#define   DRAWMODE_LOGIC_OP	0x1 << 9
#define   DRAWMODE_ALPHA_BLEND  0x1 << 10
#define   DRAWMODE_PIXEL_XFER	0x1 << 21
#define RE_PP_WINOFFSET_SRC	0x00002050
#define RE_PP_WINOFFSET_DST	0x00002058
#define RE_PP_PRIMITIVE		0x00002060	/* Drawing primitive. */
#define   PRIMITIVE_POINT	0x0 << 24
#define   PRIMITIVE_LINE	0x1 << 24
#define   PRIMITIVE_TRIANGLE	0x2 << 24
#define   PRIMITIVE_RECTANGLE	0x3 << 24
#define   PRIMITIVE_LRBT	0x0 << 16
#define   PRIMITIVE_RLBT	0x1 << 16
#define   PRIMITIVE_LRTB	0x2 << 16
#define   PRIMITIVE_RLTB	0x3 << 16
#define RE_PP_VERTEX_X_0	0x00002070	/* (x0,y0) vertex. */
#define RE_PP_VERTEX_X_1	0x00002074	/* (x1,y1) vertex. */
#define RE_PP_VERTEX_X_2	0x00002078	/* (x2,y2) vertex. */
#define RE_PP_PIXEL_XFER_SRC	0x000020a0	/* Pixel transfer source. */
#define RE_PP_PIXEL_XFER_X_STEP	0x000020a8
#define RE_PP_PIXEL_XFER_Y_STEP	0x000020ac
#define RE_PP_STIPPLE_MODE	0x000020c0
#define RE_PP_STIPPLE_PATTERN	0x000020c4
#define RE_PP_SHADE_FG_COLOUR	0x000020d0
#define RE_PP_SHADE_BG_COLOUR	0x000020d8
#define RE_PP_LOGIC_OP		0x000021b0	/* Logic operation. */
#define RE_PP_COLOUR_MASK	0x000021b8	/* Colour buffer plane mask. */
#define   COLOUR_MASK_NONE	0xffffffff
#define RE_PP_NULL		0x000021f0
#define RE_PP_FLUSH		0x000021f8

#define BUFMODE_PIXDEPTH_SHIFT	2		/* Pixel colour depth. */
#define BUFMODE_PIXTYPE_SHIFT	4		/* Pixel format. */
#define BUFMODE_BUFDEPTH_SHIFT	8		/* Buffer colour depth. */
#define BUFMODE_BUFTYPE_SHIFT	10		/* Source or destination. */

/* Status Registers. */
#define RE_PP_STATUS		0x00004000
#define   RE_PP_STATUS_IDLE	0x10000000
#define   RE_PP_STATUS_READY	0x02000000

/*
 * Rendering Engine Constants.
 */

#define COLOUR_DEPTH_8		0x0
#define COLOUR_DEPTH_16		0x1
#define COLOUR_DEPTH_32		0x2

#define PIXEL_TYPE_CI		0x0
#define PIXEL_TYPE_RGB		0x1
#define PIXEL_TYPE_RGBA		0x2
#define PIXEL_TYPE_ABGR		0x3

#define BUF_TYPE_TLB_A		0x0
#define BUF_TYPE_TLB_B		0x1
#define BUF_TYPE_TLB_C		0x2
#define BUF_TYPE_LINEAR_A	0x4
#define BUF_TYPE_LINEAR_B	0x5

/*
 * Console functions.
 */
int	gbe_cnprobe(bus_space_tag_t, bus_addr_t addr);
int	gbe_cnattach(bus_space_tag_t, bus_addr_t addr);

license: unknown


code:
/*	$OpenBSD: gl.h,v 1.1 2012/04/16 22:17:13 miod Exp $ */
/*
 * Copyright (c) 2009, 2010 Joel Sing <jsing@openbsd.org>
 *
 * Permission to use, copy, modify, and distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

/*
 * OpenGL defines
 */

/* Logic Operations. */
#define OPENGL_LOGIC_OP_CLEAR		0
#define OPENGL_LOGIC_OP_AND		1
#define OPENGL_LOGIC_OP_AND_REVERSE	2
#define OPENGL_LOGIC_OP_COPY		3
#define OPENGL_LOGIC_OP_AND_INVERTED	4
#define OPENGL_LOGIC_OP_NOOP		5
#define OPENGL_LOGIC_OP_XOR		6
#define OPENGL_LOGIC_OP_OR		7
#define OPENGL_LOGIC_OP_NOR		8
#define OPENGL_LOGIC_OP_EQUIV		9
#define OPENGL_LOGIC_OP_INVERT		10
#define OPENGL_LOGIC_OP_OR_REVERSE	11
#define OPENGL_LOGIC_OP_COPY_INVERTED	12
#define OPENGL_LOGIC_OP_OR_INVERTED	13
#define OPENGL_LOGIC_OP_NAND		14
#define OPENGL_LOGIC_OP_SET		15


code:
/*	$OpenBSD: if_iec.c,v 1.14 2015/06/24 09:40:53 mpi Exp $	*/

/*
 * Copyright (c) 2009 Miodrag Vallat.
 *
 * Permission to use, copy, modify, and distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */
/*
 * Heavily based upon if_mec.c with the following license terms:
 *
 *	OpenBSD: if_mec.c,v 1.22 2009/10/26 18:00:06 miod Exp
 *
 * Copyright (c) 2004 Izumi Tsutsui.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * Copyright (c) 2003 Christopher SEKIYA
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *          This product includes software developed for the
 *          NetBSD Project.  See http://www.NetBSD.org/ for
 *          information about NetBSD.
 * 4. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/*
 * IOC3 Ethernet driver
 */

#include "bpfilter.h"

#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <sys/timeout.h>
#include <sys/mbuf.h>
#include <sys/malloc.h>
#include <sys/kernel.h>
#include <sys/socket.h>
#include <sys/ioctl.h>
#include <sys/errno.h>

#include <net/if.h>
#include <net/if_dl.h>
#include <net/if_media.h>
#include <net/if_types.h>

#if NBPFILTER > 0
#include <net/bpf.h>
#endif

#include <netinet/in.h>
#include <netinet/if_ether.h>

#include <machine/autoconf.h>
#include <machine/bus.h>
#include <machine/intr.h>

#include <dev/mii/mii.h>
#include <dev/mii/miivar.h>

#include <sgi/dev/if_iecreg.h>
#include <sgi/dev/owmacvar.h>
#include <sgi/pci/iocreg.h>
#include <sgi/pci/iocvar.h>

#ifdef IEC_DEBUG
#define IEC_DEBUG_RESET		0x01
#define IEC_DEBUG_START		0x02
#define IEC_DEBUG_STOP		0x04
#define IEC_DEBUG_INTR		0x08
#define IEC_DEBUG_RXINTR	0x10
#define IEC_DEBUG_TXINTR	0x20
#define IEC_DEBUG_MII		0x40
uint32_t iec_debug = 0xffffffff;
#define DPRINTF(x, y)	if (iec_debug & (x)) printf y
#else
#define DPRINTF(x, y)	/* nothing */
#endif

/*
 * Transmit descriptor list size.
 */
#define IEC_NTXDESC		IEC_NTXDESC_MAX
#define IEC_NEXTTX(x)		(((x) + 1) % IEC_NTXDESC_MAX)

/*
 * Software state for TX.
 */
struct iec_txsoft {
	struct mbuf *txs_mbuf;		/* Head of our mbuf chain. */
	bus_dmamap_t txs_dmamap;	/* Our DMA map. */
	uint32_t txs_flags;
};

/*
 * Receive buffer management.
 *
 * The RX buffers chip register points to a contiguous array of
 * 512 8-bit pointers to the RX buffers themselves.
 */

/*
 * Receive descriptor list sizes (these depend on the size of the SSRAM).
 */
#define	IEC_NRXDESC_SMALL	64
#define	IEC_NRXDESC_LARGE	128

/*
 * In addition to the receive descriptor themselves, we'll need an array
 * of 512 RX descriptor pointers (regardless of how many real descriptors
 * we use), aligned on a 4KB boundary.
 */

/*
 * Control structures for DMA ops.
 */
struct iec_control_data {
	/*
	 * TX descriptors and buffers.
	 */
	struct iec_txdesc icd_txdesc[IEC_NTXDESC_MAX];

	/*
	 * RX descriptors and buffers.
	 */
	struct iec_rxdesc icd_rxdesc[1];
};

/*
 * Alignment restrictions (found by trial and error, might be slightly
 * pessimistic).
 * - base address of rx desc pointer array should be aligned on a
 *   16KB boundary.
 * - base address of rx and tx desc array should be aligned on
 *   16KB boundaries (note layout of struct iec_control_data makes sure
 *   the rx desc array starts 16KB after the tx desc array).
 * - each txdesc should be 128 byte aligned (this is also enforced by
 *   struct iec_control_data layout).
 * - each rxdesc should be aligned on a 4KB boundary (this is enforced by
 *   struct iec_control_data and struct icd_rxdesc layouts).
 */
#define	IEC_DMA_BOUNDARY	0x4000

#define IEC_CDOFF(x)	offsetof(struct iec_control_data, x)
#define IEC_CDTXOFF(x)	IEC_CDOFF(icd_txdesc[(x)])
#define IEC_CDRXOFF(x)	IEC_CDOFF(icd_rxdesc[(x)])

/*
 * Software state per device.
 */
struct iec_softc {
	struct device sc_dev;		/* Generic device structures. */
	struct arpcom sc_ac;		/* Ethernet common part. */

	bus_space_tag_t sc_st;		/* bus_space tag. */
	bus_space_handle_t sc_sh;	/* bus_space handle. */
	bus_dma_tag_t sc_dmat;		/* bus_dma tag. */

	struct mii_data sc_mii;		/* MII/media information. */
	int sc_phyaddr;			/* MII address. */
	struct timeout sc_tick;		/* Tick timeout. */

	uint64_t	*sc_rxarr;	/* kva for rx pointers array. */
	bus_dmamap_t	sc_rxarrmap;	/* bus_dma map for rx pointers array. */
#define	sc_rxptrdma	sc_rxarrmap->dm_segs[0].ds_addr

	bus_dmamap_t sc_cddmamap;	/* bus_dma map for control data. */
#define sc_cddma	sc_cddmamap->dm_segs[0].ds_addr

	/* Pointer to allocated control data. */
	struct iec_control_data *sc_control_data;
#define sc_txdesc	sc_control_data->icd_txdesc
#define sc_rxdesc	sc_control_data->icd_rxdesc

	/* Software state for TX descs. */
	struct iec_txsoft sc_txsoft[IEC_NTXDESC];

	int sc_txpending;		/* Number of TX requests pending. */
	int sc_txdirty;			/* First dirty TX descriptor. */
	int sc_txlast;			/* Last used TX descriptor. */

	uint32_t sc_rxci;		/* Saved RX consumer index. */
	uint32_t sc_rxpi;		/* Saved RX producer index. */
	uint32_t sc_nrxdesc;		/* Amount of RX descriptors. */

	uint32_t sc_mcr;		/* Current MCR value. */
};

#define IEC_CDTXADDR(sc, x)	((sc)->sc_cddma + IEC_CDTXOFF(x))
#define IEC_CDRXADDR(sc, x)	((sc)->sc_cddma + IEC_CDRXOFF(x))

#define IEC_TXDESCSYNC(sc, x, ops)					\
	bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,		\
	    IEC_CDTXOFF(x), IEC_TXDESCSIZE, (ops))
#define IEC_TXCMDSYNC(sc, x, ops)					\
	bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,		\
	    IEC_CDTXOFF(x), 2 * sizeof(uint32_t), (ops))

#define IEC_RXSTATSYNC(sc, x, ops)					\
	bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,		\
	    IEC_CDRXOFF(x), 2 * sizeof(uint32_t), (ops))
#define IEC_RXBUFSYNC(sc, x, len, ops)					\
	bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,		\
	    IEC_CDRXOFF(x) + IEC_RXD_BUFOFFSET,	(len), (ops))

/* XXX these values should be moved to <net/if_ether.h> ? */
#define ETHER_PAD_LEN	(ETHER_MIN_LEN - ETHER_CRC_LEN)

struct cfdriver iec_cd = {
	NULL, "iec", DV_IFNET
};

#define	DEVNAME(sc)	((sc)->sc_dev.dv_xname)

int	iec_match(struct device *, void *, void *);
void	iec_attach(struct device *, struct device *, void *);

struct cfattach iec_ca = {
	sizeof(struct iec_softc), iec_match, iec_attach
};

int	iec_mii_readreg(struct device *, int, int);
void	iec_mii_writereg(struct device *, int, int, int);
int	iec_mii_wait(struct iec_softc *);
void	iec_statchg(struct device *);
void	iec_mediastatus(struct ifnet *, struct ifmediareq *);
int	iec_mediachange(struct ifnet *);

int	iec_alloc_physical(struct iec_softc *, bus_dmamap_t *,
	    bus_dma_segment_t *, vaddr_t *, bus_addr_t, bus_size_t,
	    const char *);
struct mbuf *
	iec_get(struct iec_softc *, uint8_t *, size_t);
void	iec_iff(struct iec_softc *);
int	iec_init(struct ifnet * ifp);
int	iec_intr(void *arg);
int	iec_ioctl(struct ifnet *, u_long, caddr_t);
void	iec_reset(struct iec_softc *);
void	iec_rxintr(struct iec_softc *, uint32_t);
int	iec_ssram_probe(struct iec_softc *);
void	iec_start(struct ifnet *);
void	iec_stop(struct ifnet *);
void	iec_tick(void *);
void	iec_txintr(struct iec_softc *, uint32_t);
void	iec_watchdog(struct ifnet *);

int
iec_match(struct device *parent, void *match, void *aux)
{
	/*
	 * We expect ioc NOT to attach us on if there is no Ethernet
	 * component.
	 */
	return 1;
}

void
iec_attach(struct device *parent, struct device *self, void *aux)
{
	struct iec_softc *sc = (void *)self;
	struct ioc_attach_args *iaa = aux;
	struct ifnet *ifp = &sc->sc_ac.ac_if;
	struct mii_softc *child;
	bus_dma_segment_t seg1;
	bus_dma_segment_t seg2;
	bus_size_t control_size;
	int i, rc, rseg;

	sc->sc_st = iaa->iaa_memt;
	sc->sc_sh = iaa->iaa_memh;
	sc->sc_dmat = iaa->iaa_dmat;

	/*
	 * Try and figure out how much SSRAM is available, and decide
	 * how many RX buffers to use.
	 */
	i = iec_ssram_probe(sc);
	printf(": %dKB SSRAM", i);

	/*
	 * Allocate a page for RX descriptor pointers, suitable for use
	 * by the device.
	 */
	rc = iec_alloc_physical(sc, &sc->sc_rxarrmap, &seg1,
	    (vaddr_t *)&sc->sc_rxarr, IEC_DMA_BOUNDARY,
	    IEC_NRXDESC_MAX * sizeof(uint64_t), "rxdesc pointer array");
	if (rc != 0)
		return;

	/*
	 * Allocate the RX and TX descriptors.
	 */
	control_size = IEC_NTXDESC_MAX * sizeof(struct iec_txdesc) +
	    sc->sc_nrxdesc * sizeof(struct iec_rxdesc);
	rc = iec_alloc_physical(sc, &sc->sc_cddmamap, &seg2,
	    (vaddr_t *)&sc->sc_control_data, IEC_DMA_BOUNDARY,
	    control_size, "rx and tx descriptors");
	if (rc != 0)
		goto fail_1;

	/*
	 * Initialize RX pointer array.
	 */

	for (i = 0; i < IEC_NRXDESC_MAX; i++)
		sc->sc_rxarr[i] = IEC_CDRXADDR(sc, i & (sc->sc_nrxdesc - 1));

	/* Create TX buffer DMA maps. */
	for (i = 0; i < IEC_NTXDESC; i++) {
		if ((rc = bus_dmamap_create(sc->sc_dmat,
		    MCLBYTES, 1, MCLBYTES, 0, 0,
		    &sc->sc_txsoft[i].txs_dmamap)) != 0) {
			printf(": unable to create tx DMA map %d, error = %d\n",
			    i, rc);
			goto fail_4;
		}
	}

	timeout_set(&sc->sc_tick, iec_tick, sc);

	bcopy(iaa->iaa_enaddr, sc->sc_ac.ac_enaddr, ETHER_ADDR_LEN);
	printf(", address %s\n", ether_sprintf(sc->sc_ac.ac_enaddr));

	/* Reset device. */
	iec_reset(sc);

	/* Done, now attach everything. */

	sc->sc_mii.mii_ifp = ifp;
	sc->sc_mii.mii_readreg = iec_mii_readreg;
	sc->sc_mii.mii_writereg = iec_mii_writereg;
	sc->sc_mii.mii_statchg = iec_statchg;

	/* Set up PHY properties. */
	ifmedia_init(&sc->sc_mii.mii_media, 0, iec_mediachange,
	    iec_mediastatus);
	mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
	    MII_OFFSET_ANY, 0);

	child = LIST_FIRST(&sc->sc_mii.mii_phys);
	if (child == NULL) {
		/* No PHY attached. */
		ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL,
		    0, NULL);
		ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL);
	} else {
		ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO);
		sc->sc_phyaddr = child->mii_phy;
	}

	bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ);
	ifp->if_softc = sc;
	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
	ifp->if_ioctl = iec_ioctl;
	ifp->if_start = iec_start;
	ifp->if_watchdog = iec_watchdog;
	IFQ_SET_READY(&ifp->if_snd);

	if_attach(ifp);
	IFQ_SET_MAXLEN(&ifp->if_snd, IEC_NTXDESC - 1);
	ether_ifattach(ifp);

	/* Establish interrupt handler. */
	ioc_intr_establish(parent, iaa->iaa_dev, IPL_NET,
	    iec_intr, sc, sc->sc_dev.dv_xname);

	return;

	/*
	 * Free any resources we've allocated during the failed attach
	 * attempt. Do this in reverse order and fall through.
	 */
fail_4:
	for (i = 0; i < IEC_NTXDESC; i++) {
		if (sc->sc_txsoft[i].txs_dmamap != NULL)
			bus_dmamap_destroy(sc->sc_dmat,
			    sc->sc_txsoft[i].txs_dmamap);
	}

	bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap);
	bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap);
	bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data,
	    control_size);
	bus_dmamem_free(sc->sc_dmat, &seg2, rseg);
fail_1:
	bus_dmamap_unload(sc->sc_dmat, sc->sc_rxarrmap);
	bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxarrmap);
	bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_rxarr,
	    IEC_NRXDESC_MAX * sizeof(uint64_t));
	bus_dmamem_free(sc->sc_dmat, &seg1, rseg);
}

/*
 * Allocate contiguous physical memory.
 */
int
iec_alloc_physical(struct iec_softc *sc, bus_dmamap_t *dmamap,
    bus_dma_segment_t *dmaseg, vaddr_t *va, bus_addr_t alignment,
    bus_size_t len, const char *what)
{
	int nseg;
	int rc;

	rc = bus_dmamem_alloc(sc->sc_dmat, len, alignment, 0, dmaseg, 1, &nseg,
	    BUS_DMA_NOWAIT);
	if (rc != 0) {
		printf("%s: unable to allocate %s memory: error %d\n",
		    DEVNAME(sc), what, rc);
		goto fail1;
	}

	rc = bus_dmamem_map(sc->sc_dmat, dmaseg, nseg, len,
	    (caddr_t *)va, BUS_DMA_NOWAIT | BUS_DMA_COHERENT);
	if (rc != 0) {
		printf("%s: unable to map %s memory: error %d\n",
		    DEVNAME(sc), what, rc);
		goto fail2;
	}

	rc = bus_dmamap_create(sc->sc_dmat, len, 1, len, 0, BUS_DMA_NOWAIT,
	    dmamap);
	if (rc != 0) {
		printf("%s: unable to create %s dma map: error %d\n",
		    DEVNAME(sc), what, rc);
		goto fail3;
	}

	rc = bus_dmamap_load(sc->sc_dmat, *dmamap, (void *)*va, len, NULL,
	    BUS_DMA_NOWAIT);
	if (rc != 0) {
		printf("%s: unable to load %s dma map: error %d\n",
		    DEVNAME(sc), what, rc);
		goto fail4;
	}

	memset((caddr_t)*va, 0, len);
	return 0;

fail4:
	bus_dmamap_destroy(sc->sc_dmat, *dmamap);
fail3:
	bus_dmamem_unmap(sc->sc_dmat, (caddr_t)*va, PAGE_SIZE);
fail2:
	bus_dmamem_free(sc->sc_dmat, dmaseg, 1);
fail1:
	return rc;
}

int
iec_mii_readreg(struct device *self, int phy, int reg)
{
	struct iec_softc *sc = (void *)self;
	bus_space_tag_t st = sc->sc_st;
	bus_space_handle_t sh = sc->sc_sh;

	if (iec_mii_wait(sc) != 0)
		return 0;

	bus_space_write_4(st, sh, IOC3_ENET_MICR, IOC3_ENET_MICR_READ |
	    (phy << IOC3_ENET_MICR_PHY_SHIFT) |
	    (reg & IOC3_ENET_MICR_REG_MASK));
	delay(25);

	if (iec_mii_wait(sc) == 0)
		return bus_space_read_4(st, sh, IOC3_ENET_MIDR_R) &
		    IOC3_ENET_MIDR_MASK;

	DPRINTF(IEC_DEBUG_MII, ("MII timed out reading %x\n", reg));
	return 0;
}

void
iec_mii_writereg(struct device *self, int phy, int reg, int val)
{
	struct iec_softc *sc = (void *)self;
	bus_space_tag_t st = sc->sc_st;
	bus_space_handle_t sh = sc->sc_sh;

	if (iec_mii_wait(sc) != 0) {
		DPRINTF(IEC_DEBUG_MII,
		    ("MII timed out writing %x: %x\n", reg, val));
		return;
	}

	bus_space_write_4(st, sh, IOC3_ENET_MIDR_W, val & IOC3_ENET_MIDR_MASK);
	delay(60);
	bus_space_write_4(st, sh, IOC3_ENET_MICR,
	    (phy << IOC3_ENET_MICR_PHY_SHIFT) |
	    (reg & IOC3_ENET_MICR_REG_MASK));
	delay(60);

	iec_mii_wait(sc);
}

int
iec_mii_wait(struct iec_softc *sc)
{
	uint32_t busy;
	int i;

	for (i = 0; i < 100; i++) {
		busy = bus_space_read_4(sc->sc_st, sc->sc_sh, IOC3_ENET_MICR);
		if ((busy & IOC3_ENET_MICR_BUSY) == 0)
			return 0;
		delay(30);
	}

	printf("%s: MII timed out\n", sc->sc_dev.dv_xname);
	return 1;
}

void
iec_statchg(struct device *self)
{
	struct iec_softc *sc = (void *)self;
	bus_space_tag_t st = sc->sc_st;
	bus_space_handle_t sh = sc->sc_sh;
	uint32_t tcsr;

	if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) {
		tcsr = IOC3_ENET_TCSR_FULL_DUPLEX;
		sc->sc_mcr |= IOC3_ENET_MCR_DUPLEX;
	} else {
		tcsr = IOC3_ENET_TCSR_HALF_DUPLEX;
		sc->sc_mcr &= ~IOC3_ENET_MCR_DUPLEX;
	}

	bus_space_write_4(st, sh, IOC3_ENET_MCR, sc->sc_mcr);
	bus_space_write_4(st, sh, IOC3_ENET_TCSR, tcsr);
}

void
iec_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
{
	struct iec_softc *sc = ifp->if_softc;

	if ((ifp->if_flags & IFF_UP) == 0)
		return;

	mii_pollstat(&sc->sc_mii);
	ifmr->ifm_status = sc->sc_mii.mii_media_status;
	ifmr->ifm_active = sc->sc_mii.mii_media_active;
}

int
iec_mediachange(struct ifnet *ifp)
{
	struct iec_softc *sc = ifp->if_softc;

	if ((ifp->if_flags & IFF_UP) == 0)
		return 0;

	return mii_mediachg(&sc->sc_mii);
}

int
iec_init(struct ifnet *ifp)
{
	struct iec_softc *sc = ifp->if_softc;
	bus_space_tag_t st = sc->sc_st;
	bus_space_handle_t sh = sc->sc_sh;
	struct iec_rxdesc *rxd;
	int i;

	/* Cancel any pending I/O. */
	iec_stop(ifp);

	/* Reset device. */
	iec_reset(sc);

	/* Setup filter for multicast or promisc mode. */
	iec_iff(sc);

	/*
	 * Initialize TX ring.
	 */

	bus_space_write_4(st, sh, IOC3_ENET_TBR_H, IEC_CDTXADDR(sc, 0) >> 32);
	bus_space_write_4(st, sh, IOC3_ENET_TBR_L,
	    (uint32_t)IEC_CDTXADDR(sc, 0));
	bus_space_write_4(st, sh, IOC3_ENET_TCIR, 0);
	bus_space_write_4(st, sh, IOC3_ENET_TPIR, 0);
	(void)bus_space_read_4(st, sh, IOC3_ENET_TCIR);

	sc->sc_txpending = 0;
	sc->sc_txdirty = 0;
	sc->sc_txlast = IEC_NTXDESC - 1;

	/*
	 * Initialize RX ring.
	 */

	/* Point the RX base register to our RX pointers array. */
	bus_space_write_4(st, sh, IOC3_ENET_RBR_H, sc->sc_rxptrdma >> 32);
	bus_space_write_4(st, sh, IOC3_ENET_RBR_L, (uint32_t)sc->sc_rxptrdma);

	sc->sc_rxci = 0;
	sc->sc_rxpi = sc->sc_nrxdesc + 1;
	bus_space_write_4(st, sh, IOC3_ENET_RCIR,
	    sc->sc_rxci * sizeof(uint64_t));
	bus_space_write_4(st, sh, IOC3_ENET_RPIR,
	    (sc->sc_rxpi * sizeof(uint64_t)) | IOC3_ENET_PIR_SET);

	/* Interrupt as soon as available RX desc reach this limit */
	bus_space_write_4(st, sh, IOC3_ENET_RCSR,
	    sc->sc_rxpi - sc->sc_rxci - 1);
	/* Set up RX timer to interrupt immediately upon reception. */
	bus_space_write_4(st, sh, IOC3_ENET_RTR, 0);

	/* Initialize RX buffers. */
	for (i = 0; i < sc->sc_nrxdesc; i++) {
		rxd = &sc->sc_rxdesc[i];
		rxd->rxd_stat = 0;
		IEC_RXSTATSYNC(sc, i, BUS_DMASYNC_PREREAD);
		IEC_RXBUFSYNC(sc, i, ETHER_MAX_LEN, BUS_DMASYNC_PREREAD);
	}

	/* Enable DMA, and RX and TX interrupts */
	sc->sc_mcr &= IOC3_ENET_MCR_LARGE_SSRAM | IOC3_ENET_MCR_PARITY_ENABLE |
	    IOC3_ENET_MCR_PADEN;
	sc->sc_mcr |= IOC3_ENET_MCR_TX_DMA | IOC3_ENET_MCR_TX |
	    IOC3_ENET_MCR_RX_DMA | IOC3_ENET_MCR_RX |
	    ((IEC_RXD_BUFOFFSET >> 1) << IOC3_ENET_MCR_RXOFF_SHIFT);
	bus_space_write_4(st, sh, IOC3_ENET_MCR, sc->sc_mcr);
	bus_space_write_4(st, sh, IOC3_ENET_IER,
	    IOC3_ENET_ISR_RX_TIMER | IOC3_ENET_ISR_RX_THRESHOLD |
	    (IOC3_ENET_ISR_TX_ALL & ~IOC3_ENET_ISR_TX_EMPTY));
	(void)bus_space_read_4(st, sh, IOC3_ENET_IER);

	timeout_add_sec(&sc->sc_tick, 1);

	ifp->if_flags |= IFF_RUNNING;
	ifp->if_flags &= ~IFF_OACTIVE;

	iec_start(ifp);

	mii_mediachg(&sc->sc_mii);

	return 0;
}

void
iec_reset(struct iec_softc *sc)
{
	bus_space_tag_t st = sc->sc_st;
	bus_space_handle_t sh = sc->sc_sh;
	uint64_t address;
	int i;

	DPRINTF(IEC_DEBUG_RESET, ("iec_reset\n"));

	/* Reset chip. */
	bus_space_write_4(st, sh, IOC3_ENET_MCR, IOC3_ENET_MCR_RESET);
	delay(1000);
	bus_space_write_4(st, sh, IOC3_ENET_MCR, 0);
	delay(1000);

	bus_space_write_4(st, sh, IOC3_ENET_RBAR, 0);

	/* Set Ethernet address. */
	address = 0;
	for (i = 0; i < ETHER_ADDR_LEN; i++) {
		address <<= 8;
		address += sc->sc_ac.ac_enaddr[ETHER_ADDR_LEN - 1 - i];
	}
	bus_space_write_4(st, sh, IOC3_ENET_MAR_H, address >> 32);
	bus_space_write_4(st, sh, IOC3_ENET_MAR_L, (uint32_t)address);

	/* Default to 100/half and let auto-negotiation work its magic. */
	bus_space_write_4(st, sh, IOC3_ENET_TCSR, IOC3_ENET_TCSR_HALF_DUPLEX);

	/* Reset collisions counter */
	(void)bus_space_read_4(st, sh, IOC3_ENET_TCDC);

	bus_space_write_4(st, sh, IOC3_ENET_RSR, 0x4d696f64);

	bus_space_write_4(st, sh, IOC3_ENET_HAR_H, 0);
	bus_space_write_4(st, sh, IOC3_ENET_HAR_L, 0);
}

void
iec_start(struct ifnet *ifp)
{
	struct iec_softc *sc = ifp->if_softc;
	struct mbuf *m0;
	struct iec_txdesc *txd;
	struct iec_txsoft *txs;
	bus_dmamap_t dmamap;
	bus_space_tag_t st = sc->sc_st;
	bus_space_handle_t sh = sc->sc_sh;
	uint64_t txdaddr;
	int error, firstdirty, nexttx, opending;
	int len;

	if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING)
		return;

	/*
	 * Remember the previous txpending and the first transmit descriptor.
	 */
	opending = sc->sc_txpending;
	firstdirty = IEC_NEXTTX(sc->sc_txlast);

	DPRINTF(IEC_DEBUG_START, ("iec_start: opending = %d, firstdirty = %d\n",
	    opending, firstdirty));

	for (;;) {
		/* Grab a packet off the queue. */
		IFQ_POLL(&ifp->if_snd, m0);
		if (m0 == NULL)
			break;

		if (sc->sc_txpending == IEC_NTXDESC)
			break;

		/*
		 * Get the next available transmit descriptor.
		 */
		nexttx = IEC_NEXTTX(sc->sc_txlast);
		txd = &sc->sc_txdesc[nexttx];
		txs = &sc->sc_txsoft[nexttx];

		len = m0->m_pkthdr.len;

		DPRINTF(IEC_DEBUG_START,
		    ("iec_start: len = %d, nexttx = %d\n", len, nexttx));

		IFQ_DEQUEUE(&ifp->if_snd, m0);
		if (len <= IEC_TXD_BUFSIZE) {
			/*
			 * If the packet is small enough,
			 * just copy it to the buffer in txdesc and
			 * pad with zeroes.
			 */
			DPRINTF(IEC_DEBUG_START, ("iec_start: short packet\n"));

			m_copydata(m0, 0, m0->m_pkthdr.len, txd->txd_buf);
			if (len < ETHER_PAD_LEN) {
				/*
				 * XXX would IOC3_ENET_MCR_PADEN in MCR do this
				 * XXX for us?
				 */
				memset(txd->txd_buf + len, 0,
				    ETHER_PAD_LEN - len);
				len = ETHER_PAD_LEN;
			}

			txs->txs_flags = IEC_TXCMD_BUF_V;
		} else {
			/*
			 * Although the packet may fit in the txdesc
			 * itself, we do not make use of this option,
			 * and use the two data pointers to handle it.
			 * There are two pointers because each chunk must
			 * not cross a 16KB boundary.
	                 */
			dmamap = txs->txs_dmamap;
			if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0,
			    BUS_DMA_WRITE | BUS_DMA_NOWAIT) != 0) {
				struct mbuf *m;

				DPRINTF(IEC_DEBUG_START,
				    ("iec_start: re-allocating mbuf\n"));
				MGETHDR(m, M_DONTWAIT, MT_DATA);
				if (m == NULL) {
					printf("%s: unable to allocate "
					    "TX mbuf\n", sc->sc_dev.dv_xname);
					break;
				}
				if (len > (MHLEN - ETHER_ALIGN)) {
					MCLGET(m, M_DONTWAIT);
					if ((m->m_flags & M_EXT) == 0) {
						printf("%s: unable to allocate "
						    "TX cluster\n",
						    sc->sc_dev.dv_xname);
						m_freem(m);
						break;
					}
				}
				/*
				 * Each packet has the Ethernet header, so
				 * in many cases the header isn't 4-byte aligned
				 * and data after the header is 4-byte aligned.
				 * Thus adding 2-byte offset before copying to
				 * new mbuf avoids unaligned copy and this may
				 * improve performance.
				 */
				m->m_data += ETHER_ALIGN;
				m_copydata(m0, 0, len, mtod(m, caddr_t));
				m->m_pkthdr.len = m->m_len = len;
				m_freem(m0);
				m0 = m;
				error = bus_dmamap_load_mbuf(sc->sc_dmat,
				    dmamap, m, BUS_DMA_WRITE | BUS_DMA_NOWAIT);
				if (error) {
					printf("%s: unable to load TX buffer, "
					    "error = %d\n",
					    sc->sc_dev.dv_xname, error);
					m_freem(m);
					break;
				}
			}

			txdaddr = dmamap->dm_segs[0].ds_addr;
			txs->txs_flags = IEC_TXCMD_PTR0_V;
			DPRINTF(IEC_DEBUG_START,
			    ("iec_start: ds_addr = %p\n",
			    dmamap->dm_segs[0].ds_addr));

			DPRINTF(IEC_DEBUG_START,
			    ("iec_start: txdaddr = %p, len = %d\n",
			    txdaddr, len));

			/*
			 * Sync the DMA map for TX mbuf.
			 *
			 * XXX unaligned part doesn't have to be sync'ed,
			 *     but it's harmless...
			 */
			bus_dmamap_sync(sc->sc_dmat, dmamap, 0,
			    dmamap->dm_mapsize,	BUS_DMASYNC_PREWRITE);
		}

#if NBPFILTER > 0
		/*
		 * Pass packet to bpf if there is a listener.
		 */
		if (ifp->if_bpf)
			bpf_mtap(ifp->if_bpf, m0, BPF_DIRECTION_OUT);
#endif

		/*
		 * Setup the transmit descriptor.
		 * Since there is apparently no way to get status
		 * information in the TX descriptor after we issue
		 * it, we have to always ask for interrupts upon
		 * completion, so that if we get a TX error interrupt,
		 * we know which descriptor it applies to.
		 */

		txd->txd_cmd = IEC_TXCMD_TXINT | txs->txs_flags |
		    (len & IEC_TXCMD_DATALEN);

		if (txs->txs_flags & IEC_TXCMD_PTR0_V) {
			uint32_t r1, r2;

			/*
			 * The chip DMA engine can not cross 16KB boundaries.
			 * If our mbuf doesn't fit, use the second pointer.
			 */

			r1 = IEC_DMA_BOUNDARY -
			    (txdaddr & (IEC_DMA_BOUNDARY - 1));
			if (r1 >= len) {
				/* only one chunk is necessary */
				r1 = len;
				r2 = 0;
			} else
				r2 = len - r1;

			txd->txd_ptr[0] = txdaddr;
			if (r2 != 0) {
				txs->txs_flags |= IEC_TXCMD_PTR1_V;
				txd->txd_ptr[1] = txdaddr + r1;
			} else
				txd->txd_ptr[1] = 0;
			txd->txd_len = (r1 << IECTX_BUF1_LEN_SHIFT) |
			    (r2 << IECTX_BUF2_LEN_SHIFT);

			/*
			 * Store a pointer to the packet so we can
			 * free it later.
			 */
			txs->txs_mbuf = m0;
		} else {
			txd->txd_len = len << IECTX_BUF0_LEN_SHIFT;
			txd->txd_ptr[0] = 0;
			txd->txd_ptr[1] = 0;
			/*
			 * In this case all data are copied to buffer in txdesc,
			 * we can free TX mbuf here.
			 */
			m_freem(m0);
		}

		DPRINTF(IEC_DEBUG_START,
		    ("iec_start: txd_cmd = 0x%08x, txd_ptr = %p\n",
		    txd->txd_cmd, txd->txd_ptr[0]));
		DPRINTF(IEC_DEBUG_START,
		    ("iec_start: len = %d (0x%04x)\n", len, len));

		/* Sync TX descriptor. */
		IEC_TXDESCSYNC(sc, nexttx,
		    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);

		/* Advance the TX pointer. */
		sc->sc_txpending++;
		sc->sc_txlast = nexttx;
	}

	if (sc->sc_txpending == IEC_NTXDESC) {
		/* No more slots; notify upper layer. */
		ifp->if_flags |= IFF_OACTIVE;
	}

	if (sc->sc_txpending != opending) {
		/* Start TX. */
		bus_space_write_4(st, sh, IOC3_ENET_TPIR,
		    IEC_NEXTTX(sc->sc_txlast) * IEC_TXDESCSIZE);

		/*
		 * If the transmitter was idle,
		 * reset the txdirty pointer and re-enable TX interrupt.
		 */
		if (opending == 0) {
			sc->sc_txdirty = firstdirty;
			bus_space_write_4(st, sh, IOC3_ENET_IER,
			    bus_space_read_4(st, sh, IOC3_ENET_IER) |
			    IOC3_ENET_ISR_TX_EMPTY);
			(void)bus_space_read_4(st, sh, IOC3_ENET_IER);
		}

		/* Set a watchdog timer in case the chip flakes out. */
		ifp->if_timer = 5;
	}
}

void
iec_stop(struct ifnet *ifp)
{
	struct iec_softc *sc = ifp->if_softc;
	struct iec_txsoft *txs;
	int i;

	DPRINTF(IEC_DEBUG_STOP, ("iec_stop\n"));

	ifp->if_timer = 0;
	ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);

	timeout_del(&sc->sc_tick);
	mii_down(&sc->sc_mii);

	/* Disable DMA and interrupts. */
	sc->sc_mcr &= ~(IOC3_ENET_MCR_TX_DMA | IOC3_ENET_MCR_RX_DMA);
	bus_space_write_4(sc->sc_st, sc->sc_sh, IOC3_ENET_MCR, sc->sc_mcr);
	bus_space_write_4(sc->sc_st, sc->sc_sh, IOC3_ENET_IER, 0);
	(void)bus_space_read_4(sc->sc_st, sc->sc_sh, IOC3_ENET_IER);

	/* Release any TX buffers. */
	for (i = 0; i < IEC_NTXDESC; i++) {
		txs = &sc->sc_txsoft[i];
		if ((txs->txs_flags & IEC_TXCMD_PTR0_V) != 0) {
			bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap);
			m_freem(txs->txs_mbuf);
			txs->txs_mbuf = NULL;
		}
	}
}

int
iec_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
{
	struct iec_softc *sc = ifp->if_softc;
	struct ifreq *ifr = (struct ifreq *)data;
	struct ifaddr *ifa = (struct ifaddr *)data;
	int s, error = 0;

	s = splnet();

	switch (cmd) {
	case SIOCSIFADDR:
		ifp->if_flags |= IFF_UP;
		if (!(ifp->if_flags & IFF_RUNNING))
			iec_init(ifp);
		if (ifa->ifa_addr->sa_family == AF_INET)
			arp_ifinit(&sc->sc_ac, ifa);
		break;

	case SIOCSIFFLAGS:
		if (ifp->if_flags & IFF_UP) {
			if (ifp->if_flags & IFF_RUNNING)
				error = ENETRESET;
			else
				iec_init(ifp);
		} else {
			if (ifp->if_flags & IFF_RUNNING)
				iec_stop(ifp);
		}
		break;

	case SIOCSIFMEDIA:
	case SIOCGIFMEDIA:
		error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd);
		break;

	default:
		error = ether_ioctl(ifp, &sc->sc_ac, cmd, data);
	}

	if (error == ENETRESET) {
		if (ifp->if_flags & IFF_RUNNING)
			iec_iff(sc);
		error = 0;
	}

	splx(s);
	return error;
}

void
iec_watchdog(struct ifnet *ifp)
{
	struct iec_softc *sc = ifp->if_softc;

	printf("%s: device timeout\n", sc->sc_dev.dv_xname);
	ifp->if_oerrors++;

	DPRINTF(IEC_DEBUG_INTR, ("iec_watchdog: ISR %08x IER %08x\n",
	    bus_space_read_4(sc->sc_st, sc->sc_sh, IOC3_ENET_ISR),
	    bus_space_read_4(sc->sc_st, sc->sc_sh, IOC3_ENET_IER)));

	iec_init(ifp);
}

void
iec_tick(void *arg)
{
	struct iec_softc *sc = arg;
	int s;

	s = splnet();
	mii_tick(&sc->sc_mii);
	splx(s);

	timeout_add_sec(&sc->sc_tick, 1);
}

void
iec_iff(struct iec_softc *sc)
{
	struct arpcom *ac = &sc->sc_ac;
	struct ifnet *ifp = &sc->sc_ac.ac_if;
	struct ether_multi *enm;
	struct ether_multistep step;
	bus_space_tag_t st = sc->sc_st;
	bus_space_handle_t sh = sc->sc_sh;
	uint64_t mchash = 0;
	uint32_t hash;

	sc->sc_mcr &= ~IOC3_ENET_MCR_PROMISC;
	ifp->if_flags &= ~IFF_ALLMULTI;

	if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) {
		ifp->if_flags |= IFF_ALLMULTI;
		if (ifp->if_flags & IFF_PROMISC)
			sc->sc_mcr |= IOC3_ENET_MCR_PROMISC;
		mchash = 0xffffffffffffffffULL;
	} else {
		ETHER_FIRST_MULTI(step, ac, enm);
		while (enm != NULL) {
			hash = ether_crc32_be(enm->enm_addrlo,
			    ETHER_ADDR_LEN) >> 26;

			mchash |= 1 << hash;

			ETHER_NEXT_MULTI(step, enm);
		}
	}

	bus_space_write_4(st, sh, IOC3_ENET_HAR_H, mchash >> 32);
	bus_space_write_4(st, sh, IOC3_ENET_HAR_L, (uint32_t)mchash);
	bus_space_write_4(st, sh, IOC3_ENET_MCR, sc->sc_mcr);
}

struct mbuf *
iec_get(struct iec_softc *sc, uint8_t *data, size_t datalen)
{
	struct mbuf *m, **mp, *head;
	size_t len, pad;

	MGETHDR(m, M_DONTWAIT, MT_DATA);
	if (m == NULL) {
		printf("%s: unable to allocate RX mbuf\n",
		    sc->sc_dev.dv_xname);
		return NULL;
	}

	m->m_pkthdr.len = datalen;

	pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header);
	m->m_data += pad;
	len = MHLEN - pad;
	head = NULL;
	mp = &head;

	while (datalen != 0) {
		if (head != NULL) {
			MGET(m, M_DONTWAIT, MT_DATA);
			if (m == NULL) {
				printf("%s: unable to allocate RX mbuf\n",
				    sc->sc_dev.dv_xname);
				m_freem(head);
				return NULL;
			}
			len = MHLEN;
		}
		if (datalen >= MINCLSIZE) {
			MCLGET(m, M_DONTWAIT);
			if ((m->m_flags & M_EXT) == 0) {
				printf("%s: unable to allocate RX cluster\n",
				    sc->sc_dev.dv_xname);
				if (head != NULL)
					m_freem(head);
				return NULL;
			}
			len = MCLBYTES;
			if (head == NULL) {
				m->m_data += pad;
				len -= pad;
			}
		}
		m->m_len = len = min(datalen, len);
		memcpy(mtod(m, caddr_t), data, len);
		data += len;
		datalen -= len;
		*mp = m;
		mp = &m->m_next;
	}

	return head;
}

int
iec_intr(void *arg)
{
	struct iec_softc *sc = arg;
	bus_space_tag_t st = sc->sc_st;
	bus_space_handle_t sh = sc->sc_sh;
	struct ifnet *ifp = &sc->sc_ac.ac_if;
	uint32_t statreg, statack;
	int handled, sent;

	DPRINTF(IEC_DEBUG_INTR, ("iec_intr: called\n"));

	handled = sent = 0;

	for (;;) {
		statreg = bus_space_read_4(st, sh, IOC3_ENET_ISR);

		DPRINTF(IEC_DEBUG_INTR,
		    ("iec_intr: INT_STAT = 0x%x\n", statreg));

		statack = statreg & bus_space_read_4(st, sh, IOC3_ENET_IER);
		if (statack == 0)
			break;
		bus_space_write_4(st, sh, IOC3_ENET_ISR, statack);

		handled = 1;

		if (statack &
		    (IOC3_ENET_ISR_RX_TIMER | IOC3_ENET_ISR_RX_THRESHOLD)) {
			iec_rxintr(sc, statreg);
		}

		if (statack & IOC3_ENET_ISR_TX_ALL) {
			iec_txintr(sc, statreg & IOC3_ENET_ISR_TX_ALL);
			sent = 1;
		}
	}

	if (sent) {
		/* Try to get more packets going. */
		iec_start(ifp);
	}

	return handled;
}

void
iec_rxintr(struct iec_softc *sc, uint32_t stat)
{
	bus_space_tag_t st = sc->sc_st;
	bus_space_handle_t sh = sc->sc_sh;
	struct ifnet *ifp = &sc->sc_ac.ac_if;
	struct mbuf_list ml = MBUF_LIST_INITIALIZER();
	struct mbuf *m;
	struct iec_rxdesc *rxd;
	uint64_t rxstat;
	size_t len;
	u_int packets;
	uint32_t i, ci;

	/*
	 * Figure out how many RX descriptors are available for processing.
	 */
	ci = bus_space_read_4(st, sh, IOC3_ENET_RCIR) / sizeof(uint64_t);
	packets = (ci + IEC_NRXDESC_MAX - sc->sc_rxci) % IEC_NRXDESC_MAX;
	sc->sc_rxpi = (sc->sc_rxpi + packets) % IEC_NRXDESC_MAX;

	DPRINTF(IEC_DEBUG_RXINTR, ("iec_rxintr: rx %d-%d\n", sc->sc_rxci, ci));
	while (packets-- != 0) {
		i = (sc->sc_rxci++) & (sc->sc_nrxdesc - 1);

		IEC_RXSTATSYNC(sc, i, BUS_DMASYNC_POSTREAD);
		rxd = &sc->sc_rxdesc[i];
		rxstat = rxd->rxd_stat;

		DPRINTF(IEC_DEBUG_RXINTR,
		    ("iec_rxintr: rxstat = 0x%08x, rxerr = 0x%08x\n",
		    rxstat, rxd->rxd_err));

		if ((rxstat & IEC_RXSTAT_VALID) == 0)
			goto dropit;

		len = (rxstat & IEC_RXSTAT_LEN_MASK) >> IEC_RXSTAT_LEN_SHIFT;

		if (len < ETHER_MIN_LEN ||
		    len > ETHER_MAX_LEN) {
			/* Invalid length packet; drop it. */
			DPRINTF(IEC_DEBUG_RXINTR,
			    ("iec_rxintr: wrong packet\n"));
dropit:
			ifp->if_ierrors++;
			rxd->rxd_stat = 0;
			IEC_RXSTATSYNC(sc, i, BUS_DMASYNC_PREREAD);
			continue;
		}

		if (rxd->rxd_err & (IEC_RXERR_BADPACKET | IEC_RXERR_LONGEVENT |
		     IEC_RXERR_INVPREAMB | IEC_RXERR_CODE | IEC_RXERR_FRAME |
		     IEC_RXERR_CRC)) {
			printf("%s: iec_rxintr: stat = 0x%08llx err = %08x\n",
			    sc->sc_dev.dv_xname, rxstat, rxd->rxd_err);
			goto dropit;
		}

		/*
		 * Now allocate an mbuf (and possibly a cluster) to hold
		 * the received packet.
		 */
		len -= ETHER_CRC_LEN;
		IEC_RXBUFSYNC(sc, i, len, BUS_DMASYNC_POSTREAD);
		m = iec_get(sc, rxd->rxd_buf, len);
		IEC_RXBUFSYNC(sc, i, ETHER_MAX_LEN, BUS_DMASYNC_PREREAD);
		if (m == NULL)
			goto dropit;

		rxd->rxd_stat = 0;
		IEC_RXSTATSYNC(sc, i, BUS_DMASYNC_PREREAD);

		ml_enqueue(&ml, m);
	}

	/* Update RX index pointers. */
	sc->sc_rxci = ci;
	bus_space_write_4(st, sh, IOC3_ENET_RPIR,
	    (sc->sc_rxpi * sizeof(uint64_t)) | IOC3_ENET_PIR_SET);
	DPRINTF(IEC_DEBUG_RXINTR, ("iec_rxintr: new rxci %d rxpi %d\n",
	    sc->sc_rxci, sc->sc_rxpi));

	if_input(ifp, &ml);
}

void
iec_txintr(struct iec_softc *sc, uint32_t stat)
{
	bus_space_tag_t st = sc->sc_st;
	bus_space_handle_t sh = sc->sc_sh;
	struct ifnet *ifp = &sc->sc_ac.ac_if;
	struct iec_txsoft *txs;
	bus_dmamap_t dmamap;
	uint32_t tcir;
	int i, once, last;

	ifp->if_flags &= ~IFF_OACTIVE;

	tcir = bus_space_read_4(st, sh, IOC3_ENET_TCIR) & ~IOC3_ENET_TCIR_IDLE;
	last = (tcir / IEC_TXDESCSIZE) % IEC_NTXDESC_MAX;

	DPRINTF(IEC_DEBUG_TXINTR, ("iec_txintr: dirty %d last %d\n",
	    sc->sc_txdirty, last));
	once = 0;
	for (i = sc->sc_txdirty; i != last && sc->sc_txpending != 0;
	    i = IEC_NEXTTX(i), sc->sc_txpending--) {
		txs = &sc->sc_txsoft[i];
		if ((txs->txs_flags & IEC_TXCMD_PTR0_V) != 0) {
			dmamap = txs->txs_dmamap;
			bus_dmamap_sync(sc->sc_dmat, dmamap, 0,
			    dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
			bus_dmamap_unload(sc->sc_dmat, dmamap);
			m_freem(txs->txs_mbuf);
			txs->txs_mbuf = NULL;
		}

		if ((stat & IOC3_ENET_ISR_TX_EXPLICIT) == 0) {
			if (stat == IOC3_ENET_ISR_TX_EMPTY)
				continue;
			if (once == 0) {
				printf("%s: TX error: txstat = %08x\n",
				    DEVNAME(sc), stat);
				once = 1;
			}
			ifp->if_oerrors++;
		} else {
			ifp->if_collisions += IOC3_ENET_TCDC_COLLISION_MASK &
			    bus_space_read_4(st, sh, IOC3_ENET_TCDC);
			ifp->if_opackets++;
		}
	}

	/* Update the dirty TX buffer pointer. */
	sc->sc_txdirty = i;
	DPRINTF(IEC_DEBUG_INTR,
	    ("iec_txintr: sc_txdirty = %2d, sc_txpending = %2d\n",
	    sc->sc_txdirty, sc->sc_txpending));

	/* Cancel the watchdog timer if there are no pending TX packets. */
	if (sc->sc_txpending == 0)
		ifp->if_timer = 0;

	if (stat & IOC3_ENET_ISR_TX_EMPTY) {
		bus_space_write_4(st, sh, IOC3_ENET_IER,
		    bus_space_read_4(st, sh, IOC3_ENET_IER) &
		      ~IOC3_ENET_ISR_TX_EMPTY);
		(void)bus_space_read_4(st, sh, IOC3_ENET_IER);
	}
}

int
iec_ssram_probe(struct iec_softc *sc)
{
	/*
	 * Depending on the hardware, there is either 64KB or 128KB of
	 * 16-bit SSRAM, which is used as internal RX buffers by the chip.
	 */

	/* default to large size */
	sc->sc_mcr = IOC3_ENET_MCR_PARITY_ENABLE | IOC3_ENET_MCR_LARGE_SSRAM;
	bus_space_write_4(sc->sc_st, sc->sc_sh, IOC3_ENET_MCR, sc->sc_mcr);

	bus_space_write_4(sc->sc_st, sc->sc_sh,
	    IOC3_SSRAM_BASE, 0x55aa);
	bus_space_write_4(sc->sc_st, sc->sc_sh,
	    IOC3_SSRAM_BASE + IOC3_SSRAM_SMALL_SIZE, 0xffff ^ 0x55aa);

	if ((bus_space_read_4(sc->sc_st, sc->sc_sh, IOC3_SSRAM_BASE) &
	     IOC3_SSRAM_DATA_MASK) != 0x55aa ||
	    (bus_space_read_4(sc->sc_st, sc->sc_sh,
	     IOC3_SSRAM_BASE + IOC3_SSRAM_SMALL_SIZE) != (0xffff ^ 0x55aa))) {
		sc->sc_mcr &= ~IOC3_ENET_MCR_LARGE_SSRAM;
		sc->sc_nrxdesc = IEC_NRXDESC_SMALL;
		return IOC3_SSRAM_SMALL_SIZE / 2 / 1024;
	} else {
		sc->sc_nrxdesc = IEC_NRXDESC_LARGE;
		return IOC3_SSRAM_LARGE_SIZE / 2 / 1024;
	}
}


code:
/*	$OpenBSD: if_iecreg.h,v 1.3 2009/11/03 21:41:42 miod Exp $	*/

/*
 * Copyright (c) 2009 Miodrag Vallat.
 *
 * Permission to use, copy, modify, and distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

/*
 * Ethernet controller part of the IOC3 ASIC.
 */

/*
 * Receive buffer descriptor.
 */

#define	IEC_NRXDESC_MAX		512

#define IEC_RXDESCSIZE		(4096)
#define IEC_RXD_BUFOFFSET	(64 + 2)	/* to align Ethernet header */
#define IEC_RXD_NRXPAD		(IEC_RXD_BUFOFFSET - 2 * sizeof(uint32_t))
#define IEC_RXD_BUFSIZE		(IEC_RXDESCSIZE - IEC_RXD_BUFOFFSET)

/*
 * IEC_RXDESCSIZE is the smallest multiple of 128 bytes (hardware requirement)
 * able to store ETHER_MAX_DIX_LEN bytes and the rxdesc administrative data.
 *
 * IEC_RXD_BUFOFFSET is choosen to use a different cache line on the CPU.
 * A value of 128 (IOC3 cache line) would be even better, but would not fit
 * in the MCR register.
 */

struct	iec_rxdesc {
	volatile uint32_t	rxd_stat;
#define	IEC_RXSTAT_VALID		0x80000000	/* descriptor valid */
#define	IEC_RXSTAT_LEN_MASK		0x07ff0000
#define	IEC_RXSTAT_LEN_SHIFT		16
#define	IEC_RXSTAT_CHECKSUM_MASK	0x0000ffff
	uint32_t		rxd_err;
#define	IEC_RXERR_CRC			0x00000001	/* CRC error */
#define	IEC_RXERR_FRAME			0x00000002	/* Framing erorr */
#define	IEC_RXERR_CODE			0x00000004	/* Code violation */
#define	IEC_RXERR_INVPREAMB		0x00000008	/* Invalid preamble */
#define	IEC_RXERR_MULTICAST		0x04000000	/* Multicast packet */
#define	IEC_RXERR_BROADCAST		0x08000000	/* Broadcast packet */
#define	IEC_RXERR_LONGEVENT		0x10000000	/* Long packet */
#define	IEC_RXERR_BADPACKET		0x20000000	/* Bad packet */
#define	IEC_RXERR_GOODPACKET		0x40000000
#define	IEC_RXERR_CARRIER		0x80000000	/* Carrier event */
	uint8_t			rxd_pad[IEC_RXD_NRXPAD];
	uint8_t			rxd_buf[IEC_RXD_BUFSIZE];
};

/*
 * Transmit buffer descriptor.
 */

#define	IEC_NTXDESC_MAX		128

#define IEC_TXDESCSIZE		128
#define IEC_NTXPTR		2
#define IEC_TXD_BUFOFFSET	\
	(2 * sizeof(uint32_t) + IEC_NTXPTR * sizeof(uint64_t))
#define IEC_TXD_BUFSIZE		(IEC_TXDESCSIZE - IEC_TXD_BUFOFFSET)

struct	iec_txdesc {
	uint32_t	txd_cmd;
#define	IEC_TXCMD_DATALEN		0x000007ff
#define	IEC_TXCMD_TXINT			0x00001000	/* interrupt after TX */
#define	IEC_TXCMD_BUF_V			0x00010000	/* txd_buf valid */
#define	IEC_TXCMD_PTR0_V		0x00020000	/* tx_ptr[0] valid */
#define	IEC_TXCMD_PTR1_V		0x00040000	/* tx_ptr[1] valid */
#define	IEC_TXCMD_HWCHECKSUM		0x00080000	/* perform hw cksum */
#define	IEC_TXCMD_CHECKSUM_POS_MASK	0x07f00000	/* hw cksum byte pos */
#define	IEC_TXCMD_CHECKSUM_POS_SHIFT	20
	uint32_t	txd_len;
#define	IECTX_BUF0_LEN_MASK		0x0000007f
#define	IECTX_BUF0_LEN_SHIFT		0
#define	IECTX_BUF1_LEN_MASK		0x0007ff00
#define	IECTX_BUF1_LEN_SHIFT		8
#define	IECTX_BUF2_LEN_MASK		0x7ff00000
#define	IECTX_BUF2_LEN_SHIFT		20
	uint64_t	txd_ptr[IEC_NTXPTR];
	uint8_t		txd_buf[IEC_TXD_BUFSIZE];
};