code:
/*	$OpenBSD: tmureg.h,v 1.1.1.1 2006/10/06 21:02:55 miod Exp $	*/
/*	$NetBSD: tmureg.h,v 1.11 2006/03/04 01:55:03 uwe Exp $	*/

/*-
 * Copyright (C) 1999 SAITOH Masanobu.  All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef _SH_TMUREG_H_
#define	_SH_TMUREG_H_
#include <sh/devreg.h>

/*
 * TMU
 */
#define	SH3_TOCR			0xfffffe90
#define	SH3_TSTR			0xfffffe92
#define	SH3_TCOR0			0xfffffe94
#define	SH3_TCNT0			0xfffffe98
#define	SH3_TCR0			0xfffffe9c
#define	SH3_TCOR1			0xfffffea0
#define	SH3_TCNT1			0xfffffea4
#define	SH3_TCR1			0xfffffea8
#define	SH3_TCOR2			0xfffffeac
#define	SH3_TCNT2			0xfffffeb0
#define	SH3_TCR2			0xfffffeb4
#define	SH3_TCPR2			0xfffffeb8

#define	SH4_TOCR			0xffd80000
#define	SH4_TSTR			0xffd80004
#define	SH4_TCOR0			0xffd80008
#define	SH4_TCNT0			0xffd8000c
#define	SH4_TCR0			0xffd80010
#define	SH4_TCOR1			0xffd80014
#define	SH4_TCNT1			0xffd80018
#define	SH4_TCR1			0xffd8001c
#define	SH4_TCOR2			0xffd80020
#define	SH4_TCNT2			0xffd80024
#define	SH4_TCR2			0xffd80028
#define	SH4_TCPR2			0xffd8002c
#define	SH4_TSTR2			0xfe100004
#define	SH4_TCOR3			0xfe100008
#define	SH4_TCNT3			0xfe10000c
#define	SH4_TCR3			0xfe100010
#define	SH4_TCOR4			0xfe100014
#define	SH4_TCNT4			0xfe100018
#define	SH4_TCR4			0xfe10001c

#define	TOCR_TCOE			0x01
#define	TSTR_STR2			0x04
#define	TSTR_STR1			0x02
#define	TSTR_STR0			0x01
#define	TCR_ICPF			0x0200
#define	TCR_UNF				0x0100
#define	TCR_ICPE1			0x0080
#define	TCR_ICPE0			0x0040
#define	TCR_UNIE			0x0020
#define	TCR_CKEG1			0x0010
#define	TCR_CKEG0			0x0008
#define	TCR_TPSC2			0x0004
#define	TCR_TPSC1			0x0002
#define	TCR_TPSC0			0x0001
#define	TCR_TPSC_P4			0x0000
#define	TCR_TPSC_P16			0x0001
#define	TCR_TPSC_P64			0x0002
#define	TCR_TPSC_P256			0x0003
#define	SH3_TCR_TPSC_RTC		0x0004
#define	SH3_TCR_TPSC_TCLK		0x0005
#define	SH4_TCR_TPSC_P1024		0x0004
#define	SH4_TCR_TPSC_RTC		0x0006
#define	SH4_TCR_TPSC_TCLK		0x0007
#define	SH4_TSTR2_STR4			0x02
#define	SH4_TSTR2_STR3			0x01

#ifndef _LOCORE
#if defined(SH3) && defined(SH4)
extern uint32_t __sh_TOCR;
extern uint32_t __sh_TSTR;
extern uint32_t __sh_TCOR0;
extern uint32_t __sh_TCNT0;
extern uint32_t __sh_TCR0;
extern uint32_t __sh_TCOR1;
extern uint32_t __sh_TCNT1;
extern uint32_t __sh_TCR1;
extern uint32_t __sh_TCOR2;
extern uint32_t __sh_TCNT2;
extern uint32_t __sh_TCR2;
extern uint32_t __sh_TCPR2;
#endif /* SH3 && SH4 */
#endif /* !_LOCORE */

#endif	/* !_SH_TMUREG_H_ */


code:
/*	$OpenBSD: trap.h,v 1.4 2011/03/23 16:54:37 pirofti Exp $	*/
/*	$NetBSD: exception.h,v 1.9 2006/07/22 21:58:29 uwe Exp $	*/

/*-
 * Copyright (c) 2002 The NetBSD Foundation, Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef _SH_TRAP_H_
#define	_SH_TRAP_H_
/*
 * SH3/SH4 Exception handling.
 */
#include <sh/devreg.h>

#ifdef _KERNEL
#define	SH3_TRA			0xffffffd0	/* 32bit */
#define	SH3_EXPEVT		0xffffffd4	/* 32bit */
#define	SH3_INTEVT		0xffffffd8	/* 32bit */
#define	SH7709_INTEVT2		0xa4000000	/* 32bit */

#define	SH4_TRA			0xff000020	/* 32bit */
#define	SH4_EXPEVT		0xff000024	/* 32bit */
#define	SH4_INTEVT		0xff000028	/* 32bit */

/*
 * EXPEVT
 */
/* Reset exception */
#define	EXPEVT_RESET_POWER	0x000	/* Power-On reset */
#define	EXPEVT_RESET_MANUAL	0x020	/* Manual reset */
#define	EXPEVT_RESET_TLB_MULTI_HIT	0x140	/* SH4 only */

/* General exception */
#define	EXPEVT_TLB_MISS_LD	0x040	/* TLB miss (load) */
#define	EXPEVT_TLB_MISS_ST	0x060	/* TLB miss (store) */
#define	EXPEVT_TLB_MOD		0x080	/* Initial page write */
#define	EXPEVT_TLB_PROT_LD	0x0a0	/* Protection violation (load) */
#define	EXPEVT_TLB_PROT_ST	0x0c0	/* Protection violation (store)*/
#define	EXPEVT_ADDR_ERR_LD	0x0e0	/* Address error (load) */
#define	EXPEVT_ADDR_ERR_ST	0x100	/* Address error (store) */
#define	EXPEVT_FPU		0x120	/* FPU exception */
#define	EXPEVT_TRAPA		0x160	/* Unconditional trap (TRAPA) */
#define	EXPEVT_RES_INST		0x180	/* Illegal instruction */
#define	EXPEVT_SLOT_INST	0x1a0	/* Illegal slot instruction */
#define	EXPEVT_BREAK		0x1e0	/* User break */
#define	EXPEVT_FPU_DISABLE	0x800	/* FPU disabled */
#define	EXPEVT_FPU_SLOT_DISABLE	0x820	/* Slot FPU disabled */

/* Software bit */
#define	EXP_USER		0x001	/* exception from user-mode */

#define	_SH_TRA_SYSCALL		0x80	/* syscall trapa number */
#define	_SH_TRA_CACHECTL	0x81	/* cachectl trapa number */
#define	_SH_TRA_BREAK		0xc3	/* magic number for debugger */

/*
 * INTEVT/INTEVT2
 */
/* External interrupt */
#define	SH_INTEVT_NMI		0x1c0

#define	SH_INTEVT_TMU0_TUNI0	0x400
#define	SH_INTEVT_TMU1_TUNI1	0x420
#define	SH_INTEVT_TMU2_TUNI2	0x440
#define	SH_INTEVT_TMU2_TICPI2	0x460

#define	SH_INTEVT_SCI_ERI	0x4e0
#define	SH_INTEVT_SCI_RXI	0x500
#define	SH_INTEVT_SCI_TXI	0x520
#define	SH_INTEVT_SCI_TEI	0x540

#define	SH_INTEVT_WDT_ITI	0x560

#define	SH_INTEVT_IRL9		0x320
#define	SH_INTEVT_IRL11		0x360
#define	SH_INTEVT_IRL13		0x3a0

#define	SH4_INTEVT_SCIF_ERI	0x700
#define	SH4_INTEVT_SCIF_RXI	0x720
#define	SH4_INTEVT_SCIF_BRI	0x740
#define	SH4_INTEVT_SCIF_TXI	0x760

#define	SH7709_INTEVT2_IRQ0	0x600
#define	SH7709_INTEVT2_IRQ1	0x620
#define	SH7709_INTEVT2_IRQ2	0x640
#define	SH7709_INTEVT2_IRQ3	0x660
#define	SH7709_INTEVT2_IRQ4	0x680
#define	SH7709_INTEVT2_IRQ5	0x6a0

#define	SH7709_INTEVT2_PINT07	0x700
#define	SH7709_INTEVT2_PINT8F	0x720

#define SH7709_INTEVT2_DEI0	0x800
#define SH7709_INTEVT2_DEI1	0x820
#define SH7709_INTEVT2_DEI2	0x840
#define SH7709_INTEVT2_DEI3	0x860

#define	SH7709_INTEVT2_IRDA_ERI	0x880
#define	SH7709_INTEVT2_IRDA_RXI	0x8a0
#define	SH7709_INTEVT2_IRDA_BRI	0x8c0
#define	SH7709_INTEVT2_IRDA_TXI	0x8e0

#define	SH7709_INTEVT2_SCIF_ERI	0x900
#define	SH7709_INTEVT2_SCIF_RXI	0x920
#define	SH7709_INTEVT2_SCIF_BRI	0x940
#define	SH7709_INTEVT2_SCIF_TXI	0x960

#define	SH7709_INTEVT2_ADC	0x980

/* SH7750R, SH7751, SH7751R */
#define	SH4_INTEVT_IRL0		0x240
#define	SH4_INTEVT_IRL1		0x2a0
#define	SH4_INTEVT_IRL2		0x300
#define	SH4_INTEVT_IRL3		0x360

#define	SH4_INTEVT_IRQ0		0x200
#define	SH4_INTEVT_IRQ1		0x220
#define	SH4_INTEVT_IRQ2		0x240
#define	SH4_INTEVT_IRQ3		0x260
#define	SH4_INTEVT_IRQ4		0x280
#define	SH4_INTEVT_IRQ5		0x2a0
#define	SH4_INTEVT_IRQ6		0x2c0
#define	SH4_INTEVT_IRQ7		0x2e0
#define	SH4_INTEVT_IRQ8		0x300
#define	SH4_INTEVT_IRQ9		0x320
#define	SH4_INTEVT_IRQ10	0x340
#define	SH4_INTEVT_IRQ11	0x360
#define	SH4_INTEVT_IRQ12	0x380
#define	SH4_INTEVT_IRQ13	0x3a0
#define	SH4_INTEVT_IRQ14	0x3c0
#define	SH4_INTEVT_IRQ15	0x3e0

#define	SH4_INTEVT_TMU3		0xb00
#define	SH4_INTEVT_TMU4		0xb80

#define	SH4_INTEVT_PCISERR	0xa00
#define	SH4_INTEVT_PCIERR	0xae0
#define	SH4_INTEVT_PCIPWDWN	0xac0
#define	SH4_INTEVT_PCIPWON	0xaa0
#define	SH4_INTEVT_PCIDMA0	0xa80
#define	SH4_INTEVT_PCIDMA1	0xa60
#define	SH4_INTEVT_PCIDMA2	0xa40
#define	SH4_INTEVT_PCIDMA3	0xa20

#ifndef _LOCORE

#if defined(SH3) && defined(SH4)
extern uint32_t __sh_TRA;
extern uint32_t __sh_EXPEVT;
extern uint32_t __sh_INTEVT;
#endif /* SH3 && SH4 */

extern const char * const exp_type[];
extern const int exp_types;

#endif /* !_LOCORE */

#endif /* _KERNEL */
#endif /* !_SH_TRAP_H_ */

license: unknown


code:
/*	$OpenBSD: ubcreg.h,v 1.1.1.1 2006/10/06 21:02:55 miod Exp $	*/
/*	$NetBSD: ubcreg.h,v 1.4 2006/03/04 01:55:03 uwe Exp $	*/

/*-
 * Copyright (C) 1999 SAITOH Masanobu.  All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef _SH_UBCREG_H_
#define	_SH_UBCREG_H_
#include <sh/devreg.h>

/*
 * User Break Controller
 */

/* ch-A */
#define	SH3_BARA		0xffffffb0
#define	SH3_BAMRA		0xffffffb4
#define	SH3_BASRA		0xffffffe4
#define	SH3_BBRA		0xffffffb8
/* ch-B */
#define	SH3_BARB		0xffffffa0
#define	SH3_BAMRB		0xffffffa4
#define	SH3_BASRB		0xffffffe8
#define	SH3_BBRB		0xffffffa8
#define	SH3_BDRB		0xffffff90
#define	SH3_BDMRB		0xffffff94
/* common */
#define	SH3_BRCR		0xffffff98

/* ch-A */
#define	SH4_BARA		0xff200000
#define	SH4_BAMRA		0xff200004
#define	SH4_BASRA		0xff000014
#define	SH4_BBRA		0xff200008

/* ch-B */
#define	SH4_BARB		0xff20000c
#define	SH4_BAMRB		0xff200010
#define	SH4_BASRB		0xff000018
#define	SH4_BBRB		0xff200014
#define	SH4_BDRB		0xff200018
#define	SH4_BDMRB		0xff20001c
/* common */
#define	SH4_BRCR		0xff200020

#ifndef _LOCORE
#if defined(SH3) && defined(SH4)
extern uint32_t __sh_BARA;
extern uint32_t __sh_BAMRA;
extern uint32_t __sh_BASRA;
extern uint32_t __sh_BBRA;
extern uint32_t __sh_BARB;
extern uint32_t __sh_BAMRB;
extern uint32_t __sh_BASRB;
extern uint32_t __sh_BBRB;
extern uint32_t __sh_BDRB;
extern uint32_t __sh_BDMRB;
extern uint32_t __sh_BRCR;
#endif /* SH3 && SH4 */
#endif /* !_LOCORE */

#endif	/* !_SH_UBCREG_H_ */


code:
/*	$OpenBSD: varargs.h,v 1.1.1.1 2006/10/06 21:02:55 miod Exp $	*/
/*	$NetBSD: varargs.h,v 1.7 2006/05/21 22:39:04 uwe Exp $	*/

/*
 * Copyright (c) 1990, 1993
 *	The Regents of the University of California.  All rights reserved.
 * (c) UNIX System Laboratories, Inc.
 * All or some portions of this file are derived from material licensed
 * to the University of California by American Telephone and Telegraph
 * Co. or Unix System Laboratories, Inc. and are reproduced herein with
 * the permission of UNIX System Laboratories, Inc.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of the University nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 *	from: @(#)varargs.h	8.2 (Berkeley) 3/22/94
 */

#ifndef _SH_VARARGS_H_
#define	_SH_VARARGS_H_

#include <machine/stdarg.h>

#if __GNUC__ == 1
#define	__va_ellipsis
#else
#define	__va_ellipsis	...
#endif

#define	va_alist	__builtin_va_alist
#define	va_dcl		__builtin_va_alist_t __builtin_va_alist; __va_ellipsis

#undef va_start
#define	va_start(ap)	__builtin_varargs_start((ap))

#endif /* !_SH_VARARGS_H_ */


code:
/*	$OpenBSD: vmparam.h,v 1.10 2014/01/30 18:16:41 miod Exp $	*/
/*	$NetBSD: vmparam.h,v 1.17 2006/03/04 01:55:03 uwe Exp $	*/

/*-
 * Copyright (c) 2002 The NetBSD Foundation, Inc.
 * All rights reserved.
 *
 * This code is derived from software contributed to The NetBSD Foundation
 * by UCHIYAMA Yasushi.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef _SH_VMPARAM_H_
#define	_SH_VMPARAM_H_
#include <sys/queue.h>

/* Virtual address map. */
#define	VM_MIN_ADDRESS		((vaddr_t)PAGE_SIZE)
#define	VM_MAXUSER_ADDRESS	((vaddr_t)0x7ffff000)
#define	VM_MAX_ADDRESS		((vaddr_t)0x7ffff000)
#define	VM_MIN_KERNEL_ADDRESS	((vaddr_t)0xc0000000)
#define	VM_MAX_KERNEL_ADDRESS	((vaddr_t)0xe0000000)

/* map PIE below 4MB (non-pie link address) to avoid mmap pressure */
#define VM_PIE_MIN_ADDR		PAGE_SIZE
#define VM_PIE_MAX_ADDR		0x400000UL

/* top of stack */
#define	USRSTACK		VM_MAXUSER_ADDRESS

/* Virtual memory resource limit. */
#define	MAXTSIZ			(64 * 1024 * 1024)	/* max text size */
#ifndef MAXDSIZ
#define	MAXDSIZ			(512 * 1024 * 1024)	/* max data size */
#endif
#ifndef BRKSIZ
#define	BRKSIZ			MAXDSIZ			/* heap gap size */
#endif
#ifndef	MAXSSIZ
#define	MAXSSIZ			(32 * 1024 * 1024)	/* max stack size */
#endif

/* initial data size limit */
#ifndef DFLDSIZ
#define	DFLDSIZ			(128 * 1024 * 1024)
#endif
/* initial stack size limit */
#ifndef	DFLSSIZ
#define	DFLSSIZ			(2 * 1024 * 1024)
#endif

#define	STACKGAP_RANDOM		(256 * 1024)

/*
 * Size of shared memory map
 */
#ifndef SHMMAXPGS
#define	SHMMAXPGS		1024
#endif

/* Size of user raw I/O map */
#ifndef USRIOSIZE
#define	USRIOSIZE		(MAXBSIZE / PAGE_SIZE * 8)
#endif

#define	VM_PHYS_SIZE		(USRIOSIZE * PAGE_SIZE)

#endif /* !_SH_VMPARAM_H_ */


code: src/sys/arch/sh/sh

path: sys/arch/sh/sh/CVS/Repository


code:
/*	$OpenBSD: cache.c,v 1.4 2008/06/26 05:42:13 ray Exp $	*/
/*	$NetBSD: cache.c,v 1.11 2006/01/02 23:37:34 uwe Exp $	*/

/*-
 * Copyright (c) 2002 The NetBSD Foundation, Inc.
 * All rights reserved.
 *
 * This code is derived from software contributed to The NetBSD Foundation
 * by UCHIYAMA Yasushi.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

#include <sys/param.h>
#include <sys/systm.h>

#include <sh/cache.h>
#include <sh/cache_sh3.h>
#include <sh/cache_sh4.h>

/*
 * __cache_flush is used before sh_cache_config() is called.
 */
static void __cache_flush(void);

struct sh_cache_ops sh_cache_ops = {
	._icache_sync_all = (void (*)(void))__cache_flush,
	._icache_sync_range = (void (*)(vaddr_t, vsize_t))__cache_flush,
	._icache_sync_range_index = (void (*)(vaddr_t, vsize_t))__cache_flush,
	._dcache_wbinv_all = (void (*)(void))__cache_flush,
	._dcache_wbinv_range = (void (*)(vaddr_t, vsize_t))__cache_flush,
	._dcache_wbinv_range_index = (void (*)(vaddr_t, vsize_t))__cache_flush,
	._dcache_inv_range = (void (*)(vaddr_t, vsize_t))__cache_flush,
	._dcache_wb_range = (void (*)(vaddr_t, vsize_t))__cache_flush
};

int sh_cache_enable_icache;
int sh_cache_enable_dcache;
int sh_cache_write_through;
int sh_cache_write_through_p0_u0_p3;
int sh_cache_write_through_p1;
int sh_cache_unified;
int sh_cache_ways;
int sh_cache_size_icache;
int sh_cache_size_dcache;
int sh_cache_line_size;
int sh_cache_ram_mode;
int sh_cache_index_mode_icache;
int sh_cache_index_mode_dcache;
int sh_cache_prefer_mask;

void
sh_cache_init()
{
#ifdef CACHE_DEBUG
	return;
#endif
#ifdef SH3
	if (CPU_IS_SH3)
		sh3_cache_config();
#endif
#ifdef SH4
	if (CPU_IS_SH4)
		sh4_cache_config();
#endif
}

void
sh_cache_information()
{
#ifdef CACHE_DEBUG
	printf("*** USE CPU INDEPENDENT CACHE OPS. ***\n");
	return;
#endif

	/* I-cache or I/D-unified cache */
	printf("cpu0: %dKB/%dB",
	       sh_cache_size_icache >> 10, sh_cache_line_size);
	if (sh_cache_ways > 1)
		printf(" %d-way associative", sh_cache_ways);
	else
		printf(" direct");
	if (sh_cache_unified)
		printf(" I/D-");
	else
		printf(" I-");
	printf("cache");
	if (!sh_cache_enable_icache)
		printf(" DISABLED");
	if (sh_cache_unified && sh_cache_ram_mode)
		printf(" RAM-mode");
	if (sh_cache_index_mode_icache)
		printf(" INDEX-mode");

	/* D-cache */
	if (!sh_cache_unified) {
		printf(", %dKB/%dB", sh_cache_size_dcache >> 10,
		    sh_cache_line_size);
		if (sh_cache_ways > 1)
			printf(" %d-way associative", sh_cache_ways);
		else
			printf(" direct");
		printf(" D-cache");
		if (!sh_cache_enable_dcache)
			printf(" DISABLED");
		if (sh_cache_ram_mode)
			printf(" RAM-mode");
		if (sh_cache_index_mode_dcache)
			printf(" INDEX-mode");
	}
	printf("\n");

#ifdef CACHE_DEBUG
	/* Write-through/back */
	printf("cpu0: P0, U0, P3 write-%s; P1 write-%s\n",
	    sh_cache_write_through_p0_u0_p3 ? "through" : "back",
	    sh_cache_write_through_p1 ? "through" : "back");
#endif
}

/*
 * CPU-independent cache flush.
 */
void
__cache_flush()
{
	volatile int *p = (int *)SH3_PHYS_TO_P1SEG(IOM_RAM_BEGIN);
	int i;
	int d;

	/* Flush D-Cache */
	/*
	 * Access address range [13:4].
	 * max:
	 * 16KB line-size 16B 4-way ... [11:4]  * 4
	 * 16KB line-size 32B 1-way ... [13:5]
	 */
	for (i = 0; i < 256/*entry*/ * 4/*way*/; i++) {
		d = *p;
		p += 4;	/* next line index (16B) */
	}

	/* Flush I-Cache */
	/*
	 * this code flush I-cache. but can't compile..
	 *  __asm volatile(".space 8192");
	 *
	 */
}


code:
/*	$OpenBSD: cache_sh3.c,v 1.2 2008/06/26 05:42:13 ray Exp $	*/
/*	$NetBSD: cache_sh3.c,v 1.12 2006/03/04 01:13:35 uwe Exp $	*/

/*-
 * Copyright (c) 2002 The NetBSD Foundation, Inc.
 * All rights reserved.
 *
 * This code is derived from software contributed to The NetBSD Foundation
 * by UCHIYAMA Yasushi.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

#include <sys/param.h>
#include <sys/systm.h>

#include <sh/cache.h>
#include <sh/cache_sh3.h>

#define	round_line(x)		(((x) + 15) & ~15)
#define	trunc_line(x)		((x) & ~15)

void sh3_cache_wbinv_all(void);
void sh3_cache_wbinv_range(vaddr_t, vsize_t);
void sh3_cache_wbinv_range_index(vaddr_t, vsize_t);
void sh3_cache_panic(vaddr_t, vsize_t);
void sh3_cache_nop(vaddr_t, vsize_t);

int sh_cache_way_size;
int sh_cache_way_shift;
int sh_cache_entry_mask;

static inline void cache_sh3_op_line_16_nway(int, vaddr_t, uint32_t);
static inline void cache_sh3_op_8lines_16_nway(int, vaddr_t, uint32_t);

void
sh3_cache_config()
{
	size_t cache_size;
	uint32_t r;

	/* Determine cache size */
	switch (cpu_product) {
	default:
		/* FALLTHROUGH */
	case CPU_PRODUCT_7708:
		/* FALLTHROUGH */
	case CPU_PRODUCT_7708S:
		/* FALLTHROUGH */
	case CPU_PRODUCT_7708R:
		cache_size = 8 * 1024;
		break;
	case CPU_PRODUCT_7709:
		cache_size = 8 * 1024;
		break;
	case CPU_PRODUCT_7709A:
		cache_size = 16 * 1024;
		break;
	}

	r = _reg_read_4(SH3_CCR);

	sh_cache_unified = 1;
	sh_cache_enable_unified = (r & SH3_CCR_CE);
	sh_cache_line_size = 16;
	sh_cache_write_through_p0_u0_p3 = r & SH3_CCR_WT;
	sh_cache_write_through_p1 = !(r & SH3_CCR_CB);
	sh_cache_write_through = sh_cache_write_through_p0_u0_p3 &&
	    sh_cache_write_through_p1;

	sh_cache_ram_mode = r & SH3_CCR_RA;
	if (sh_cache_ram_mode) {
		/*
		 * In RAM-mode, way 2 and 3 are used as RAM.
		 */
		sh_cache_ways = 2;
		sh_cache_size_unified = cache_size / 2;
	} else {
		sh_cache_ways = 4;
		sh_cache_size_unified = cache_size;
	}

	/* size enough to access foreach entries */
	sh_cache_way_size = sh_cache_size_unified / 4/*way*/;
	/* mask for extracting entry select */
	sh_cache_entry_mask = (sh_cache_way_size - 1) & ~15/*line-mask*/;
	/* shift for way selection (16KB/8KB) */
	sh_cache_way_shift =
	    /* entry bits */
	    ffs(sh_cache_size_unified / (4/*way*/ * 16/*line-size*/)) - 1
	    /* line bits */
	    + 4;

	sh_cache_ops._icache_sync_all		= sh3_cache_wbinv_all;
	sh_cache_ops._icache_sync_range		= sh3_cache_wbinv_range;
	sh_cache_ops._icache_sync_range_index	= sh3_cache_wbinv_range_index;
	sh_cache_ops._dcache_wbinv_all		= sh3_cache_wbinv_all;
	sh_cache_ops._dcache_wbinv_range	= sh3_cache_wbinv_range;
	sh_cache_ops._dcache_wbinv_range_index	= sh3_cache_wbinv_range_index;
	/* SH3 can't invalidate without write-back */
	sh_cache_ops._dcache_inv_range		= sh3_cache_panic;
	if (sh_cache_write_through) {
		sh_cache_ops._dcache_wb_range		= sh3_cache_nop;
	} else {
		/* SH3 can't write-back without invalidate */
		sh_cache_ops._dcache_wb_range		= sh3_cache_wbinv_range;
	}
}

/*
 * cache_sh3_op_line_16_nway: (index-operation)
 *
 *	Clear the specified bits on single 16-byte cache line. n-ways.
 *
 */
static inline void
cache_sh3_op_line_16_nway(int n, vaddr_t va, uint32_t bits)
{
	vaddr_t cca;
	int way;

	/* extract entry # */
	va &= sh_cache_entry_mask;

	/* operate for each way */
	for (way = 0; way < n; way++) {
		cca = (SH3_CCA | way << sh_cache_way_shift | va);
		_reg_bclr_4(cca, bits);
	}
}

/*
 * cache_sh3_op_8lines_16_nway: (index-operation)
 *
 *	Clear the specified bits on 8 16-byte cache lines, n-ways.
 *
 */
static inline void
cache_sh3_op_8lines_16_nway(int n, vaddr_t va, uint32_t bits)
{
	volatile uint32_t *cca;
	int way;

	/* extract entry # */
	va &= sh_cache_entry_mask;

	/* operate for each way */
	for (way = 0; way < n; way++) {
		cca = (volatile uint32_t *)
		    (SH3_CCA | way << sh_cache_way_shift | va);
		cca[ 0] &= ~bits;
		cca[ 4] &= ~bits;
		cca[ 8] &= ~bits;
		cca[12] &= ~bits;
		cca[16] &= ~bits;
		cca[20] &= ~bits;
		cca[24] &= ~bits;
		cca[28] &= ~bits;
	}
}

void
sh3_cache_wbinv_all()
{
	vaddr_t va;

	for (va = 0; va < sh_cache_way_size; va += 16 * 8)
		cache_sh3_op_8lines_16_nway(sh_cache_ways, va, CCA_U | CCA_V);
}

void
sh3_cache_wbinv_range_index(vaddr_t va, vsize_t sz)
{
	vaddr_t eva = round_line(va + sz);

	va = trunc_line(va);

	while ((eva - va) >= (8 * 16)) {
		cache_sh3_op_8lines_16_nway(sh_cache_ways, va, CCA_U | CCA_V);
		va += 16 * 8;
	}

	while (va < eva) {
		cache_sh3_op_line_16_nway(sh_cache_ways, va, CCA_U | CCA_V);
		va += 16;
	}
}

void
sh3_cache_wbinv_range(vaddr_t va, vsize_t sz)
{
	vaddr_t eva = round_line(va + sz);
	vaddr_t cca;

	va = trunc_line(va);

	while (va < eva) {
		cca = SH3_CCA | CCA_A | (va & sh_cache_entry_mask);
		/*
		 * extract virtual tag-address.
		 * MMU translates it to physical address tag,
		 * and write to address-array.
		 * implicitly specified U = 0, V = 0.
		 */
		_reg_write_4(cca, va & CCA_TAGADDR_MASK);
		va += 16;
	}
}

void
sh3_cache_panic(vaddr_t va, vsize_t size)
{
	panic("SH3 can't invalidate without write-back");
}

void
sh3_cache_nop(vaddr_t va, vsize_t sz)
{
	/* NO-OP */
}


code:
/*	$OpenBSD: cache_sh4.c,v 1.6 2010/01/01 13:20:33 miod Exp $	*/
/*	$NetBSD: cache_sh4.c,v 1.15 2005/12/24 23:24:02 perry Exp $	*/

/*-
 * Copyright (c) 2002 The NetBSD Foundation, Inc.
 * All rights reserved.
 *
 * This code is derived from software contributed to The NetBSD Foundation
 * by UCHIYAMA Yasushi.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

#include <sys/param.h>
#include <sys/systm.h>

#include <sh/cache.h>
#include <sh/cache_sh4.h>

#define	round_line(x)		(((x) + 31) & ~31)
#define	trunc_line(x)		((x) & ~31)

void sh4_icache_sync_all(void);
void sh4_icache_sync_range(vaddr_t, vsize_t);
void sh4_icache_sync_range_index(vaddr_t, vsize_t);
void sh4_dcache_wbinv_all(void);
void sh4_dcache_wbinv_range(vaddr_t, vsize_t);
void sh4_dcache_wbinv_range_index(vaddr_t, vsize_t);
void sh4_dcache_inv_range(vaddr_t, vsize_t);
void sh4_dcache_wb_range(vaddr_t, vsize_t);

/* EMODE */
void sh4_emode_icache_sync_all(void);
void sh4_emode_icache_sync_range_index(vaddr_t, vsize_t);
void sh4_emode_dcache_wbinv_all(void);
void sh4_emode_dcache_wbinv_range_index(vaddr_t, vsize_t);

/* must be inlined. */
static inline void cache_sh4_op_line_32(vaddr_t, vaddr_t, uint32_t,
    uint32_t);
static inline void cache_sh4_op_8lines_32(vaddr_t, vaddr_t, uint32_t,
    uint32_t);
static inline void cache_sh4_emode_op_line_32(vaddr_t, vaddr_t,
    uint32_t, uint32_t, uint32_t);
static inline void cache_sh4_emode_op_8lines_32(vaddr_t, vaddr_t,
    uint32_t, uint32_t, uint32_t);

void
sh4_cache_config(void)
{
	int icache_size;
	int dcache_size;
	int ways;
	uint32_t r;

        /* Determine cache size */
	switch (cpu_product) {
	default:
		/* FALLTHROUGH */
	case CPU_PRODUCT_7750:
	case CPU_PRODUCT_7750S:
	case CPU_PRODUCT_7751:
#if defined(SH4_CACHE_DISABLE_EMODE)
	case CPU_PRODUCT_7750R:
	case CPU_PRODUCT_7751R:
#endif
		icache_size = SH4_ICACHE_SIZE;
		dcache_size = SH4_DCACHE_SIZE;
		ways = 1;
		r = SH4_CCR_ICE|SH4_CCR_OCE|SH4_CCR_WT;
		break;

#if !defined(SH4_CACHE_DISABLE_EMODE)
	case CPU_PRODUCT_7750R:
	case CPU_PRODUCT_7751R:
		icache_size = SH4_EMODE_ICACHE_SIZE;
		dcache_size = SH4_EMODE_DCACHE_SIZE;
		ways = 2;
		r = SH4_CCR_EMODE|SH4_CCR_ICE|SH4_CCR_OCE|SH4_CCR_WT;
		break;
#endif
	}
#if defined(SH4_CACHE_DISABLE_ICACHE)
	r &= ~SH4_CCR_ICE;
#endif
#if defined(SH4_CACHE_DISABLE_DCACHE)
	r &= ~SH4_CCR_OCE;
#endif
#if !defined (SH4_CACHE_WT)
#define	SH4_CACHE_WB_U0_P0_P3
#define	SH4_CACHE_WB_P1
#endif
#if defined(SH4_CACHE_WB_U0_P0_P3)
	r &= ~SH4_CCR_WT;
#endif
#if defined(SH4_CACHE_WB_P1)
	r |= SH4_CCR_CB;
#endif

	sh4_icache_sync_all();
	RUN_P2;
	_reg_write_4(SH4_CCR, SH4_CCR_ICI|SH4_CCR_OCI);
	_reg_write_4(SH4_CCR, r);
	RUN_P1;

	r = _reg_read_4(SH4_CCR);

	sh_cache_unified = 0;
	sh_cache_enable_icache = (r & SH4_CCR_ICE);
	sh_cache_enable_dcache = (r & SH4_CCR_OCE);
	sh_cache_ways = ways;
	sh_cache_line_size = SH4_CACHE_LINESZ;
	sh_cache_prefer_mask = (dcache_size / ways - 1);
	sh_cache_write_through_p0_u0_p3 = (r & SH4_CCR_WT);
	sh_cache_write_through_p1 = !(r & SH4_CCR_CB);
	sh_cache_write_through = sh_cache_write_through_p0_u0_p3 &&
	    sh_cache_write_through_p1;
	sh_cache_ram_mode = (r & SH4_CCR_ORA);
	sh_cache_index_mode_icache = (r & SH4_CCR_IIX);
	sh_cache_index_mode_dcache = (r & SH4_CCR_OIX);

	sh_cache_size_dcache = dcache_size;
	if (sh_cache_ram_mode)
		sh_cache_size_dcache /= 2;
	sh_cache_size_icache = icache_size;

	sh_cache_ops._icache_sync_all		= sh4_icache_sync_all;
	sh_cache_ops._icache_sync_range		= sh4_icache_sync_range;
	sh_cache_ops._icache_sync_range_index	= sh4_icache_sync_range_index;

	sh_cache_ops._dcache_wbinv_all		= sh4_dcache_wbinv_all;
	sh_cache_ops._dcache_wbinv_range	= sh4_dcache_wbinv_range;
	sh_cache_ops._dcache_wbinv_range_index	= sh4_dcache_wbinv_range_index;
	sh_cache_ops._dcache_inv_range		= sh4_dcache_inv_range;
	sh_cache_ops._dcache_wb_range		= sh4_dcache_wb_range;

	switch (cpu_product) {
	case CPU_PRODUCT_7750:
	case CPU_PRODUCT_7750S:
		/* memory mapped D$ can only be accessed from p2 */
		sh_cache_ops._dcache_wbinv_all =
		    (void *)SH3_P1SEG_TO_P2SEG(sh4_dcache_wbinv_all);
		sh_cache_ops._dcache_wbinv_range_index =
		    (void *)SH3_P1SEG_TO_P2SEG(sh4_dcache_wbinv_range_index);
		break;
	case CPU_PRODUCT_7750R:
	case CPU_PRODUCT_7751R:
		if (!(r & SH4_CCR_EMODE)) {
			break;
		}
		sh_cache_ops._icache_sync_all = sh4_emode_icache_sync_all;
		sh_cache_ops._icache_sync_range_index = sh4_emode_icache_sync_range_index;
		sh_cache_ops._dcache_wbinv_all = sh4_emode_dcache_wbinv_all;
		sh_cache_ops._dcache_wbinv_range_index = sh4_emode_dcache_wbinv_range_index;
		break;
	}
}

/*
 * cache_sh4_op_line_32: (index-operation)
 *
 *	Clear the specified bits on single 32-byte cache line.
 */
static inline void
cache_sh4_op_line_32(vaddr_t va, vaddr_t base, uint32_t mask, uint32_t bits)
{
	vaddr_t cca;

	cca = base | (va & mask);
	_reg_bclr_4(cca, bits);
}

/*
 * cache_sh4_op_8lines_32: (index-operation)
 *
 *	Clear the specified bits on 8 32-byte cache lines.
 */
static inline void
cache_sh4_op_8lines_32(vaddr_t va, vaddr_t base, uint32_t mask, uint32_t bits)
{
	volatile uint32_t *cca = (volatile uint32_t *)
	    (base | (va & mask));

	cca[ 0] &= ~bits;
	cca[ 8] &= ~bits;
	cca[16] &= ~bits;
	cca[24] &= ~bits;
	cca[32] &= ~bits;
	cca[40] &= ~bits;
	cca[48] &= ~bits;
	cca[56] &= ~bits;
}

void
sh4_icache_sync_all(void)
{
	vaddr_t va = 0;
	vaddr_t eva = SH4_ICACHE_SIZE;

	sh4_dcache_wbinv_all();

	RUN_P2;
	while (va < eva) {
		cache_sh4_op_8lines_32(va, SH4_CCIA, CCIA_ENTRY_MASK, CCIA_V);
		va += 32 * 8;
	}
	PAD_P1_SWITCH;
}

void
sh4_icache_sync_range(vaddr_t va, vsize_t sz)
{
	vaddr_t ccia;
	vaddr_t eva = round_line(va + sz);
	va = trunc_line(va);

	sh4_dcache_wbinv_range(va, (eva - va));

	RUN_P2;
	while (va < eva) {
		/* CCR.IIX has no effect on this entry specification */
		ccia = SH4_CCIA | CCIA_A | (va & CCIA_ENTRY_MASK);
		_reg_write_4(ccia, va & CCIA_TAGADDR_MASK); /* V = 0 */
		va += 32;
	}
	PAD_P1_SWITCH;
}

void
sh4_icache_sync_range_index(vaddr_t va, vsize_t sz)
{
	vaddr_t eva = round_line(va + sz);
	va = trunc_line(va);

	sh4_dcache_wbinv_range_index(va, eva - va);

	RUN_P2;
	while ((eva - va) >= (8 * 32)) {
		cache_sh4_op_8lines_32(va, SH4_CCIA, CCIA_ENTRY_MASK, CCIA_V);
		va += 32 * 8;
	}

	while (va < eva) {
		cache_sh4_op_line_32(va, SH4_CCIA, CCIA_ENTRY_MASK, CCIA_V);
		va += 32;
	}
	PAD_P1_SWITCH;
}

void
sh4_dcache_wbinv_all(void)
{
	vaddr_t va = 0;
	vaddr_t eva = SH4_DCACHE_SIZE;

	/* RUN_P2; */ /* called via P2 address if necessary */
	while (va < eva) {
		cache_sh4_op_8lines_32(va, SH4_CCDA, CCDA_ENTRY_MASK,
		    (CCDA_U | CCDA_V));
		va += 32 * 8;
	}
	PAD_P1_SWITCH;
}

void
sh4_dcache_wbinv_range(vaddr_t va, vsize_t sz)
{
	vaddr_t eva = round_line(va + sz);
	va = trunc_line(va);

	while (va < eva) {
		__asm volatile("ocbp @%0" : : "r"(va));
		va += 32;
	}
}

void
sh4_dcache_wbinv_range_index(vaddr_t va, vsize_t sz)
{
	vaddr_t eva = round_line(va + sz);
	va = trunc_line(va);

	/* RUN_P2; */ /* called via P2 address if necessary */
	while ((eva - va) >= (8 * 32)) {
		cache_sh4_op_8lines_32(va, SH4_CCDA, CCDA_ENTRY_MASK,
		    (CCDA_U | CCDA_V));
		va += 32 * 8;
	}

	while (va < eva) {
		cache_sh4_op_line_32(va, SH4_CCDA, CCDA_ENTRY_MASK,
		    (CCDA_U | CCDA_V));
		va += 32;
	}
	PAD_P1_SWITCH;
}

void
sh4_dcache_inv_range(vaddr_t va, vsize_t sz)
{
	vaddr_t eva = round_line(va + sz);
	va = trunc_line(va);

	while (va < eva) {
		__asm volatile("ocbi @%0" : : "r"(va));
		va += 32;
	}
}

void
sh4_dcache_wb_range(vaddr_t va, vsize_t sz)
{
	vaddr_t eva = round_line(va + sz);
	va = trunc_line(va);

	while (va < eva) {
		__asm volatile("ocbwb @%0" : : "r"(va));
		va += 32;
	}
}

/*
 * EMODE operation
 */
/*
 * cache_sh4_emode_op_line_32: (index-operation)
 *
 *	Clear the specified bits on single 32-byte cache line. 2-ways.
 */
static inline void
cache_sh4_emode_op_line_32(vaddr_t va, vaddr_t base, uint32_t mask,
    uint32_t bits, uint32_t way_shift)
{
	vaddr_t cca;

	/* extract entry # */
	va &= mask;

	/* operate for each way */
	cca = base | (0 << way_shift) | va;
	_reg_bclr_4(cca, bits);

	cca = base | (1 << way_shift) | va;
	_reg_bclr_4(cca, bits);
}

/*
 * cache_sh4_emode_op_8lines_32: (index-operation)
 *
 *	Clear the specified bits on 8 32-byte cache lines. 2-ways.
 */
static inline void
cache_sh4_emode_op_8lines_32(vaddr_t va, vaddr_t base, uint32_t mask,
    uint32_t bits, uint32_t way_shift)
{
	volatile uint32_t *cca;

	/* extract entry # */
	va &= mask;

	/* operate for each way */
	cca = (volatile uint32_t *)(base | (0 << way_shift) | va);
	cca[ 0] &= ~bits;
	cca[ 8] &= ~bits;
	cca[16] &= ~bits;
	cca[24] &= ~bits;
	cca[32] &= ~bits;
	cca[40] &= ~bits;
	cca[48] &= ~bits;
	cca[56] &= ~bits;

	cca = (volatile uint32_t *)(base | (1 << way_shift) | va);
	cca[ 0] &= ~bits;
	cca[ 8] &= ~bits;
	cca[16] &= ~bits;
	cca[24] &= ~bits;
	cca[32] &= ~bits;
	cca[40] &= ~bits;
	cca[48] &= ~bits;
	cca[56] &= ~bits;
}

void
sh4_emode_icache_sync_all(void)
{
	vaddr_t va = 0;
	vaddr_t eva = SH4_ICACHE_SIZE;

	sh4_emode_dcache_wbinv_all();

	RUN_P2;
	while (va < eva) {
		cache_sh4_emode_op_8lines_32(va, SH4_CCIA, CCIA_ENTRY_MASK,
		    CCIA_V, 13);
		va += 32 * 8;
	}
	PAD_P1_SWITCH;
}

void
sh4_emode_icache_sync_range_index(vaddr_t va, vsize_t sz)
{
	vaddr_t eva = round_line(va + sz);
	va = trunc_line(va);

	sh4_emode_dcache_wbinv_range_index(va, eva - va);

	RUN_P2;
	while ((eva - va) >= (8 * 32)) {
		cache_sh4_emode_op_8lines_32(va, SH4_CCIA, CCIA_ENTRY_MASK,
		    CCIA_V, 13);
		va += 32 * 8;
	}

	while (va < eva) {
		cache_sh4_emode_op_line_32(va, SH4_CCIA, CCIA_ENTRY_MASK,
		    CCIA_V, 13);
		va += 32;
	}
	PAD_P1_SWITCH;
}

void
sh4_emode_dcache_wbinv_all(void)
{
	vaddr_t va = 0;
	vaddr_t eva = SH4_DCACHE_SIZE;

	while (va < eva) {
		cache_sh4_emode_op_8lines_32(va, SH4_CCDA, CCDA_ENTRY_MASK,
		    (CCDA_U | CCDA_V), 14);
		va += 32 * 8;
	}
}

void
sh4_emode_dcache_wbinv_range_index(vaddr_t va, vsize_t sz)
{
	vaddr_t eva = round_line(va + sz);
	va = trunc_line(va);

	while ((eva - va) >= (8 * 32)) {
		cache_sh4_emode_op_8lines_32(va, SH4_CCDA, CCDA_ENTRY_MASK,
		    (CCDA_U | CCDA_V), 14);
		va += 32 * 8;
	}

	while (va < eva) {
		cache_sh4_emode_op_line_32(va, SH4_CCDA, CCDA_ENTRY_MASK,
		    (CCDA_U | CCDA_V), 14);
		va += 32;
	}
}


code:
/*	$OpenBSD: clock.c,v 1.7 2012/09/08 22:01:25 miod Exp $	*/
/*	$NetBSD: clock.c,v 1.32 2006/09/05 11:09:36 uwe Exp $	*/

/*-
 * Copyright (c) 2002 The NetBSD Foundation, Inc.
 * All rights reserved.
 *
 * This code is derived from software contributed to The NetBSD Foundation
 * by UCHIYAMA Yasushi.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/device.h>
#include <sys/timetc.h>

#include <dev/clock_subr.h>

#include <sh/clock.h>
#include <sh/trap.h>
#include <sh/rtcreg.h>
#include <sh/tmureg.h>

#include <machine/intr.h>

#define	NWDOG 0

#ifndef HZ
#define	HZ		64
#endif
#define	MINYEAR		2002	/* "today" */
#define	SH_RTC_CLOCK	16384	/* Hz */

/*
 * OpenBSD/sh clock module
 *  + default 64Hz
 *  + use TMU channel 0 as clock interrupt source.
 *  + use TMU channel 1 as emulated software interrupt source.
 *  + use TMU channel 2 as freeruuning counter for timecounter.
 *  + If RTC module is active, TMU channel 0 input source is RTC output.
 *    (1.6384kHz)
 */
struct {
	/* Hard clock */
	uint32_t hz_cnt;	/* clock interrupt interval count */
	uint32_t cpucycle_1us;	/* calibrated loop variable (1 us) */
	uint32_t tmuclk;	/* source clock of TMU0 (Hz) */

	/* RTC ops holder. default SH RTC module */
	struct rtc_ops rtc;
	int rtc_initialized;

	uint32_t pclock;	/* PCLOCK */
	uint32_t cpuclock;	/* CPU clock */
	int flags;

	struct timecounter tc;
} sh_clock = {
#ifdef PCLOCK
	.pclock = PCLOCK,
#endif
	.rtc = {
		/* SH RTC module to default RTC */
		.init	= sh_rtc_init,
		.get	= sh_rtc_get,
		.set	= sh_rtc_set
	}
};

uint32_t maxwdog;

/* TMU */
/* interrupt handler is timing critical. prepared for each. */
int sh3_clock_intr(void *);
int sh4_clock_intr(void *);
u_int sh_timecounter_get(struct timecounter *);

/*
 * Estimate CPU and Peripheral clock.
 */
#define	TMU_START(x)							\
do {									\
	_reg_bclr_1(SH_(TSTR), TSTR_STR##x);				\
	_reg_write_4(SH_(TCNT ## x), 0xffffffff);			\
	_reg_bset_1(SH_(TSTR), TSTR_STR##x);				\
} while (/*CONSTCOND*/0)

#define	TMU_ELAPSED(x)							\
	(0xffffffff - _reg_read_4(SH_(TCNT ## x)))

void
sh_clock_init(int flags, struct rtc_ops *rtc)
{
	uint32_t s, t0, cnt_1s;

	sh_clock.flags = flags;
	if (rtc != NULL)
		sh_clock.rtc = *rtc;	/* structure copy */

	/* Initialize TMU */
	_reg_write_2(SH_(TCR0), 0);
	_reg_write_2(SH_(TCR1), 0);
	_reg_write_2(SH_(TCR2), 0);

	/* Reset RTC alarm and interrupt */
	_reg_write_1(SH_(RCR1), 0);

	/* Stop all counter */
	_reg_write_1(SH_(TSTR), 0);

	/*
	 * Estimate CPU clock.
	 */
	if (sh_clock.flags & SH_CLOCK_NORTC) {
		/* Set TMU channel 0 source to PCLOCK / 16 */
		_reg_write_2(SH_(TCR0), TCR_TPSC_P16);
		sh_clock.tmuclk = sh_clock.pclock / 16;
	} else {
		/* Set TMU channel 0 source to RTC counter clock (16.384kHz) */
		_reg_write_2(SH_(TCR0),
		    CPU_IS_SH3 ? SH3_TCR_TPSC_RTC : SH4_TCR_TPSC_RTC);
		sh_clock.tmuclk = SH_RTC_CLOCK;

		/* Make sure RTC oscillator is enabled */
		_reg_bset_1(SH_(RCR2), SH_RCR2_ENABLE);
	}

	s = _cpu_exception_suspend();
	_cpu_spin(1);	/* load function on cache. */
	TMU_START(0);
	_cpu_spin(10000000);
	t0 = TMU_ELAPSED(0);
	_cpu_exception_resume(s);

	sh_clock.cpucycle_1us = (sh_clock.tmuclk * 10) / t0;

	cnt_1s = ((uint64_t)sh_clock.tmuclk * 10000000 * 10 + t0 / 2) / t0;
	if (CPU_IS_SH4)
		sh_clock.cpuclock = cnt_1s / 2;	/* two-issue */
	else
		sh_clock.cpuclock = cnt_1s;

	/*
	 * Estimate PCLOCK
	 */
	if (sh_clock.pclock == 0) {
		uint32_t t1;

		/* set TMU channel 1 source to PCLOCK / 4 */
		_reg_write_2(SH_(TCR1), TCR_TPSC_P4);
		s = _cpu_exception_suspend();
		_cpu_spin(1);	/* load function on cache. */
		TMU_START(0);
		TMU_START(1);
		_cpu_spin(cnt_1s); /* 1 sec. */
		t0 = TMU_ELAPSED(0);
		t1 = TMU_ELAPSED(1);
		_cpu_exception_resume(s);

		sh_clock.pclock =
		    ((uint64_t)t1 * 4 * SH_RTC_CLOCK + t0 / 2) / t0;
	}

	/* Stop all counters */
	_reg_write_1(SH_(TSTR), 0);

#undef TMU_START
#undef TMU_ELAPSED
}

int
sh_clock_get_cpuclock()
{
	return (sh_clock.cpuclock);
}

int
sh_clock_get_pclock()
{
	return (sh_clock.pclock);
}

void
setstatclockrate(int newhz)
{
	/* XXX not yet */
}

u_int
sh_timecounter_get(struct timecounter *tc)
{
	return 0xffffffff - _reg_read_4(SH_(TCNT2));
}

/*
 *  Wait at least `n' usec.
 */
void
delay(int n)
{
	_cpu_spin(sh_clock.cpucycle_1us * n);
}

/*
 * Start the clock interrupt.
 */
void
cpu_initclocks()
{
	if (sh_clock.pclock == 0)
		panic("No PCLOCK information.");

	/* Set global variables. */
	hz = HZ;
	tick = 1000000 / hz;

	/*
	 * Use TMU channel 0 as hard clock
	 */
	_reg_bclr_1(SH_(TSTR), TSTR_STR0);

	if (sh_clock.flags & SH_CLOCK_NORTC) {
		/* use PCLOCK/16 as TMU0 source */
		_reg_write_2(SH_(TCR0), TCR_UNIE | TCR_TPSC_P16);
	} else {
		/* use RTC clock as TMU0 source */
		_reg_write_2(SH_(TCR0), TCR_UNIE |
		    (CPU_IS_SH3 ? SH3_TCR_TPSC_RTC : SH4_TCR_TPSC_RTC));
	}
	sh_clock.hz_cnt = sh_clock.tmuclk / hz - 1;

	_reg_write_4(SH_(TCOR0), sh_clock.hz_cnt);
	_reg_write_4(SH_(TCNT0), sh_clock.hz_cnt);

	intc_intr_establish(SH_INTEVT_TMU0_TUNI0, IST_LEVEL, IPL_CLOCK,
	    CPU_IS_SH3 ? sh3_clock_intr : sh4_clock_intr, NULL, "clock");
	/* start hardclock */
	_reg_bset_1(SH_(TSTR), TSTR_STR0);

	/*
	 * TMU channel 1 is one shot timer for soft interrupts.
	 */
	_reg_write_2(SH_(TCR1), TCR_UNIE | TCR_TPSC_P4);
	_reg_write_4(SH_(TCOR1), 0xffffffff);

	/*
	 * TMU channel 2 is freerunning counter for timecounter.
	 */
	_reg_write_2(SH_(TCR2), TCR_TPSC_P4);
	_reg_write_4(SH_(TCOR2), 0xffffffff);

	/*
	 * Start and initialize timecounter.
	 */
	_reg_bset_1(SH_(TSTR), TSTR_STR2);

	sh_clock.tc.tc_get_timecount = sh_timecounter_get;
	sh_clock.tc.tc_frequency = sh_clock.pclock / 4;
	sh_clock.tc.tc_name = "tmu_pclock_4";
	sh_clock.tc.tc_quality = 100;
	sh_clock.tc.tc_counter_mask = 0xffffffff;
	tc_init(&sh_clock.tc);

	/* Make sure to start RTC */
	if (sh_clock.rtc.init != NULL)
		sh_clock.rtc.init(sh_clock.rtc._cookie);
}

void
inittodr(time_t base)
{
	struct clock_ymdhms dt;
	struct timespec ts;
	time_t rtc;

	if (!sh_clock.rtc_initialized)
		sh_clock.rtc_initialized = 1;

	sh_clock.rtc.get(sh_clock.rtc._cookie, base, &dt);
	rtc = clock_ymdhms_to_secs(&dt);

#ifdef DEBUG
	printf("inittodr: %d/%d/%d/%d/%d/%d(%d)\n", dt.dt_year,
	    dt.dt_mon, dt.dt_day, dt.dt_hour, dt.dt_min, dt.dt_sec,
	    dt.dt_wday);
#endif

	if (!(sh_clock.flags & SH_CLOCK_NOINITTODR) &&
	    (rtc < base ||
		dt.dt_year < MINYEAR || dt.dt_year > 2037 ||
		dt.dt_mon < 1 || dt.dt_mon > 12 ||
		dt.dt_wday > 6 ||
		dt.dt_day < 1 || dt.dt_day > 31 ||
		dt.dt_hour > 23 || dt.dt_min > 59 || dt.dt_sec > 59)) {
		/*
		 * Believe the time in the file system for lack of
		 * anything better, resetting the RTC.
		 */
		ts.tv_sec = base;
		ts.tv_nsec = 0;
		tc_setclock(&ts);
		printf("WARNING: preposterous clock chip time\n");
		resettodr();
		printf(" -- CHECK AND RESET THE DATE!\n");
		return;
	}

	ts.tv_sec = rtc;
	ts.tv_nsec = 0;
	tc_setclock(&ts);

	return;
}

void
resettodr()
{
	struct clock_ymdhms dt;
	int s;

	if (!sh_clock.rtc_initialized)
		return;

	s = splclock();
	clock_secs_to_ymdhms(time_second, &dt);
	splx(s);

	sh_clock.rtc.set(sh_clock.rtc._cookie, &dt);
#ifdef DEBUG
        printf("%s: %d/%d/%d/%d/%d/%d(%d)\n", __FUNCTION__,
	    dt.dt_year, dt.dt_mon, dt.dt_day, dt.dt_hour, dt.dt_min, dt.dt_sec,
	    dt.dt_wday);
#endif
}

#ifdef SH3
int
sh3_clock_intr(void *arg) /* trap frame */
{
#if (NWDOG > 0)
	uint32_t i;

	i = (uint32_t)SHREG_WTCNT_R;
	if (i > maxwdog)
		maxwdog = i;
	wdog_wr_cnt(0);			/* reset to zero */
#endif
	/* clear underflow status */
	_reg_bclr_2(SH3_TCR0, TCR_UNF);

	hardclock(arg);

	return (1);
}
#endif /* SH3 */

#ifdef SH4
int
sh4_clock_intr(void *arg) /* trap frame */
{
#if (NWDOG > 0)
	uint32_t i;

	i = (uint32_t)SHREG_WTCNT_R;
	if (i > maxwdog)
		maxwdog = i;
	wdog_wr_cnt(0);			/* reset to zero */
#endif
	/* clear underflow status */
	_reg_bclr_2(SH4_TCR0, TCR_UNF);

	hardclock(arg);

	return (1);
}
#endif /* SH4 */

/*
 * SH3 RTC module ops.
 */

void
sh_rtc_init(void *cookie)
{
	/* Make sure to start RTC */
	_reg_write_1(SH_(RCR2), SH_RCR2_ENABLE | SH_RCR2_START);
}

void
sh_rtc_get(void *cookie, time_t base, struct clock_ymdhms *dt)
{
	int retry = 8;

	/* disable carry interrupt */
	_reg_bclr_1(SH_(RCR1), SH_RCR1_CIE);

	do {
		uint8_t r = _reg_read_1(SH_(RCR1));
		r &= ~SH_RCR1_CF;
		r |= SH_RCR1_AF; /* don't clear alarm flag */
		_reg_write_1(SH_(RCR1), r);

		if (CPU_IS_SH3)
			dt->dt_year = FROMBCD(_reg_read_1(SH3_RYRCNT));
		else
			dt->dt_year = FROMBCD(_reg_read_2(SH4_RYRCNT) & 0x00ff);

		/* read counter */
#define	RTCGET(x, y)	dt->dt_ ## x = FROMBCD(_reg_read_1(SH_(R ## y ## CNT)))
		RTCGET(mon, MON);
		RTCGET(wday, WK);
		RTCGET(day, DAY);
		RTCGET(hour, HR);
		RTCGET(min, MIN);
		RTCGET(sec, SEC);
#undef RTCGET
	} while ((_reg_read_1(SH_(RCR1)) & SH_RCR1_CF) && --retry > 0);

	if (retry == 0) {
		printf("rtc_gettime: couldn't read RTC register.\n");
		memset(dt, 0, sizeof(*dt));
		return;
	}

	dt->dt_year = (dt->dt_year % 100) + 1900;
	if (dt->dt_year < 1970)
		dt->dt_year += 100;
}

void
sh_rtc_set(void *cookie, struct clock_ymdhms *dt)
{
	uint8_t r;

	/* stop clock */
	r = _reg_read_1(SH_(RCR2));
	r |= SH_RCR2_RESET;
	r &= ~SH_RCR2_START;
	_reg_write_1(SH_(RCR2), r);

	/* set time */
	if (CPU_IS_SH3)
		_reg_write_1(SH3_RYRCNT, TOBCD(dt->dt_year % 100));
	else
		_reg_write_2(SH4_RYRCNT, TOBCD(dt->dt_year % 100));
#define	RTCSET(x, y)	_reg_write_1(SH_(R ## x ## CNT), TOBCD(dt->dt_ ## y))
	RTCSET(MON, mon);
	RTCSET(WK, wday);
	RTCSET(DAY, day);
	RTCSET(HR, hour);
	RTCSET(MIN, min);
	RTCSET(SEC, sec);
#undef RTCSET
	/* start clock */
	_reg_write_1(SH_(RCR2), r | SH_RCR2_START);
}


code:
/*	$OpenBSD: cpu.c,v 1.3 2008/06/26 05:42:13 ray Exp $	*/
/*	$NetBSD: cpu.c,v 1.8 2006/01/02 23:16:20 uwe Exp $	*/

/*-
 * Copyright (c) 2002 The NetBSD Foundation, Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>

#include <sh/clock.h>
#include <sh/cache.h>
#include <sh/mmu.h>

#include <machine/autoconf.h>

int	cpu_match(struct device *, void *, void *);
void	cpu_attach(struct device *, struct device *, void *);

struct cfattach cpu_ca = {
	sizeof(struct device), cpu_match, cpu_attach
};

struct cfdriver cpu_cd = {
	0, "cpu", DV_DULL
};

struct cpu_info cpu_info_store;

int
cpu_match(struct device *parent, void *vcf, void *aux)
{
	struct mainbus_attach_args *ma = aux;

	if (strcmp(ma->ma_name, cpu_cd.cd_name) != 0)
		return (0);

	return (1);
}

void
cpu_attach(struct device *parent, struct device *self, void *aux)
{
#define	MHZ(x) ((x) / 1000000), (((x) % 1000000) / 1000)
	printf(": HITACHI SH%d %d.%02d MHz PCLOCK %d.%02d MHz\n",
	    CPU_IS_SH3 ? 3 : 4, MHZ(sh_clock_get_cpuclock()),
	    MHZ(sh_clock_get_pclock()));
#undef MHZ
	sh_cache_information();
	sh_mmu_information();
}


code:
/*	$OpenBSD: db_disasm.c,v 1.3 2007/02/26 19:33:41 miod Exp $	*/
/*	$NetBSD: db_disasm.c,v 1.13 2006/01/21 02:09:06 uwe Exp $	*/

/*
 * Copyright (c) 1998-2000 Internet Initiative Japan Inc.
 * All rights reserved.
 *
 * Author: Akinori Koketsu
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistribution with functional modification must include
 *    prominent notice stating how and when and by whom it is
 *    modified.
 * 3. Redistributions in binary form have to be along with the source
 *    code or documentation which include above copyright notice, this
 *    list of conditions and the following disclaimer.
 * 4. All commercial advertising materials mentioning features or use
 *    of this software must display the following acknowledgement:
 *      This product includes software developed by Internet
 *      Initiative Japan Inc.
 *
 * THIS SOFTWARE IS PROVIDED BY ``AS IS'' AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED.
 */

#include <sys/param.h>
#include <sys/systm.h>

#include <machine/db_machdep.h>

#include <ddb/db_interface.h>
#include <ddb/db_output.h>
#include <ddb/db_sym.h>

static void	disasm_branch(char *, size_t, const char *, db_addr_t);
static void	get_ascii(unsigned char *, char *);
static void	get_opcode(db_addr_t, char *, size_t);
static void	f_02(db_addr_t, u_int, char *, size_t);
static void	f_03(db_addr_t, u_int, char *, size_t);
static void	f_04(db_addr_t, u_int, char *, size_t);
static void	f_08(db_addr_t, u_int, char *, size_t);
static void	f_09(db_addr_t, u_int, char *, size_t);
static void	f_0a(db_addr_t, u_int, char *, size_t);
static void	f_0b(db_addr_t, u_int, char *, size_t);
static void	f_0c(db_addr_t, u_int, char *, size_t);
static void	f_10(db_addr_t, u_int, char *, size_t);
static void	f_20(db_addr_t, u_int, char *, size_t);
static void	f_24(db_addr_t, u_int, char *, size_t);
static void	f_28(db_addr_t, u_int, char *, size_t);
static void	f_2c(db_addr_t, u_int, char *, size_t);
static void	f_30(db_addr_t, u_int, char *, size_t);
static void	f_34(db_addr_t, u_int, char *, size_t);
static void	f_38(db_addr_t, u_int, char *, size_t);
static void	f_3c(db_addr_t, u_int, char *, size_t);
static void	f_40(db_addr_t, u_int, char *, size_t);
static void	f_41(db_addr_t, u_int, char *, size_t);
static void	f_42(db_addr_t, u_int, char *, size_t);
static void	f_43(db_addr_t, u_int, char *, size_t);
static void	f_44(db_addr_t, u_int, char *, size_t);
static void	f_45(db_addr_t, u_int, char *, size_t);
static void	f_46(db_addr_t, u_int, char *, size_t);
static void	f_47(db_addr_t, u_int, char *, size_t);
static void	f_48(db_addr_t, u_int, char *, size_t);
static void	f_49(db_addr_t, u_int, char *, size_t);
static void	f_4a(db_addr_t, u_int, char *, size_t);
static void	f_4b(db_addr_t, u_int, char *, size_t);
static void	f_4c(db_addr_t, u_int, char *, size_t);
static void	f_4d(db_addr_t, u_int, char *, size_t);
static void	f_4e(db_addr_t, u_int, char *, size_t);
static void	f_4f(db_addr_t, u_int, char *, size_t);
static void	f_50(db_addr_t, u_int, char *, size_t);
static void	f_60(db_addr_t, u_int, char *, size_t);
static void	f_64(db_addr_t, u_int, char *, size_t);
static void	f_68(db_addr_t, u_int, char *, size_t);
static void	f_6c(db_addr_t, u_int, char *, size_t);
static void	f_70(db_addr_t, u_int, char *, size_t);
static void	f_80(db_addr_t, u_int, char *, size_t);
static void	f_90(db_addr_t, u_int, char *, size_t);
static void	f_a0(db_addr_t, u_int, char *, size_t);
static void	f_b0(db_addr_t, u_int, char *, size_t);
static void	f_c0(db_addr_t, u_int, char *, size_t);
static void	f_d0(db_addr_t, u_int, char *, size_t);
static void	f_e0(db_addr_t, u_int, char *, size_t);
static void	f_f0(db_addr_t, u_int, char *, size_t);
static void	f_f4(db_addr_t, u_int, char *, size_t);
static void	f_f8(db_addr_t, u_int, char *, size_t);
static void	f_fc(db_addr_t, u_int, char *, size_t);
static void	f_fd(db_addr_t, u_int, char *, size_t);
static void	f_fe(db_addr_t, u_int, char *, size_t);

typedef	void (*rasm_t)(db_addr_t, u_int, char *, size_t);
static const rasm_t f[16][16] = {
	{ /* [0][0-7] */	NULL, NULL, f_02, f_03, f_04, f_04, f_04, f_04,
	  /* [0][8-f] */	f_08, f_09, f_0a, f_0b, f_0c, f_0c, f_0c, f_0c },
	{ /* [1][0-7] */	f_10, f_10, f_10, f_10, f_10, f_10, f_10, f_10,
	  /* [1][8-f] */	f_10, f_10, f_10, f_10, f_10, f_10, f_10, f_10 },
	{ /* [2][0-7] */	f_20, f_20, f_20, f_20, f_24, f_24, f_24, f_24,
	  /* [2][8-f] */	f_28, f_28, f_28, f_28, f_2c, f_2c, f_2c, f_2c },
	{ /* [3][0-7] */	f_30, f_30, f_30, f_30, f_34, f_34, f_34, f_34,
	  /* [3][8-f] */	f_38, f_38, f_38, f_38, f_3c, f_3c, f_3c, f_3c },
	{ /* [4][0-7] */	f_40, f_41, f_42, f_43, f_44, f_45, f_46, f_47,
	  /* [4][8-f] */	f_48, f_49, f_4a, f_4b, f_4c, f_4d, f_4e, f_4f },
	{ /* [5][0-7] */	f_50, f_50, f_50, f_50, f_50, f_50, f_50, f_50,
	  /* [5][8-f] */	f_50, f_50, f_50, f_50, f_50, f_50, f_50, f_50 },
	{ /* [6][0-7] */	f_60, f_60, f_60, f_60, f_64, f_64, f_64, f_64,
	  /* [6][8-f] */	f_68, f_68, f_68, f_68, f_6c, f_6c, f_6c, f_6c },
	{ /* [7][0-7] */	f_70, f_70, f_70, f_70, f_70, f_70, f_70, f_70,
	  /* [7][8-f] */	f_70, f_70, f_70, f_70, f_70, f_70, f_70, f_70 },
	{ /* [8][0-7] */	f_80, f_80, f_80, f_80, f_80, f_80, f_80, f_80,
	  /* [8][8-f] */	f_80, f_80, f_80, f_80, f_80, f_80, f_80, f_80 },
	{ /* [9][0-7] */	f_90, f_90, f_90, f_90, f_90, f_90, f_90, f_90,
	  /* [9][8-f] */	f_90, f_90, f_90, f_90, f_90, f_90, f_90, f_90 },
	{ /* [a][0-7] */	f_a0, f_a0, f_a0, f_a0, f_a0, f_a0, f_a0, f_a0,
	  /* [a][8-f] */	f_a0, f_a0, f_a0, f_a0, f_a0, f_a0, f_a0, f_a0 },
	{ /* [b][0-7] */	f_b0, f_b0, f_b0, f_b0, f_b0, f_b0, f_b0, f_b0,
	  /* [b][8-f] */	f_b0, f_b0, f_b0, f_b0, f_b0, f_b0, f_b0, f_b0 },
	{ /* [c][0-7] */	f_c0, f_c0, f_c0, f_c0, f_c0, f_c0, f_c0, f_c0,
	  /* [c][8-f] */	f_c0, f_c0, f_c0, f_c0, f_c0, f_c0, f_c0, f_c0 },
	{ /* [d][0-7] */	f_d0, f_d0, f_d0, f_d0, f_d0, f_d0, f_d0, f_d0,
	  /* [d][8-f] */	f_d0, f_d0, f_d0, f_d0, f_d0, f_d0, f_d0, f_d0 },
	{ /* [e][0-7] */	f_e0, f_e0, f_e0, f_e0, f_e0, f_e0, f_e0, f_e0,
	  /* [e][8-f] */	f_e0, f_e0, f_e0, f_e0, f_e0, f_e0, f_e0, f_e0 },
	{ /* [f][0-7] */	f_f0, f_f0, f_f0, f_f0, f_f4, f_f4, f_f4, f_f4,
	  /* [f][8-f] */	f_f8, f_f8, f_f8, f_f8, f_fc, f_fd, f_fe, NULL }
};

db_addr_t
db_disasm(db_addr_t loc, boolean_t altfmt)
{
	char line[40], ascii[4];
	void *pc = (void *)loc;

	get_opcode(loc, line, sizeof line);
	if (altfmt) {
		get_ascii(pc, ascii);
		db_printf("%-32s ! %s\n", line, ascii);
	} else
		db_printf("%s\n", line);

	return (loc + 2);
}

static void
disasm_branch(char *buf, size_t bufsiz, const char *opstr, db_addr_t addr)
{
	size_t len;
	db_expr_t d, value;
	char *name;
	db_sym_t cursym;
	extern unsigned long db_lastsym;
	extern unsigned int db_maxoff;

	snprintf(buf, bufsiz, "%-8s", opstr);
	len = strlen(buf);
	buf += len;
	bufsiz -= len;

	if (addr <= db_lastsym) {
		cursym = db_search_symbol(addr, DB_STGY_PROC, &d);
		db_symbol_values(cursym, &name, &value);
		if (name && d < db_maxoff && value) {
			if (d == 0)
				snprintf(buf, bufsiz, "%s", name);
			else {
				snprintf(buf, bufsiz, "%s+", name);
				len = strlen(buf);
				buf += len;
				bufsiz -= len;
				db_format(buf, bufsiz, d, DB_FORMAT_R, 1, 0);
			}
			return;
		}
	}

	db_format(buf, bufsiz, addr, DB_FORMAT_N, 1, 0);
}

static void
get_ascii(unsigned char *cp, char *str)
{
	*str++ = (0x20 <= *cp && *cp < 0x7f) ? *cp : '.';
	cp++;
	*str++ = (0x20 <= *cp && *cp < 0x7f) ? *cp : '.';
	*str = '\0';
}

static void
get_opcode(db_addr_t loc, char *buf, size_t bufsiz)
{
	int n0, n3;
	u_int insn = *(u_int16_t *)loc;

	snprintf(buf, bufsiz, ".word 0x%x", insn);

	n0 = (insn & 0xf000) >> 12;
	n3 = (insn & 0x000f);

	if (f[n0][n3] != NULL)
		(*f[n0][n3])(loc, insn, buf, bufsiz);
}

static void
f_02(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	rn, type, md;

	rn   = (insn & 0x0f00) >> 8;
	type = (insn & 0x00c0) >> 6;
	md   = (insn & 0x0030) >> 4;

	switch (type) {
	case 0:
		switch (md) {
		case 0:
			snprintf(buf, bufsiz, "stc     sr, r%d", rn);
			break;
		case 1:
			snprintf(buf, bufsiz, "stc     gbr, r%d", rn);
			break;
		case 2:
			snprintf(buf, bufsiz, "stc     vbr, r%d", rn);
			break;
		case 3:
			snprintf(buf, bufsiz, "stc     ssr, r%d", rn);
			break;
		}
		break;
	case 1:
		switch (md) {
		case 0:
			snprintf(buf, bufsiz, "stc     spc, r%d", rn);
			break;
		}
		break;
	case 2:
		snprintf(buf, bufsiz, "stc     r%d_bank, r%d", md, rn);
		break;
	case 3:
		snprintf(buf, bufsiz, "stc     r%d_bank, r%d", md + 4, rn);
		break;
	} /* end of switch (type) */
}

static void
f_03(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	rn, type, md;

	rn   = (insn & 0x0f00) >> 8;
	type = (insn & 0x00c0) >> 6;
	md   = (insn & 0x0030) >> 4;

	switch (type) {
	case 0:
		switch (md) {
		case 0:
			snprintf(buf, bufsiz, "bsrf    r%d", rn);
			break;
		case 2:
			snprintf(buf, bufsiz, "braf    r%d", rn);
			break;
		}
		break;
	case 2:
		switch (md) {
		case 0:
			snprintf(buf, bufsiz, "pref    @r%d", rn);
			break;
		}
		break;
	} /* end of switch (type) */
}

static void
f_04(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	rn, rm, md;

	rn   = (insn & 0x0f00) >> 8;
	rm   = (insn & 0x00f0) >> 4;
	md   = (insn & 0x0003);

	switch (md) {
	case 0:
		snprintf(buf, bufsiz, "mov.b   r%d, @(r0, r%d)", rm, rn);
		break;
	case 1:
		snprintf(buf, bufsiz, "mov.w   r%d, @(r0, r%d)", rm, rn);
		break;
	case 2:
		snprintf(buf, bufsiz, "mov.l   r%d, @(r0, r%d)", rm, rn);
		break;
	case 3:
		snprintf(buf, bufsiz, "mul.l   r%d, r%d", rm, rn);
		break;
	} /* end of switch (md) */
}

static void
f_08(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	n1, type, md;

	n1   = (insn & 0x0f00) >> 8;
	type = (insn & 0x00c0) >> 6;
	md   = (insn & 0x0030) >> 4;

	if (n1 != 0)
		return;

	switch (type) {
	case 0:
		switch (md) {
		case 0:
			strlcpy(buf, "clrt", bufsiz);
			break;
		case 1:
			strlcpy(buf, "sett", bufsiz);
			break;
		case 2:
			strlcpy(buf, "clrmac", bufsiz);
			break;
		case 3:
			strlcpy(buf, "ldtlb", bufsiz);
			break;
		}
		break;
	case 1:
		switch (md) {
		case 0:
			strlcpy(buf, "clrs", bufsiz);
			break;
		case 1:
			strlcpy(buf, "sets", bufsiz);
			break;
		}
		break;
	} /* end of switch (type) */
}

static void
f_09(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	rn, fx;

	rn = (insn & 0x0f00) >> 8;
	fx = (insn & 0x00f0) >> 4;

	switch (fx) {
	case 0:
		if (rn != 0)
			return;
		strlcpy(buf, "nop", bufsiz);
		break;
	case 1:
		if (rn != 0)
			return;
		strlcpy(buf, "div0u", bufsiz);
		break;
	case 2:
		snprintf(buf, bufsiz, "movt    r%d", rn);
		break;
	} /* end of switch (fx) */
}

static void
f_0a(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	rn, type, md;

	rn   = (insn & 0x0f00) >> 8;
	type = (insn & 0x00c0) >> 6;
	md   = (insn & 0x0030) >> 4;

	switch (type) {
	case 0:
		switch (md) {
		case 0:
			snprintf(buf, bufsiz, "sts     mach, r%d", rn);
			break;
		case 1:
			snprintf(buf, bufsiz, "sts     macl, r%d", rn);
			break;
		case 2:
			snprintf(buf, bufsiz, "sts     pr, r%d", rn);
			break;
		}
		break;
	case 1:
		switch (md) {
		case 1:
			snprintf(buf, bufsiz, "sts     fpul, r%d", rn);
			break;
		case 2:
			snprintf(buf, bufsiz, "sts     fpscr, r%d", rn);
			break;
		}
		break;
	} /* end of switch (type) */
}

static void
f_0b(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	n1, fx;

	n1 = (insn & 0x0f00) >> 8;
	if (n1 != 0)
		return;

	fx = (insn & 0x00f0) >> 4;
	switch (fx) {
	case 0:
		strlcpy(buf, "rts", bufsiz);
		break;
	case 1:
		strlcpy(buf, "sleep", bufsiz);
		break;
	case 2:
		strlcpy(buf, "rte", bufsiz);
		break;
	} /* end of switch (fx) */
}

static void
f_0c(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	rn, rm, md;

	rn   = (insn & 0x0f00) >> 8;
	rm   = (insn & 0x00f0) >> 4;
	md   = (insn & 0x0003);

	switch (md) {
	case 0:
		snprintf(buf, bufsiz, "mov.b   @(r0, r%d), r%d", rm, rn);
		break;
	case 1:
		snprintf(buf, bufsiz, "mov.w   @(r0, r%d), r%d", rm, rn);
		break;
	case 2:
		snprintf(buf, bufsiz, "mov.l   @(r0, r%d), r%d", rm, rn);
		break;
	case 3:
		snprintf(buf, bufsiz, "mac.l   @r%d+, r%d+", rm, rn);
		break;
	} /* end of switch (md) */
}

static void
f_10(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	rn, rm, disp;

	rn   = (insn & 0x0f00) >> 8;
	rm   = (insn & 0x00f0) >> 4;
	disp = (insn & 0x000f);
	disp *= 4;

	snprintf(buf, bufsiz, "mov.l   r%d, @(%d, r%d)", rm, disp, rn);
}

static void
f_20(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	rn, rm, md;

	rn   = (insn & 0x0f00) >> 8;
	rm   = (insn & 0x00f0) >> 4;
	md   = (insn & 0x0003);

	switch (md) {
	case 0:
		snprintf(buf, bufsiz, "mov.b   r%d, @r%d", rm, rn);
		break;
	case 1:
		snprintf(buf, bufsiz, "mov.w   r%d, @r%d", rm, rn);
		break;
	case 2:
		snprintf(buf, bufsiz, "mov.l   r%d, @r%d", rm, rn);
		break;
	} /* end of switch (md) */
}

static void
f_24(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	rn, rm, md;

	rn   = (insn & 0x0f00) >> 8;
	rm   = (insn & 0x00f0) >> 4;
	md   = (insn & 0x0003);

	switch (md) {
	case 0:
		snprintf(buf, bufsiz, "mov.b   r%d, @-r%d", rm, rn);
		break;
	case 1:
		snprintf(buf, bufsiz, "mov.w   r%d, @-r%d", rm, rn);
		break;
	case 2:
		snprintf(buf, bufsiz, "mov.l   r%d, @-r%d", rm, rn);
		break;
	case 3:
		snprintf(buf, bufsiz, "div0s   r%d, r%d", rm, rn);
		break;
	} /* end of switch (md) */
}

static void
f_28(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	rn, rm, md;

	rn   = (insn & 0x0f00) >> 8;
	rm   = (insn & 0x00f0) >> 4;
	md   = (insn & 0x0003);

	switch (md) {
	case 0:
		snprintf(buf, bufsiz, "tst     r%d, r%d", rm, rn);
		break;
	case 1:
		snprintf(buf, bufsiz, "and     r%d, r%d", rm, rn);
		break;
	case 2:
		snprintf(buf, bufsiz, "xor     r%d, r%d", rm, rn);
		break;
	case 3:
		snprintf(buf, bufsiz, "or      r%d, r%d", rm, rn);
		break;
	} /* end of switch (md) */
}

static void
f_2c(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	rn, rm, md;

	rn   = (insn & 0x0f00) >> 8;
	rm   = (insn & 0x00f0) >> 4;
	md   = (insn & 0x0003);

	switch (md) {
	case 0:
		snprintf(buf, bufsiz, "cmp/str r%d, r%d", rm, rn);
		break;
	case 1:
		snprintf(buf, bufsiz, "xtrct   r%d, r%d", rm, rn);
		break;
	case 2:
		snprintf(buf, bufsiz, "mulu.w  r%d, r%d", rm, rn);
		break;
	case 3:
		snprintf(buf, bufsiz, "muls.w  r%d, r%d", rm, rn);
		break;
	} /* end of switch (md) */
}

static void
f_30(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	rn, rm, md;

	rn   = (insn & 0x0f00) >> 8;
	rm   = (insn & 0x00f0) >> 4;
	md   = (insn & 0x0003);

	switch (md) {
	case 0:
		snprintf(buf, bufsiz, "cmp/eq  r%d, r%d", rm, rn);
		break;
	case 2:
		snprintf(buf, bufsiz, "cmp/hs  r%d, r%d", rm, rn);
		break;
	case 3:
		snprintf(buf, bufsiz, "cmp/ge  r%d, r%d", rm, rn);
		break;
	} /* end of switch (md) */
}

static void
f_34(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	rn, rm, md;

	rn   = (insn & 0x0f00) >> 8;
	rm   = (insn & 0x00f0) >> 4;
	md   = (insn & 0x0003);

	switch (md) {
	case 0:
		snprintf(buf, bufsiz, "div1    r%d, r%d", rm, rn);
		break;
	case 1:
		snprintf(buf, bufsiz, "dmulu.l r%d, r%d", rm, rn);
		break;
	case 2:
		snprintf(buf, bufsiz, "cmp/hi  r%d, r%d", rm, rn);
		break;
	case 3:
		snprintf(buf, bufsiz, "cmp/gt  r%d, r%d", rm, rn);
		break;
	} /* end of switch (md) */
}

static void
f_38(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	rn, rm, md;

	rn   = (insn & 0x0f00) >> 8;
	rm   = (insn & 0x00f0) >> 4;
	md   = (insn & 0x0003);

	switch (md) {
	case 0:
		snprintf(buf, bufsiz, "sub     r%d, r%d", rm, rn);
		break;
	case 2:
		snprintf(buf, bufsiz, "subc    r%d, r%d", rm, rn);
		break;
	case 3:
		snprintf(buf, bufsiz, "subv    r%d, r%d", rm, rn);
		break;
	} /* end of switch (md) */
}

static void
f_3c(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	rn, rm, md;

	rn   = (insn & 0x0f00) >> 8;
	rm   = (insn & 0x00f0) >> 4;
	md   = (insn & 0x0003);

	switch (md) {
	case 0:
		snprintf(buf, bufsiz, "add     r%d, r%d", rm, rn);
		break;
	case 1:
		snprintf(buf, bufsiz, "dmulu.l r%d, r%d", rm, rn);
		break;
	case 2:
		snprintf(buf, bufsiz, "addc    r%d, r%d", rm, rn);
		break;
	case 3:
		snprintf(buf, bufsiz, "addv    r%d, r%d", rm, rn);
		break;
	} /* end of switch (md) */
}

static void
f_40(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	rn, fx;

	rn   = (insn & 0x0f00) >> 8;
	fx   = (insn & 0x00f0) >> 4;

	switch (fx) {
	case 0:
		snprintf(buf, bufsiz, "shll    r%d", rn);
		break;
	case 1:
		snprintf(buf, bufsiz, "dt      r%d", rn);
		break;
	case 2:
		snprintf(buf, bufsiz, "shal    r%d", rn);
		break;
	} /* end of switch (fx) */
}

static void
f_41(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	rn, fx;

	rn   = (insn & 0x0f00) >> 8;
	fx   = (insn & 0x00f0) >> 4;

	switch (fx) {
	case 0:
		snprintf(buf, bufsiz, "shlr    r%d", rn);
		break;
	case 1:
		snprintf(buf, bufsiz, "cmp/pz  r%d", rn);
		break;
	case 2:
		snprintf(buf, bufsiz, "shar    r%d", rn);
		break;
	} /* end of switch (fx) */
}

static void
f_42(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	rn, type, md;

	rn   = (insn & 0x0f00) >> 8;
	type = (insn & 0x00c0) >> 6;
	md   = (insn & 0x0030) >> 4;

	switch (type) {
	case 0:
		switch (md) {
		case 0:
			snprintf(buf, bufsiz, "sts.l   mach, @-r%d", rn);
			break;
		case 1:
			snprintf(buf, bufsiz, "sts.l   macl, @-r%d", rn);
			break;
		case 2:
			snprintf(buf, bufsiz, "sts.l   pr, @-r%d", rn);
			break;
		}
		break;
	case 1:
		switch (md) {
		case 1:
			snprintf(buf, bufsiz, "sts.l   fpul, @-r%d", rn);
			break;
		case 2:
			snprintf(buf, bufsiz, "sts.l   fpscr, @-r%d", rn);
			break;
		}
		break;
	} /* end of switch (type) */
}

static void
f_43(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	rn, type, md;

	rn   = (insn & 0x0f00) >> 8;
	type = (insn & 0x00c0) >> 6;
	md   = (insn & 0x0030) >> 4;

	switch (type) {
	case 0:
		switch (md) {
		case 0:
			snprintf(buf, bufsiz, "stc.l   sr, @-r%d", rn);
			break;
		case 1:
			snprintf(buf, bufsiz, "stc.l   gbr, @-r%d", rn);
			break;
		case 2:
			snprintf(buf, bufsiz, "stc.l   vbr, @-r%d", rn);
			break;
		case 3:
			snprintf(buf, bufsiz, "stc.l   ssr, @-r%d", rn);
			break;
		}
		break;
	case 1:
		switch (md) {
		case 0:
			snprintf(buf, bufsiz, "stc.l   spc, @-r%d", rn);
			break;
		}
		break;
	case 2:
		snprintf(buf, bufsiz, "stc.l   r%d_bank, @-r%d", md, rn);
		break;
	case 3:
		snprintf(buf, bufsiz, "stc.l   r%d_bank, @-r%d", md + 4, rn);
		break;
	} /* end of switch (type) */
}

static void
f_44(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	rn, fx;

	rn   = (insn & 0x0f00) >> 8;
	fx   = (insn & 0x00f0) >> 4;

	switch (fx) {
	case 0:
		snprintf(buf, bufsiz, "rotl    r%d", rn);
		break;
	case 2:
		snprintf(buf, bufsiz, "rotcl   r%d", rn);
		break;
	} /* end of switch (fx) */
}

static void
f_45(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	rn, fx;

	rn   = (insn & 0x0f00) >> 8;
	fx   = (insn & 0x00f0) >> 4;

	switch (fx) {
	case 0:
		snprintf(buf, bufsiz, "rotr    r%d", rn);
		break;
	case 1:
		snprintf(buf, bufsiz, "cmp/pl  r%d", rn);
		break;
	case 2:
		snprintf(buf, bufsiz, "rotcr   r%d", rn);
		break;
	} /* end of switch (fx) */
}

static void
f_46(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	rm, type, md;

	rm   = (insn & 0x0f00) >> 8;
	type = (insn & 0x00c0) >> 6;
	md   = (insn & 0x0030) >> 4;

	switch (type) {
	case 0:
		switch (md) {
		case 0:
			snprintf(buf, bufsiz, "lds.l   @r%d+, mach", rm);
			break;
		case 1:
			snprintf(buf, bufsiz, "lds.l   @r%d+, macl", rm);
			break;
		case 2:
			snprintf(buf, bufsiz, "lds.l   @r%d+, pr", rm);
			break;
		}
		break;
	case 1:
		switch (md) {
		case 1:
			snprintf(buf, bufsiz, "lds.l   @r%d+, fpul", rm);
			break;
		case 2:
			snprintf(buf, bufsiz, "lds.l   @r%d+, fpscr", rm);
			break;
		}
		break;
	} /* end of switch (type) */
}

static void
f_47(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	rm, type, md;

	rm   = (insn & 0x0f00) >> 8;
	type = (insn & 0x00c0) >> 6;
	md   = (insn & 0x0030) >> 4;

	switch (type) {
	case 0:
		switch (md) {
		case 0:
			snprintf(buf, bufsiz, "ldc.l   @r%d+, sr", rm);
			break;
		case 1:
			snprintf(buf, bufsiz, "ldc.l   @r%d+, gbr", rm);
			break;
		case 2:
			snprintf(buf, bufsiz, "ldc.l   @r%d+, vbr", rm);
			break;
		case 3:
			snprintf(buf, bufsiz, "ldc.l   @r%d+, ssr", rm);
			break;
		}
		break;
	case 1:
		switch (md) {
		case 0:
			snprintf(buf, bufsiz, "ldc.l   @r%d+, spc", rm);
			break;
		}
		break;
	case 2:
		snprintf(buf, bufsiz, "ldc.l   @r%d+, r%d_bank", rm, md);
		break;
	case 3:
		snprintf(buf, bufsiz, "ldc.l   @r%d+, r%d_bank", rm, md + 4);
		break;
	} /* end of switch (type) */
}

static void
f_48(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	rn, fx;

	rn   = (insn & 0x0f00) >> 8;
	fx   = (insn & 0x00f0) >> 4;

	switch (fx) {
	case 0:
		snprintf(buf, bufsiz, "shll2   r%d", rn);
		break;
	case 1:
		snprintf(buf, bufsiz, "shll8   r%d", rn);
		break;
	case 2:
		snprintf(buf, bufsiz, "shll16  r%d", rn);
		break;
	} /* end of switch (fx) */
}

static void
f_49(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	rn, fx;

	rn   = (insn & 0x0f00) >> 8;
	fx   = (insn & 0x00f0) >> 4;

	switch (fx) {
	case 0:
		snprintf(buf, bufsiz, "shlr2   r%d", rn);
		break;
	case 1:
		snprintf(buf, bufsiz, "shlr8   r%d", rn);
		break;
	case 2:
		snprintf(buf, bufsiz, "shlr16  r%d", rn);
		break;
	} /* end of switch (fx) */
}

static void
f_4a(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	rm, type, md;

	rm   = (insn & 0x0f00) >> 8;
	type = (insn & 0x00c0) >> 6;
	md   = (insn & 0x0030) >> 4;

	switch (type) {
	case 0:
		switch (md) {
		case 0:
			snprintf(buf, bufsiz, "lds     r%d, mach", rm);
			break;
		case 1:
			snprintf(buf, bufsiz, "lds     r%d, macl", rm);
			break;
		case 2:
			snprintf(buf, bufsiz, "lds     r%d, pr", rm);
			break;
		}
		break;
	case 1:
		switch (md) {
		case 1:
			snprintf(buf, bufsiz, "lds     r%d, fpul", rm);
			break;
		case 2:
			snprintf(buf, bufsiz, "lds     r%d, fpscr", rm);
			break;
		}
		break;
	} /* end of switch (type) */
}

static void
f_4b(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	rm, fx;

	rm   = (insn & 0x0f00) >> 8;
	fx   = (insn & 0x00f0) >> 4;

	switch (fx) {
	case 0:
		snprintf(buf, bufsiz, "jsr     @r%d", rm);
		break;
	case 1:
		snprintf(buf, bufsiz, "tas.b   @r%d", rm);
		break;
	case 2:
		snprintf(buf, bufsiz, "jmp     @r%d", rm);
		break;
	} /* end of switch (fx) */
}

static void
f_4c(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	rn, rm;

	rn   = (insn & 0x0f00) >> 8;
	rm   = (insn & 0x00f0) >> 4;
	snprintf(buf, bufsiz, "shad    r%d, r%d", rm, rn);
}

static void
f_4d(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	rn, rm;

	rn   = (insn & 0x0f00) >> 8;
	rm   = (insn & 0x00f0) >> 4;
	snprintf(buf, bufsiz, "shld    r%d, r%d", rm, rn);
}

static void
f_4e(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	rm, type, md;

	rm   = (insn & 0x0f00) >> 8;
	type = (insn & 0x00c0) >> 6;
	md   = (insn & 0x0030) >> 4;

	switch (type) {
	case 0:
		switch (md) {
		case 0:
			snprintf(buf, bufsiz, "ldc     r%d, sr", rm);
			break;
		case 1:
			snprintf(buf, bufsiz, "ldc     r%d, gbr", rm);
			break;
		case 2:
			snprintf(buf, bufsiz, "ldc     r%d, vbr", rm);
			break;
		case 3:
			snprintf(buf, bufsiz, "ldc     r%d, ssr", rm);
			break;
		}
		break;
	case 1:
		switch (md) {
		case 0:
			snprintf(buf, bufsiz, "ldc     r%d, spc", rm);
			break;
		}
		break;
	case 2:
		snprintf(buf, bufsiz, "ldc     r%d, r%d_bank", rm, md);
		break;
	case 3:
		snprintf(buf, bufsiz, "ldc     r%d, r%d_bank", rm, md + 4);
		break;
	} /* end of switch (type) */
}

static void
f_4f(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	rn, rm;

	rn   = (insn & 0x0f00) >> 8;
	rm   = (insn & 0x00f0) >> 4;
	snprintf(buf, bufsiz, "mac.w   @r%d+, @r%d+", rm, rn);
}

static void
f_50(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	rn, rm, disp;

	rn   = (insn & 0x0f00) >> 8;
	rm   = (insn & 0x00f0) >> 4;
	disp = (insn & 0x000f);
	disp *= 4;

	snprintf(buf, bufsiz, "mov.l   @(%d, r%d), r%d", disp, rm, rn);
}

static void
f_60(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	rn, rm, md;

	rn   = (insn & 0x0f00) >> 8;
	rm   = (insn & 0x00f0) >> 4;
	md   = (insn & 0x0003);

	switch (md) {
	case 0:
		snprintf(buf, bufsiz, "mov.b   @r%d, r%d", rm, rn);
		break;
	case 1:
		snprintf(buf, bufsiz, "mov.w   @r%d, r%d", rm, rn);
		break;
	case 2:
		snprintf(buf, bufsiz, "mov.l   @r%d, r%d", rm, rn);
		break;
	case 3:
		snprintf(buf, bufsiz, "mov     r%d, r%d", rm, rn);
		break;
	} /* end of switch (md) */
}

static void
f_64(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	rn, rm, md;

	rn   = (insn & 0x0f00) >> 8;
	rm   = (insn & 0x00f0) >> 4;
	md   = (insn & 0x0003);

	switch (md) {
	case 0:
		snprintf(buf, bufsiz, "mov.b   @r%d+, r%d", rm, rn);
		break;
	case 1:
		snprintf(buf, bufsiz, "mov.w   @r%d+, r%d", rm, rn);
		break;
	case 2:
		snprintf(buf, bufsiz, "mov.l   @r%d+, r%d", rm, rn);
		break;
	case 3:
		snprintf(buf, bufsiz, "not     r%d, r%d", rm, rn);
		break;
	} /* end of switch (md) */
}

static void
f_68(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	rn, rm, md;

	rn   = (insn & 0x0f00) >> 8;
	rm   = (insn & 0x00f0) >> 4;
	md   = (insn & 0x0003);

	switch (md) {
	case 0:
		snprintf(buf, bufsiz, "swap.b  r%d, r%d", rm, rn);
		break;
	case 1:
		snprintf(buf, bufsiz, "swap.w  r%d, r%d", rm, rn);
		break;
	case 2:
		snprintf(buf, bufsiz, "negc    r%d, r%d", rm, rn);
		break;
	case 3:
		snprintf(buf, bufsiz, "neg     r%d, r%d", rm, rn);
		break;
	} /* end of switch (md) */
}

static void
f_6c(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	rn, rm, md;

	rn   = (insn & 0x0f00) >> 8;
	rm   = (insn & 0x00f0) >> 4;
	md   = (insn & 0x0003);

	switch (md) {
	case 0:
		snprintf(buf, bufsiz, "extu.b  r%d, r%d", rm, rn);
		break;
	case 1:
		snprintf(buf, bufsiz, "extu.w  r%d, r%d", rm, rn);
		break;
	case 2:
		snprintf(buf, bufsiz, "exts.b  r%d, r%d", rm, rn);
		break;
	case 3:
		snprintf(buf, bufsiz, "exts.w  r%d, r%d", rm, rn);
		break;
	} /* end of switch (md) */
}

static void
f_70(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	rn, imm;

	rn   = (insn & 0x0f00) >> 8;
	imm  = (int) ((char) (insn & 0x00ff));

	snprintf(buf, bufsiz, "add     #0x%x, r%d", imm, rn);
}

static void
f_80(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	type, md, rn, disp;

	type = (insn & 0x0c00) >> 10;
	md   = (insn & 0x0300) >> 8;

	switch (type) {
	case 0:
		rn   = (insn & 0x00f0) >> 4;
		disp = (insn & 0x000f);

		switch (md) {
		case 0:
			snprintf(buf, bufsiz, "mov.b   r0, @(%d, r%d)",
			    disp, rn);
			break;
		case 1:
			disp *= 2;
			snprintf(buf, bufsiz, "mov.w   r0, @(%d, r%d)",
			    disp, rn);
			break;
		}
		break;
	case 1:
		rn   = (insn & 0x00f0) >> 4;
		disp = (insn & 0x000f);

		switch (md) {
		case 0:
			snprintf(buf, bufsiz, "mov.b   @(%d, r%d), r0",
			    disp, rn);
			break;
		case 1:
			disp *= 2;
			snprintf(buf, bufsiz, "mov.w   @(%d, r%d), r0",
			    disp, rn);
			break;
		}
		break;
	case 2:
		disp = (insn & 0x00ff);

		switch (md) {
		case 0:
			snprintf(buf, bufsiz, "cmp/eq  #%d, r0", disp);
			break;
		case 1:
			disp = (int) ((char) disp);
			disp *= 2;
			disasm_branch(buf, bufsiz, "bt", loc + 4 + disp);
			break;
		case 3:
			disp = (int) ((char) disp);
			disp *= 2;
			disasm_branch(buf, bufsiz, "bf", loc + 4 + disp);
			break;
		}
		break;
	case 3:
		disp = (int) ((char) (insn & 0x00ff));
		disp *= 2;

		switch (md) {
		case 1:
			disasm_branch(buf, bufsiz, "bt/s", loc + 4 + disp);
			break;
		case 3:
			disasm_branch(buf, bufsiz, "bf/s", loc + 4 + disp);
			break;
		}
		break;
	} /* end of switch (type) */
}

static void
f_90(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	rn, disp;

	rn   = (insn & 0x0f00) >> 8;
	disp = (insn & 0x00ff);
	disp *= 2;

	snprintf(buf, bufsiz, "mov.w   @(%d, pc), r%d", disp, rn);
}

static void
f_a0(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	disp;

	disp = (insn & 0x0fff);
	if (disp & 0x0800)	/* negative displacement? */
		disp |= 0xfffff000; /* sign extend */
	disp *= 2;

	disasm_branch(buf, bufsiz, "bra", loc + 4 + disp);
}

static void
f_b0(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	disp;

	disp = (insn & 0x0fff);
	if (disp & 0x0800)	/* negative displacement? */
		disp |= 0xfffff000; /* sign extend */
	disp *= 2;

	disasm_branch(buf, bufsiz, "bsr", loc + 4 + disp);
}

static void
f_c0(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	type, md, imm;

	type = (insn & 0x0c00) >> 10;
	md   = (insn & 0x0300) >> 8;
	imm  = (insn & 0x00ff);

	switch (type) {
	case 0:
		switch (md) {
		case 0:
			snprintf(buf, bufsiz, "mov.b   r0, @(%d, gbr)", imm);
			break;
		case 1:
			imm *= 2;
			snprintf(buf, bufsiz, "mov.w   r0, @(%d, gbr)", imm);
			break;
		case 2:
			imm *= 4;
			snprintf(buf, bufsiz, "mov.l   r0, @(%d, gbr)", imm);
			break;
		case 3:
			snprintf(buf, bufsiz, "trapa   #%d", imm);
			break;
		}
		break;
	case 1:
		switch (md) {
		case 0:
			snprintf(buf, bufsiz, "mov.b   @(%d, gbr), r0", imm);
			break;
		case 1:
			imm *= 2;
			snprintf(buf, bufsiz, "mov.w   @(%d, gbr), r0", imm);
			break;
		case 2:
			imm *= 4;
			snprintf(buf, bufsiz, "mov.l   @(%d, gbr), r0", imm);
			break;
		case 3:
			imm *= 4;
			snprintf(buf, bufsiz, "mova    @(%d, pc), r0", imm);
			break;
		}
		break;
	case 2:
		switch (md) {
		case 0:
			snprintf(buf, bufsiz, "tst     #%d, r0", imm);
			break;
		case 1:
			snprintf(buf, bufsiz, "and     #%d, r0", imm);
			break;
		case 2:
			snprintf(buf, bufsiz, "xor     #%d, r0", imm);
			break;
		case 3:
			snprintf(buf, bufsiz, "or      #%d, r0", imm);
			break;
		}
		break;
	case 3:
		switch (md) {
		case 0:
			snprintf(buf, bufsiz, "tst.b   #%d, @(r0, gbr)", imm);
			break;
		case 1:
			snprintf(buf, bufsiz, "and.b   #%d, @(r0, gbr)", imm);
			break;
		case 2:
			snprintf(buf, bufsiz, "xor.b   #%d, @(r0, gbr)", imm);
			break;
		case 3:
			snprintf(buf, bufsiz, "or.b    #%d, @(r0, gbr)", imm);
			break;
		}
		break;
	} /* end of switch (type) */
}

static void
f_d0(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	rn, disp;

	rn   = (insn & 0x0f00) >> 8;
	disp = (insn & 0x00ff);
	disp *= 4;

	snprintf(buf, bufsiz, "mov.l   @(%d, pc), r%d", disp, rn);
}

static void
f_e0(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	rn, imm;

	rn   = (insn & 0x0f00) >> 8;
	imm  = (int) ((char) (insn & 0x00ff));

	snprintf(buf, bufsiz, "mov     #0x%x, r%d", imm, rn);
}

static void
f_f0(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	rn, rm, md;

	rn   = (insn & 0x0f00) >> 8;
	rm   = (insn & 0x00f0) >> 4;
	md   = (insn & 0x0003);

	switch (md) {
	case 0:
		snprintf(buf, bufsiz, "fadd    fr%d, fr%d", rm, rn);
		break;
	case 1:
		snprintf(buf, bufsiz, "fsub    fr%d, fr%d", rm, rn);
		break;
	case 2:
		snprintf(buf, bufsiz, "fmul    fr%d, fr%d", rm, rn);
		break;
	case 3:
		snprintf(buf, bufsiz, "fdiv    fr%d, fr%d", rm, rn);
		break;
	} /* end of switch (md) */
}

static void
f_f4(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	rn, rm, md;

	rn   = (insn & 0x0f00) >> 8;
	rm   = (insn & 0x00f0) >> 4;
	md   = (insn & 0x0003);

	switch (md) {
	case 0:
		snprintf(buf, bufsiz, "fcmp/eq fr%d, fr%d", rm, rn);
		break;
	case 1:
		snprintf(buf, bufsiz, "fcmp/gt fr%d, fr%d", rm, rn);
		break;
	case 2:
		snprintf(buf, bufsiz, "fmov.s  @(r0, r%d), fr%d", rm, rn);
		break;
	case 3:
		snprintf(buf, bufsiz, "fmov.s  fr%d, @(r0, r%d)", rm, rn);
		break;
	} /* end of switch (md) */
}

static void
f_f8(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	rn, rm, md;

	rn   = (insn & 0x0f00) >> 8;
	rm   = (insn & 0x00f0) >> 4;
	md   = (insn & 0x0003);

	switch (md) {
	case 0:
		snprintf(buf, bufsiz, "fmov.s  @r%d, fr%d", rm, rn);
		break;
	case 1:
		snprintf(buf, bufsiz, "fmov.s  @r%d+, fr%d", rm, rn);
		break;
	case 2:
		snprintf(buf, bufsiz, "fmov.s  fr%d, @r%d", rm, rn);
		break;
	case 3:
		snprintf(buf, bufsiz, "fmov.s  fr%d, @-r%d", rm, rn);
		break;
	} /* end of switch (md) */
}

static void
f_fc(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	rn, rm;

	rn   = (insn & 0x0f00) >> 8;
	rm   = (insn & 0x00f0) >> 4;

	snprintf(buf, bufsiz, "fmov    fr%d, fr%d", rm, rn);
}

static void
f_fd(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	rn, type, md;

	rn   = (insn & 0x0f00) >> 8;
	type = (insn & 0x00c0) >> 6;
	md   = (insn & 0x0030) >> 4;

	switch (type) {
	case 0:
		switch (md) {
		case 0:
			snprintf(buf, bufsiz, "fsts    fpul, fr%d", rn);
			break;
		case 1:
			snprintf(buf, bufsiz, "flds    fr%d, fpul", rn);
			break;
		case 2:
			snprintf(buf, bufsiz, "float   fpul, fr%d", rn);
			break;
		case 3:
			snprintf(buf, bufsiz, "ftrc    fr%d, fpul", rn);
			break;
		}
		break;
	case 1:
		switch (md) {
		case 0:
			snprintf(buf, bufsiz, "fneg    fr%d", rn);
			break;
		case 1:
			snprintf(buf, bufsiz, "fabs    fr%d", rn);
			break;
		case 2:
			snprintf(buf, bufsiz, "fsqrt   fr%d", rn);
			break;
		}
		break;
	case 2:
		switch (md) {
		case 0:
		case 1:
			snprintf(buf, bufsiz, "fldi%d   fr%d", md, rn);
			break;
		}
		break;
	} /* end of switch (type) */
}

static void
f_fe(db_addr_t loc, u_int insn, char *buf, size_t bufsiz)
{
	int	rn, rm;

	rn   = (insn & 0x0f00) >> 8;
	rm   = (insn & 0x00f0) >> 4;

	snprintf(buf, bufsiz, "fmac    fr0, fr%d, fr%d", rm, rn);
}