code:
/*	$OpenBSD: athnreg.h,v 1.18 2012/06/10 21:23:36 kettenis Exp $	*/

/*-
 * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
 * Copyright (c) 2008-2009 Atheros Communications Inc.
 *
 * Permission to use, copy, modify, and distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

/*
 * MAC registers.
 */
#define AR_CR				0x0008
#define AR_RXDP				0x000c
#define AR_CFG				0x0014
#define AR_RXBP_THRESH			0x0018
#define AR_MIRT				0x0020
#define AR_IER				0x0024
#define AR_TIMT				0x0028
#define AR_RIMT				0x002c
#define AR_TXCFG			0x0030
#define AR_RXCFG			0x0034
#define AR_MIBC				0x0040
#define AR_TOPS				0x0044
#define AR_RXNPTO			0x0048
#define AR_TXNPTO			0x004c
#define AR_RPGTO			0x0050
#define AR_RPCNT			0x0054
#define AR_MACMISC			0x0058
#define AR_DATABUF_SIZE			0x0060
#define AR_GTXTO			0x0064
#define AR_GTTM				0x0068
#define AR_CST				0x006c
#define AR_HP_RXDP			0x0074
#define AR_LP_RXDP			0x0078
#define AR_ISR				0x0080
#define AR_ISR_S0			0x0084
#define AR_ISR_S1			0x0088
#define AR_ISR_S2			0x008c
#define AR_ISR_S3			0x0090
#define AR_ISR_S4			0x0094
#define AR_ISR_S5			0x0098
#define AR_IMR				0x00a0
#define AR_IMR_S0			0x00a4
#define AR_IMR_S1			0x00a8
#define AR_IMR_S2			0x00ac
#define AR_IMR_S3			0x00b0
#define AR_IMR_S4			0x00b4
#define AR_IMR_S5			0x00b8
#define AR_ISR_RAC			0x00c0
#define AR_ISR_S0_S			0x00c4
#define AR_ISR_S1_S			0x00c8
#define AR_DMADBG(i)			(0x00e0 + (i) * 4)
#define AR_QTXDP(i)			(0x0800 + (i) * 4)
#define AR_Q_STATUS_RING_START		0x0830
#define AR_Q_STATUS_RING_END		0x0834
#define AR_Q_TXE			0x0840
#define AR_Q_TXD			0x0880
#define AR_QCBRCFG(i)			(0x08c0 + (i) * 4)
#define AR_QRDYTIMECFG(i)		(0x0900 + (i) * 4)
#define AR_Q_ONESHOTARM_SC		0x0940
#define AR_Q_ONESHOTARM_CC		0x0980
#define AR_QMISC(i)			(0x09c0 + (i) * 4)
#define AR_QSTS(i)			(0x0a00 + (i) * 4)
#define AR_Q_RDYTIMESHDN		0x0a40
#define AR_Q_DESC_CRCCHK		0x0a44
#define AR_DQCUMASK(i)			(0x1000 + (i) * 4)
#define AR_D_GBL_IFS_SIFS		0x1030
#define AR_D_TXBLK_CMD			0x1038
#define AR_DLCL_IFS(i)			(0x1040 + (i) * 4)
#define AR_D_GBL_IFS_SLOT		0x1070
#define AR_DRETRY_LIMIT(i)		(0x1080 + (i) * 4)
#define AR_D_GBL_IFS_EIFS		0x10b0
#define AR_DCHNTIME(i)			(0x10c0 + (i) * 4)
#define AR_D_GBL_IFS_MISC		0x10f0
#define AR_DMISC(i)			(0x1100 + (i) * 4)
#define AR_D_SEQNUM			0x1140
#define AR_D_FPCTL			0x1230
#define AR_D_TXPSE			0x1270
#define AR_D_TXSLOTMASK			0x12f0
#define AR_MAC_SLEEP			0x1f00
#define AR_CFG_LED			0x1f04
#define AR_EEPROM_OFFSET(i)		(0x2000 + (i) * 4)
#define AR_RC				0x4000
#define AR_WA				0x4004
#define AR_PM_STATE			0x4008
#define AR_PCIE_PM_CTRL			0x4014
#define AR_HOST_TIMEOUT			0x4018
#define AR_EEPROM			0x401c
#define AR_SREV				0x4020
#define AR_AHB_MODE			0x4024
#define AR_INTR_SYNC_CAUSE		0x4028
#define AR_INTR_SYNC_ENABLE		0x402c
#define AR_INTR_ASYNC_MASK		0x4030
#define AR_INTR_SYNC_MASK		0x4034
#define AR_INTR_ASYNC_CAUSE		0x4038
#define AR_INTR_ASYNC_ENABLE		0x403c
#define AR_PCIE_SERDES			0x4040
#define AR_PCIE_SERDES2			0x4044
#define AR_INTR_PRIO_SYNC_ENABLE	0x40c4
#define AR_INTR_PRIO_ASYNC_MASK		0x40c8
#define AR_INTR_PRIO_SYNC_MASK		0x40cc
#define AR_INTR_PRIO_ASYNC_ENABLE	0x40d4
#define AR_RTC_RC			0x7000
#define AR_RTC_XTAL_CONTROL		0x7004
#define AR_RTC_REG_CONTROL0		0x7008
#define AR_RTC_REG_CONTROL1		0x700c
#define AR_RTC_PLL_CONTROL		0x7014
#define AR_RTC_PLL_CONTROL2		0x703c
#define AR_RTC_RESET			0x7040
#define AR_RTC_STATUS 			0x7044
#define AR_RTC_SLEEP_CLK		0x7048
#define AR_RTC_FORCE_WAKE		0x704c
#define AR_RTC_INTR_CAUSE		0x7050
#define AR_RTC_INTR_ENABLE		0x7054
#define AR_RTC_INTR_MASK		0x7058
#define AR_STA_ID0			0x8000
#define AR_STA_ID1			0x8004
#define AR_BSS_ID0			0x8008
#define AR_BSS_ID1			0x800c
#define AR_BCN_RSSI_AVE			0x8010
#define AR_TIME_OUT			0x8014
#define AR_RSSI_THR			0x8018
#define AR_USEC				0x801c
#define AR_RESET_TSF			0x8020
#define AR_MAX_CFP_DUR			0x8038
#define AR_RX_FILTER			0x803c
#define AR_MCAST_FIL0			0x8040
#define AR_MCAST_FIL1			0x8044
#define AR_DIAG_SW			0x8048
#define AR_TSF_L32			0x804c
#define AR_TSF_U32			0x8050
#define AR_TST_ADDAC			0x8054
#define AR_DEF_ANTENNA			0x8058
#define AR_AES_MUTE_MASK0		0x805c
#define AR_AES_MUTE_MASK1		0x8060
#define AR_GATED_CLKS			0x8064
#define AR_OBS_BUS_CTRL			0x8068
#define AR_OBS_BUS_1			0x806c
#define AR_LAST_TSTP			0x8080
#define AR_NAV				0x8084
#define AR_RTS_OK			0x8088
#define AR_RTS_FAIL			0x808c
#define AR_ACK_FAIL			0x8090
#define AR_FCS_FAIL			0x8094
#define AR_BEACON_CNT			0x8098
#define AR_SLEEP1			0x80d4
#define AR_SLEEP2			0x80d8
#define AR_BSSMSKL			0x80e0
#define AR_BSSMSKU			0x80e4
#define AR_TPC				0x80e8
#define AR_TFCNT			0x80ec
#define AR_RFCNT			0x80f0
#define AR_RCCNT			0x80f4
#define AR_CCCNT			0x80f8
#define AR_QUIET1			0x80fc
#define AR_QUIET2			0x8100
#define AR_TSF_PARM			0x8104
#define AR_QOS_NO_ACK			0x8108
#define AR_PHY_ERR			0x810c
#define AR_RXFIFO_CFG			0x8114
#define AR_MIC_QOS_CONTROL		0x8118
#define AR_MIC_QOS_SELECT		0x811c
#define AR_PCU_MISC			0x8120
#define AR_FILT_OFDM			0x8124
#define AR_FILT_CCK			0x8128
#define AR_PHY_ERR_1			0x812c
#define AR_PHY_ERR_MASK_1		0x8130
#define AR_PHY_ERR_2			0x8134
#define AR_PHY_ERR_MASK_2		0x8138
#define AR_TSFOOR_THRESHOLD		0x813c
#define AR_PHY_ERR_EIFS_MASK		0x8144
#define AR_PHY_ERR_3			0x8168
#define AR_PHY_ERR_MASK_3		0x816c
#define AR_BT_COEX_MODE			0x8170
#define AR_BT_COEX_WEIGHT		0x8174
#define AR_BT_COEX_MODE2		0x817c
#define AR_NEXT_NDP2_TIMER(i)		(0x8180 + (i) * 4)
#define AR_NDP2_PERIOD(i)		(0x81a0 + (i) * 4)
#define AR_NDP2_TIMER_MODE		0x81c0
#define AR_TXSIFS			0x81d0
#define AR_TXOP_X			0x81ec
#define AR_TXOP_0_3			0x81f0
#define AR_TXOP_4_7			0x81f4
#define AR_TXOP_8_11			0x81f8
#define AR_TXOP_12_15			0x81fc
#define AR_GEN_TIMER(i)			(0x8200 + (i) * 4)
#define AR_NEXT_TBTT_TIMER		AR_GEN_TIMER(0)
#define AR_NEXT_DMA_BEACON_ALERT	AR_GEN_TIMER(1)
#define AR_NEXT_CFP			AR_GEN_TIMER(2)
#define AR_NEXT_HCF			AR_GEN_TIMER(3)
#define AR_NEXT_TIM			AR_GEN_TIMER(4)
#define AR_NEXT_DTIM			AR_GEN_TIMER(5)
#define AR_NEXT_QUIET_TIMER		AR_GEN_TIMER(6)
#define AR_NEXT_NDP_TIMER		AR_GEN_TIMER(7)
#define AR_BEACON_PERIOD		AR_GEN_TIMER(8)
#define AR_DMA_BEACON_PERIOD		AR_GEN_TIMER(9)
#define AR_SWBA_PERIOD			AR_GEN_TIMER(10)
#define AR_HCF_PERIOD			AR_GEN_TIMER(11)
#define AR_TIM_PERIOD			AR_GEN_TIMER(12)
#define AR_DTIM_PERIOD			AR_GEN_TIMER(13)
#define AR_QUIET_PERIOD			AR_GEN_TIMER(14)
#define AR_NDP_PERIOD			AR_GEN_TIMER(15)
#define AR_TIMER_MODE			0x8240
#define AR_SLP32_MODE			0x8244
#define AR_SLP32_WAKE			0x8248
#define AR_SLP32_INC			0x824c
#define AR_SLP_CNT			0x8250
#define AR_SLP_CYCLE_CNT		0x8254
#define AR_SLP_MIB_CTRL			0x8258
#define AR_WOW_PATTERN_REG		0x825c
#define AR_WOW_COUNT_REG		0x8260
#define AR_MAC_PCU_LOGIC_ANALYZER	0x8264
#define AR_WOW_BCN_EN_REG		0x8270
#define AR_WOW_BCN_TIMO_REG		0x8274
#define AR_WOW_KEEP_ALIVE_TIMO_REG	0x8278
#define AR_WOW_KEEP_ALIVE_REG		0x827c
#define AR_WOW_US_SCALAR_REG		0x8284
#define AR_WOW_KEEP_ALIVE_DELAY_REG	0x8288
#define AR_WOW_PATTERN_MATCH_REG	0x828c
#define AR_WOW_PATTERN_OFF1_REG		0x8290
#define AR_WOW_PATTERN_OFF2_REG		0x8294
#define AR_WOW_EXACT_REG		0x829c
#define AR_2040_MODE			0x8318
#define AR_EXTRCCNT			0x8328
#define AR_SELFGEN_MASK			0x832c
#define AR_PCU_TXBUF_CTRL		0x8340
#define AR_PCU_MISC_MODE2		0x8344
#define AR_MAC_PCU_ASYNC_FIFO_REG3	0x8358
#define AR_WOW_LENGTH1_REG		0x8360
#define AR_WOW_LENGTH2_REG		0x8364
#define AR_WOW_PATTERN_MATCH_LT_256B	0x8368
#define AR_RATE_DURATION(i)		(0x8700 + (i) * 4)
#define AR_KEYTABLE(i)			(0x8800 + (i) * 32)
#define AR_KEYTABLE_KEY0(i)		(AR_KEYTABLE(i) +  0)
#define AR_KEYTABLE_KEY1(i)		(AR_KEYTABLE(i) +  4)
#define AR_KEYTABLE_KEY2(i)		(AR_KEYTABLE(i) +  8)
#define AR_KEYTABLE_KEY3(i)		(AR_KEYTABLE(i) + 12)
#define AR_KEYTABLE_KEY4(i)		(AR_KEYTABLE(i) + 16)
#define AR_KEYTABLE_TYPE(i)		(AR_KEYTABLE(i) + 20)
#define AR_KEYTABLE_MAC0(i)		(AR_KEYTABLE(i) + 24)
#define AR_KEYTABLE_MAC1(i)		(AR_KEYTABLE(i) + 28)

/* Bits for AR_CR. */
#define AR_CR_RXE	0x00000004
#define AR_CR_RXD	0x00000020
#define AR_CR_SWI	0x00000040

/* Bits for AR_CFG. */
#define AR_CFG_SWTD				0x00000001
#define AR_CFG_SWTB				0x00000002
#define AR_CFG_SWRD				0x00000004
#define AR_CFG_SWRB				0x00000008
#define AR_CFG_SWRG				0x00000010
#define AR_CFG_AP_ADHOC_INDICATION		0x00000020
#define AR_CFG_PHOK				0x00000100
#define AR_CFG_EEBS				0x00000200
#define AR_CFG_CLK_GATE_DIS			0x00000400
#define AR_CFG_PCI_MASTER_REQ_Q_THRESH_M	0x00060000
#define AR_CFG_PCI_MASTER_REQ_Q_THRESH_S	17

/* Bits for AR_RXBP_THRESH. */
#define AR_RXBP_THRESH_HP_M	0x0000000f
#define AR_RXBP_THRESH_HP_S	0
#define AR_RXBP_THRESH_LP_M	0x00003f00
#define AR_RXBP_THRESH_LP_S	8

/* Bits for AR_IER. */
#define AR_IER_ENABLE	0x00000001

/* Bits for AR_TIMT. */
#define AR_TIMT_LAST_M	0x0000ffff
#define AR_TIMT_LAST_S	0
#define AR_TIMT_FIRST_M	0xffff0000
#define AR_TIMT_FIRST_S	16

/* Bits for AR_RIMT. */
#define AR_RIMT_LAST_M	0x0000ffff
#define AR_RIMT_LAST_S	0
#define AR_RIMT_FIRST_M	0xffff0000
#define AR_RIMT_FIRST_S	16

/* Bits for AR_[TR]XCFG_DMASZ fields. */
#define AR_DMASZ_4B	0
#define AR_DMASZ_8B	1
#define AR_DMASZ_16B	2
#define AR_DMASZ_32B	3
#define AR_DMASZ_64B	4
#define AR_DMASZ_128B	5
#define AR_DMASZ_256B	6
#define AR_DMASZ_512B	7

/* Bits for AR_TXCFG. */
#define AR_TXCFG_DMASZ_M			0x00000007
#define AR_TXCFG_DMASZ_S			0
#define AR_TXCFG_FTRIG_M			0x000003f0
#define AR_TXCFG_FTRIG_S			4
#define AR_TXCFG_FTRIG_IMMED			(  0 / 64)
#define AR_TXCFG_FTRIG_64B			( 64 / 64)
#define AR_TXCFG_FTRIG_128B			(128 / 64)
#define AR_TXCFG_FTRIG_192B			(192 / 64)
#define AR_TXCFG_FTRIG_256B			(256 / 64)
#define AR_TXCFG_FTRIG_512B			(512 / 64)
#define AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY	0x00000800

/* Bits for AR_RXCFG. */
#define AR_RXCFG_DMASZ_M	0x00000007
#define AR_RXCFG_DMASZ_S	0
#define AR_RXCFG_CHIRP		0x00000008
#define AR_RXCFG_ZLFDMA		0x00000010

/* Bits for AR_MIBC. */
#define AR_MIBC_COW	0x00000001
#define AR_MIBC_FMC	0x00000002
#define AR_MIBC_CMC	0x00000004
#define AR_MIBC_MCS	0x00000008

/* Bits for AR_TOPS. */
#define AR_TOPS_MASK	0x0000ffff

/* Bits for AR_RXNPTO. */
#define AR_RXNPTO_MASK	0x000003ff

/* Bits for AR_TXNPTO. */
#define AR_TXNPTO_MASK		0x000003ff
#define AR_TXNPTO_QCU_MASK	0x000ffc00

/* Bits for AR_RPGTO. */
#define AR_RPGTO_MASK	0x000003ff

/* Bits for AR_RPCNT. */
#define AR_RPCNT_MASK	0x0000001f

/* Bits for AR_MACMISC. */
#define AR_MACMISC_PCI_EXT_FORCE	0x00000010
#define AR_MACMISC_DMA_OBS_M		0x000001e0
#define AR_MACMISC_DMA_OBS_S		5
#define AR_MACMISC_MISC_OBS_M		0x00000e00
#define AR_MACMISC_MISC_OBS_S		9
#define AR_MACMISC_MISC_OBS_BUS_LSB_M	0x00007000
#define AR_MACMISC_MISC_OBS_BUS_LSB_S	12
#define AR_MACMISC_MISC_OBS_BUS_MSB_M	0x00038000
#define AR_MACMISC_MISC_OBS_BUS_MSB_S	15

/* Bits for AR_GTXTO. */
#define AR_GTXTO_TIMEOUT_COUNTER_M	0x0000ffff
#define AR_GTXTO_TIMEOUT_COUNTER_S	0
#define AR_GTXTO_TIMEOUT_LIMIT_M	0xffff0000
#define AR_GTXTO_TIMEOUT_LIMIT_S	16

/* Bits for AR_GTTM. */
#define AR_GTTM_USEC		0x00000001
#define AR_GTTM_IGNORE_IDLE	0x00000002
#define AR_GTTM_RESET_IDLE	0x00000004
#define AR_GTTM_CST_USEC	0x00000008

/* Bits for AR_CST. */
#define AR_CST_TIMEOUT_COUNTER_M	0x0000ffff
#define AR_CST_TIMEOUT_COUNTER_S	0
#define AR_CST_TIMEOUT_LIMIT_M		0xffff0000
#define AR_CST_TIMEOUT_LIMIT_S		16

/* Bits for AR_ISR. */
#define AR_ISR_RXOK	0x00000001
#define AR_ISR_HP_RXOK	0x00000001
#define AR_ISR_RXDESC	0x00000002
#define AR_ISR_LP_RXOK	0x00000002
#define AR_ISR_RXERR	0x00000004
#define AR_ISR_RXNOPKT	0x00000008
#define AR_ISR_RXEOL	0x00000010
#define AR_ISR_RXORN	0x00000020
#define AR_ISR_TXOK	0x00000040
#define AR_ISR_TXDESC	0x00000080
#define AR_ISR_TXERR	0x00000100
#define AR_ISR_TXNOPKT	0x00000200
#define AR_ISR_TXEOL	0x00000400
#define AR_ISR_TXURN	0x00000800
#define AR_ISR_MIB	0x00001000
#define AR_ISR_SWI	0x00002000
#define AR_ISR_RXPHY	0x00004000
#define AR_ISR_RXKCM	0x00008000
#define AR_ISR_SWBA	0x00010000
#define AR_ISR_BRSSI	0x00020000
#define AR_ISR_BMISS	0x00040000
#define AR_ISR_TXMINTR	0x00080000
#define AR_ISR_BNR	0x00100000
#define AR_ISR_RXCHIRP	0x00200000
#define AR_ISR_BCNMISC	0x00800000
#define AR_ISR_TIM	0x00800000
#define AR_ISR_RXMINTR	0x01000000
#define AR_ISR_QCBROVF	0x02000000
#define AR_ISR_QCBRURN	0x04000000
#define AR_ISR_QTRIG	0x08000000
#define AR_ISR_GENTMR	0x10000000
#define AR_ISR_TXINTM	0x40000000
#define AR_ISR_RXINTM	0x80000000

/* Bits for AR_ISR_S0. */
#define AR_ISR_S0_QCU_TXOK_M	0x000003ff
#define AR_ISR_S0_QCU_TXOK_S	0
#define AR_ISR_S0_QCU_TXDESC_M	0x03ff0000
#define AR_ISR_S0_QCU_TXDESC_S	16

/* Bits for AR_ISR_S1. */
#define AR_ISR_S1_QCU_TXERR_M	0x000003ff
#define AR_ISR_S1_QCU_TXERR_S	0
#define AR_ISR_S1_QCU_TXEOL_M	0x03ff0000
#define AR_ISR_S1_QCU_TXEOL_S	16

/* Bits for AR_ISR_S2. */
#define AR_ISR_S2_QCU_TXURN_M		0x000003ff
#define AR_ISR_S2_QCU_TXURN_S		0
#define AR_ISR_S2_BB_WATCHDOG		0x00010000
#define AR_ISR_S2_CST			0x00400000
#define AR_ISR_S2_GTT			0x00800000
#define AR_ISR_S2_TIM			0x01000000
#define AR_ISR_S2_CABEND		0x02000000
#define AR_ISR_S2_DTIMSYNC		0x04000000
#define AR_ISR_S2_BCNTO			0x08000000
#define AR_ISR_S2_CABTO			0x10000000
#define AR_ISR_S2_DTIM			0x20000000
#define AR_ISR_S2_TSFOOR		0x40000000
#define AR_ISR_S2_TBTT_TIME		0x80000000

/* Bits for AR_ISR_S3. */
#define AR_ISR_S3_QCU_QCBROVF_M	0x000003ff
#define AR_ISR_S3_QCU_QCBROVF_S	0
#define AR_ISR_S3_QCU_QCBRURN_M	0x03ff0000
#define AR_ISR_S3_QCU_QCBRURN_S	0

/* Bits for  AR_ISR_S4. */
#define AR_ISR_S4_QCU_QTRIG_M	0x000003ff
#define AR_ISR_S4_QCU_QTRIG_S	0

/* Bits for AR_ISR_S5. */
#define AR_ISR_S5_TIMER_TRIG_M		0x000000ff
#define AR_ISR_S5_TIMER_TRIG_S		0
#define AR_ISR_S5_TIMER_THRESH_M	0x0007fe00
#define AR_ISR_S5_TIMER_THRESH_S	9
#define AR_ISR_S5_TIM_TIMER		0x00000010
#define AR_ISR_S5_DTIM_TIMER		0x00000020
#define AR_ISR_S5_GENTIMER_TRIG_M	0x0000ff80
#define AR_ISR_S5_GENTIMER_TRIG_S	0
#define AR_ISR_S5_GENTIMER_THRESH_M	0xff800000
#define AR_ISR_S5_GENTIMER_THRESH_S	16

/* Bits for AR_IMR. */
#define AR_IMR_RXOK	0x00000001
#define AR_IMR_HP_RXOK	0x00000001
#define AR_IMR_RXDESC	0x00000002
#define AR_IMR_LP_RXOK	0x00000002
#define AR_IMR_RXERR	0x00000004
#define AR_IMR_RXNOPKT	0x00000008
#define AR_IMR_RXEOL	0x00000010
#define AR_IMR_RXORN	0x00000020
#define AR_IMR_TXOK	0x00000040
#define AR_IMR_TXDESC	0x00000080
#define AR_IMR_TXERR	0x00000100
#define AR_IMR_TXNOPKT	0x00000200
#define AR_IMR_TXEOL	0x00000400
#define AR_IMR_TXURN	0x00000800
#define AR_IMR_MIB	0x00001000
#define AR_IMR_SWI	0x00002000
#define AR_IMR_RXPHY	0x00004000
#define AR_IMR_RXKCM	0x00008000
#define AR_IMR_SWBA	0x00010000
#define AR_IMR_BRSSI	0x00020000
#define AR_IMR_BMISS	0x00040000
#define AR_IMR_TXMINTR	0x00080000
#define AR_IMR_BNR	0x00100000
#define AR_IMR_RXCHIRP	0x00200000
#define AR_IMR_BCNMISC	0x00800000
#define AR_IMR_TIM	0x00800000
#define AR_IMR_RXMINTR	0x01000000
#define AR_IMR_QCBROVF	0x02000000
#define AR_IMR_QCBRURN	0x04000000
#define AR_IMR_QTRIG	0x08000000
#define AR_IMR_GENTMR	0x10000000
#define AR_IMR_TXINTM	0x40000000
#define AR_IMR_RXINTM	0x80000000

#define AR_IMR_DEFAULT	\
	(AR_IMR_TXERR | AR_IMR_TXURN | AR_IMR_RXERR |	\
	 AR_IMR_RXORN | AR_IMR_BCNMISC | AR_IMR_RXINTM |	\
	 AR_IMR_RXMINTR | AR_IMR_TXOK)
#define AR_IMR_HOSTAP	(AR_IMR_DEFAULT | AR_IMR_MIB)

/* Bits for AR_IMR_S0. */
#define AR_IMR_S0_QCU_TXOK(qid)		(1 << (qid))
#define AR_IMR_S0_QCU_TXDESC(qid)	(1 << (16 + (qid)))

/* Bits for AR_IMR_S1. */
#define AR_IMR_S1_QCU_TXERR(qid)	(1 << (qid))
#define AR_IMR_S1_QCU_TXEOL(qid)	(1 << (16 + (qid)))

/* Bits for AR_IMR_S2. */
#define AR_IMR_S2_QCU_TXURN(qid)	(1 << (qid))
#define AR_IMR_S2_CST			0x00400000
#define AR_IMR_S2_GTT			0x00800000
#define AR_IMR_S2_TIM			0x01000000
#define AR_IMR_S2_CABEND		0x02000000
#define AR_IMR_S2_DTIMSYNC		0x04000000
#define AR_IMR_S2_BCNTO			0x08000000
#define AR_IMR_S2_CABTO			0x10000000
#define AR_IMR_S2_DTIM			0x20000000
#define AR_IMR_S2_TSFOOR		0x40000000

/* Bits for AR_IMR_S3. */
#define AR_IMR_S3_QCU_QCBROVF(qid)	(1 << (qid))
#define AR_IMR_S3_QCU_QCBRURN(qid)	(1 << (16 + (qid)))

/* Bits for AR_IMR_S4. */
#define AR_IMR_S4_QCU_QTRIG(qid)	(1 << (qid))

/* Bits for AR_IMR_S5. */
#define AR_IMR_S5_TIM_TIMER		0x00000010
#define AR_IMR_S5_DTIM_TIMER		0x00000020
#define AR_IMR_S5_TIMER_TRIG_M		0x000000ff
#define AR_IMR_S5_TIMER_TRIG_S		0
#define AR_IMR_S5_TIMER_THRESH_M	0x0000ff00
#define AR_IMR_S5_TIMER_THRESH_S	0

#define AR_NUM_QCU	10
#define AR_QCU(x)	(1 << (x))

/* Bits for AR_Q_TXE. */
#define AR_Q_TXE_M	0x000003ff
#define AR_Q_TXE_S	0

/* Bits for AR_Q_TXD. */
#define AR_Q_TXD_M	0x000003ff
#define AR_Q_TXD_S	0

/* Bits for AR_QCBRCFG_*. */
#define AR_Q_CBRCFG_INTERVAL_M		0x00ffffff
#define AR_Q_CBRCFG_INTERVAL_S		0
#define AR_Q_CBRCFG_OVF_THRESH_M	0xff000000
#define AR_Q_CBRCFG_OVF_THRESH_S	24

/* Bits for AR_QRDYTIMECFG_*. */
#define AR_Q_RDYTIMECFG_DURATION_M	0x00ffffff
#define AR_Q_RDYTIMECFG_DURATION_S	0
#define AR_Q_RDYTIMECFG_EN		0x01000000

/* Bits for AR_QMISC_*. */
#define AR_Q_MISC_FSP_M			0x0000000f
#define AR_Q_MISC_FSP_S			0
#define AR_Q_MISC_FSP_ASAP		0
#define AR_Q_MISC_FSP_CBR		1
#define AR_Q_MISC_FSP_DBA_GATED		2
#define AR_Q_MISC_FSP_TIM_GATED		3
#define AR_Q_MISC_FSP_BEACON_SENT_GATED	4
#define AR_Q_MISC_FSP_BEACON_RCVD_GATED	5
#define AR_Q_MISC_ONE_SHOT_EN		0x00000010
#define AR_Q_MISC_CBR_INCR_DIS1		0x00000020
#define AR_Q_MISC_CBR_INCR_DIS0		0x00000040
#define AR_Q_MISC_BEACON_USE		0x00000080
#define AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN	0x00000100
#define AR_Q_MISC_RDYTIME_EXP_POLICY	0x00000200
#define AR_Q_MISC_RESET_CBR_EXP_CTR	0x00000400
#define AR_Q_MISC_DCU_EARLY_TERM_REQ	0x00000800

/* Bits for AR_QSTS_*. */
#define AR_Q_STS_PEND_FR_CNT_M	0x00000003
#define AR_Q_STS_PEND_FR_CNT_S	0
#define AR_Q_STS_CBR_EXP_CNT_M	0x0000ff00
#define AR_Q_STS_CBR_EXP_CNT_S	8

/* Bits for AR_Q_DESC_CRCCHK. */
#define AR_Q_DESC_CRCCHK_EN	0x00000001

#define AR_NUM_DCU	10
#define AR_DCU(x)	(1 << (x))

/* Bits for AR_D_QCUMASK_*. */
#define AR_D_QCUMASK_M	0x000003ff
#define AR_D_QCUMASK_S	0

/* Bits for AR_D_GBL_IFS_SIFS. */
#define AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR	0x000003ab

/* Bits for AR_D_TXBLK_CMD. */
#define AR_D_TXBLK_WRITE_BITMASK_M	0x0000ffff
#define AR_D_TXBLK_WRITE_BITMASK_S	0
#define AR_D_TXBLK_WRITE_SLICE_M	0x000f0000
#define AR_D_TXBLK_WRITE_SLICE_S	16
#define AR_D_TXBLK_WRITE_DCU_M		0x00f00000
#define AR_D_TXBLK_WRITE_DCU_S		20
#define AR_D_TXBLK_WRITE_COMMAND_M	0x0f000000
#define AR_D_TXBLK_WRITE_COMMAND_S	24

/* Bits for AR_DLCL_IFS. */
#define AR_D_LCL_IFS_CWMIN_M	0x000003ff
#define AR_D_LCL_IFS_CWMIN_S	0
#define AR_D_LCL_IFS_CWMAX_M	0x000ffc00
#define AR_D_LCL_IFS_CWMAX_S	10
#define AR_D_LCL_IFS_AIFS_M	0x0ff00000
#define AR_D_LCL_IFS_AIFS_S	20

/* Bits for AR_D_GBL_IFS_SLOT. */
#define AR_D_GBL_IFS_SLOT_M			0x0000ffff
#define AR_D_GBL_IFS_SLOT_S			0
#define AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR	0x00000420

/* Bits for AR_DRETRY_LIMIT_*. */
#define AR_D_RETRY_LIMIT_FR_SH_M	0x0000000f
#define AR_D_RETRY_LIMIT_FR_SH_S	0
#define AR_D_RETRY_LIMIT_STA_SH_M	0x00003f00
#define AR_D_RETRY_LIMIT_STA_SH_S	8
#define AR_D_RETRY_LIMIT_STA_LG_M	0x000fc000
#define AR_D_RETRY_LIMIT_STA_LG_S	14

/* Bits for AR_D_GBL_IFS_EIFS. */
#define AR_D_GBL_IFS_EIFS_M			0x0000ffff
#define AR_D_GBL_IFS_EIFS_S			0
#define AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR	0x0000a5eb

/* Bits for AR_DCHNTIME_*. */
#define AR_D_CHNTIME_DUR_M	0x000fffff
#define AR_D_CHNTIME_DUR_S	0
#define AR_D_CHNTIME_EN		0x00100000

/* Bits for AR_D_GBL_IFS_MISC. */
#define AR_D_GBL_IFS_MISC_LFSR_SLICE_SEL	0x00000007
#define AR_D_GBL_IFS_MISC_TURBO_MODE		0x00000008
#define AR_D_GBL_IFS_MISC_USEC_DURATION		0x000ffc00
#define AR_D_GBL_IFS_MISC_DCU_ARBITER_DLY	0x00300000
#define AR_D_GBL_IFS_MISC_RANDOM_LFSR_SLICE_DIS	0x01000000
#define AR_D_GBL_IFS_MISC_SLOT_XMIT_WIND_LEN	0x06000000
#define AR_D_GBL_IFS_MISC_FORCE_XMIT_SLOT_BOUND	0x08000000
#define AR_D_GBL_IFS_MISC_IGNORE_BACKOFF	0x10000000

/* Bits for AR_DMISC_*. */
#define AR_D_MISC_BKOFF_THRESH_M		0x0000003f
#define AR_D_MISC_BKOFF_THRESH_S		0
#define AR_D_MISC_RETRY_CNT_RESET_EN		0x00000040
#define AR_D_MISC_CW_RESET_EN			0x00000080
#define AR_D_MISC_FRAG_WAIT_EN			0x00000100
#define AR_D_MISC_FRAG_BKOFF_EN			0x00000200
#define AR_D_MISC_CW_BKOFF_EN			0x00001000
#define AR_D_MISC_VIR_COL_HANDLING_M		0x0000c000
#define AR_D_MISC_VIR_COL_HANDLING_S		14
#define AR_D_MISC_VIR_COL_HANDLING_DEFAULT	0
#define AR_D_MISC_VIR_COL_HANDLING_IGNORE	1
#define AR_D_MISC_BEACON_USE			0x00010000
#define AR_D_MISC_ARB_LOCKOUT_CNTRL_M		0x00060000
#define AR_D_MISC_ARB_LOCKOUT_CNTRL_S		17
#define AR_D_MISC_ARB_LOCKOUT_CNTRL_NONE	0
#define AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR	1
#define AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL	2
#define AR_D_MISC_ARB_LOCKOUT_IGNORE		0x00080000
#define AR_D_MISC_SEQ_NUM_INCR_DIS		0x00100000
#define AR_D_MISC_POST_FR_BKOFF_DIS		0x00200000
#define AR_D_MISC_VIT_COL_CW_BKOFF_EN		0x00400000
#define AR_D_MISC_BLOWN_IFS_RETRY_EN		0x00800000

/* Bits for AR_D_FPCTL. */
#define AR_D_FPCTL_DCU_M		0x0000000f
#define AR_D_FPCTL_DCU_S		0
#define AR_D_FPCTL_PREFETCH_EN		0x00000010
#define AR_D_FPCTL_BURST_PREFETCH_M	0x00007fe0
#define AR_D_FPCTL_BURST_PREFETCH_S	5

/* Bits for AR_D_TXPSE. */
#define AR_D_TXPSE_CTRL_M	0x000003ff
#define AR_D_TXPSE_CTRL_S	0
#define AR_D_TXPSE_STATUS	0x00010000

/* Bits for AR_D_TXSLOTMASK. */
#define AR_D_TXSLOTMASK_NUM	0x0000000f

/* Bits for AR_MAC_SLEEP. */
#define AR_MAC_SLEEP_MAC_ASLEEP	0x00000001

/* Bits for AR_CFG_LED. */
#define AR_CFG_SCLK_RATE_IND_M		0x00000003
#define AR_CFG_SCLK_RATE_IND_S		0
#define AR_CFG_SCLK_32MHZ		0
#define AR_CFG_SCLK_4MHZ		1
#define AR_CFG_SCLK_1MHZ		2
#define AR_CFG_SCLK_32KHZ		3
#define AR_CFG_LED_BLINK_SLOW		0x00000008
#define AR_CFG_LED_BLINK_THRESH_SEL_M	0x00000070
#define AR_CFG_LED_BLINK_THRESH_SEL_S	4
#define AR_CFG_LED_MODE_SEL_M		0x00000380
#define AR_CFG_LED_MODE_SEL_S		7
#define AR_CFG_LED_POWER_M		0x00000280
#define AR_CFG_LED_POWER_S		7
#define AR_CFG_LED_NETWORK_M		0x00000300
#define AR_CFG_LED_NETWORK_S		7
#define AR_CFG_LED_MODE_PROP		0
#define AR_CFG_LED_MODE_RPROP		1
#define AR_CFG_LED_MODE_SPLIT		2
#define AR_CFG_LED_MODE_RAND		3
#define AR_CFG_LED_MODE_POWER_OFF	4
#define AR_CFG_LED_MODE_POWER_ON	5
#define AR_CFG_LED_MODE_NETWORK_OFF	4
#define AR_CFG_LED_MODE_NETWORK_ON	6
#define AR_CFG_LED_ASSOC_CTL_M		0x00000c00
#define AR_CFG_LED_ASSOC_CTL_S		10
#define AR_CFG_LED_ASSOC_NONE		0
#define AR_CFG_LED_ASSOC_ACTIVE		1
#define AR_CFG_LED_ASSOC_PENDING	2

/* Bit for AR_RC. */
#define AR_RC_AHB	0x00000001
#define AR_RC_APB	0x00000002
#define AR_RC_HOSTIF	0x00000100

/* Bits for AR_WA. */
#define AR5416_WA_DEFAULT	0x0000073f
#define AR9280_WA_DEFAULT	0x0040073b
#define AR9285_WA_DEFAULT	0x004a050b
#define AR_WA_UNTIE_RESET_EN	0x00008000
#define AR_WA_RESET_EN		0x00040000
#define AR_WA_ANALOG_SHIFT	0x00100000
#define AR_WA_POR_SHORT		0x00200000

/* Bits for AR_PM_STATE. */
#define AR_PM_STATE_PME_D3COLD_VAUX	0x00100000

/* Bits for AR_PCIE_PM_CTRL. */
#define AR_PCIE_PM_CTRL_ENA	0x00080000

/* Bits for AR_HOST_TIMEOUT. */
#define AR_HOST_TIMEOUT_APB_CNTR_M	0x0000ffff
#define AR_HOST_TIMEOUT_APB_CNTR_S	0
#define AR_HOST_TIMEOUT_LCL_CNTR_M	0xffff0000
#define AR_HOST_TIMEOUT_LCL_CNTR_S	16

/* Bits for AR_EEPROM. */
#define AR_EEPROM_ABSENT	0x00000100
#define AR_EEPROM_CORRUPT	0x00000200
#define AR_EEPROM_PROT_MASK_M	0x03fffc00
#define AR_EEPROM_PROT_MASK_S	10

/* Bits for AR_SREV. */
#define AR_SREV_ID_M			0x000000ff
#define AR_SREV_ID_S			0
#define AR_SREV_REVISION_M		0x00000007
#define AR_SREV_REVISION_S		0
#define AR_SREV_VERSION_M		0x000000f0
#define AR_SREV_VERSION_S		4
#define AR_SREV_VERSION2_M		0xfffc0000
#define AR_SREV_VERSION2_S		12		/* XXX Hack. */
#define AR_SREV_TYPE2_M			0x0003f000
#define AR_SREV_TYPE2_S			12
#define AR_SREV_TYPE2_CHAIN		0x00001000
#define AR_SREV_TYPE2_HOST_MODE		0x00002000
#define AR_SREV_REVISION2_M		0x00000f00
#define AR_SREV_REVISION2_S		8
#define AR_SREV_VERSION_5416_PCI	0x00d
#define AR_SREV_VERSION_5416_PCIE	0x00c
#define AR_SREV_REVISION_5416_10	0
#define AR_SREV_REVISION_5416_20	1
#define AR_SREV_REVISION_5416_22	2
#define AR_SREV_VERSION_9100		0x014
#define AR_SREV_VERSION_9160		0x040
#define AR_SREV_REVISION_9160_10	0
#define AR_SREV_REVISION_9160_11	1
#define AR_SREV_VERSION_9280		0x080
#define AR_SREV_REVISION_9280_10	0
#define AR_SREV_REVISION_9280_20	1
#define AR_SREV_REVISION_9280_21	2
#define AR_SREV_VERSION_9285		0x0c0
#define AR_SREV_REVISION_9285_10	0
#define AR_SREV_REVISION_9285_11	1
#define AR_SREV_REVISION_9285_12	2
#define AR_SREV_VERSION_9271		0x140
#define AR_SREV_REVISION_9271_10	0
#define AR_SREV_REVISION_9271_11	1
#define AR_SREV_VERSION_9287		0x180
#define AR_SREV_REVISION_9287_10	0
#define AR_SREV_REVISION_9287_11	1
#define AR_SREV_REVISION_9287_12	2
#define AR_SREV_REVISION_9287_13	3
#define AR_SREV_VERSION_9380		0x1c0
#define AR_SREV_REVISION_9380_10	0
#define AR_SREV_REVISION_9380_20	2
#define AR_SREV_VERSION_9485		0x240
#define AR_SREV_REVISION_9485_10	0

/* Bits for AR_AHB_MODE. */
#define AR_AHB_EXACT_WR_EN			0x00000000
#define AR_AHB_BUF_WR_EN			0x00000001
#define AR_AHB_EXACT_RD_EN			0x00000000
#define AR_AHB_CACHELINE_RD_EN			0x00000002
#define AR_AHB_PREFETCH_RD_EN			0x00000004
#define AR_AHB_PAGE_SIZE_1K			0x00000000
#define AR_AHB_PAGE_SIZE_2K			0x00000008
#define AR_AHB_PAGE_SIZE_4K			0x00000010
#define AR_AHB_CUSTOM_BURST_M			0x000000c0
#define AR_AHB_CUSTOM_BURST_S			6
#define AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL	3

/* Bits for AR_INTR_SYNC_CAUSE. */
#define AR_INTR_SYNC_RTC_IRQ			0x00000001
#define AR_INTR_SYNC_MAC_IRQ			0x00000002
#define AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS	0x00000004
#define AR_INTR_SYNC_APB_TIMEOUT		0x00000008
#define AR_INTR_SYNC_PCI_MODE_CONFLICT		0x00000010
#define AR_INTR_SYNC_HOST1_FATAL		0x00000020
#define AR_INTR_SYNC_HOST1_PERR			0x00000040
#define AR_INTR_SYNC_TRCV_FIFO_PERR		0x00000080
#define AR_INTR_SYNC_RADM_CPL_EP		0x00000100
#define AR_INTR_SYNC_RADM_CPL_DLLP_ABORT	0x00000200
#define AR_INTR_SYNC_RADM_CPL_TLP_ABORT		0x00000400
#define AR_INTR_SYNC_RADM_CPL_ECRC_ERR		0x00000800
#define AR_INTR_SYNC_RADM_CPL_TIMEOUT		0x00001000
#define AR_INTR_SYNC_LOCAL_TIMEOUT		0x00002000
#define AR_INTR_SYNC_PM_ACCESS			0x00004000
#define AR_INTR_SYNC_MAC_AWAKE			0x00008000
#define AR_INTR_SYNC_MAC_ASLEEP			0x00010000
#define AR_INTR_SYNC_MAC_SLEEP_ACCESS		0x00020000
#define AR_INTR_SYNC_ALL			0x0003ffff
#define AR_INTR_SYNC_GPIO_PIN(i)		(1 << (18 + (i)))

#define AR_INTR_SYNC_DEFAULT			\
	(AR_INTR_SYNC_HOST1_FATAL |		\
	 AR_INTR_SYNC_HOST1_PERR |		\
	 AR_INTR_SYNC_RADM_CPL_EP |		\
	 AR_INTR_SYNC_RADM_CPL_DLLP_ABORT |	\
	 AR_INTR_SYNC_RADM_CPL_TLP_ABORT |	\
	 AR_INTR_SYNC_RADM_CPL_ECRC_ERR |	\
	 AR_INTR_SYNC_RADM_CPL_TIMEOUT |	\
	 AR_INTR_SYNC_LOCAL_TIMEOUT |		\
	 AR_INTR_SYNC_MAC_SLEEP_ACCESS)

/* Bits for AR_INTR_ASYNC_CAUSE. */
#define AR_INTR_RTC_IRQ		0x00000001
#define AR_INTR_MAC_IRQ		0x00000002
#define AR_INTR_EEP_PROT_ACCESS	0x00000004
#define AR_INTR_MAC_AWAKE	0x00020000
#define AR_INTR_MAC_ASLEEP	0x00040000
#define AR_INTR_GPIO_PIN(i)	(1 << (18 + (i)))
#define AR_INTR_SPURIOUS	0xffffffff

/* Bits for AR_GPIO_OE_OUT. */
#define AR_GPIO_OE_OUT_DRV_M	0x00000003
#define AR_GPIO_OE_OUT_DRV_S	0
#define AR_GPIO_OE_OUT_DRV_NO	0
#define AR_GPIO_OE_OUT_DRV_LOW	1
#define AR_GPIO_OE_OUT_DRV_HI	2
#define AR_GPIO_OE_OUT_DRV_ALL	3

/* Bits for AR_GPIO_INTR_POL. */
#define AR_GPIO_INTR_POL_PIN(i)		(1 << (i))

/* Bits for AR_GPIO_INPUT_EN_VAL. */
#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF	0x00000004
#define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF	0x00000008
#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_DEF	0x00000010
#define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF	0x00000080
#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB	0x00000400
#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB	0x00001000
#define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB	0x00008000
#define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE	0x00010000
#define AR_GPIO_JTAG_DISABLE			0x00020000

/* Bits for AR_GPIO_INPUT_MUX1. */
#define AR_GPIO_INPUT_MUX1_BT_PRIORITY_M	0x00000f00
#define AR_GPIO_INPUT_MUX1_BT_PRIORITY_S	8
#define AR_GPIO_INPUT_MUX1_BT_ACTIVE_M		0x000f0000
#define AR_GPIO_INPUT_MUX1_BT_ACTIVE_S		16

/* Bits for AR_GPIO_INPUT_MUX2. */
#define AR_GPIO_INPUT_MUX2_CLK25_M		0x0000000f
#define AR_GPIO_INPUT_MUX2_CLK25_S		0
#define AR_GPIO_INPUT_MUX2_RFSILENT_M		0x000000f0
#define AR_GPIO_INPUT_MUX2_RFSILENT_S		4
#define AR_GPIO_INPUT_MUX2_RTC_RESET_M		0x00000f00
#define AR_GPIO_INPUT_MUX2_RTC_RESET_S		8

/* Bits for AR_GPIO_OUTPUT_MUX[1-3]. */
#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT			0
#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED	1
#define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED		2
#define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME			3
#define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL		4
#define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED		5
#define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED		6

/* Bits for AR_EEPROM_STATUS_DATA. */
#define AR_EEPROM_STATUS_DATA_VAL_M		0x0000ffff
#define AR_EEPROM_STATUS_DATA_VAL_S		0
#define AR_EEPROM_STATUS_DATA_BUSY		0x00010000
#define AR_EEPROM_STATUS_DATA_BUSY_ACCESS	0x00020000
#define AR_EEPROM_STATUS_DATA_PROT_ACCESS	0x00040000
#define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS	0x00080000

/* Bits for AR_PCIE_MSI. */
#define AR_PCIE_MSI_ENABLE	0x00000001

/* Bits for AR_RTC_RC. */
#define AR_RTC_RC_MAC_WARM	0x00000001
#define AR_RTC_RC_MAC_COLD	0x00000002
#define AR_RTC_RC_COLD_RESET	0x00000004
#define AR_RTC_RC_WARM_RESET	0x00000008

/* Bits for AR_RTC_REG_CONTROL1. */
#define AR_RTC_REG_CONTROL1_SWREG_PROGRAM	0x00000001

/* Bits for AR_RTC_PLL_CONTROL. */
#define AR_RTC_PLL_DIV_M		0x0000001f
#define AR_RTC_PLL_DIV_S		0
#define AR_RTC_PLL_DIV2			0x00000020
#define AR_RTC_PLL_REFDIV_5		0x000000c0
#define AR_RTC_PLL_CLKSEL_M		0x00000300
#define AR_RTC_PLL_CLKSEL_S		8
#define AR_RTC_9160_PLL_DIV_M		0x000003ff
#define AR_RTC_9160_PLL_DIV_S		0
#define AR_RTC_9160_PLL_REFDIV_M	0x00003c00
#define AR_RTC_9160_PLL_REFDIV_S	10
#define AR_RTC_9160_PLL_CLKSEL_M	0x0000c000
#define AR_RTC_9160_PLL_CLKSEL_S	14

/* Bits for AR_RTC_RESET. */
#define AR_RTC_RESET_EN		0x00000001

/* Bits for AR_RTC_STATUS. */
#define AR_RTC_STATUS_M		0x0000000f
#define AR_RTC_STATUS_S		0
#define AR_RTC_STATUS_SHUTDOWN	0x00000001
#define AR_RTC_STATUS_ON	0x00000002
#define AR_RTC_STATUS_SLEEP	0x00000004
#define AR_RTC_STATUS_WAKEUP	0x00000008

/* Bits for AR_RTC_SLEEP_CLK. */
#define AR_RTC_FORCE_DERIVED_CLK	0x00000002
#define AR_RTC_FORCE_SWREG_PRD		0x00000004

/* Bits for AR_RTC_FORCE_WAKE. */
#define AR_RTC_FORCE_WAKE_EN		0x00000001
#define AR_RTC_FORCE_WAKE_ON_INT	0x00000002

/* Bits for AR_STA_ID1. */
#define AR_STA_ID1_SADH_M		0x0000ffff
#define AR_STA_ID1_SADH_S		0
#define AR_STA_ID1_STA_AP		0x00010000
#define AR_STA_ID1_ADHOC		0x00020000
#define AR_STA_ID1_PWR_SAV		0x00040000
#define AR_STA_ID1_KSRCHDIS		0x00080000
#define AR_STA_ID1_PCF			0x00100000
#define AR_STA_ID1_USE_DEFANT		0x00200000
#define AR_STA_ID1_DEFANT_UPDATE	0x00400000
#define AR_STA_ID1_RTS_USE_DEF		0x00800000
#define AR_STA_ID1_ACKCTS_6MB		0x01000000
#define AR_STA_ID1_BASE_RATE_11B	0x02000000
#define AR_STA_ID1_SECTOR_SELF_GEN	0x04000000
#define AR_STA_ID1_CRPT_MIC_ENABLE	0x08000000
#define AR_STA_ID1_KSRCH_MODE		0x10000000
#define AR_STA_ID1_PRESERVE_SEQNUM	0x20000000
#define AR_STA_ID1_CBCIV_ENDIAN		0x40000000
#define AR_STA_ID1_MCAST_KSRCH		0x80000000

/* Bits for AR_BSS_ID1. */
#define AR_BSS_ID1_U16_M	0x0000ffff
#define AR_BSS_ID1_U16_S	0
#define AR_BSS_ID1_AID_M	0x07ff0000
#define AR_BSS_ID1_AID_S	16

/* Bits for AR_TIME_OUT. */
#define AR_TIME_OUT_ACK_M			0x00003fff
#define AR_TIME_OUT_ACK_S			0
#define AR_TIME_OUT_CTS_M			0x3fff0000
#define AR_TIME_OUT_CTS_S			16
#define AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR	0x16001d56

/* Bits for AR_RSSI_THR. */
#define AR_RSSI_THR_M		0x000000ff
#define AR_RSSI_THR_S		0
#define AR_RSSI_THR_BM_THR_M	0x0000ff00
#define AR_RSSI_THR_BM_THR_S	8
#define AR_RSSI_BCN_WEIGHT_M	0x1f000000
#define AR_RSSI_BCN_WEIGHT_S	24
#define AR_RSSI_BCN_RSSI_RST	0x20000000

/* Bits for AR_USEC. */
#define AR_USEC_USEC_M		0x0000007f
#define AR_USEC_USEC_S		0
#define AR_USEC_TX_LAT_M	0x007fc000
#define AR_USEC_TX_LAT_S	14
#define AR_USEC_RX_LAT_M	0x1f800000
#define AR_USEC_RX_LAT_S	23
#define AR_USEC_ASYNC_FIFO_DUR	0x12e00074

/* Bits for AR_RESET_TSF. */
#define AR_RESET_TSF_ONCE	0x01000000

/* Bits for AR_RX_FILTER. */
#define AR_RX_FILTER_UCAST	0x00000001
#define AR_RX_FILTER_MCAST	0x00000002
#define AR_RX_FILTER_BCAST	0x00000004
#define AR_RX_FILTER_CONTROL	0x00000008
#define AR_RX_FILTER_BEACON	0x00000010
#define AR_RX_FILTER_PROM	0x00000020
#define AR_RX_FILTER_PROBEREQ	0x00000080
#define AR_RX_FILTER_MYBEACON	0x00000200
#define AR_RX_FILTER_COMPR_BAR	0x00000400
#define AR_RX_FILTER_PSPOLL	0x00004000

/* Bits for AR_DIAG_SW. */
#define AR_DIAG_CACHE_ACK		0x00000001
#define AR_DIAG_ACK_DIS			0x00000002
#define AR_DIAG_CTS_DIS			0x00000004
#define AR_DIAG_ENCRYPT_DIS		0x00000008
#define AR_DIAG_DECRYPT_DIS		0x00000010
#define AR_DIAG_RX_DIS			0x00000020
#define AR_DIAG_LOOP_BACK		0x00000040
#define AR_DIAG_CORR_FCS		0x00000080
#define AR_DIAG_CHAN_INFO		0x00000100
#define AR_DIAG_SCRAM_SEED_M		0x0001fe00
#define AR_DIAG_SCRAM_SEED_S		8	/* XXX should be 9? */
#define AR_DIAG_FRAME_NV0		0x00020000
#define AR_DIAG_OBS_PT_SEL1_M		0x000c0000
#define AR_DIAG_OBS_PT_SEL1_S		18
#define AR_DIAG_FORCE_RX_CLEAR		0x00100000
#define AR_DIAG_IGNORE_VIRT_CS		0x00200000
#define AR_DIAG_FORCE_CH_IDLE_HIGH	0x00400000
#define AR_DIAG_EIFS_CTRL_ENA		0x00800000
#define AR_DIAG_DUAL_CHAIN_INFO		0x01000000
#define AR_DIAG_RX_ABORT		0x02000000
#define AR_DIAG_SATURATE_CYCLE_CNT	0x04000000
#define AR_DIAG_OBS_PT_SEL2		0x08000000
#define AR_DIAG_RX_CLEAR_CTL_LOW	0x10000000
#define AR_DIAG_RX_CLEAR_EXT_LOW	0x20000000

/* Bits for AR_AES_MUTE_MASK0. */
#define AR_AES_MUTE_MASK0_FC_M	0x0000ffff
#define AR_AES_MUTE_MASK0_FC_S	0
#define AR_AES_MUTE_MASK0_QOS_M	0xffff0000
#define AR_AES_MUTE_MASK0_QOS_S	16

/* Bits for AR_AES_MUTE_MASK1. */
#define AR_AES_MUTE_MASK1_SEQ_M		0x0000ffff
#define AR_AES_MUTE_MASK1_SEQ_S		0
#define AR_AES_MUTE_MASK1_FC_MGMT_M	0xffff0000
#define AR_AES_MUTE_MASK1_FC_MGMT_S	16
#define AR_AES_MUTE_MASK1_FC0_MGMT_M	0x00ff0000
#define AR_AES_MUTE_MASK1_FC0_MGMT_S	16
#define AR_AES_MUTE_MASK1_FC1_MGMT_M	0xff000000
#define AR_AES_MUTE_MASK1_FC1_MGMT_S	24

/* Bits for AR_GATED_CLKS. */
#define AR_GATED_CLKS_TX	0x00000002
#define AR_GATED_CLKS_RX	0x00000004
#define AR_GATED_CLKS_REG	0x00000008

/* Bits for AR_OBS_BUS_CTRL. */
#define AR_OBS_BUS_SEL_1	0x00040000
#define AR_OBS_BUS_SEL_2	0x00080000
#define AR_OBS_BUS_SEL_3	0x000c0000
#define AR_OBS_BUS_SEL_4	0x08040000
#define AR_OBS_BUS_SEL_5	0x08080000

/* Bits for AR_OBS_BUS_1. */
#define AR_OBS_BUS_1_PCU		0x00000001
#define AR_OBS_BUS_1_RX_END		0x00000002
#define AR_OBS_BUS_1_RX_WEP		0x00000004
#define AR_OBS_BUS_1_RX_BEACON		0x00000008
#define AR_OBS_BUS_1_RX_FILTER		0x00000010
#define AR_OBS_BUS_1_TX_HCF		0x00000020
#define AR_OBS_BUS_1_QUIET_TIME		0x00000040
#define AR_OBS_BUS_1_CHAN_IDLE		0x00000080
#define AR_OBS_BUS_1_TX_HOLD		0x00000100
#define AR_OBS_BUS_1_TX_FRAME		0x00000200
#define AR_OBS_BUS_1_RX_FRAME		0x00000400
#define AR_OBS_BUS_1_RX_CLEAR		0x00000800
#define AR_OBS_BUS_1_WEP_STATE_M	0x0003f000
#define AR_OBS_BUS_1_WEP_STATE_S	12
#define AR_OBS_BUS_1_RX_STATE_M		0x01f00000
#define AR_OBS_BUS_1_RX_STATE_S		20
#define AR_OBS_BUS_1_TX_STATE_M		0x7e000000
#define AR_OBS_BUS_1_TX_STATE_S		25

/* Bits for AR_SLEEP1. */
#define AR_SLEEP1_ASSUME_DTIM		0x00080000
#define AR_SLEEP1_CAB_TIMEOUT_M		0xffe00000
#define AR_SLEEP1_CAB_TIMEOUT_S		21
/* Default value. */
#define AR_CAB_TIMEOUT_VAL		10

/* Bits for AR_SLEEP2. */
#define AR_SLEEP2_BEACON_TIMEOUT_M	0xffe00000
#define AR_SLEEP2_BEACON_TIMEOUT_S	21

/* Bits for AR_TPC. */
#define AR_TPC_ACK_M	0x0000003f
#define AR_TPC_ACK_S	0
#define AR_TPC_CTS_M	0x00003f00
#define AR_TPC_CTS_S	8
#define AR_TPC_CHIRP_M	0x003f0000
#define AR_TPC_CHIRP_S	16

/* Bits for AR_QUIET1. */
#define AR_QUIET1_NEXT_QUIET_M		0x0000ffff
#define AR_QUIET1_NEXT_QUIET_S		0
#define AR_QUIET1_QUIET_ENABLE		0x00010000
#define AR_QUIET1_QUIET_ACK_CTS_ENABLE	0x00020000

/* Bits for AR_QUIET2. */
#define AR_QUIET2_QUIET_PERIOD_M	0x0000ffff
#define AR_QUIET2_QUIET_PERIOD_S	0
#define AR_QUIET2_QUIET_DUR_M		0xffff0000
#define AR_QUIET2_QUIET_DUR_S		16

/* Bits for AR_TSF_PARM. */
#define AR_TSF_INCREMENT_M	0x000000ff
#define AR_TSF_INCREMENT_S	0

/* Bits for AR_QOS_NO_ACK. */
#define AR_QOS_NO_ACK_TWO_BIT_M		0x0000000f
#define AR_QOS_NO_ACK_TWO_BIT_S		0
#define AR_QOS_NO_ACK_BIT_OFF_M		0x0000007f
#define AR_QOS_NO_ACK_BIT_OFF_S		4
#define AR_QOS_NO_ACK_BYTE_OFF_M	0x00000180
#define AR_QOS_NO_ACK_BYTE_OFF_S	7

/* Bits for AR_PHY_ERR. */
#define AR_PHY_ERR_DCHIRP	0x00000008
#define AR_PHY_ERR_RADAR	0x00000020
#define AR_PHY_ERR_OFDM_TIMING	0x00020000
#define AR_PHY_ERR_CCK_TIMING	0x02000000

/* Bits for AR_PCU_MISC. */
#define AR_PCU_FORCE_BSSID_MATCH	0x00000001
#define AR_PCU_MIC_NEW_LOC_ENA		0x00000004
#define AR_PCU_TX_ADD_TSF		0x00000008
#define AR_PCU_CCK_SIFS_MODE		0x00000010
#define AR_PCU_RX_ANT_UPDT		0x00000800
#define AR_PCU_TXOP_TBTT_LIMIT_ENA	0x00001000
#define AR_PCU_MISS_BCN_IN_SLEEP	0x00004000
#define AR_PCU_BUG_12306_FIX_ENA	0x00020000
#define AR_PCU_FORCE_QUIET_COLL		0x00040000
#define AR_PCU_BT_ANT_PREVENT_RX	0x00100000
#define AR_PCU_TBTT_PROTECT		0x00200000
#define AR_PCU_CLEAR_VMF		0x01000000
#define AR_PCU_CLEAR_BA_VALID		0x04000000

/* Bits for AR_BT_COEX_MODE. */
#define AR_BT_TIME_EXTEND_M	0x000000ff
#define AR_BT_TIME_EXTEND_S	0
#define AR_BT_TXSTATE_EXTEND	0x00000100
#define AR_BT_TX_FRAME_EXTEND	0x00000200
#define AR_BT_MODE_M		0x00000c00
#define AR_BT_MODE_S		10
#define AR_BT_MODE_LEGACY	0
#define AR_BT_MODE_UNSLOTTED	1
#define AR_BT_MODE_SLOTTED	2
#define AR_BT_MODE_DISABLED	3
#define AR_BT_QUIET		0x00001000
#define AR_BT_QCU_THRESH_M	0x0001e000
#define AR_BT_QCU_THRESH_S	13
#define AR_BT_RX_CLEAR_POLARITY	0x00020000
#define AR_BT_PRIORITY_TIME_M	0x00fc0000
#define AR_BT_PRIORITY_TIME_S	18
#define AR_BT_FIRST_SLOT_TIME_M	0xff000000
#define AR_BT_FIRST_SLOT_TIME_S	24

/* Bits for AR_BT_COEX_WEIGHT. */
#define AR_BTCOEX_BT_WGHT_M	0x0000ffff
#define AR_BTCOEX_BT_WGHT_S	0
#define AR_STOMP_LOW_BT_WGHT	0xff55
#define AR_BTCOEX_WL_WGHT_M	0xffff0000
#define AR_BTCOEX_WL_WGHT_S	16
#define AR_STOMP_LOW_WL_WGHT	0xaaa8

/* Bits for AR_BT_COEX_MODE2. */
#define AR_BT_BCN_MISS_THRESH_M	0x000000ff
#define AR_BT_BCN_MISS_THRESH_S	0
#define AR_BT_BCN_MISS_CNT_M	0x0000ff00
#define AR_BT_BCN_MISS_CNT_S	8
#define AR_BT_HOLD_RX_CLEAR	0x00010000
#define AR_BT_DISABLE_BT_ANT	0x00100000

/* Bits for AR_PCU_TXBUF_CTRL. */
#define AR_PCU_TXBUF_CTRL_SIZE_M		0x000007ff
#define AR_PCU_TXBUF_CTRL_SIZE_S		0
#define AR_PCU_TXBUF_CTRL_USABLE_SIZE		1792
#define AR9285_PCU_TXBUF_CTRL_USABLE_SIZE	(1792 / 2)

/* Bits for AR_PCU_MISC_MODE2. */
#define AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE		0x00000002
#define AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT	0x00000004
#define AR_PCU_MISC_MODE2_AGG_WEP_ENABLE_FIX		0x00000008
#define AR_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE	0x00000040
#define AR_PCU_MISC_MODE2_CFP_IGNORE			0x00000080
#define AR_PCU_MISC_MODE2_MGMT_QOS_M			0x0000ff00
#define AR_PCU_MISC_MODE2_MGMT_QOS_S			8
#define AR_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DUR	0x00010000
#define AR_PCU_MISC_MODE2_ENABLE_AGGWEP			0x00020000
#define AR_PCU_MISC_MODE2_HWWAR1			0x00100000
#define AR_PCU_MISC_MODE2_HWWAR2			0x02000000

/* Bits for AR_MAC_PCU_LOGIC_ANALYZER. */
#define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768	0x20000000

/* Bits for AR_MAC_PCU_ASYNC_FIFO_REG3. */
#define AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL	0x00000400
#define AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET	0x80000000

/* Bits for AR_PHY_ERR_[123]. */
#define AR_PHY_ERR_COUNT_M	0x00ffffff
#define AR_PHY_ERR_COUNT_S	0

/* Bits for AR_TSFOOR_THRESHOLD. */
#define AR_TSFOOR_THRESHOLD_VAL_M	0x0000ffff
#define AR_TSFOOR_THRESHOLD_VAL_S	0

/* Bit for AR_TXSIFS. */
#define AR_TXSIFS_TIME_M	0x000000ff
#define AR_TXSIFS_TIME_S	0
#define AR_TXSIFS_TX_LATENCY_M	0x00000f00
#define AR_TXSIFS_TX_LATENCY_S	8
#define AR_TXSIFS_ACK_SHIFT_M	0x00007000
#define AR_TXSIFS_ACK_SHIFT_S	12

/* Bits for AR_TXOP_X. */
#define AR_TXOP_X_VAL	0x000000ff

/* Bits for AR_TIMER_MODE. */
#define AR_TBTT_TIMER_EN		0x00000001
#define AR_DBA_TIMER_EN			0x00000002
#define AR_SWBA_TIMER_EN		0x00000004
#define AR_HCF_TIMER_EN			0x00000008
#define AR_TIM_TIMER_EN			0x00000010
#define AR_DTIM_TIMER_EN		0x00000020
#define AR_QUIET_TIMER_EN		0x00000040
#define AR_NDP_TIMER_EN			0x00000080
#define AR_TIMER_OVERFLOW_INDEX_M	0x00000700
#define AR_TIMER_OVERFLOW_INDEX_S	8
#define AR_TIMER_THRESH_M		0xfffff000
#define AR_TIMER_THRESH_S		12

/* Bits for AR_SLP32_MODE. */
#define AR_SLP32_HALF_CLK_LATENCY_M	0x000fffff
#define AR_SLP32_HALF_CLK_LATENCY_S	0
#define AR_SLP32_ENA			0x00100000
#define AR_SLP32_TSF_WRITE_STATUS	0x00200000

/* Bits for AR_SLP32_WAKE. */
#define AR_SLP32_WAKE_XTL_TIME_M	0x0000ffff
#define AR_SLP32_WAKE_XTL_TIME_S	0

/* Bits for AR_SLP_MIB_CTRL. */
#define AR_SLP_MIB_CLEAR	0x00000001
#define AR_SLP_MIB_PENDING	0x00000002

/* Bits for AR_2040_MODE. */
#define AR_2040_JOINED_RX_CLEAR	0x00000001

/* Bits for AR_KEYTABLE_TYPE. */
#define AR_KEYTABLE_TYPE_M	0x00000007
#define AR_KEYTABLE_TYPE_S	0
#define AR_KEYTABLE_TYPE_40	0
#define AR_KEYTABLE_TYPE_104	1
#define AR_KEYTABLE_TYPE_128	3
#define AR_KEYTABLE_TYPE_TKIP	4
#define AR_KEYTABLE_TYPE_AES	5
#define AR_KEYTABLE_TYPE_CCM	6
#define AR_KEYTABLE_TYPE_CLR	7
#define AR_KEYTABLE_ANT		0x00000008
#define AR_KEYTABLE_VALID	0x00008000

/*
 * AR9271 specific registers.
 */
#define AR9271_RESET_POWER_DOWN_CONTROL	0x050044
#define AR9271_FIRMWARE			0x501000
#define AR9271_FIRMWARE_TEXT		0x903000
#define AR7010_FIRMWARE_TEXT		0x906000

/* Bits for AR9271_RESET_POWER_DOWN_CONTROL. */
#define AR9271_RADIO_RF_RST	0x00000020
#define AR9271_GATE_MAC_CTL	0x00004000

#define AR_BASE_PHY_ACTIVE_DELAY	100

#define AR_CLOCK_RATE_CCK		22
#define AR_CLOCK_RATE_5GHZ_OFDM		40
#define AR_CLOCK_RATE_FAST_5GHZ_OFDM	44
#define AR_CLOCK_RATE_2GHZ_OFDM		44

#define AR_PWR_DECREASE_FOR_2_CHAIN	6	/* 10 * log10(2) * 2 */
#define AR_PWR_DECREASE_FOR_3_CHAIN	9	/* 10 * log10(3) * 2 */

#define AR_SLEEP_SLOP	3	/* TUs */

#define AR_MIN_BEACON_TIMEOUT_VAL	1
#define AR_FUDGE			2
#define AR_BEACON_DMA_DELAY		2
#define AR_SWBA_DELAY			10
/* Divides by 1024 (usecs to TU) without doing 64-bit arithmetic. */
#define AR_TSF_TO_TU(hi, lo)	((hi) << 22 | (lo) >> 10)

#define AR_KEY_CACHE_SIZE		128
#define AR_RSVD_KEYTABLE_ENTRIES	4

#define AR_CAL_SAMPLES	64	/* XXX AR9280? */
#define AR_MAX_LOG_CAL	2	/* XXX AR9280? */

/* Maximum number of chains supported by any chipset. */
#define AR_MAX_CHAINS	3

/* Default number of key cache entries. */
#define AR_KEYTABLE_SIZE	128

/* GPIO pins. */
#define AR_GPIO_WLANACTIVE_PIN	5
#define AR_GPIO_BTACTIVE_PIN	6
#define AR_GPIO_BTPRIORITY_PIN	7

#define AR_SREV_5416(sc) \
	((sc)->mac_ver == AR_SREV_VERSION_5416_PCI || \
	 (sc)->mac_ver == AR_SREV_VERSION_5416_PCIE)
#define AR_SREV_5416_20_OR_LATER(sc) \
	((AR_SREV_5416(sc) && \
	  (sc)->mac_rev >= AR_SREV_REVISION_5416_20) || \
	 (sc)->mac_ver >= AR_SREV_VERSION_9100)
#define AR_SREV_5416_22_OR_LATER(sc) \
	((AR_SREV_5416(sc) && \
	  (sc)->mac_rev >= AR_SREV_REVISION_5416_22) || \
	 (sc)->mac_ver >= AR_SREV_VERSION_9100)

#define AR_SREV_9160(sc) \
	((sc)->mac_ver == AR_SREV_VERSION_9160)
#define AR_SREV_9160_10_OR_LATER(sc) \
	((sc)->mac_ver >= AR_SREV_VERSION_9160)
#define AR_SREV_9160_11(sc) \
	(AR_SREV_9160(sc) && \
	 (sc)->mac_rev == AR_SREV_REVISION_9160_11)

#define AR_SREV_9280(sc) \
	((sc)->mac_ver == AR_SREV_VERSION_9280)
#define AR_SREV_9280_10_OR_LATER(sc) \
	((sc)->mac_ver >= AR_SREV_VERSION_9280)
#define AR_SREV_9280_10(sc) \
	(AR_SREV_9280(sc) && \
	 (sc)->mac_rev == AR_SREV_REVISION_9280_10)
#define AR_SREV_9280_20(sc) \
	(AR_SREV_9280(sc) && \
	 (sc)->mac_rev >= AR_SREV_REVISION_9280_20)
#define AR_SREV_9280_20_OR_LATER(sc) \
	((sc)->mac_ver > AR_SREV_VERSION_9280 || \
	 (AR_SREV_9280(sc) && (sc)->mac_rev >= AR_SREV_REVISION_9280_20))

#define AR_SREV_9285(sc) \
	((sc)->mac_ver == AR_SREV_VERSION_9285)
#define AR_SREV_9285_10_OR_LATER(sc) \
	((sc)->mac_ver >= AR_SREV_VERSION_9285)
#define AR_SREV_9285_11(sc) \
	(AR_SREV_9285(sc) && \
	 (sc)->mac_rev == AR_SREV_REVISION_9285_11)
#define AR_SREV_9285_11_OR_LATER(sc) \
	((sc)->mac_ver > AR_SREV_VERSION_9285 || \
	 (AR_SREV_9285(sc) && (sc)->mac_rev >= AR_SREV_REVISION_9285_11))
#define AR_SREV_9285_12(sc) \
	(AR_SREV_9285(sc) && \
	 ((sc)->mac_rev == AR_SREV_REVISION_9285_12))
#define AR_SREV_9285_12_OR_LATER(sc) \
	((sc)->mac_ver > AR_SREV_VERSION_9285 || \
	 (AR_SREV_9285(sc) && (sc)->mac_rev >= AR_SREV_REVISION_9285_12))

#define AR_SREV_9271(sc) \
	((sc)->mac_ver == AR_SREV_VERSION_9271)
#define AR_SREV_9271_10(sc) \
	(AR_SREV_9271(sc) && \
	 (sc)->mac_rev == AR_SREV_REVISION_9271_10)

#define AR_SREV_9287(sc) \
	((sc)->mac_ver == AR_SREV_VERSION_9287)
#define AR_SREV_9287_10_OR_LATER(sc) \
	((sc)->mac_ver >= AR_SREV_VERSION_9287)
#define AR_SREV_9287_10(sc) \
	((sc)->mac_ver == AR_SREV_VERSION_9287 && \
	 (sc)->mac_rev == AR_SREV_REVISION_9287_10)
#define AR_SREV_9287_11(sc) \
	((sc)->mac_ver == AR_SREV_VERSION_9287 && \
	 (sc)->mac_rev == AR_SREV_REVISION_9287_11)
#define AR_SREV_9287_11_OR_LATER(sc) \
	((sc)->mac_ver > AR_SREV_VERSION_9287 || \
	 (AR_SREV_9287(sc) && (sc)->mac_rev >= AR_SREV_REVISION_9287_11))
#define AR_SREV_9287_12(sc) \
	((sc)->mac_ver == AR_SREV_VERSION_9287 && \
	 (sc)->mac_rev == AR_SREV_REVISION_9287_12)
#define AR_SREV_9287_12_OR_LATER(sc) \
	((sc)->mac_ver > AR_SREV_VERSION_9287 || \
	 (AR_SREV_9287(sc) && (sc)->mac_rev >= AR_SREV_REVISION_9287_12))
#define AR_SREV_9287_13_OR_LATER(sc) \
	((sc)->mac_ver > AR_SREV_VERSION_9287 || \
	 (AR_SREV_9287(sc) && (sc)->mac_rev >= AR_SREV_REVISION_9287_13))

#define AR_SREV_9380(sc) \
	((sc)->mac_ver == AR_SREV_VERSION_9380)
#define AR_SREV_9380_10_OR_LATER(sc) \
	((sc)->mac_ver >= AR_SREV_VERSION_9380)
#define AR_SREV_9380_20(sc) \
	(AR_SREV_9380(sc) && \
	 (sc)->mac_rev == AR_SREV_REVISION_9380_20)
#define AR_SREV_9380_20_OR_LATER(sc) \
	((sc)->mac_ver > AR_SREV_VERSION_9380 || \
	 (AR_SREV_9380(sc) && (sc)->mac_rev >= AR_SREV_REVISION_9380_20))

#define AR_SREV_9485(sc) \
	((sc)->mac_ver == AR_SREV_VERSION_9485)

#define AR_SINGLE_CHIP(sc)	AR_SREV_9280_10_OR_LATER(sc)

#define AR_RADIO_SREV_MAJOR	0xf0
#define AR_RAD5133_SREV_MAJOR	0xc0
#define AR_RAD2133_SREV_MAJOR	0xd0
#define AR_RAD5122_SREV_MAJOR	0xe0
#define AR_RAD2122_SREV_MAJOR	0xf0

#define AR_BCHAN_UNUSED		0xff
#define AR_PD_GAINS_IN_MASK	4	/* NB: Max for all chips. */
#define AR_MAX_RATE_POWER	63

#define AR_HT40_POWER_INC_FOR_PDADC	2
#define AR_PWR_TABLE_OFFSET_DB		(-5)
#define AR9280_TX_GAIN_TABLE_SIZE	22
#define AR9003_TX_GAIN_TABLE_SIZE	32
#define AR9003_PAPRD_MEM_TAB_SIZE	24

#define AR_BASE_FREQ_2GHZ	2300
#define AR_BASE_FREQ_5GHZ	4900

#define AR_SD_NO_CTL	0xe0
#define AR_NO_CTL	0xff
#define AR_CTL_MODE_M	0x07
#define AR_CTL_MODE_S	0
#define AR_CTL_11A	0
#define AR_CTL_11B	1
#define AR_CTL_11G	2
#define AR_CTL_2GHT20	5
#define AR_CTL_5GHT20	6
#define AR_CTL_2GHT40	7
#define AR_CTL_5GHT40	8

/*
 * Macros to access registers.
 */
#define AR_READ(sc, reg)						\
	(sc)->ops.read((sc), (reg))

#define AR_WRITE(sc, reg, val)						\
	(sc)->ops.write((sc), (reg), (val))

#define AR_WRITE_BARRIER(sc)						\
	(sc)->ops.write_barrier((sc))

#define AR_SETBITS(sc, reg, mask)					\
	AR_WRITE(sc, reg, AR_READ(sc, reg) | (mask))

#define AR_CLRBITS(sc, reg, mask)					\
	AR_WRITE(sc, reg, AR_READ(sc, reg) & ~(mask))

/*
 * Macros to access subfields in registers.
 */
/* Mask and Shift (getter). */
#define MS(val, field)							\
	(((val) & field##_M) >> field##_S)

/* Shift and Mask (setter). */
#define SM(field, val)							\
	(((val) << field##_S) & field##_M)

/* Rewrite. */
#define RW(var, field, val)						\
	(((var) & ~field##_M) | SM(field, val))


code:
/*	$OpenBSD: athnvar.h,v 1.35 2013/12/06 21:03:02 deraadt Exp $	*/

/*-
 * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
 *
 * Permission to use, copy, modify, and distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#ifdef notyet
#define ATHN_BT_COEXISTENCE	1
#endif

#ifdef ATHN_DEBUG
#define DPRINTF(x)	do { if (athn_debug > 0) printf x; } while (0)
#define DPRINTFN(n, x)	do { if (athn_debug >= (n)) printf x; } while (0)
extern int athn_debug;
#else
#define DPRINTF(x)
#define DPRINTFN(n, x)
#endif

#define LE_READ_4(p)	((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24)
#define LE_READ_2(p)	((p)[0] | (p)[1] << 8)

#define ATHN_RXBUFSZ	3872
#define ATHN_TXBUFSZ	4096

#define ATHN_NRXBUFS	64
#define ATHN_NTXBUFS	64	/* Shared between all Tx queues. */

struct athn_rx_radiotap_header {
	struct ieee80211_radiotap_header wr_ihdr;
	uint64_t	wr_tsft;
	uint8_t		wr_flags;
	uint8_t		wr_rate;
	uint16_t	wr_chan_freq;
	uint16_t	wr_chan_flags;
	int8_t		wr_dbm_antsignal;
	uint8_t		wr_antenna;
} __packed;

#define ATHN_RX_RADIOTAP_PRESENT						\
	(1 << IEEE80211_RADIOTAP_TSFT |					\
	 1 << IEEE80211_RADIOTAP_FLAGS |				\
	 1 << IEEE80211_RADIOTAP_RATE |					\
	 1 << IEEE80211_RADIOTAP_CHANNEL |				\
	 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL |			\
	 1 << IEEE80211_RADIOTAP_ANTENNA)

struct athn_tx_radiotap_header {
	struct ieee80211_radiotap_header wt_ihdr;
	uint8_t		wt_flags;
	uint8_t		wt_rate;
	uint16_t	wt_chan_freq;
	uint16_t	wt_chan_flags;
	uint8_t		wt_hwqueue;
} __packed;

#define ATHN_TX_RADIOTAP_PRESENT						\
	(1 << IEEE80211_RADIOTAP_FLAGS |				\
	 1 << IEEE80211_RADIOTAP_RATE |					\
	 1 << IEEE80211_RADIOTAP_CHANNEL |				\
	 1 << IEEE80211_RADIOTAP_HWQUEUE)

struct athn_tx_buf {
	SIMPLEQ_ENTRY(athn_tx_buf)	bf_list;

	void				*bf_descs;
	bus_dmamap_t			bf_map;
	bus_addr_t			bf_daddr;

	struct mbuf			*bf_m;
	struct ieee80211_node		*bf_ni;
	int				bf_txflags;
#define ATHN_TXFLAG_PAPRD	(1 << 0)
#define ATHN_TXFLAG_CAB		(1 << 1)
};

struct athn_txq {
	SIMPLEQ_HEAD(, athn_tx_buf)	head;
	void				*lastds;
	struct athn_tx_buf		*wait;
	int				queued;
};

struct athn_rx_buf {
	SIMPLEQ_ENTRY(athn_rx_buf)	bf_list;

	void				*bf_desc;
	bus_dmamap_t			bf_map;

	struct mbuf			*bf_m;
	bus_addr_t			bf_daddr;
};

struct athn_rxq {
	struct athn_rx_buf		*bf;

	void				*descs;
	void				*lastds;
	bus_dmamap_t			map;
	bus_dma_segment_t		seg;
	int				count;

	SIMPLEQ_HEAD(, athn_rx_buf)	head;
};

/* Software rate indexes. */
#define ATHN_RIDX_CCK1	0
#define ATHN_RIDX_CCK2	1
#define ATHN_RIDX_OFDM6	4
#define ATHN_RIDX_MCS0	12
#define ATHN_RIDX_MCS15	27
#define ATHN_RIDX_MAX	27
#define ATHN_IS_HT_RIDX(ridx)	((ridx) >= ATHN_RIDX_MCS0)

static const struct athn_rate {
	uint8_t	rate;		/* Rate in 500Kbps unit or MCS if 0x80. */
	uint8_t	hwrate;		/* HW representation. */
	uint8_t	rspridx;	/* Control Response Frame rate index. */
	enum	ieee80211_phytype phy;
} athn_rates[] = {
	{    2, 0x1b, 0, IEEE80211_T_DS },
	{    4, 0x1a, 1, IEEE80211_T_DS },
	{   11, 0x19, 1, IEEE80211_T_DS },
	{   22, 0x18, 1, IEEE80211_T_DS },
	{   12, 0x0b, 4, IEEE80211_T_OFDM },
	{   18, 0x0f, 4, IEEE80211_T_OFDM },
	{   24, 0x0a, 6, IEEE80211_T_OFDM },
	{   36, 0x0e, 6, IEEE80211_T_OFDM },
	{   48, 0x09, 8, IEEE80211_T_OFDM },
	{   72, 0x0d, 8, IEEE80211_T_OFDM },
	{   96, 0x08, 8, IEEE80211_T_OFDM },
	{  108, 0x0c, 8, IEEE80211_T_OFDM },
	{ 0x80, 0x80, 8, IEEE80211_T_OFDM },
	{ 0x81, 0x81, 8, IEEE80211_T_OFDM },
	{ 0x82, 0x82, 8, IEEE80211_T_OFDM },
	{ 0x83, 0x83, 8, IEEE80211_T_OFDM },
	{ 0x84, 0x84, 8, IEEE80211_T_OFDM },
	{ 0x85, 0x85, 8, IEEE80211_T_OFDM },
	{ 0x86, 0x86, 8, IEEE80211_T_OFDM },
	{ 0x87, 0x87, 8, IEEE80211_T_OFDM },
	{ 0x88, 0x88, 8, IEEE80211_T_OFDM },
	{ 0x89, 0x89, 8, IEEE80211_T_OFDM },
	{ 0x8a, 0x8a, 8, IEEE80211_T_OFDM },
	{ 0x8b, 0x8b, 8, IEEE80211_T_OFDM },
	{ 0x8c, 0x8c, 8, IEEE80211_T_OFDM },
	{ 0x8d, 0x8d, 8, IEEE80211_T_OFDM },
	{ 0x8e, 0x8e, 8, IEEE80211_T_OFDM },
	{ 0x8f, 0x8f, 8, IEEE80211_T_OFDM }
};

struct athn_series {
	uint16_t	dur;
	uint8_t		hwrate;
};

struct athn_pier {
	uint8_t		fbin;
	const uint8_t	*pwr[AR_PD_GAINS_IN_MASK];
	const uint8_t	*vpd[AR_PD_GAINS_IN_MASK];
};

/*
 * Structures used to store initialization values.
 */
struct athn_ini {
	int		nregs;
	const uint16_t	*regs;
	const uint32_t	*vals_5g20;
#ifndef IEEE80211_NO_HT
	const uint32_t	*vals_5g40;
	const uint32_t	*vals_2g40;
#endif
	const uint32_t	*vals_2g20;
	int		ncmregs;
	const uint16_t	*cmregs;
	const uint32_t	*cmvals;
	int		nfastregs;
	const uint16_t	*fastregs;
	const uint32_t	*fastvals_5g20;
#ifndef IEEE80211_NO_HT
	const uint32_t	*fastvals_5g40;
#endif
};

struct athn_gain {
	int		nregs;
	const uint16_t	*regs;
	const uint32_t	*vals_5g;
	const uint32_t	*vals_2g;
};

struct athn_addac {
	int		nvals;
	const uint32_t	*vals;
};

struct athn_serdes {
	int		nvals;
	const uint32_t	*regs;
	const uint32_t	*vals;
};

/* Rx queue software indexes. */
#define ATHN_QID_LP		0
#define ATHN_QID_HP		1

/* Tx queue software indexes. */
#define ATHN_QID_AC_BE		0
#define ATHN_QID_PSPOLL		1
#define ATHN_QID_AC_BK		2
#define ATHN_QID_AC_VI		3
#define ATHN_QID_AC_VO		4
#define ATHN_QID_UAPSD		5
#define ATHN_QID_CAB		6
#define ATHN_QID_BEACON		7
#define ATHN_QID_COUNT		8

/* Map Access Category to Tx queue Id. */
static const uint8_t athn_ac2qid[EDCA_NUM_AC] = {
	ATHN_QID_AC_BE,	/* EDCA_AC_BE */
	ATHN_QID_AC_BK,	/* EDCA_AC_BK */
	ATHN_QID_AC_VI,	/* EDCA_AC_VI */
	ATHN_QID_AC_VO	/* EDCA_AC_VO */
};

static const uint8_t athn_5ghz_chans[] = {
	/* UNII 1. */
	36, 40, 44, 48,
	/* UNII 2. */
	52, 56, 60, 64,
	/* Middle band. */
	100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140,
	/* UNII 3. */
	149, 153, 157, 161, 165
};

/* Number of data bits per OFDM symbol for MCS[0-15]. */
/* See tables 20-29, 20-30, 20-33, 20-34. */
static const uint16_t ar_mcs_ndbps[][2] = {
	/* 20MHz  40MHz */
	{     26,    54 },	/* MCS0 */
	{     52,   108 },	/* MCS1 */
	{     78,   162 },	/* MCS2 */
	{    104,   216 },	/* MCS3 */
	{    156,   324 },	/* MCS4 */
	{    208,   432 },	/* MCS5 */
	{    234,   486 },	/* MCS6 */
	{    260,   540 },	/* MCS7 */
	{     26,   108 },	/* MCS8 */
	{     52,   216 },	/* MCS9 */
	{     78,   324 },	/* MCS10 */
	{    104,   432 },	/* MCS11 */
	{    156,   648 },	/* MCS12 */
	{    208,   864 },	/* MCS13 */
	{    234,   972 },	/* MCS14 */
	{    260,  1080 }	/* MCS15 */
};

#define ATHN_POWER_OFDM6	0
#define ATHN_POWER_OFDM9	1
#define ATHN_POWER_OFDM12	2
#define ATHN_POWER_OFDM18	3
#define ATHN_POWER_OFDM24	4
#define ATHN_POWER_OFDM36	5
#define ATHN_POWER_OFDM48	6
#define ATHN_POWER_OFDM54	7
#define ATHN_POWER_CCK1_LP	8
#define ATHN_POWER_CCK2_LP	9
#define ATHN_POWER_CCK2_SP	10
#define ATHN_POWER_CCK55_LP	11
#define ATHN_POWER_CCK55_SP	12
#define ATHN_POWER_CCK11_LP	13
#define ATHN_POWER_CCK11_SP	14
#define ATHN_POWER_XR		15
#define ATHN_POWER_HT20(mcs)	(16 + (mcs))
#define ATHN_POWER_HT40(mcs)	(40 + (mcs))
#define ATHN_POWER_CCK_DUP	64
#define ATHN_POWER_OFDM_DUP	65
#define ATHN_POWER_CCK_EXT	66
#define ATHN_POWER_OFDM_EXT	67
#define ATHN_POWER_COUNT	68

struct athn_node {
	struct ieee80211_node		ni;
	struct ieee80211_amrr_node	amn;
	uint8_t				ridx[IEEE80211_RATE_MAXSIZE];
	uint8_t				fallback[IEEE80211_RATE_MAXSIZE];
	uint8_t				sta_index;
};

/*
 * Adaptive noise immunity state.
 */
#define ATHN_ANI_PERIOD		100
#define ATHN_ANI_RSSI_THR_HIGH	40
#define ATHN_ANI_RSSI_THR_LOW	7
struct athn_ani {
	uint8_t		noise_immunity_level;
	uint8_t		spur_immunity_level;
	uint8_t		firstep_level;
	uint8_t		ofdm_weak_signal;
	uint8_t		cck_weak_signal;

	uint32_t	listen_time;

	uint32_t	ofdm_trig_high;
	uint32_t	ofdm_trig_low;

	int32_t		cck_trig_high;
	int32_t		cck_trig_low;

	uint32_t	ofdm_phy_err_base;
	uint32_t	cck_phy_err_base;
	uint32_t	ofdm_phy_err_count;
	uint32_t	cck_phy_err_count;

	uint32_t	cyccnt;
	uint32_t	txfcnt;
	uint32_t	rxfcnt;
};

struct athn_iq_cal {
	uint32_t	pwr_meas_i;
	uint32_t	pwr_meas_q;
	int32_t		iq_corr_meas;
};

struct athn_adc_cal {
	uint32_t	pwr_meas_odd_i;
	uint32_t	pwr_meas_even_i;
	uint32_t	pwr_meas_odd_q;
	uint32_t	pwr_meas_even_q;
};

struct athn_calib {
	int			nsamples;
	struct athn_iq_cal	iq[AR_MAX_CHAINS];
	struct athn_adc_cal	adc_gain[AR_MAX_CHAINS];
	struct athn_adc_cal	adc_dc_offset[AR_MAX_CHAINS];
};

#define ATHN_NF_CAL_HIST_MAX	5

struct athn_softc;

struct athn_ops {
	/* Bus callbacks. */
	uint32_t	(*read)(struct athn_softc *, uint32_t);
	void		(*write)(struct athn_softc *, uint32_t, uint32_t);
	void		(*write_barrier)(struct athn_softc *);

	void	(*setup)(struct athn_softc *);
	void	(*set_txpower)(struct athn_softc *, struct ieee80211_channel *,
		    struct ieee80211_channel *);
	void	(*spur_mitigate)(struct athn_softc *,
		    struct ieee80211_channel *, struct ieee80211_channel *);
	const struct ar_spur_chan *
		(*get_spur_chans)(struct athn_softc *, int);
	void	(*init_from_rom)(struct athn_softc *,
		    struct ieee80211_channel *, struct ieee80211_channel *);
	int	(*set_synth)(struct athn_softc *, struct ieee80211_channel *,
		    struct ieee80211_channel *);
	int	(*read_rom_data)(struct athn_softc *, uint32_t, void *, int);
	const uint8_t *
		(*get_rom_template)(struct athn_softc *, uint8_t);
	void	(*swap_rom)(struct athn_softc *);
	void	(*olpc_init)(struct athn_softc *);
	void	(*olpc_temp_compensation)(struct athn_softc *);
	/* GPIO callbacks. */
	int	(*gpio_read)(struct athn_softc *, int);
	void	(*gpio_write)(struct athn_softc *, int, int);
	void	(*gpio_config_input)(struct athn_softc *, int);
	void	(*gpio_config_output)(struct athn_softc *, int, int);
	void	(*rfsilent_init)(struct athn_softc *);
	/* DMA callbacks. */
	int	(*dma_alloc)(struct athn_softc *);
	void	(*dma_free)(struct athn_softc *);
	void	(*rx_enable)(struct athn_softc *);
	int	(*intr)(struct athn_softc *);
	int	(*tx)(struct athn_softc *, struct mbuf *,
		    struct ieee80211_node *, int);
	/* PHY callbacks. */
	void	(*set_rf_mode)(struct athn_softc *,
		    struct ieee80211_channel *);
	int	(*rf_bus_request)(struct athn_softc *);
	void	(*rf_bus_release)(struct athn_softc *);
	void	(*set_phy)(struct athn_softc *, struct ieee80211_channel *,
		    struct ieee80211_channel *);
	void	(*set_delta_slope)(struct athn_softc *,
		    struct ieee80211_channel *, struct ieee80211_channel *);
	void	(*enable_antenna_diversity)(struct athn_softc *);
	void	(*init_baseband)(struct athn_softc *);
	void	(*disable_phy)(struct athn_softc *);
	void	(*set_rxchains)(struct athn_softc *);
	void	(*noisefloor_calib)(struct athn_softc *);
	void	(*do_calib)(struct athn_softc *);
	void	(*next_calib)(struct athn_softc *);
	void	(*hw_init)(struct athn_softc *, struct ieee80211_channel *,
		    struct ieee80211_channel *);
	void	(*get_paprd_masks)(struct athn_softc *sc,
		    struct ieee80211_channel *, uint32_t *, uint32_t *);
	/* ANI callbacks. */
	void	(*set_noise_immunity_level)(struct athn_softc *, int);
	void	(*enable_ofdm_weak_signal)(struct athn_softc *);
	void	(*disable_ofdm_weak_signal)(struct athn_softc *);
	void	(*set_cck_weak_signal)(struct athn_softc *, int);
	void	(*set_firstep_level)(struct athn_softc *, int);
	void	(*set_spur_immunity_level)(struct athn_softc *, int);
};

struct athn_softc {
	struct device			sc_dev;
	struct ieee80211com		sc_ic;

	int				(*sc_enable)(struct athn_softc *);
	void				(*sc_disable)(struct athn_softc *);
	void				(*sc_power)(struct athn_softc *, int);
	void				(*sc_disable_aspm)(struct athn_softc *);
	void				(*sc_enable_extsynch)(
					    struct athn_softc *);

	int				(*sc_newstate)(struct ieee80211com *,
					    enum ieee80211_state, int);

	bus_dma_tag_t			sc_dmat;

	struct timeout			scan_to;
	struct timeout			calib_to;
	struct ieee80211_amrr		amrr;

	u_int				flags;
#define ATHN_FLAG_PCIE			(1 << 0)
#define ATHN_FLAG_USB			(1 << 1)
#define ATHN_FLAG_OLPC			(1 << 2)
#define ATHN_FLAG_PAPRD			(1 << 3)
#define ATHN_FLAG_FAST_PLL_CLOCK	(1 << 4)
#define ATHN_FLAG_RFSILENT		(1 << 5)
#define ATHN_FLAG_RFSILENT_REVERSED	(1 << 6)
#define ATHN_FLAG_BTCOEX2WIRE		(1 << 7)
#define ATHN_FLAG_BTCOEX3WIRE		(1 << 8)
/* Shortcut. */
#define ATHN_FLAG_BTCOEX	(ATHN_FLAG_BTCOEX2WIRE | ATHN_FLAG_BTCOEX3WIRE)
#define ATHN_FLAG_11A			(1 << 9)
#define ATHN_FLAG_11G			(1 << 10)
#define ATHN_FLAG_11N			(1 << 11)
#define ATHN_FLAG_AN_TOP2_FIXUP		(1 << 12)
#define ATHN_FLAG_NON_ENTERPRISE	(1 << 13)
#define ATHN_FLAG_3TREDUCE_CHAIN	(1 << 14)

	uint8_t				ngpiopins;
	int				led_pin;
	int				rfsilent_pin;
	int				led_state;
	uint32_t			isync;
	uint32_t			imask;

	uint16_t			mac_ver;
	uint8_t				mac_rev;
	uint8_t				rf_rev;
	uint16_t			eep_rev;

	uint8_t				txchainmask;
	uint8_t				rxchainmask;
	uint8_t				ntxchains;
	uint8_t				nrxchains;

	uint8_t				sup_calib_mask;
	uint8_t				cur_calib_mask;
#define ATHN_CAL_IQ		(1 << 0)
#define ATHN_CAL_ADC_GAIN	(1 << 1)
#define ATHN_CAL_ADC_DC		(1 << 2)
#define ATHN_CAL_TEMP		(1 << 3)

	struct ieee80211_channel	*curchan;
	struct ieee80211_channel	*curchanext;

	/* Open Loop Power Control. */
	int8_t				tx_gain_tbl[AR9280_TX_GAIN_TABLE_SIZE];
	int8_t				pdadc;
	int8_t				tcomp;
	int				olpc_ticks;

	/* PA predistortion. */
	uint16_t			gain1[AR_MAX_CHAINS];
	uint32_t			txgain[AR9003_TX_GAIN_TABLE_SIZE];
	int16_t				pa_in[AR_MAX_CHAINS]
					     [AR9003_PAPRD_MEM_TAB_SIZE];
	int16_t				angle[AR_MAX_CHAINS]
					     [AR9003_PAPRD_MEM_TAB_SIZE];
	int32_t				trainpow;
	uint8_t				paprd_curchain;

	uint32_t			rwbuf[64];

	int				kc_entries;

	void				*eep;
	const void			*eep_def;
	uint32_t			eep_base;
	uint32_t			eep_size;

	struct athn_rxq			rxq[2];
	struct athn_txq			txq[31];

	void				*descs;
	bus_dmamap_t			map;
	bus_dma_segment_t		seg;
	SIMPLEQ_HEAD(, athn_tx_buf)	txbufs;
	struct athn_tx_buf		*bcnbuf;
	struct athn_tx_buf		txpool[ATHN_NTXBUFS];

	bus_dmamap_t			txsmap;
	bus_dma_segment_t		txsseg;
	void				*txsring;
	int				txscur;

	int				sc_if_flags;
	int				sc_tx_timer;

	const struct athn_ini		*ini;
	const struct athn_gain		*rx_gain;
	const struct athn_gain		*tx_gain;
	const struct athn_addac		*addac;
	const struct athn_serdes	*serdes;
	uint32_t			workaround;
	uint32_t			obs_off;
	uint32_t			gpio_input_en_off;

	struct athn_ops			ops;

	int				fixed_ridx;

	int16_t				cca_min_2g;
	int16_t				cca_max_2g;
	int16_t				cca_min_5g;
	int16_t				cca_max_5g;
	int16_t				def_nf;
	struct {
		int16_t	nf[AR_MAX_CHAINS];
		int16_t	nf_ext[AR_MAX_CHAINS];
	}				nf_hist[ATHN_NF_CAL_HIST_MAX];
	int				nf_hist_cur;
	int16_t				nf_priv[AR_MAX_CHAINS];
	int16_t				nf_ext_priv[AR_MAX_CHAINS];
	int				pa_calib_ticks;

	struct athn_calib		calib;
	struct athn_ani			ani;

#if NBPFILTER > 0
	caddr_t				sc_drvbpf;

	union {
		struct athn_rx_radiotap_header th;
		uint8_t pad[IEEE80211_RADIOTAP_HDRLEN];
	} sc_rxtapu;
#define sc_rxtap			sc_rxtapu.th
	int				sc_rxtap_len;

	union {
		struct athn_tx_radiotap_header th;
		uint8_t pad[IEEE80211_RADIOTAP_HDRLEN];
	} sc_txtapu;
#define sc_txtap			sc_txtapu.th
	int				sc_txtap_len;
#endif
};

extern int	athn_attach(struct athn_softc *);
extern void	athn_detach(struct athn_softc *);
extern void	athn_suspend(struct athn_softc *);
extern void	athn_wakeup(struct athn_softc *);
extern int	athn_intr(void *);

license: unknown


code:
/*      $OpenBSD: athvar.h,v 1.32 2011/04/27 16:06:13 deraadt Exp $  */
/*	$NetBSD: athvar.h,v 1.10 2004/08/10 01:03:53 dyoung Exp $	*/

/*-
 * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer,
 *    without modification.
 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
 *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
 *    redistribution must be conditioned upon including a substantially
 *    similar Disclaimer requirement for further binary redistribution.
 * 3. Neither the names of the above-listed copyright holders nor the names
 *    of any contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * NO WARRANTY
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
 * THE POSSIBILITY OF SUCH DAMAGES.
 *
 * $FreeBSD: src/sys/dev/ath/if_athvar.h,v 1.14 2004/04/03 03:33:02 sam Exp $
 */

/*
 * Definitions for the Atheros Wireless LAN controller driver.
 */
#ifndef _DEV_ATH_ATHVAR_H
#define _DEV_ATH_ATHVAR_H

#ifdef _KERNEL

#include <net80211/ieee80211_radiotap.h>
#include <dev/ic/ar5xxx.h>

#include "bpfilter.h"

#ifdef notyet
#include "gpio.h"
#endif

#define	ATH_TIMEOUT		1000

#define	ATH_RXBUF	40		/* number of RX buffers */
#define	ATH_TXBUF	60		/* number of TX buffers */
#define	ATH_TXDESC	8		/* number of descriptors per buffer */
#define ATH_MAXGPIO	10		/* maximal number of gpio pins */

struct ath_recv_hist {
	int		arh_ticks;	/* sample time by system clock */
	u_int8_t	arh_rssi;	/* rssi */
	u_int8_t	arh_antenna;	/* antenna */
};
#define	ATH_RHIST_SIZE		16	/* number of samples */
#define	ATH_RHIST_NOTIME	(~0)

/*
 * Ioctl-related definitions for the Atheros Wireless LAN controller driver.
 */
struct ath_stats {
	u_int32_t	ast_watchdog;	/* device reset by watchdog */
	u_int32_t	ast_hardware;	/* fatal hardware error interrupts */
	u_int32_t	ast_bmiss;	/* beacon miss interrupts */
	u_int32_t	ast_mib;	/* MIB counter interrupts */
	u_int32_t	ast_rxorn;	/* rx overrun interrupts */
	u_int32_t	ast_rxeol;	/* rx eol interrupts */
	u_int32_t	ast_txurn;	/* tx underrun interrupts */
	u_int32_t	ast_intrcoal;	/* interrupts coalesced */
	u_int32_t	ast_tx_mgmt;	/* management frames transmitted */
	u_int32_t	ast_tx_discard;	/* frames discarded prior to assoc */
	u_int32_t	ast_tx_qstop;	/* output stopped 'cuz no buffer */
	u_int32_t	ast_tx_encap;	/* tx encapsulation failed */
	u_int32_t	ast_tx_nonode;	/* tx failed 'cuz no node */
	u_int32_t	ast_tx_nombuf;	/* tx failed 'cuz no mbuf */
	u_int32_t	ast_tx_nomcl;	/* tx failed 'cuz no cluster */
	u_int32_t	ast_tx_linear;	/* tx linearized to cluster */
	u_int32_t	ast_tx_nodata;	/* tx discarded empty frame */
	u_int32_t	ast_tx_busdma;	/* tx failed for dma resrcs */
	u_int32_t	ast_tx_xretries;/* tx failed 'cuz too many retries */
	u_int32_t	ast_tx_fifoerr;	/* tx failed 'cuz FIFO underrun */
	u_int32_t	ast_tx_filtered;/* tx failed 'cuz xmit filtered */
	u_int32_t	ast_tx_shortretry;/* tx on-chip retries (short) */
	u_int32_t	ast_tx_longretry;/* tx on-chip retries (long) */
	u_int32_t	ast_tx_badrate;	/* tx failed 'cuz bogus xmit rate */
	u_int32_t	ast_tx_noack;	/* tx frames with no ack marked */
	u_int32_t	ast_tx_rts;	/* tx frames with rts enabled */
	u_int32_t	ast_tx_cts;	/* tx frames with cts enabled */
	u_int32_t	ast_tx_shortpre;/* tx frames with short preamble */
	u_int32_t	ast_tx_altrate;	/* tx frames with alternate rate */
	u_int32_t	ast_tx_protect;	/* tx frames with protection */
	u_int32_t	ast_rx_nombuf;	/* rx setup failed 'cuz no mbuf */
	u_int32_t	ast_rx_busdma;	/* rx setup failed for dma resrcs */
	u_int32_t	ast_rx_orn;	/* rx failed 'cuz of desc overrun */
	u_int32_t	ast_rx_crcerr;	/* rx failed 'cuz of bad CRC */
	u_int32_t	ast_rx_fifoerr;	/* rx failed 'cuz of FIFO overrun */
	u_int32_t	ast_rx_badcrypt;/* rx failed 'cuz decryption */
	u_int32_t	ast_rx_phyerr;	/* rx failed 'cuz of PHY err */
	u_int32_t	ast_rx_phy[32];	/* rx PHY error per-code counts */
	u_int32_t	ast_rx_tooshort;/* rx discarded 'cuz frame too short */
	u_int32_t	ast_rx_toobig;	/* rx discarded 'cuz frame too large */
	u_int32_t	ast_rx_ctl;	/* rx discarded 'cuz ctl frame */
	u_int32_t	ast_be_nombuf;	/* beacon setup failed 'cuz no mbuf */
	u_int32_t	ast_per_cal;	/* periodic calibration calls */
	u_int32_t	ast_per_calfail;/* periodic calibration failed */
	u_int32_t	ast_per_rfgain;	/* periodic calibration rfgain reset */
	u_int32_t	ast_rate_calls;	/* rate control checks */
	u_int32_t	ast_rate_raise;	/* rate control raised xmit rate */
	u_int32_t	ast_rate_drop;	/* rate control dropped xmit rate */
};

/*
 * Radio capture format.
 */
#define ATH_RX_RADIOTAP_PRESENT (		\
	(1 << IEEE80211_RADIOTAP_FLAGS)		| \
	(1 << IEEE80211_RADIOTAP_RATE)		| \
	(1 << IEEE80211_RADIOTAP_CHANNEL)	| \
	(1 << IEEE80211_RADIOTAP_ANTENNA)	| \
	(1 << IEEE80211_RADIOTAP_RSSI)		| \
	0)

struct ath_rx_radiotap_header {
	struct ieee80211_radiotap_header wr_ihdr;
	u_int8_t	wr_flags;
	u_int8_t	wr_rate;
	u_int16_t	wr_chan_freq;
	u_int16_t	wr_chan_flags;
	u_int8_t	wr_antenna;
	u_int8_t	wr_rssi;
	u_int8_t	wr_max_rssi;
} __packed;

#define ATH_TX_RADIOTAP_PRESENT (		\
	(1 << IEEE80211_RADIOTAP_FLAGS)		| \
	(1 << IEEE80211_RADIOTAP_RATE)		| \
	(1 << IEEE80211_RADIOTAP_CHANNEL)	| \
	(1 << IEEE80211_RADIOTAP_DBM_TX_POWER)	| \
	(1 << IEEE80211_RADIOTAP_ANTENNA)	| \
	(1 << IEEE80211_RADIOTAP_HWQUEUE)	| \
	0)

struct ath_tx_radiotap_header {
	struct ieee80211_radiotap_header wt_ihdr;
	u_int8_t	wt_flags;
	u_int8_t	wt_rate;
	u_int16_t	wt_chan_freq;
	u_int16_t	wt_chan_flags;
	u_int8_t	wt_txpower;
	u_int8_t	wt_antenna;
	u_int8_t	wt_hwqueue;
} __packed;

/*
 * driver-specific node
 */
struct ath_node {
	struct ieee80211_node		an_node;	/* base class */
	struct ieee80211_rssadapt	an_rssadapt;	/* rate adaption */
	u_int				an_tx_antenna;	/* antenna for last good frame */
	u_int				an_rx_antenna;	/* antenna for last rcvd frame */
	struct ath_recv_hist		an_rx_hist[ATH_RHIST_SIZE];
	u_int				an_rx_hist_next;/* index of next ``free entry'' */
};
#define	ATH_NODE(_n)	((struct ath_node *)(_n))

struct ath_buf {
	TAILQ_ENTRY(ath_buf)		bf_list;
	bus_dmamap_t			bf_dmamap;	/* DMA map of the buffer */
#define bf_nseg				bf_dmamap->dm_nsegs
#define bf_mapsize			bf_dmamap->dm_mapsize
#define bf_segs				bf_dmamap->dm_segs
	struct ath_desc			*bf_desc;	/* virtual addr of desc */
	bus_addr_t			bf_daddr;	/* physical addr of desc */
	struct mbuf			*bf_m;		/* mbuf for buf */
	struct ieee80211_node		*bf_node;	/* pointer to the node */
	struct ieee80211_rssdesc	bf_id;
#define	ATH_MAX_SCATTER			64
};

typedef struct ath_task {
	void	(*t_func)(void*, int);
	void	*t_context;
} ath_task_t;

struct ath_softc {
#ifndef __FreeBSD__
	struct device		sc_dev;
#endif
	struct ieee80211com	sc_ic;		/* IEEE 802.11 common */
#ifndef __FreeBSD__
	int			(*sc_enable)(struct ath_softc *);
	void			(*sc_disable)(struct ath_softc *);
	void			(*sc_power)(struct ath_softc *, int);
#endif
	int			(*sc_newstate)(struct ieee80211com *,
					enum ieee80211_state, int);
	void			(*sc_node_free)(struct ieee80211com *,
					struct ieee80211_node *);
	void			(*sc_node_copy)(struct ieee80211com *,
					struct ieee80211_node *,
					const struct ieee80211_node *);
	void			(*sc_recv_mgmt)(struct ieee80211com *,
				    struct mbuf *, struct ieee80211_node *,
				    struct ieee80211_rxinfo *, int);
#ifdef __FreeBSD__
	device_t		sc_dev;
#endif
	bus_space_tag_t		sc_st;		/* bus space tag */
	bus_space_handle_t	sc_sh;		/* bus space handle */
	bus_size_t		sc_ss;		/* bus space size */
	bus_dma_tag_t		sc_dmat;	/* bus DMA tag */
#ifdef __FreeBSD__
	struct mtx		sc_mtx;		/* master lock (recursive) */
#endif
	struct ath_hal		*sc_ah;		/* Atheros HAL */
	unsigned int		sc_invalid : 1,	/* disable hardware accesses */
				sc_doani : 1,	/* dynamic noise immunity */
				sc_veol : 1,	/* tx VEOL support */
				sc_softled : 1,	/* GPIO software LED */
				sc_probing : 1,	/* probing AP on beacon miss */
				sc_pcie : 1;	/* indicates PCI Express */
	u_int			sc_nchan;	/* number of valid channels */
	const HAL_RATE_TABLE	*sc_rates[IEEE80211_MODE_MAX];
	const HAL_RATE_TABLE	*sc_currates;	/* current rate table */
	enum ieee80211_phymode	sc_curmode;	/* current phy mode */
	u_int8_t		sc_rixmap[256];	/* IEEE to h/w rate table ix */
	u_int8_t		sc_hwmap[32];	/* h/w rate ix to IEEE table */
	HAL_INT			sc_imask;	/* interrupt mask copy */

#if NBPFILTER > 0
	caddr_t			sc_drvbpf;

	union {
		struct ath_rx_radiotap_header	th;
		uint8_t				pad[IEEE80211_RADIOTAP_HDRLEN];
	}			sc_rxtapu;
#define sc_rxtap		sc_rxtapu.th
	int			sc_rxtap_len;

	union {
		struct ath_tx_radiotap_header	th;
		uint8_t				pad[IEEE80211_RADIOTAP_HDRLEN];
	}			sc_txtapu;
#define sc_txtap		sc_txtapu.th
	int			sc_txtap_len;
#endif

	struct ath_desc		*sc_desc;	/* TX/RX descriptors */
	bus_dma_segment_t	sc_dseg;
	int			sc_dnseg;	/* number of segments */
	bus_dmamap_t		sc_ddmamap;	/* DMA map for descriptors */
	bus_addr_t		sc_desc_paddr;	/* physical addr of sc_desc */
	bus_addr_t		sc_desc_len;	/* size of sc_desc */

	ath_task_t		sc_fataltask;	/* fatal int processing */
	ath_task_t		sc_rxorntask;	/* rxorn int processing */

	TAILQ_HEAD(, ath_buf)	sc_rxbuf;	/* receive buffer */
	u_int32_t		*sc_rxlink;	/* link ptr in last RX desc */
	ath_task_t		sc_rxtask;	/* rx int processing */

	u_int			sc_txhalq[HAL_NUM_TX_QUEUES];	/* HAL q for outgoing frames */
	u_int32_t		*sc_txlink;	/* link ptr in last TX desc */
	int			sc_tx_timer;	/* transmit timeout */
	TAILQ_HEAD(, ath_buf)	sc_txbuf;	/* transmit buffer */
#ifdef __FreeBSD__
	struct mtx		sc_txbuflock;	/* txbuf lock */
#endif
	TAILQ_HEAD(, ath_buf)	sc_txq;		/* transmitting queue */
#ifdef __FreeBSD__
	struct mtx		sc_txqlock;	/* lock on txq and txlink */
#endif
	ath_task_t		sc_txtask;	/* tx int processing */

	u_int			sc_bhalq;	/* HAL q for outgoing beacons */
	struct ath_buf		*sc_bcbuf;	/* beacon buffer */
	struct ath_buf		*sc_bufptr;	/* allocated buffer ptr */
	ath_task_t		sc_swbatask;	/* swba int processing */
	ath_task_t		sc_bmisstask;	/* bmiss int processing */

#ifdef __OpenBSD__
	struct timeval		sc_last_ch;
	struct timeout		sc_cal_to;
	struct timeval		sc_last_beacon;
	struct timeout		sc_scan_to;
	struct timeout		sc_rssadapt_to;
#else
	struct callout		sc_cal_ch;	/* callout handle for cals */
	struct callout		sc_scan_ch;	/* callout handle for scan */
#endif
	struct ath_stats	sc_stats;	/* interface statistics */
	HAL_MIB_STATS		sc_mib_stats;	/* MIB counter statistics */

#ifndef __FreeBSD__
	u_int			sc_flags;	/* misc flags */
#endif

	u_int8_t                sc_broadcast_addr[IEEE80211_ADDR_LEN];

	struct gpio_chipset_tag sc_gpio_gc;	/* gpio(4) framework */
	gpio_pin_t		sc_gpio_pins[ATH_MAXGPIO];
};

/* unaligned little endian access */
#define LE_READ_2(p)							\
	((u_int16_t)							\
	 ((((u_int8_t *)(p))[0]      ) | (((u_int8_t *)(p))[1] <<  8)))
#define LE_READ_4(p)							\
	((u_int32_t)							\
	 ((((u_int8_t *)(p))[0]      ) | (((u_int8_t *)(p))[1] <<  8) |	\
	 (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24)))

#ifdef AR_DEBUG
enum {
	ATH_DEBUG_XMIT		= 0x00000001,	/* basic xmit operation */
	ATH_DEBUG_XMIT_DESC	= 0x00000002,	/* xmit descriptors */
	ATH_DEBUG_RECV		= 0x00000004,	/* basic recv operation */
	ATH_DEBUG_RECV_DESC	= 0x00000008,	/* recv descriptors */
	ATH_DEBUG_RATE		= 0x00000010,	/* rate control */
	ATH_DEBUG_RESET		= 0x00000020,	/* reset processing */
	ATH_DEBUG_MODE		= 0x00000040,	/* mode init/setup */
	ATH_DEBUG_BEACON	= 0x00000080,	/* beacon handling */
	ATH_DEBUG_WATCHDOG	= 0x00000100,	/* watchdog timeout */
	ATH_DEBUG_INTR		= 0x00001000,	/* ISR */
	ATH_DEBUG_TX_PROC	= 0x00002000,	/* tx ISR proc */
	ATH_DEBUG_RX_PROC	= 0x00004000,	/* rx ISR proc */
	ATH_DEBUG_BEACON_PROC	= 0x00008000,	/* beacon ISR proc */
	ATH_DEBUG_CALIBRATE	= 0x00010000,	/* periodic calibration */
	ATH_DEBUG_ANY		= 0xffffffff
};
#define	IFF_DUMPPKTS(_ifp, _m) \
	((ath_debug & _m) || \
	    ((_ifp)->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2))
#define	DPRINTF(_m,X)	if (ath_debug & (_m)) printf X
#else
#define	IFF_DUMPPKTS(_ifp, _m) \
	(((_ifp)->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2))
#define	DPRINTF(_m, X)
#endif

/*
 * Wrapper code
 */
#ifndef __FreeBSD__
#undef KASSERT
#define KASSERT(cond, complaint) if (!(cond)) panic complaint

#define	ATH_ATTACHED		0x0001		/* attach has succeeded */
#define ATH_ENABLED		0x0002		/* chip is enabled */
#define ATH_GPIO		0x0004		/* gpio device attached */

#define	ATH_IS_ENABLED(sc)	((sc)->sc_flags & ATH_ENABLED)
#endif

#define	ATH_LOCK_INIT(_sc) \
	mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \
		 MTX_NETWORK_LOCK, MTX_DEF | MTX_RECURSE)
#define	ATH_LOCK_DESTROY(_sc)	mtx_destroy(&(_sc)->sc_mtx)
#define	ATH_LOCK(_sc)		mtx_lock(&(_sc)->sc_mtx)
#define	ATH_UNLOCK(_sc)		mtx_unlock(&(_sc)->sc_mtx)
#define	ATH_LOCK_ASSERT(_sc)	mtx_assert(&(_sc)->sc_mtx, MA_OWNED)

#define	ATH_TXBUF_LOCK_INIT(_sc) \
	mtx_init(&(_sc)->sc_txbuflock, \
		device_get_nameunit((_sc)->sc_dev), "xmit buf q", MTX_DEF)
#define	ATH_TXBUF_LOCK_DESTROY(_sc)	mtx_destroy(&(_sc)->sc_txbuflock)
#define	ATH_TXBUF_LOCK(_sc)		mtx_lock(&(_sc)->sc_txbuflock)
#define	ATH_TXBUF_UNLOCK(_sc)		mtx_unlock(&(_sc)->sc_txbuflock)
#define	ATH_TXBUF_LOCK_ASSERT(_sc) \
	mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED)

#define	ATH_TXQ_LOCK_INIT(_sc) \
	mtx_init(&(_sc)->sc_txqlock, \
		device_get_nameunit((_sc)->sc_dev), "xmit q", MTX_DEF)
#define	ATH_TXQ_LOCK_DESTROY(_sc)	mtx_destroy(&(_sc)->sc_txqlock)
#define	ATH_TXQ_LOCK(_sc)		mtx_lock(&(_sc)->sc_txqlock)
#define	ATH_TXQ_UNLOCK(_sc)		mtx_unlock(&(_sc)->sc_txqlock)
#define	ATH_TXQ_LOCK_ASSERT(_sc)	mtx_assert(&(_sc)->sc_txqlock, MA_OWNED)

#define ATH_TICKS() (tick)
#define ATH_CALLOUT_INIT(chp) callout_init((chp))
#define ATH_TASK_INIT(task, func, context)	\
	do {					\
		(task)->t_func = (func);	\
		(task)->t_context = (context);	\
	} while (0)
#define ATH_TASK_RUN_OR_ENQUEUE(task) ((*(task)->t_func)((task)->t_context, 1))

typedef unsigned long u_intptr_t;

int	ath_attach(u_int16_t, struct ath_softc *);
int	ath_detach(struct ath_softc *, int);
int	ath_enable(struct ath_softc *);
int	ath_activate(struct device *, int);
int	ath_intr(void *);
int	ath_enable(struct ath_softc *);

/*
 * HAL definitions to comply with local coding convention.
 */
#define	ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \
	((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus)))
#define	ath_hal_get_rate_table(_ah, _mode) \
	((*(_ah)->ah_get_rate_table)((_ah), (_mode)))
#define	ath_hal_get_lladdr(_ah, _mac) \
	((*(_ah)->ah_get_lladdr)((_ah), (_mac)))
#define	ath_hal_set_lladdr(_ah, _mac) \
	((*(_ah)->ah_set_lladdr)((_ah), (_mac)))
#define	ath_hal_set_intr(_ah, _mask) \
	((*(_ah)->ah_set_intr)((_ah), (_mask)))
#define	ath_hal_get_intr(_ah) \
	((*(_ah)->ah_get_intr)((_ah)))
#define	ath_hal_is_intr_pending(_ah) \
	((*(_ah)->ah_is_intr_pending)((_ah)))
#define	ath_hal_get_isr(_ah, _pmask) \
	((*(_ah)->ah_get_isr)((_ah), (_pmask)))
#define	ath_hal_update_tx_triglevel(_ah, _inc) \
	((*(_ah)->ah_update_tx_triglevel)((_ah), (_inc)))
#define	ath_hal_set_power(_ah, _mode, _sleepduration) \
	((*(_ah)->ah_set_power)((_ah), (_mode), AH_TRUE, (_sleepduration)))
#define	ath_hal_reset_key(_ah, _ix) \
	((*(_ah)->ah_reset_key)((_ah), (_ix)))
#define	ath_hal_set_key(_ah, _ix, _pk) \
	((*(_ah)->ah_set_key)((_ah), (_ix), (_pk), NULL, AH_FALSE))
#define	ath_hal_is_key_valid(_ah, _ix) \
	(((*(_ah)->ah_is_key_valid)((_ah), (_ix))))
#define	ath_hal_set_key_lladdr(_ah, _ix, _mac) \
	((*(_ah)->ah_set_key_lladdr)((_ah), (_ix), (_mac)))
#define	ath_hal_softcrypto(_ah, _val ) \
	((*(_ah)->ah_softcrypto)((_ah), (_val)))
#define	ath_hal_get_rx_filter(_ah) \
	((*(_ah)->ah_get_rx_filter)((_ah)))
#define	ath_hal_set_rx_filter(_ah, _filter) \
	((*(_ah)->ah_set_rx_filter)((_ah), (_filter)))
#define	ath_hal_set_mcast_filter(_ah, _mfilt0, _mfilt1) \
	((*(_ah)->ah_set_mcast_filter)((_ah), (_mfilt0), (_mfilt1)))
#define	ath_hal_wait_for_beacon(_ah, _bf) \
	((*(_ah)->ah_wait_for_beacon)((_ah), (_bf)->bf_daddr))
#define	ath_hal_put_rx_buf(_ah, _bufaddr) \
	((*(_ah)->ah_put_rx_buf)((_ah), (_bufaddr)))
#define	ath_hal_get_tsf32(_ah) \
	((*(_ah)->ah_get_tsf32)((_ah)))
#define	ath_hal_get_tsf64(_ah) \
	((*(_ah)->ah_get_tsf64)((_ah)))
#define	ath_hal_reset_tsf(_ah) \
	((*(_ah)->ah_reset_tsf)((_ah)))
#define	ath_hal_start_rx(_ah) \
	((*(_ah)->ah_start_rx)((_ah)))
#define	ath_hal_put_tx_buf(_ah, _q, _bufaddr) \
	((*(_ah)->ah_put_tx_buf)((_ah), (_q), (_bufaddr)))
#define	ath_hal_get_tx_buf(_ah, _q) \
	((*(_ah)->ah_get_tx_buf)((_ah), (_q)))
#define	ath_hal_get_rx_buf(_ah) \
	((*(_ah)->ah_get_rx_buf)((_ah)))
#define	ath_hal_tx_start(_ah, _q) \
	((*(_ah)->ah_tx_start)((_ah), (_q)))
#define	ath_hal_setchannel(_ah, _chan) \
	((*(_ah)->ah_setchannel)((_ah), (_chan)))
#define	ath_hal_calibrate(_ah, _chan) \
	((*(_ah)->ah_calibrate)((_ah), (_chan)))
#define	ath_hal_set_ledstate(_ah, _state) \
	((*(_ah)->ah_set_ledstate)((_ah), (_state)))
#define	ath_hal_init_beacon(_ah, _nextb, _bperiod) \
	((*(_ah)->ah_init_beacon)((_ah), (_nextb), (_bperiod)))
#define	ath_hal_reset_beacon(_ah) \
	((*(_ah)->ah_reset_beacon)((_ah)))
#define	ath_hal_set_beacon_timers(_ah, _bs, _tsf, _dc, _cc) \
	((*(_ah)->ah_set_beacon_timers)((_ah), (_bs), (_tsf), \
	 (_dc), (_cc)))
#define	ath_hal_set_associd(_ah, _bss, _associd) \
	((*(_ah)->ah_set_associd)((_ah), (_bss), (_associd), 0))
#define	ath_hal_get_regdomain(_ah, _prd) \
	(*(_prd) = (_ah)->ah_get_regdomain(_ah))
#define	ath_hal_detach(_ah) \
	((*(_ah)->ah_detach)(_ah))
#define ath_hal_set_slot_time(_ah, _t) \
	((*(_ah)->ah_set_slot_time)(_ah, _t))
#define ath_hal_set_gpio_output(_ah, _gpio) \
	((*(_ah)->ah_set_gpio_output)((_ah), (_gpio)))
#define ath_hal_set_gpio_input(_ah, _gpio) \
	((*(_ah)->ah_set_gpio_input)((_ah), (_gpio)))
#define ath_hal_get_gpio(_ah, _gpio) \
	((*(_ah)->ah_get_gpio)((_ah), (_gpio)))
#define ath_hal_set_gpio(_ah, _gpio, _b) \
	((*(_ah)->ah_set_gpio)((_ah), (_gpio), (_b)))
#define ath_hal_set_gpio_intr(_ah, _gpio, _b) \
	((*(_ah)->ah_set_gpio_intr)((_ah), (_gpio), (_b)))

#define	ath_hal_set_opmode(_ah) \
	((*(_ah)->ah_set_opmode)((_ah)))
#define	ath_hal_stop_tx_dma(_ah, _qnum) \
	((*(_ah)->ah_stop_tx_dma)((_ah), (_qnum)))
#define	ath_hal_stop_pcu_recv(_ah) \
	((*(_ah)->ah_stop_pcu_recv)((_ah)))
#define	ath_hal_start_rx_pcu(_ah) \
	((*(_ah)->ah_start_rx_pcu)((_ah)))
#define	ath_hal_stop_rx_dma(_ah) \
	((*(_ah)->ah_stop_rx_dma)((_ah)))
#define	ath_hal_get_diag_state(_ah, _id, _indata, _insize, _outdata, _outsize) \
	((*(_ah)->ah_get_diag_state)((_ah), (_id), \
	 (_indata), (_insize), (_outdata), (_outsize)))

#define	ath_hal_setup_tx_queue(_ah, _type, _qinfo) \
	((*(_ah)->ah_setup_tx_queue)((_ah), (_type), (_qinfo)))
#define	ath_hal_reset_tx_queue(_ah, _q) \
	((*(_ah)->ah_reset_tx_queue)((_ah), (_q)))
#define	ath_hal_release_tx_queue(_ah, _q) \
	((*(_ah)->ah_release_tx_queue)((_ah), (_q)))
#define	ath_hal_has_veol(_ah) \
	((*(_ah)->ah_has_veol)((_ah)))
#define ath_hal_update_mib_counters(_ah, _stats) \
	((*(_ah)->ah_update_mib_counters)((_ah), (_stats)))
#define	ath_hal_get_rf_gain(_ah) \
	((*(_ah)->ah_get_rf_gain)((_ah)))
#define	ath_hal_set_rx_signal(_ah) \
	((*(_ah)->ah_set_rx_signal)((_ah)))

#define	ath_hal_setup_rx_desc(_ah, _ds, _size, _intreq) \
	((*(_ah)->ah_setup_rx_desc)((_ah), (_ds), (_size), (_intreq)))
#define	ath_hal_proc_rx_desc(_ah, _ds, _dspa, _dsnext) \
	((*(_ah)->ah_proc_rx_desc)((_ah), (_ds), (_dspa), (_dsnext)))
#define	ath_hal_setup_tx_desc(_ah, _ds, _plen, _hlen, _atype, _txpow, \
	    _txr0, _txtr0, _keyix, _ant, _flags, \
	    _rtsrate, _rtsdura) \
	((*(_ah)->ah_setup_tx_desc)((_ah), (_ds), (_plen), (_hlen), (_atype), \
	    (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \
	    (_flags), (_rtsrate), (_rtsdura)))
#define	ath_hal_setup_xtx_desc(_ah, _ds, \
	    _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \
	((*(_ah)->ah_setup_xtx_desc)((_ah), (_ds), \
	    (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3)))
#define	ath_hal_fill_tx_desc(_ah, _ds, _l, _first, _last) \
	((*(_ah)->ah_fill_tx_desc)((_ah), (_ds), (_l), (_first), (_last)))
#define	ath_hal_proc_tx_desc(_ah, _ds) \
	((*(_ah)->ah_proc_tx_desc)((_ah), (_ds)))

#endif /* _KERNEL */

#define	SIOCGATHSTATS	_IOWR('i', 137, struct ifreq)

#endif /* _DEV_ATH_ATHVAR_H */