code:
/*	$OpenBSD: if_sq.c,v 1.14 2015/06/24 09:40:53 mpi Exp $	*/
/*	$NetBSD: if_sq.c,v 1.42 2011/07/01 18:53:47 dyoung Exp $	*/

/*
 * Copyright (c) 2001 Rafal K. Boni
 * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc.
 * All rights reserved.
 *
 * Portions of this code are derived from software contributed to The
 * NetBSD Foundation by Jason R. Thorpe of the Numerical Aerospace
 * Simulation Facility, NASA Ames Research Center.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include "bpfilter.h"

#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <sys/timeout.h>
#include <sys/mbuf.h>
#include <sys/pool.h>
#include <sys/kernel.h>
#include <sys/socket.h>
#include <sys/ioctl.h>
#include <sys/errno.h>
#include <sys/syslog.h>

#include <uvm/uvm_extern.h>

#include <net/if.h>
#include <net/if_dl.h>
#include <net/if_media.h>
#include <net/if_types.h>

#if NBPFILTER > 0
#include <net/bpf.h>
#endif

#include <netinet/in.h>
#include <netinet/if_ether.h>

#include <machine/autoconf.h>
#include <machine/bus.h>
#include <machine/cpu.h>	/* guarded_read_4 */
#include <machine/intr.h>
#include <mips64/arcbios.h>	/* bios_enaddr */
#include <sgi/sgi/ip22.h>

#include <dev/ic/seeq8003reg.h>

#include <sgi/hpc/hpcvar.h>
#include <sgi/hpc/hpcreg.h>
#include <sgi/hpc/iocreg.h>	/* IOC_READ / IOC_WRITE */
#include <sgi/hpc/if_sqvar.h>

/*
 * Short TODO list:
 *	(1) Do counters for bad-RX packets.
 *	(2) Allow multi-segment transmits, instead of copying to a single,
 *	    contiguous mbuf.
 *	(3) Verify sq_stop() turns off enough stuff; I was still getting
 *	    seeq interrupts after sq_stop().
 *	(5) Should the driver filter out its own transmissions in non-EDLC
 *	    mode?
 *	(6) Multicast support -- multicast filter, address management, ...
 *	(7) Deal with RB0 (recv buffer overflow) on reception.  Will need
 *	    to figure out if RB0 is read-only as stated in one spot in the
 *	    HPC spec or read-write (ie, is the 'write a one to clear it')
 *	    the correct thing?
 *
 * Note that it is no use to implement EDLC auto-padding: the HPC glue will
 * not start a packet transfer until it has been fed 64 bytes, which defeats
 * the auto-padding purpose.
 */

#ifdef SQ_DEBUG
int sq_debug = 0;
#define SQ_DPRINTF(x) do { if (sq_debug) printf x; } while (0)
#else
#define SQ_DPRINTF(x) do { } while (0)
#endif

int	sq_match(struct device *, void *, void *);
void	sq_attach(struct device *, struct device *, void *);
int	sq_init(struct ifnet *);
void	sq_start(struct ifnet *);
void	sq_stop(struct ifnet *);
void	sq_watchdog(struct ifnet *);
int	sq_ioctl(struct ifnet *, u_long, caddr_t);

void	sq_set_filter(struct sq_softc *);
int	sq_intr(void *);
void	sq_rxintr(struct sq_softc *);
void	sq_txintr(struct sq_softc *);
void	sq_txring_hpc1(struct sq_softc *);
void	sq_txring_hpc3(struct sq_softc *);
void	sq_reset(struct sq_softc *);
int	sq_add_rxbuf(struct sq_softc *, int);
#ifdef SQ_DEBUG
void	sq_trace_dump(struct sq_softc *);
#endif

int	sq_ifmedia_change_ip22(struct ifnet *);
int	sq_ifmedia_change_singlemedia(struct ifnet *);
void	sq_ifmedia_status_ip22(struct ifnet *, struct ifmediareq *);
void	sq_ifmedia_status_singlemedia(struct ifnet *, struct ifmediareq *);

const struct cfattach sq_ca = {
	sizeof(struct sq_softc), sq_match, sq_attach
};

struct cfdriver sq_cd = {
	NULL, "sq", DV_IFNET
};

/* XXX these values should be moved to <net/if_ether.h> ? */
#define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN)

#define sq_seeq_read(sc, off) \
	bus_space_read_1(sc->sc_regt, sc->sc_regh, ((off) << 2) | 3)
#define sq_seeq_write(sc, off, val) \
	bus_space_write_1(sc->sc_regt, sc->sc_regh, ((off) << 2) | 3, val)

#define sq_hpc_read(sc, off) \
	bus_space_read_4(sc->sc_hpct, sc->sc_hpch, off)
#define sq_hpc_write(sc, off, val) \
	bus_space_write_4(sc->sc_hpct, sc->sc_hpch, off, val)

/* MAC address offset for non-onboard implementations */
#define SQ_HPC_EEPROM_ENADDR	250

#define SGI_OUI_0		0x08
#define SGI_OUI_1		0x00
#define SGI_OUI_2		0x69

int
sq_match(struct device *parent, void *vcf, void *aux)
{
	struct hpc_attach_args *ha = aux;
	struct cfdata *cf = vcf;
	vaddr_t reset, txstat;
	uint32_t dummy;

	if (strcmp(ha->ha_name, cf->cf_driver->cd_name) != 0)
		return 0;

	reset = PHYS_TO_XKPHYS(ha->ha_sh + ha->ha_dmaoff +
	    ha->hpc_regs->enetr_reset, CCA_NC);
	txstat = PHYS_TO_XKPHYS(ha->ha_sh + ha->ha_devoff + (SEEQ_TXSTAT << 2),
	    CCA_NC);

	if (guarded_read_4(reset, &dummy) != 0)
		return 0;

	*(volatile uint32_t *)reset = 0x1;
	delay(20);
	*(volatile uint32_t *)reset = 0x0;

	if (guarded_read_4(txstat, &dummy) != 0)
		return 0;

	if ((*(volatile uint32_t *)txstat & 0xff) != TXSTAT_OLDNEW)
		return 0;

	return 1;
}

void
sq_attach(struct device *parent, struct device *self, void *aux)
{
	struct sq_softc *sc = (struct sq_softc *)self;
	struct hpc_attach_args *haa = aux;
	struct ifnet *ifp = &sc->sc_ac.ac_if;
	int media;
	int i, rc;

	sc->sc_hpct = haa->ha_st;
	sc->sc_hpcbh = haa->ha_sh;
	sc->hpc_regs = haa->hpc_regs;      /* HPC register definitions */

	if ((rc = bus_space_subregion(haa->ha_st, haa->ha_sh,
	    haa->ha_dmaoff, sc->hpc_regs->enet_regs_size,
	    &sc->sc_hpch)) != 0) {
		printf(": can't map HPC DMA registers, error = %d\n", rc);
		goto fail_0;
	}

	sc->sc_regt = haa->ha_st;
	if ((rc = bus_space_subregion(haa->ha_st, haa->ha_sh,
	    haa->ha_devoff, sc->hpc_regs->enet_devregs_size,
	    &sc->sc_regh)) != 0) {
		printf(": can't map Seeq registers, error = %d\n", rc);
		goto fail_0;
	}

	sc->sc_dmat = haa->ha_dmat;

	if ((rc = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct sq_control),
	    0, 0, &sc->sc_cdseg, 1, &sc->sc_ncdseg, BUS_DMA_NOWAIT)) != 0) {
		printf(": unable to allocate control data, error = %d\n", rc);
		goto fail_0;
	}

	/*
	 * Note that we need to pass BUS_DMA_BUS1 in order to get this
	 * allocation to succeed on ECC MC systems. This code is
	 * uncached-write safe, as all updates of the DMA descriptors are
	 * handled in RCU style with hpc_{read,write}_dma_desc().
	 */
	if ((rc = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_ncdseg,
	    sizeof(struct sq_control), (caddr_t *)&sc->sc_control,
	    BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_BUS1)) != 0) {
		printf(": unable to map control data, error = %d\n", rc);
		goto fail_1;
	}

	if ((rc = bus_dmamap_create(sc->sc_dmat,
	    sizeof(struct sq_control), 1, sizeof(struct sq_control),
	    0, BUS_DMA_NOWAIT, &sc->sc_cdmap)) != 0) {
		printf(": unable to create DMA map for control data, error "
		    "= %d\n", rc);
		goto fail_2;
	}

	if ((rc = bus_dmamap_load(sc->sc_dmat, sc->sc_cdmap,
	    sc->sc_control, sizeof(struct sq_control), NULL,
	    BUS_DMA_NOWAIT)) != 0) {
		printf(": unable to load DMA map for control data, error "
		    "= %d\n", rc);
		goto fail_3;
	}

	memset(sc->sc_control, 0, sizeof(struct sq_control));

	/* Create transmit buffer DMA maps */
	for (i = 0; i < SQ_NTXDESC; i++) {
		if ((rc = bus_dmamap_create(sc->sc_dmat,
		    MCLBYTES, 1, MCLBYTES, 0,
		    BUS_DMA_NOWAIT, &sc->sc_txmap[i])) != 0) {
			printf(": unable to create tx DMA map %d, error = %d\n",
			    i, rc);
			goto fail_4;
		}
	}

	/* Create receive buffer DMA maps */
	for (i = 0; i < SQ_NRXDESC; i++) {
		if ((rc = bus_dmamap_create(sc->sc_dmat,
		    MCLBYTES, 1, MCLBYTES, 0,
		    BUS_DMA_NOWAIT, &sc->sc_rxmap[i])) != 0) {
			printf(": unable to create rx DMA map %d, error = %d\n",
			    i, rc);
			goto fail_5;
		}
	}

	/* Pre-allocate the receive buffers.  */
	for (i = 0; i < SQ_NRXDESC; i++) {
		if ((rc = sq_add_rxbuf(sc, i)) != 0) {
			printf(": unable to allocate or map rx buffer %d\n,"
			    " error = %d\n", i, rc);
			goto fail_6;
		}
	}

	bcopy(&haa->hpc_eeprom[SQ_HPC_EEPROM_ENADDR], sc->sc_ac.ac_enaddr,
	    ETHER_ADDR_LEN);

	/*
	 * If our mac address is bogus, obtain it from ARCBIOS. This will
	 * be true of the onboard HPC3 on IP22, since there is no eeprom,
	 * but rather the DS1386 RTC's battery-backed ram is used.
	 */
	if (sc->sc_ac.ac_enaddr[0] != SGI_OUI_0 ||
	    sc->sc_ac.ac_enaddr[1] != SGI_OUI_1 ||
	    sc->sc_ac.ac_enaddr[2] != SGI_OUI_2)
		enaddr_aton(bios_enaddr, sc->sc_ac.ac_enaddr);

	if ((hpc_intr_establish(haa->ha_irq, IPL_NET, sq_intr, sc,
	    self->dv_xname)) == NULL) {
		printf(": unable to establish interrupt!\n");
		goto fail_6;
	}

	/*
	 * Set up HPC Ethernet PIO and DMA configurations.
	 *
	 * The PROM appears to do most of this for the onboard HPC3, but
	 * not for the Challenge S's IOPLUS chip. We copy how the onboard
	 * chip is configured and assume that it's correct for both.
	 */
	if (haa->hpc_regs->revision == 3 &&
	    sys_config.system_subtype != IP22_INDIGO2) {
		uint32_t dmareg, pioreg;

		if (haa->ha_giofast) {
			pioreg =
			    HPC3_ENETR_PIOCFG_P1(1) |
			    HPC3_ENETR_PIOCFG_P2(5) |
			    HPC3_ENETR_PIOCFG_P3(0);
			dmareg =
			    HPC3_ENETR_DMACFG_D1(5) |
			    HPC3_ENETR_DMACFG_D2(1) |
			    HPC3_ENETR_DMACFG_D3(0);
		} else {
			pioreg =
			    HPC3_ENETR_PIOCFG_P1(1) |
			    HPC3_ENETR_PIOCFG_P2(6) |
			    HPC3_ENETR_PIOCFG_P3(1);
			dmareg =
			    HPC3_ENETR_DMACFG_D1(6) |
			    HPC3_ENETR_DMACFG_D2(2) |
			    HPC3_ENETR_DMACFG_D3(0);
		}
		dmareg |= HPC3_ENETR_DMACFG_FIX_RXDC |
		    HPC3_ENETR_DMACFG_FIX_INTR | HPC3_ENETR_DMACFG_FIX_EOP |
		    HPC3_ENETR_DMACFG_TIMEOUT;

		sq_hpc_write(sc, HPC3_ENETR_PIOCFG, pioreg);
		sq_hpc_write(sc, HPC3_ENETR_DMACFG, dmareg);
	}

	/* Reset the chip to a known state. */
	sq_reset(sc);

	/*
	 * Determine if we're an 8003 or 80c03 by setting the first
	 * MAC address register to non-zero, and then reading it back.
	 * If it's zero, we have an 80c03, because we will have read
	 * the TxCollLSB register.
	 */
	sq_seeq_write(sc, SEEQ_TXCOLLS0, 0xa5);
	if (sq_seeq_read(sc, SEEQ_TXCOLLS0) == 0)
		sc->sc_type = SQ_TYPE_80C03;
	else
		sc->sc_type = SQ_TYPE_8003;
	sq_seeq_write(sc, SEEQ_TXCOLLS0, 0x00);

	printf(": Seeq %s, address %s\n",
	    sc->sc_type == SQ_TYPE_80C03 ? "80c03" : "8003",
	    ether_sprintf(sc->sc_ac.ac_enaddr));

	bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ);
	ifp->if_softc = sc;
	ifp->if_start = sq_start;
	ifp->if_ioctl = sq_ioctl;
	ifp->if_watchdog = sq_watchdog;
	ifp->if_flags = IFF_BROADCAST | IFF_NOTRAILERS | IFF_MULTICAST;
	IFQ_SET_READY(&ifp->if_snd);

	if_attach(ifp);
	IFQ_SET_MAXLEN(&ifp->if_snd, SQ_NTXDESC - 1);
	ether_ifattach(ifp);

	if (haa->hpc_regs->revision == 3) {
		uint8_t mask, set;
		if (/* sys_config.system_type != SGI_IP20 && */ /* implied */
		    sys_config.system_subtype == IP22_CHALLS) {
			/*
			 * Challenge S: onboard has AUI connector only,
			 * IO+ has TP connector only.
			 */
			if (haa->ha_base == HPC_BASE_ADDRESS_0) {
				ifmedia_init(&sc->sc_ifmedia, 0,
				    sq_ifmedia_change_singlemedia,
				    sq_ifmedia_status_singlemedia);
				/*
				 * Force 10Base5.
				 */
				media = IFM_ETHER | IFM_10_5;
				mask = IOC_WRITE_ENET_AUTO;
				set = IOC_WRITE_ENET_AUI;
			} else {
				ifmedia_init(&sc->sc_ifmedia, 0,
				    sq_ifmedia_change_singlemedia,
				    sq_ifmedia_status_singlemedia);
				/*
				 * Force 10BaseT, and set the 10BaseT port
				 * to use UTP cable.
				 */
				media = IFM_ETHER | IFM_10_T;
				mask = set = 0;
			}
		} else {
			/*
			 * Indy, Indigo 2: onboard has AUI and TP connectors.
			 */
			ifmedia_init(&sc->sc_ifmedia, 0,
			    sq_ifmedia_change_ip22, sq_ifmedia_status_ip22);
			ifmedia_add(&sc->sc_ifmedia,
			    IFM_ETHER | IFM_10_5, 0, NULL);
			ifmedia_add(&sc->sc_ifmedia,
			    IFM_ETHER | IFM_10_T, 0, NULL);

			/*
			 * Force autoselect, and set the the 10BaseT port
			 * to use UTP cable.
			 */
			media = IFM_ETHER | IFM_AUTO;
			mask = IOC_WRITE_ENET_AUI;
			set = IOC_WRITE_ENET_AUTO | IOC_WRITE_ENET_UTP;
		}

		if (haa->ha_base == HPC_BASE_ADDRESS_0) {
			bus_space_write_4(haa->ha_st, haa->ha_sh,
			    IOC_BASE + IOC_WRITE,
			    (bus_space_read_4(haa->ha_st, haa->ha_sh,
			      IOC_BASE + IOC_WRITE) & ~mask) | set);
			bus_space_barrier(haa->ha_st, haa->ha_sh,
			    IOC_BASE + IOC_WRITE, 4,
			    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
		}
	} else {
		/*
		 * HPC1/1.5: IP20 on-board, or E++: AUI connector only,
		 * and career information unreliable.
		 */
		ifmedia_init(&sc->sc_ifmedia, 0,
		    sq_ifmedia_change_singlemedia,
		    sq_ifmedia_status_singlemedia);
		media = IFM_ETHER | IFM_10_5;
		sc->sc_flags |= SQF_NOLINKDOWN;
	}

	ifmedia_add(&sc->sc_ifmedia, media, 0, NULL);
	ifmedia_set(&sc->sc_ifmedia, media);

	/* supposedly connected, until TX says otherwise */
	sc->sc_flags |= SQF_LINKUP;

	/* Done! */
	return;

	/*
	 * Free any resources we've allocated during the failed attach
	 * attempt.  Do this in reverse order and fall through.
	 */
 fail_6:
	for (i = 0; i < SQ_NRXDESC; i++) {
		if (sc->sc_rxmbuf[i] != NULL) {
			bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmap[i]);
			m_freem(sc->sc_rxmbuf[i]);
		}
	}
 fail_5:
	for (i = 0; i < SQ_NRXDESC; i++) {
		if (sc->sc_rxmap[i] != NULL)
			bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmap[i]);
	}
 fail_4:
	for (i = 0; i < SQ_NTXDESC; i++) {
		if (sc->sc_txmap[i] !=  NULL)
			bus_dmamap_destroy(sc->sc_dmat, sc->sc_txmap[i]);
	}
	bus_dmamap_unload(sc->sc_dmat, sc->sc_cdmap);
 fail_3:
	bus_dmamap_destroy(sc->sc_dmat, sc->sc_cdmap);
 fail_2:
	bus_dmamem_unmap(sc->sc_dmat,
	    (void *)sc->sc_control, sizeof(struct sq_control));
 fail_1:
	bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_ncdseg);
 fail_0:
	return;
}

/* Set up data to get the interface up and running. */
int
sq_init(struct ifnet *ifp)
{
	struct sq_softc *sc = ifp->if_softc;
	int i;

	/* Cancel any in-progress I/O */
	sq_stop(ifp);

	sc->sc_nextrx = 0;

	sc->sc_nfreetx = SQ_NTXDESC;
	sc->sc_nexttx = sc->sc_prevtx = 0;

	SQ_TRACE(SQ_RESET, sc, 0, 0);

	/* Set into 8003 or 80C03 mode, bank 0 to program Ethernet address */
	if (sc->sc_type == SQ_TYPE_80C03)
		sq_seeq_write(sc, SEEQ_TXCMD, TXCMD_ENABLE_C);
	sq_seeq_write(sc, SEEQ_TXCMD, TXCMD_BANK0);

	/* Now write the address */
	for (i = 0; i < ETHER_ADDR_LEN; i++)
		sq_seeq_write(sc, i, sc->sc_ac.ac_enaddr[i]);

	sc->sc_rxcmd = RXCMD_IE_CRC | RXCMD_IE_DRIB | RXCMD_IE_SHORT |
	    RXCMD_IE_END | RXCMD_IE_GOOD;

	/*
	 * Set the receive filter -- this will add some bits to the
	 * prototype RXCMD register.  Do this before setting the
	 * transmit config register, since we might need to switch
	 * banks.
	 */
	sq_set_filter(sc);

	if (sc->sc_type == SQ_TYPE_80C03) {
		sq_seeq_write(sc, SEEQ_TXCMD, TXCMD_BANK2);
		sq_seeq_write(sc, SEEQ_TXCTRL, 0);
		sq_seeq_write(sc, SEEQ_TXCTRL, TXCTRL_SQE | TXCTRL_NOCARR);
#if 0 /* HPC expects a minimal packet size of ETHER_MIN_LEN anyway */
		sq_seeq_write(sc, SEEQ_CFG, CFG_TX_AUTOPAD);
#endif
		sq_seeq_write(sc, SEEQ_TXCMD, TXCMD_BANK0);
	}

	/* Set up Seeq transmit command register */
	sc->sc_txcmd =
	    TXCMD_IE_UFLOW | TXCMD_IE_COLL | TXCMD_IE_16COLL | TXCMD_IE_GOOD;
	sq_seeq_write(sc, SEEQ_TXCMD, sc->sc_txcmd);

	/* Now write the receive command register. */
	sq_seeq_write(sc, SEEQ_RXCMD, sc->sc_rxcmd);

	/* Pass the start of the receive ring to the HPC */
	sq_hpc_write(sc, sc->hpc_regs->enetr_ndbp, SQ_CDRXADDR(sc, 0));

	/* And turn on the HPC Ethernet receive channel */
	sq_hpc_write(sc, sc->hpc_regs->enetr_ctl,
	    sc->hpc_regs->enetr_ctl_active);

	/*
	 * Turn off delayed receive interrupts on HPC1.
	 * (see Hollywood HPC Specification 2.1.4.3)
	 */
	if (sc->hpc_regs->revision != 3)
		sq_hpc_write(sc, HPC1_ENET_INTDELAY, HPC1_ENET_INTDELAY_OFF);

	ifp->if_flags |= IFF_RUNNING;
	ifp->if_flags &= ~IFF_OACTIVE;
	sq_start(ifp);

	return 0;
}

void
sq_set_filter(struct sq_softc *sc)
{
	struct arpcom *ac = &sc->sc_ac;
	struct ifnet *ifp = &sc->sc_ac.ac_if;

	sc->sc_rxcmd &= ~RXCMD_REC_MASK;
	ifp->if_flags &= ~IFF_ALLMULTI;

	/*
	 * The 8003 has no hash table.  If we have any multicast
	 * addresses on the list, enable reception of all multicast
	 * frames.
	 *
	 * XXX The 80c03 has a hash table.  We should use it.
	 */
	if (ifp->if_flags & IFF_PROMISC || ac->ac_multicnt > 0) {
		ifp->if_flags |= IFF_ALLMULTI;
		if (ifp->if_flags & IFF_PROMISC)
			sc->sc_rxcmd |= RXCMD_REC_ALL;
		else
			sc->sc_rxcmd |= RXCMD_REC_MULTI;
	}

	/*
	 * Unless otherwise specified, always accept broadcast frames.
	 */
	if ((sc->sc_rxcmd & ~RXCMD_REC_MASK) == RXCMD_REC_NONE)
		sc->sc_rxcmd |= RXCMD_REC_BROAD;
}

int
sq_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
{
	struct sq_softc *sc = ifp->if_softc;
	struct ifaddr *ifa = (struct ifaddr *)data;
	struct ifreq *ifr = (struct ifreq *)data;
	int s, error = 0;

	SQ_TRACE(SQ_IOCTL, sc, 0, 0);

	s = splnet();

	switch (cmd) {
	case SIOCSIFADDR:
		ifp->if_flags |= IFF_UP;
		if (!(ifp->if_flags & IFF_RUNNING))
			sq_init(ifp);
		if (ifa->ifa_addr->sa_family == AF_INET)
			arp_ifinit(&sc->sc_ac, ifa);
		break;

	case SIOCSIFMEDIA:
	case SIOCGIFMEDIA:
		error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, cmd);
		break;

	case SIOCSIFFLAGS:
		if (ifp->if_flags & IFF_UP) {
			if (ifp->if_flags & IFF_RUNNING)
				error = ENETRESET;
			else
				sq_init(ifp);
		} else {
			if (ifp->if_flags & IFF_RUNNING)
				sq_stop(ifp);
		}
		break;

	default:
		error = ether_ioctl(ifp, &sc->sc_ac, cmd, data);
		break;
	}

	if (error == ENETRESET) {
		/*
		 * Multicast list has changed; set the hardware filter
		 * accordingly.
		 */
		if (ifp->if_flags & IFF_RUNNING)
			error = sq_init(ifp);
		else
			error = 0;
	}

	splx(s);
	return error;
}

void
sq_start(struct ifnet *ifp)
{
	struct sq_softc *sc = ifp->if_softc;
	struct mbuf *m0, *m;
	struct hpc_dma_desc *txd, txd_store;
	bus_dmamap_t dmamap;
	uint32_t status;
	int err, len, totlen, nexttx, firsttx, lasttx = -1, ofree, seg;

	if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING)
		return;

	/*
	 * Remember the previous number of free descriptors and
	 * the first descriptor we'll use.
	 */
	ofree = sc->sc_nfreetx;
	firsttx = sc->sc_nexttx;

	/*
	 * Loop through the send queue, setting up transmit descriptors
	 * until we drain the queue, or use up all available transmit
	 * descriptors.
	 */
	while (sc->sc_nfreetx != 0) {
		/*
		 * Grab a packet off the queue.
		 */
		IFQ_POLL(&ifp->if_snd, m0);
		if (m0 == NULL)
			break;
		m = NULL;

		dmamap = sc->sc_txmap[sc->sc_nexttx];

		/*
		 * Load the DMA map.  If this fails, the packet either
		 * didn't fit in the alloted number of segments, or we were
		 * short on resources.  In this case, we'll copy and try
		 * again.
		 * Also copy it if we need to pad, so that we are sure there
		 * is room for the pad buffer.
		 * XXX the right way of doing this is to use a static buffer
		 * for padding and adding it to the transmit descriptor (see
		 * sys/dev/pci/if_tl.c for example). We can't do this here yet
		 * because we can't send packets with more than one fragment.
		 */
		len = m0->m_pkthdr.len;
		if (len < ETHER_PAD_LEN ||
		    bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0,
		    BUS_DMA_NOWAIT) != 0) {
			MGETHDR(m, M_DONTWAIT, MT_DATA);
			if (m == NULL) {
				printf("%s: unable to allocate Tx mbuf\n",
				    sc->sc_dev.dv_xname);
				break;
			}
			if (len > MHLEN) {
				MCLGET(m, M_DONTWAIT);
				if ((m->m_flags & M_EXT) == 0) {
					printf("%s: unable to allocate Tx "
					    "cluster\n",
					    sc->sc_dev.dv_xname);
					m_freem(m);
					break;
				}
			}

			m_copydata(m0, 0, len, mtod(m, void *));
			if (len < ETHER_PAD_LEN /* &&
			    sc->sc_type != SQ_TYPE_80C03 */) {
				memset(mtod(m, char *) + len, 0,
				    ETHER_PAD_LEN - len);
				len = ETHER_PAD_LEN;
			}
			m->m_pkthdr.len = m->m_len = len;

			if ((err = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap,
			    m, BUS_DMA_NOWAIT)) != 0) {
				printf("%s: unable to load Tx buffer, "
				    "error = %d\n",
				    sc->sc_dev.dv_xname, err);
				break;
			}
		}

		/*
		 * Ensure we have enough descriptors free to describe
		 * the packet.
		 */
		if (dmamap->dm_nsegs > sc->sc_nfreetx) {
			/*
			 * Not enough free descriptors to transmit this
			 * packet.  We haven't committed to anything yet,
			 * so just unload the DMA map, put the packet
			 * back on the queue, and punt.  Notify the upper
			 * layer that there are no more slots left.
			 *
			 * XXX We could allocate an mbuf and copy, but
			 * XXX it is worth it?
			 */
			ifp->if_flags |= IFF_OACTIVE;
			bus_dmamap_unload(sc->sc_dmat, dmamap);
			if (m != NULL)
				m_freem(m);
			break;
		}

		IFQ_DEQUEUE(&ifp->if_snd, m0);
#if NBPFILTER > 0
		/*
		 * Pass the packet to any BPF listeners.
		 */
		if (ifp->if_bpf)
			bpf_mtap(ifp->if_bpf, m0, BPF_DIRECTION_OUT);
#endif
		if (m != NULL) {
			m_freem(m0);
			m0 = m;
		}

		/*
		 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET.
		 */

		SQ_TRACE(SQ_ENQUEUE, sc, sc->sc_nexttx, 0);

		/* Sync the DMA map. */
		bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
		    BUS_DMASYNC_PREWRITE);

		/*
		 * Initialize the transmit descriptors.
		 */
		for (nexttx = sc->sc_nexttx, seg = 0, totlen = 0;
		     seg < dmamap->dm_nsegs;
		     seg++, nexttx = SQ_NEXTTX(nexttx)) {
			txd = hpc_read_dma_desc(sc->sc_txdesc + nexttx,
			    &txd_store);
			if (sc->hpc_regs->revision == 3) {
				txd->hpc3_hdd_bufptr =
				    dmamap->dm_segs[seg].ds_addr;
				txd->hpc3_hdd_ctl = dmamap->dm_segs[seg].ds_len;
			} else {
				txd->hpc1_hdd_bufptr =
				    dmamap->dm_segs[seg].ds_addr;
				txd->hpc1_hdd_ctl = dmamap->dm_segs[seg].ds_len;
			}
			txd->hdd_descptr = SQ_CDTXADDR(sc, SQ_NEXTTX(nexttx));
			hpc_write_dma_desc(sc->sc_txdesc + nexttx, txd);
			lasttx = nexttx;
			totlen += dmamap->dm_segs[seg].ds_len;
		}

		/* Last descriptor gets end-of-packet */
		KASSERT(lasttx != -1);
		/* txd = hpc_read_dma_desc(sc->sc_txdesc + lasttx, &txd_store); */
		if (sc->hpc_regs->revision == 3)
			txd->hpc3_hdd_ctl |= HPC3_HDD_CTL_EOPACKET;
		else
			txd->hpc1_hdd_ctl |= HPC1_HDD_CTL_EOPACKET;
		hpc_write_dma_desc(sc->sc_txdesc + lasttx, txd);

		SQ_DPRINTF(("%s: transmit %d-%d, len %d\n",
		    sc->sc_dev.dv_xname, sc->sc_nexttx, lasttx, totlen));

		if (ifp->if_flags & IFF_DEBUG) {
			printf("     transmit chain:\n");
			for (seg = sc->sc_nexttx;; seg = SQ_NEXTTX(seg)) {
				printf("     descriptor %d:\n", seg);
				printf("       hdd_bufptr:      0x%08x\n",
				    (sc->hpc_regs->revision == 3) ?
				    sc->sc_txdesc[seg].hpc3_hdd_bufptr :
				    sc->sc_txdesc[seg].hpc1_hdd_bufptr);
				printf("       hdd_ctl: 0x%08x\n",
				    (sc->hpc_regs->revision == 3) ?
				    sc->sc_txdesc[seg].hpc3_hdd_ctl:
				    sc->sc_txdesc[seg].hpc1_hdd_ctl);
				printf("       hdd_descptr:      0x%08x\n",
				    sc->sc_txdesc[seg].hdd_descptr);

				if (seg == lasttx)
					break;
			}
		}

		/* Sync the descriptors we're using. */
		SQ_CDTXSYNC(sc, sc->sc_nexttx, dmamap->dm_nsegs,
		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);

		/* Store a pointer to the packet so we can free it later */
		sc->sc_txmbuf[sc->sc_nexttx] = m0;

		/* Advance the tx pointer. */
		sc->sc_nfreetx -= dmamap->dm_nsegs;
		sc->sc_nexttx = nexttx;
	}

	/* All transmit descriptors used up, let upper layers know */
	if (sc->sc_nfreetx == 0)
		ifp->if_flags |= IFF_OACTIVE;

	if (sc->sc_nfreetx != ofree) {
		SQ_DPRINTF(("%s: %d packets enqueued, first %d, INTR on %d\n",
		    sc->sc_dev.dv_xname, lasttx - firsttx + 1,
		    firsttx, lasttx));

		/*
		 * Cause a transmit interrupt to happen on the
		 * last packet we enqueued, mark it as the last
		 * descriptor.
		 *
		 * HPC1_HDD_CTL_INTR will generate an interrupt on
		 * HPC1. HPC3 requires HPC3_HDD_CTL_EOCHAIN in
		 * addition to HPC3_HDD_CTL_INTR to interrupt.
		 */
		KASSERT(lasttx != -1);
		txd = hpc_read_dma_desc(sc->sc_txdesc + lasttx, &txd_store);
		if (sc->hpc_regs->revision == 3) {
			txd->hpc3_hdd_ctl |=
			    HPC3_HDD_CTL_INTR | HPC3_HDD_CTL_EOCHAIN;
		} else {
			txd->hpc1_hdd_ctl |= HPC1_HDD_CTL_INTR;
			txd->hpc1_hdd_bufptr |= HPC1_HDD_CTL_EOCHAIN;
		}
		hpc_write_dma_desc(sc->sc_txdesc + lasttx, txd);
		SQ_CDTXSYNC(sc, lasttx, 1,
		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);

		/*
		 * There is a potential race condition here if the HPC
		 * DMA channel is active and we try and either update
		 * the 'next descriptor' pointer in the HPC PIO space
		 * or the 'next descriptor' pointer in a previous desc-
		 * riptor.
		 *
		 * To avoid this, if the channel is active, we rely on
		 * the transmit interrupt routine noticing that there
		 * are more packets to send and restarting the HPC DMA
		 * engine, rather than mucking with the DMA state here.
		 */
		status = sq_hpc_read(sc, sc->hpc_regs->enetx_ctl);

		if ((status & sc->hpc_regs->enetx_ctl_active) != 0) {
			SQ_TRACE(SQ_ADD_TO_DMA, sc, firsttx, status);

			txd = hpc_read_dma_desc(sc->sc_txdesc +
			    SQ_PREVTX(firsttx), &txd_store);
			/*
			 * NB: hpc3_hdd_ctl == hpc1_hdd_bufptr, and
			 * HPC1_HDD_CTL_EOCHAIN == HPC3_HDD_CTL_EOCHAIN
			 */
			txd->hpc3_hdd_ctl &= ~HPC3_HDD_CTL_EOCHAIN;
			if (sc->hpc_regs->revision != 3)
				txd->hpc1_hdd_ctl &= ~HPC1_HDD_CTL_INTR;

			hpc_write_dma_desc(sc->sc_txdesc + SQ_PREVTX(firsttx),
			    txd);
			SQ_CDTXSYNC(sc, SQ_PREVTX(firsttx),  1,
			    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
		} else if (sc->hpc_regs->revision == 3) {
			SQ_TRACE(SQ_START_DMA, sc, firsttx, status);

			sq_hpc_write(sc, HPC3_ENETX_NDBP, SQ_CDTXADDR(sc,
			    firsttx));

			/* Kick DMA channel into life */
			sq_hpc_write(sc, HPC3_ENETX_CTL, HPC3_ENETX_CTL_ACTIVE);
		} else {
			/*
			 * In the HPC1 case where transmit DMA is
			 * inactive, we can either kick off if
			 * the ring was previously empty, or call
			 * our transmit interrupt handler to
			 * figure out if the ring stopped short
			 * and restart at the right place.
			 */
			if (ofree == SQ_NTXDESC) {
				SQ_TRACE(SQ_START_DMA, sc, firsttx, status);

				sq_hpc_write(sc, HPC1_ENETX_NDBP,
				    SQ_CDTXADDR(sc, firsttx));
				sq_hpc_write(sc, HPC1_ENETX_CFXBP,
				    SQ_CDTXADDR(sc, firsttx));
				sq_hpc_write(sc, HPC1_ENETX_CBP,
				    SQ_CDTXADDR(sc, firsttx));

				/* Kick DMA channel into life */
				sq_hpc_write(sc, HPC1_ENETX_CTL,
				    HPC1_ENETX_CTL_ACTIVE);
			} else
				sq_txring_hpc1(sc);
		}

		/* Set a watchdog timer in case the chip flakes out. */
		ifp->if_timer = 5;
	}
}

void
sq_stop(struct ifnet *ifp)
{
	struct sq_softc *sc = ifp->if_softc;
	int i;

	ifp->if_timer = 0;
	ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);

	for (i = 0; i < SQ_NTXDESC; i++) {
		if (sc->sc_txmbuf[i] != NULL) {
			bus_dmamap_unload(sc->sc_dmat, sc->sc_txmap[i]);
			m_freem(sc->sc_txmbuf[i]);
			sc->sc_txmbuf[i] = NULL;
		}
	}

	/* Clear Seeq transmit/receive command registers */
	sc->sc_txcmd = 0;
	sq_seeq_write(sc, SEEQ_TXCMD, 0);
	sq_seeq_write(sc, SEEQ_RXCMD, 0);

	sq_reset(sc);
}

/* Device timeout/watchdog routine. */
void
sq_watchdog(struct ifnet *ifp)
{
	struct sq_softc *sc = ifp->if_softc;
	uint32_t status;

	status = sq_hpc_read(sc, sc->hpc_regs->enetx_ctl);
	log(LOG_ERR, "%s: device timeout (prev %d, next %d, free %d, "
	    "status %08x)\n", sc->sc_dev.dv_xname, sc->sc_prevtx,
	    sc->sc_nexttx, sc->sc_nfreetx, status);

#ifdef SQ_DEBUG
	sq_trace_dump(sc);
#endif

	++ifp->if_oerrors;

	sq_init(ifp);
}

#ifdef SQ_DEBUG
void
sq_trace_dump(struct sq_softc *sc)
{
	int i;
	const char *act;

	for (i = 0; i < sc->sq_trace_idx; i++) {
		switch (sc->sq_trace[i].action) {
		case SQ_RESET:		act = "SQ_RESET";		break;
		case SQ_ADD_TO_DMA:	act = "SQ_ADD_TO_DMA";		break;
		case SQ_START_DMA:	act = "SQ_START_DMA";		break;
		case SQ_DONE_DMA:	act = "SQ_DONE_DMA";		break;
		case SQ_RESTART_DMA:	act = "SQ_RESTART_DMA";		break;
		case SQ_TXINTR_ENTER:	act = "SQ_TXINTR_ENTER";	break;
		case SQ_TXINTR_EXIT:	act = "SQ_TXINTR_EXIT";		break;
		case SQ_TXINTR_BUSY:	act = "SQ_TXINTR_BUSY";		break;
		case SQ_IOCTL:		act = "SQ_IOCTL";		break;
		case SQ_ENQUEUE:	act = "SQ_ENQUEUE";		break;
		default:		act = "UNKNOWN";
		}

		printf("%s: [%03d] action %-16s buf %03d free %03d "
		    "status %08x line %d\n", sc->sc_dev.dv_xname, i, act,
		    sc->sq_trace[i].bufno, sc->sq_trace[i].freebuf,
		    sc->sq_trace[i].status, sc->sq_trace[i].line);
	}

	memset(&sc->sq_trace, 0, sizeof(sc->sq_trace));
	sc->sq_trace_idx = 0;
}
#endif

int
sq_intr(void *arg)
{
	struct sq_softc *sc = arg;
	struct ifnet *ifp = &sc->sc_ac.ac_if;
	int oldlink = sc->sc_flags & SQF_LINKUP;
	uint32_t stat;
	uint8_t sqe;

	stat = sq_hpc_read(sc, sc->hpc_regs->enetr_reset);

	if ((stat & 2) == 0) {
		SQ_DPRINTF(("%s: Unexpected interrupt!\n",
		    sc->sc_dev.dv_xname));
	} else
		sq_hpc_write(sc, sc->hpc_regs->enetr_reset, (stat | 2));

	/*
	 * If the interface isn't running, the interrupt couldn't
	 * possibly have come from us.
	 */
	if ((ifp->if_flags & IFF_RUNNING) == 0)
		return 0;

	/*
	 * Check for loss of carrier detected during transmission if we
	 * can detect it.
	 * Unfortunately, this does not work on IP20 and E++ designs.
	 */
	if (sc->sc_type == SQ_TYPE_80C03 &&
	    !ISSET(sc->sc_flags, SQF_NOLINKDOWN)) {
		sqe = sq_seeq_read(sc, SEEQ_SQE) & (SQE_FLAG | SQE_NOCARR);
		if (sqe != 0) {
			sq_seeq_write(sc, SEEQ_TXCMD,
			    TXCMD_BANK2 | sc->sc_txcmd);
			/* reset counters */
			sq_seeq_write(sc, SEEQ_TXCTRL, 0);
			sq_seeq_write(sc, SEEQ_TXCTRL,
			    TXCTRL_SQE | TXCTRL_NOCARR);
			sq_seeq_write(sc, SEEQ_TXCMD,
			    TXCMD_BANK0 | sc->sc_txcmd);
			if (sqe == (SQE_FLAG | SQE_NOCARR))
				sc->sc_flags &= ~SQF_LINKUP;
		}
	}

	/* Always check for received packets */
	sq_rxintr(sc);

	/* Only handle transmit interrupts if we actually sent something */
	if (sc->sc_nfreetx < SQ_NTXDESC)
		sq_txintr(sc);

	/* Notify link status change */
	if (oldlink != (sc->sc_flags & SQF_LINKUP)) {
		if (oldlink != 0) {
			ifp->if_link_state = LINK_STATE_DOWN;
			ifp->if_baudrate = 0;
		} else {
			ifp->if_link_state = LINK_STATE_UP;
			ifp->if_baudrate = IF_Mbps(10);
		}
		if_link_state_change(ifp);
	}

	/*
	 * XXX Always claim the interrupt, even if we did nothing.
	 * XXX There seem to be extra interrupts when the receiver becomes
	 * XXX idle.
	 */
	return 1;
}

void
sq_rxintr(struct sq_softc *sc)
{
	struct ifnet *ifp = &sc->sc_ac.ac_if;
	struct mbuf_list ml = MBUF_LIST_INITIALIZER();
	struct mbuf* m;
	struct hpc_dma_desc *rxd, rxd_store;
	int i, framelen;
	uint8_t pktstat;
	uint32_t status;
	uint32_t ctl_reg;
	int new_end, orig_end;

	for (i = sc->sc_nextrx; ; i = SQ_NEXTRX(i)) {
		SQ_CDRXSYNC(sc, i,
		    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);

		/*
		 * If this is a CPU-owned buffer, we're at the end of the list.
		 */
		if (sc->hpc_regs->revision == 3)
			ctl_reg =
			    sc->sc_rxdesc[i].hpc3_hdd_ctl & HPC3_HDD_CTL_OWN;
		else
			ctl_reg =
			    sc->sc_rxdesc[i].hpc1_hdd_ctl & HPC1_HDD_CTL_OWN;

		if (ctl_reg) {
#if defined(SQ_DEBUG)
			uint32_t reg;

			reg = sq_hpc_read(sc, sc->hpc_regs->enetr_ctl);
			SQ_DPRINTF(("%s: rxintr: done at %d (ctl %08x)\n",
			    sc->sc_dev.dv_xname, i, reg));
#endif
			break;
		}

		m = sc->sc_rxmbuf[i];
		framelen = m->m_ext.ext_size - 3;
		if (sc->hpc_regs->revision == 3)
		    framelen -=
			HPC3_HDD_CTL_BYTECNT(sc->sc_rxdesc[i].hpc3_hdd_ctl);
		else
		    framelen -=
			HPC1_HDD_CTL_BYTECNT(sc->sc_rxdesc[i].hpc1_hdd_ctl);

		/* Now sync the actual packet data */
		bus_dmamap_sync(sc->sc_dmat, sc->sc_rxmap[i], 0,
		    sc->sc_rxmap[i]->dm_mapsize, BUS_DMASYNC_POSTREAD);

		pktstat = *((uint8_t *)m->m_data + framelen + 2);

		if ((pktstat & RXSTAT_GOOD) == 0) {
			ifp->if_ierrors++;

			if (pktstat & RXSTAT_OFLOW)
				printf("%s: receive FIFO overflow\n",
				    sc->sc_dev.dv_xname);

			bus_dmamap_sync(sc->sc_dmat, sc->sc_rxmap[i], 0,
			    sc->sc_rxmap[i]->dm_mapsize, BUS_DMASYNC_PREREAD);
			SQ_INIT_RXDESC(sc, i);
			SQ_DPRINTF(("%s: sq_rxintr: buf %d no RXSTAT_GOOD\n",
			    sc->sc_dev.dv_xname, i));
			continue;
		}

		/* Link must be good if we have received data. */
		sc->sc_flags |= SQF_LINKUP;

		if (sq_add_rxbuf(sc, i) != 0) {
			ifp->if_ierrors++;
			bus_dmamap_sync(sc->sc_dmat, sc->sc_rxmap[i], 0,
			    sc->sc_rxmap[i]->dm_mapsize, BUS_DMASYNC_PREREAD);
			SQ_INIT_RXDESC(sc, i);
			SQ_DPRINTF(("%s: sq_rxintr: buf %d sq_add_rxbuf() "
			    "failed\n", sc->sc_dev.dv_xname, i));
			continue;
		}

		m->m_data += 2;
		m->m_pkthdr.len = m->m_len = framelen;

		SQ_DPRINTF(("%s: sq_rxintr: buf %d len %d\n",
		    sc->sc_dev.dv_xname, i, framelen));

		ml_enqueue(&ml, m);
	}

	if_input(ifp, &ml);

	/* If anything happened, move ring start/end pointers to new spot */
	if (i != sc->sc_nextrx) {
		/*
		 * NB: hpc3_hdd_ctl == hpc1_hdd_bufptr, and
		 * HPC1_HDD_CTL_EOCHAIN == HPC3_HDD_CTL_EOCHAIN
		 */

		new_end = SQ_PREVRX(i);
		rxd = hpc_read_dma_desc(sc->sc_rxdesc + new_end, &rxd_store);
		rxd->hpc3_hdd_ctl |= HPC3_HDD_CTL_EOCHAIN;
		hpc_write_dma_desc(sc->sc_rxdesc + new_end, rxd);
		SQ_CDRXSYNC(sc, new_end,
		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);

		orig_end = SQ_PREVRX(sc->sc_nextrx);
		rxd = hpc_read_dma_desc(sc->sc_rxdesc + orig_end, &rxd_store);
		rxd->hpc3_hdd_ctl &= ~HPC3_HDD_CTL_EOCHAIN;
		hpc_write_dma_desc(sc->sc_rxdesc + orig_end, rxd);
		SQ_CDRXSYNC(sc, orig_end,
		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);

		sc->sc_nextrx = i;
	}

	status = sq_hpc_read(sc, sc->hpc_regs->enetr_ctl);

	/* If receive channel is stopped, restart it... */
	if ((status & sc->hpc_regs->enetr_ctl_active) == 0) {
		/* Pass the start of the receive ring to the HPC */
		sq_hpc_write(sc, sc->hpc_regs->enetr_ndbp,
		    SQ_CDRXADDR(sc, sc->sc_nextrx));

		/* And turn on the HPC Ethernet receive channel */
		sq_hpc_write(sc, sc->hpc_regs->enetr_ctl,
		    sc->hpc_regs->enetr_ctl_active);
	}
}

void
sq_txintr(struct sq_softc *sc)
{
	struct ifnet *ifp = &sc->sc_ac.ac_if;
	uint shift = 0;
	uint32_t status, tmp;

	if (sc->hpc_regs->revision != 3)
		shift = 16;

	status = sq_hpc_read(sc, sc->hpc_regs->enetx_ctl) >> shift;

	SQ_TRACE(SQ_TXINTR_ENTER, sc, sc->sc_prevtx, status);

	tmp = (sc->hpc_regs->enetx_ctl_active >> shift) | TXSTAT_GOOD;
	if ((status & tmp) == 0) {
		if (status & TXSTAT_COLL)
			ifp->if_collisions++;

		if (status & TXSTAT_UFLOW) {
			printf("%s: transmit underflow\n",
			    sc->sc_dev.dv_xname);
			ifp->if_oerrors++;
#ifdef SQ_DEBUG
			sq_trace_dump(sc);
#endif
			sq_init(ifp);
			return;
		}

		if (status & TXSTAT_16COLL) {
			if (ifp->if_flags & IFF_DEBUG)
				printf("%s: max collisions reached\n",
				    sc->sc_dev.dv_xname);
			ifp->if_oerrors++;
			ifp->if_collisions += 16;
		}
	}

	/* prevtx now points to next xmit packet not yet finished */
	if (sc->hpc_regs->revision == 3)
		sq_txring_hpc3(sc);
	else
		sq_txring_hpc1(sc);

	/* If we have buffers free, let upper layers know */
	if (sc->sc_nfreetx > 0)
		ifp->if_flags &= ~IFF_OACTIVE;

	/* If all packets have left the coop, cancel watchdog */
	if (sc->sc_nfreetx == SQ_NTXDESC)
		ifp->if_timer = 0;

	SQ_TRACE(SQ_TXINTR_EXIT, sc, sc->sc_prevtx, status);
	sq_start(ifp);
}

/*
 * Reclaim used transmit descriptors and restart the transmit DMA
 * engine if necessary.
 */
void
sq_txring_hpc1(struct sq_softc *sc)
{
	/*
	 * HPC1 doesn't tag transmitted descriptors, however,
	 * the NDBP register points to the next descriptor that
	 * has not yet been processed. If DMA is not in progress,
	 * we can safely reclaim all descriptors up to NDBP, and,
	 * if necessary, restart DMA at NDBP. Otherwise, if DMA
	 * is active, we can only safely reclaim up to CBP.
	 *
	 * For now, we'll only reclaim on inactive DMA and assume
	 * that a sufficiently large ring keeps us out of trouble.
	 */
	struct ifnet *ifp = &sc->sc_ac.ac_if;
	uint32_t reclaimto, status;
	int reclaimall, i = sc->sc_prevtx;

	status = sq_hpc_read(sc, HPC1_ENETX_CTL);
	if (status & HPC1_ENETX_CTL_ACTIVE) {
		SQ_TRACE(SQ_TXINTR_BUSY, sc, i, status);
		return;
	} else
		reclaimto = sq_hpc_read(sc, HPC1_ENETX_NDBP);

	if (sc->sc_nfreetx == 0 && SQ_CDTXADDR(sc, i) == reclaimto)
		reclaimall = 1;
	else
		reclaimall = 0;

	while (sc->sc_nfreetx < SQ_NTXDESC) {
		if (SQ_CDTXADDR(sc, i) == reclaimto && !reclaimall)
			break;

		SQ_CDTXSYNC(sc, i, sc->sc_txmap[i]->dm_nsegs,
		    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);

		/* Sync the packet data, unload DMA map, free mbuf */
		bus_dmamap_sync(sc->sc_dmat, sc->sc_txmap[i],
		    0, sc->sc_txmap[i]->dm_mapsize, BUS_DMASYNC_POSTWRITE);
		bus_dmamap_unload(sc->sc_dmat, sc->sc_txmap[i]);
		m_freem(sc->sc_txmbuf[i]);
		sc->sc_txmbuf[i] = NULL;

		ifp->if_opackets++;
		sc->sc_nfreetx++;

		SQ_TRACE(SQ_DONE_DMA, sc, i, status);

		i = SQ_NEXTTX(i);
	}

	if (sc->sc_nfreetx < SQ_NTXDESC) {
		SQ_TRACE(SQ_RESTART_DMA, sc, i, status);

		KASSERT(reclaimto == SQ_CDTXADDR(sc, i));

		sq_hpc_write(sc, HPC1_ENETX_CFXBP, reclaimto);
		sq_hpc_write(sc, HPC1_ENETX_CBP, reclaimto);

		/* Kick DMA channel into life */
		sq_hpc_write(sc, HPC1_ENETX_CTL, HPC1_ENETX_CTL_ACTIVE);

		/*
		 * Set a watchdog timer in case the chip
		 * flakes out.
		 */
		ifp->if_timer = 5;
	}

	sc->sc_prevtx = i;
}

/*
 * Reclaim used transmit descriptors and restart the transmit DMA
 * engine if necessary.
 */
void
sq_txring_hpc3(struct sq_softc *sc)
{
	/*
	 * HPC3 tags descriptors with a bit once they've been
	 * transmitted. We need only free each XMITDONE'd
	 * descriptor, and restart the DMA engine if any
	 * descriptors are left over.
	 */
	struct ifnet *ifp = &sc->sc_ac.ac_if;
	int i;
	uint32_t status = 0;

	i = sc->sc_prevtx;
	while (sc->sc_nfreetx < SQ_NTXDESC) {
		/*
		 * Check status first so we don't end up with a case of
		 * the buffer not being finished while the DMA channel
		 * has gone idle.
		 */
		status = sq_hpc_read(sc, HPC3_ENETX_CTL);

		SQ_CDTXSYNC(sc, i, sc->sc_txmap[i]->dm_nsegs,
		    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);

		/* Check for used descriptor and restart DMA chain if needed */
		if ((sc->sc_txdesc[i].hpc3_hdd_ctl &
		    HPC3_HDD_CTL_XMITDONE) == 0) {
			if ((status & HPC3_ENETX_CTL_ACTIVE) == 0) {
				SQ_TRACE(SQ_RESTART_DMA, sc, i, status);

				sq_hpc_write(sc, HPC3_ENETX_NDBP,
				    SQ_CDTXADDR(sc, i));

				/* Kick DMA channel into life */
				sq_hpc_write(sc, HPC3_ENETX_CTL,
				    HPC3_ENETX_CTL_ACTIVE);

				/*
				 * Set a watchdog timer in case the chip
				 * flakes out.
				 */
				ifp->if_timer = 5;
			} else
				SQ_TRACE(SQ_TXINTR_BUSY, sc, i, status);
			break;
		}

		/* Sync the packet data, unload DMA map, free mbuf */
		bus_dmamap_sync(sc->sc_dmat, sc->sc_txmap[i],
		    0, sc->sc_txmap[i]->dm_mapsize, BUS_DMASYNC_POSTWRITE);
		bus_dmamap_unload(sc->sc_dmat, sc->sc_txmap[i]);
		m_freem(sc->sc_txmbuf[i]);
		sc->sc_txmbuf[i] = NULL;

		ifp->if_opackets++;
		sc->sc_nfreetx++;

		SQ_TRACE(SQ_DONE_DMA, sc, i, status);
		i = SQ_NEXTTX(i);
	}

	sc->sc_prevtx = i;
}

void
sq_reset(struct sq_softc *sc)
{
	/* Stop HPC dma channels */
	sq_hpc_write(sc, sc->hpc_regs->enetr_ctl, 0);
	sq_hpc_write(sc, sc->hpc_regs->enetx_ctl, 0);

	sq_hpc_write(sc, sc->hpc_regs->enetr_reset, 3);
	delay(20);
	sq_hpc_write(sc, sc->hpc_regs->enetr_reset, 0);
}

/* sq_add_rxbuf: Add a receive buffer to the indicated descriptor. */
int
sq_add_rxbuf(struct sq_softc *sc, int idx)
{
	int err;
	struct mbuf *m;

	MGETHDR(m, M_DONTWAIT, MT_DATA);
	if (m == NULL)
		return ENOBUFS;

	MCLGET(m, M_DONTWAIT);
	if ((m->m_flags & M_EXT) == 0) {
		m_freem(m);
		return ENOBUFS;
	}

	if (sc->sc_rxmbuf[idx] != NULL)
		bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmap[idx]);

	sc->sc_rxmbuf[idx] = m;

	if ((err = bus_dmamap_load(sc->sc_dmat, sc->sc_rxmap[idx],
	    m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT)) != 0) {
		printf("%s: can't load rx DMA map %d, error = %d\n",
		    sc->sc_dev.dv_xname, idx, err);
		panic("sq_add_rxbuf");	/* XXX */
	}

	bus_dmamap_sync(sc->sc_dmat, sc->sc_rxmap[idx],
	    0, sc->sc_rxmap[idx]->dm_mapsize, BUS_DMASYNC_PREREAD);

	SQ_INIT_RXDESC(sc, idx);

	return 0;
}

/*
 * Media handling
 */

int
sq_ifmedia_change_ip22(struct ifnet *ifp)
{
	struct sq_softc *sc = ifp->if_softc;
	struct ifmedia *ifm = &sc->sc_ifmedia;
	uint32_t iocw;

	iocw =
	    bus_space_read_4(sc->sc_hpct, sc->sc_hpcbh, IOC_BASE + IOC_WRITE);

	switch (IFM_SUBTYPE(ifm->ifm_media)) {
	case IFM_10_5:
		iocw &= ~IOC_WRITE_ENET_AUTO;
		iocw |= IOC_WRITE_ENET_AUI;
		break;
	case IFM_10_T:
		iocw &= ~(IOC_WRITE_ENET_AUTO | IOC_WRITE_ENET_AUI);
		iocw |= IOC_WRITE_ENET_UTP;	/* in case it cleared */
		break;
	default:
	case IFM_AUTO:
		iocw |= IOC_WRITE_ENET_AUTO;
		break;
	}

	bus_space_write_4(sc->sc_hpct, sc->sc_hpcbh, IOC_BASE + IOC_WRITE,
	    iocw);
	bus_space_barrier(sc->sc_hpct, sc->sc_hpcbh, IOC_BASE + IOC_WRITE, 4,
	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
	return 0;
}

int
sq_ifmedia_change_singlemedia(struct ifnet *ifp)
{
	return 0;
}

void
sq_ifmedia_status_ip22(struct ifnet *ifp, struct ifmediareq *req)
{
	struct sq_softc *sc = ifp->if_softc;
	uint32_t iocr, iocw;

	iocw =
	    bus_space_read_4(sc->sc_hpct, sc->sc_hpcbh, IOC_BASE + IOC_WRITE);

	req->ifm_status = IFM_AVALID;
	if (sc->sc_flags & SQF_LINKUP)
		req->ifm_status |= IFM_ACTIVE;
	if ((iocw & IOC_WRITE_ENET_AUTO) != 0) {
		iocr = bus_space_read_4(sc->sc_hpct, sc->sc_hpcbh,
		    IOC_BASE + IOC_READ);
		if ((iocr & IOC_READ_ENET_LINK) != 0)
			req->ifm_active = IFM_10_5 | IFM_ETHER;
		else
			req->ifm_active = IFM_10_T | IFM_ETHER;
	} else {
		if ((iocw & IOC_WRITE_ENET_AUI) != 0)
			req->ifm_active = IFM_10_5 | IFM_ETHER;
		else
			req->ifm_active = IFM_10_T | IFM_ETHER;
	}
}

void
sq_ifmedia_status_singlemedia(struct ifnet *ifp, struct ifmediareq *req)
{
	struct sq_softc *sc = ifp->if_softc;
	struct ifmedia *ifm = &sc->sc_ifmedia;

	req->ifm_status = IFM_AVALID;
	if (sc->sc_flags & SQF_LINKUP)
		req->ifm_status |= IFM_ACTIVE;
	req->ifm_active = ifm->ifm_media;
}


code:
/*	$OpenBSD: if_sqvar.h,v 1.4 2012/05/28 17:03:36 miod Exp $	*/
/*	$NetBSD: sqvar.h,v 1.12 2011/01/25 13:12:39 tsutsui Exp $	*/

/*
 * Copyright (c) 2001 Rafal K. Boni
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/* Note, these must be powers of two for the magic NEXT/PREV macros to work */
#define SQ_NRXDESC		64
#define SQ_NTXDESC		64

#define	SQ_NRXDESC_MASK		(SQ_NRXDESC - 1)
#define	SQ_NEXTRX(x)		((x + 1) & SQ_NRXDESC_MASK)
#define	SQ_PREVRX(x)		((x - 1) & SQ_NRXDESC_MASK)

#define	SQ_NTXDESC_MASK		(SQ_NTXDESC - 1)
#define	SQ_NEXTTX(x)		((x + 1) & SQ_NTXDESC_MASK)
#define	SQ_PREVTX(x)		((x - 1) & SQ_NTXDESC_MASK)

/*
 * We pack all DMA control structures into one container so we can alloc just
 * one chunk of DMA-safe memory and pack them into it.  Otherwise, we'd have to
 * allocate a page for each descriptor, since the bus_dmamem_alloc() interface
 * does not allow us to allocate smaller chunks.
 */
struct sq_control {
	/* Receive descriptors */
	struct hpc_dma_desc	rx_desc[SQ_NRXDESC];

	/* Transmit descriptors */
	struct hpc_dma_desc	tx_desc[SQ_NTXDESC];
};

#define	SQ_CDOFF(x)		offsetof(struct sq_control, x)
#define	SQ_CDTXOFF(x)		SQ_CDOFF(tx_desc[(x)])
#define	SQ_CDRXOFF(x)		SQ_CDOFF(rx_desc[(x)])

#define	SQ_TYPE_8003		0
#define	SQ_TYPE_80C03		1

/* Trace Actions */
#define SQ_RESET		1
#define SQ_ADD_TO_DMA		2
#define SQ_START_DMA		3
#define SQ_DONE_DMA		4
#define SQ_RESTART_DMA		5
#define SQ_TXINTR_ENTER		6
#define SQ_TXINTR_EXIT		7
#define SQ_TXINTR_BUSY		8
#define SQ_IOCTL		9
#define SQ_ENQUEUE		10

struct sq_action_trace {
	int action;
	int line;
	int bufno;
	int status;
	int freebuf;
};

#ifdef SQ_DEBUG
#define SQ_TRACEBUF_SIZE	100

#define SQ_TRACE(act, sc, buf, stat) do {				\
	(sc)->sq_trace[(sc)->sq_trace_idx].action = (act);		\
	(sc)->sq_trace[(sc)->sq_trace_idx].line = __LINE__;		\
	(sc)->sq_trace[(sc)->sq_trace_idx].bufno = (buf);		\
	(sc)->sq_trace[(sc)->sq_trace_idx].status = (stat);		\
	(sc)->sq_trace[(sc)->sq_trace_idx].freebuf = (sc)->sc_nfreetx;	\
	if (++(sc)->sq_trace_idx == SQ_TRACEBUF_SIZE)			\
		(sc)->sq_trace_idx = 0;					\
} while (/* CONSTCOND */0)
#else
#define SQ_TRACE(act, sc, buf, stat) do { } while (/* CONSTCOND */0)
#endif

struct sq_softc {
	struct device		sc_dev;

	/* HPC registers */
	bus_space_tag_t		sc_hpct;
	bus_space_handle_t	sc_hpcbh;	/* HPC base, for IOC access */
	bus_space_handle_t	sc_hpch;

	/* HPC external Ethernet registers: aka Seeq 8003 registers */
	bus_space_tag_t		sc_regt;
	bus_space_handle_t	sc_regh;

	bus_dma_tag_t		sc_dmat;

	struct arpcom		sc_ac;
	uint8_t			sc_enaddr[ETHER_ADDR_LEN];
	struct ifmedia		sc_ifmedia;

	int			sc_type;
	int			sc_flags;
#define	SQF_LINKUP			0x00000001
#define	SQF_NOLINKDOWN			0x00000002

	struct sq_control*	sc_control;
#define	sc_rxdesc		sc_control->rx_desc
#define	sc_txdesc		sc_control->tx_desc

	/* DMA structures for control data (DMA RX/TX descriptors) */
	int			sc_ncdseg;
	bus_dma_segment_t	sc_cdseg;
	bus_dmamap_t		sc_cdmap;
#define	sc_cddma		sc_cdmap->dm_segs[0].ds_addr

	int			sc_nextrx;

	/* DMA structures for RX packet data */
	bus_dma_segment_t	sc_rxseg[SQ_NRXDESC];
	bus_dmamap_t		sc_rxmap[SQ_NRXDESC];
	struct mbuf*		sc_rxmbuf[SQ_NRXDESC];

	int			sc_nexttx;
	int			sc_prevtx;
	int			sc_nfreetx;

	/* DMA structures for TX packet data */
	bus_dma_segment_t	sc_txseg[SQ_NTXDESC];
	bus_dmamap_t		sc_txmap[SQ_NTXDESC];
	struct mbuf*		sc_txmbuf[SQ_NTXDESC];

	uint8_t			sc_txcmd;	/* current value of TXCMD */
	uint8_t			sc_rxcmd;	/* prototype rxcmd */

	struct hpc_values       *hpc_regs;      /* HPC register definitions */

#ifdef SQ_DEBUG
	int			sq_trace_idx;
	struct sq_action_trace	sq_trace[SQ_TRACEBUF_SIZE];
#endif
};

#define	SQ_CDTXADDR(sc, x)	((sc)->sc_cddma + SQ_CDTXOFF((x)))
#define	SQ_CDRXADDR(sc, x)	((sc)->sc_cddma + SQ_CDRXOFF((x)))

#if 0 /* not necessary as this memory is mapped uncached */
static inline void
SQ_CDTXSYNC(struct sq_softc *sc, int __x, int __n, int ops)
{
	/* If it will wrap around, sync to the end of the ring. */
	if ((__x + __n) > SQ_NTXDESC) {
		bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cdmap,
		    SQ_CDTXOFF(__x), sizeof(struct hpc_dma_desc) *
		    (SQ_NTXDESC - __x), (ops));
		__n -= (SQ_NTXDESC - __x);
		__x = 0;
	}

	/* Now sync whatever is left. */
	bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cdmap,
	    SQ_CDTXOFF(__x), sizeof(struct hpc_dma_desc) * __n, (ops));
}

#define	SQ_CDRXSYNC(sc, x, ops)						\
	bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cdmap,			\
	    SQ_CDRXOFF((x)), sizeof(struct hpc_dma_desc), (ops))
#else
#define	SQ_CDTXSYNC(sc, x, n, ops)	do { } while (0)
#define	SQ_CDRXSYNC(sc, x, ops)		do { } while (0)
#endif

static inline void
SQ_INIT_RXDESC(struct sq_softc *sc, unsigned int x)
{
	struct hpc_dma_desc *__rxd, rxd_store;
	struct mbuf *__m = (sc)->sc_rxmbuf[(x)];

	__rxd = hpc_read_dma_desc(&(sc)->sc_rxdesc[(x)], &rxd_store);
	__m->m_data = __m->m_ext.ext_buf;
	if (sc->hpc_regs->revision == 3) {
		__rxd->hpc3_hdd_bufptr =
		    (sc)->sc_rxmap[(x)]->dm_segs[0].ds_addr;
		__rxd->hpc3_hdd_ctl = __m->m_ext.ext_size | HPC3_HDD_CTL_OWN |
		    HPC3_HDD_CTL_INTR | HPC3_HDD_CTL_EOPACKET |
		    ((x) == (SQ_NRXDESC  - 1) ? HPC3_HDD_CTL_EOCHAIN : 0);
	} else {
		__rxd->hpc1_hdd_bufptr =
		    (sc)->sc_rxmap[(x)]->dm_segs[0].ds_addr |
		    ((x) == (SQ_NRXDESC - 1) ? HPC1_HDD_CTL_EOCHAIN : 0);
		__rxd->hpc1_hdd_ctl = __m->m_ext.ext_size | HPC1_HDD_CTL_OWN |
		    HPC1_HDD_CTL_INTR | HPC1_HDD_CTL_EOPACKET;
	}
	__rxd->hdd_descptr = SQ_CDRXADDR((sc), SQ_NEXTRX((x)));
	hpc_write_dma_desc(&(sc)->sc_rxdesc[(x)], __rxd);
	SQ_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
}

license: unknown


code:
/*	$OpenBSD: iocreg.h,v 1.2 2012/04/08 22:08:25 miod Exp $	*/
/* $NetBSD: iocreg.h,v 1.2 2005/12/11 12:18:53 christos Exp $	 */

/*
 * Copyright (c) 2003 Christopher Sekiya
 * Copyright (c) 2001 Rafal K. Boni
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/*
 * IOC1/2 memory map.
 *
 * The IOC1/2 is connected to the HPC#0, PBus channel 6, so these registers
 * are based from the external register window for PBus channel 6 on HPC#0.
 *
 */

#define	IOC_BASE			HPC3_PBUS_CH6_DEVREGS

#define IOC_PLP_REGS			0x00	/* Parallel port registers */
#define IOC_PLP_REGS_SIZE		0x2c

#define IOC_PLP_DATA			0x00	/* Data register */
#define IOC_PLP_CTL			0x04	/* Control register */
#define IOC_PLP_STAT			0x08	/* Status register */
#define IOC_PLP_DMACTL			0x0c	/* DMA control register */
#define IOC_PLP_INTSTAT			0x10	/* Interrupt status register */
#define IOC_PLP_INTMASK			0x14	/* Interrupt mask register */
#define IOC_PLP_TIMER1			0x18	/* Timer 1 register */
#define IOC_PLP_TIMER2			0x1c	/* Timer 2 register */
#define IOC_PLP_TIMER3			0x20	/* Timer 3 register */
#define IOC_PLP_TIMER4			0x24	/* Timer 4 register */

#define IOC_SERIAL_REGS			0x30	/* Serial port registers */
#define IOC_SERIAL_REGS_SIZE		0x0c

#define IOC_SERIAL_PORT1_CMD		0x00	/* Port 1 command transfer */
#define IOC_SERIAL_PORT1_DATA		0x04	/* Port 1 data transfer */
#define IOC_SERIAL_PORT2_CMD		0x08	/* Port 2 command transfer */
#define IOC_SERIAL_PORT2_DATA		0x0c	/* Port 2 data transfer */

#define IOC_KB_REGS			0x40	/* Keyboard/mouse registers */
#define IOC_KB_REGS_SIZE		0x08

/* Miscellaneous registers */

#define IOC_MISC_REGS			0x48	/* Misc. IOC regs */
#define IOC_MISC_REGS_SIZE		0x34

#define IOC_GCSEL			0x48	/* General select register */

#define IOC_GCREG			0x4c	/* General control register */
#define	IOC_GCREG_GIO_33MHZ		0x08

#define IOC_PANEL			0x50	/* Front Panel register */
#define IOC_PANEL_POWER_STATE		0x01
#define IOC_PANEL_POWER_IRQ		0x02
#define IOC_PANEL_VDOWN_IRQ		0x10
#define IOC_PANEL_VDOWN_HOLD		0x20
#define IOC_PANEL_VUP_IRQ		0x40
#define IOC_PANEL_VUP_HOLD		0x80

#define IOC_SYSID			0x58	/* System ID register */
#define IOC_SYSID_SYSTYPE		0x01	/* 0: Sapphire, 1: Full House */
#define IOC_SYSID_BOARDREV		0x1e
#define IOC_SYSID_BOARDREV_SHIFT	1
#define IOC_SYSID_CHIPREV		0xe0
#define IOC_SYSID_CHIPREV_SHIFT		5

#define IOC_READ			0x60	/* Read register */
#define IOC_READ_SCSI0_POWER		0x10
#define IOC_READ_SCSI1_POWER		0x20
#define IOC_READ_ENET_POWER		0x40
#define IOC_READ_ENET_LINK		0x80

#define IOC_DMASEL			0x68	/* DMA select register */
#define IOC_DMASEL_ISDN_B		0x01
#define IOC_DMASEL_ISDN_A		0x02
#define IOC_DMASEL_PARALLEL		0x04
#define IOC_DMASEL_SERIAL_10MHZ		0x00
#define IOC_DMASEL_SERIAL_6MHZ		0x10
#define IOC_DMASEL_SERIAL_EXTERNAL	0x20

#define IOC_RESET			0x70	/* Reset (IP24) / Write 1 (IP22)
						   register */
#define IOC_RESET_PARALLEL		0x01
#define IOC_RESET_PCKBC			0x02
#define IOC_RESET_EISA			0x04
#define IOC_RESET_ISDN			0x08
#define IOC_RESET_LED_GREEN		0x10
#define IOC_RESET_LED_RED		0x20
#define IOC_RESET_LED_ORANGE		0x40

#define IOC_WRITE			0x78	/* Write (IP24) / Write 2 (IP22)
						   register */
#define IOC_WRITE_ENET_NTH		0x01
#define IOC_WRITE_ENET_UTP		0x02
#define IOC_WRITE_ENET_AUI		0x04
#define IOC_WRITE_ENET_AUTO		0x08
#define IOC_WRITE_PC_UART2		0x10
#define IOC_WRITE_PC_UART1		0x20
#define IOC_WRITE_MARGIN_LOW		0x40
#define IOC_WRITE_MARGIN_HIGH		0x80


code:
#! /usr/bin/awk -f
#	$OpenBSD: makemap.awk,v 1.1 2014/05/22 19:39:37 miod Exp $
#
# Copyright (c) 2005, 2014, Miodrag Vallat
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
# 1. Redistributions of source code must retain the above copyright
#    notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
#    notice, this list of conditions and the following disclaimer in the
#    documentation and/or other materials provided with the distribution.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
# DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
# INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
# STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
#
# This script attempts to convert, with minimal hacks and losses, the
# regular PS/2 keyboard (pckbd) layout tables into SGI serial keyboard (zskbd)
# layout tables.
#

BEGIN {
	rcsid = "$OpenBSD: makemap.awk,v 1.1 2014/05/22 19:39:37 miod Exp $"
	ifdepth = 0
	ignore = 0
	haskeys = 0
	summary = 0

	# PS/2 -> SGI conversion table
	for (i = 0; i < 256; i++)
		conv[i] = -1

	conv[1] = 6
	conv[2] = 7
	conv[3] = 13
	conv[4] = 14
	conv[5] = 21
	conv[6] = 22
	conv[7] = 29
	conv[8] = 30
	conv[9] = 37
	conv[10] = 38
	conv[11] = 45
	conv[12] = 46
	conv[13] = 53
	conv[14] = 60
	conv[15] = 8
	conv[16] = 9
	conv[17] = 15
	conv[18] = 16
	conv[19] = 23
	conv[20] = 24
	conv[21] = 31
	conv[22] = 32
	conv[23] = 39
	conv[24] = 40
	conv[25] = 47
	conv[26] = 48
	conv[27] = 55
	conv[28] = 50
	conv[29] = 2
	conv[30] = 10
	conv[31] = 11
	conv[32] = 17
	conv[33] = 18
	conv[34] = 25
	conv[35] = 26
	conv[36] = 33
	conv[37] = 34
	conv[38] = 41
	conv[39] = 42
	conv[40] = 49
	conv[41] = 54
	conv[42] = 5
	conv[43] = 56
	conv[44] = 19
	conv[45] = 20
	conv[46] = 27
	conv[47] = 28
	conv[48] = 35
	conv[49] = 36
	conv[50] = 43
	conv[51] = 44
	conv[52] = 51
	conv[53] = 52
	conv[54] = 4
	conv[55] = 108
	conv[56] = 83
	conv[57] = 82
	conv[58] = 3
	conv[59] = 86
	conv[60] = 87
	conv[61] = 88
	conv[62] = 89
	conv[63] = 90
	conv[64] = 91
	conv[65] = 92
	conv[66] = 93
	conv[67] = 94
	conv[68] = 95
	conv[69] = 106
	conv[70] = 99
	conv[71] = 66
	conv[72] = 67
	conv[73] = 74
	conv[74] = 75
	conv[75] = 62
	conv[76] = 68
	conv[77] = 69
	conv[78] = 109
	conv[79] = 57
	conv[80] = 63
	conv[81] = 64
	conv[82] = 58
	conv[83] = 65
	conv[86] = 111
	conv[87] = 96
	conv[88] = 97
	conv[127] = 100
	conv[156] = 81
	conv[157] = 85
	conv[170] = 98
	conv[181] = 107
	conv[183] = 98
	conv[184] = 84
	conv[199] = 102
	conv[200] = 80
	conv[201] = 103
	conv[203] = 72
	conv[205] = 79
	conv[207] = 104
	conv[208] = 73
	conv[209] = 105
	conv[210] = 101
	conv[211] = 61
}
NR == 1 {
	VERSION = $0
	gsub("\\$", "", VERSION)
	gsub("\\$", "", rcsid)

	printf("/*\t\$OpenBSD\$\t*/\n\n")
	printf("/*\n")
	printf(" * THIS FILE IS AUTOMAGICALLY GENERATED.  DO NOT EDIT.\n")
	printf(" *\n")
	printf(" * generated by:\n")
	printf(" *\t%s\n", rcsid)
	printf(" * generated from:\n")
	printf(" */\n")
	print VERSION

	next
}

#
# A very limited #if ... #endif parser. We only want to correctly detect
# ``#if 0'' constructs, so as not to process their contents. This is necessary
# since our output is out-of-order from our input.
#
# Note that this does NOT handle ``#ifdef notyet'' correctly - please only use
# ``#if 0'' constructs in the input.
#

/^#if/ {
	ignores[ifdepth] = ignore
	if ($2 == "0")
		ignore = 1
	#else
	#	ignore = 0
	ifdepth++
	if (ignore)
		next
}
/^#endif/ {
	oldignore = ignore
	ifdepth--
	ignore = ignores[ifdepth]
	ignores[ifdepth] = 0
	if (oldignore)
		next
}

$1 == "#include" {
	if (ignore)
		next
	if ($2 == "<dev/pckbc/wskbdmap_mfii.h>")
		next
	printf("#include %s\n", $2)
	next
}
$1 == "#define" || $1 == "#undef" {
	if (ignore)
		next
	print $0
	next
}

/pckbd/ {
	gsub("pckbd", "zskbd", $0)
}
/zskbd_keydesctab/ {
	gsub("zskbd", "wssgi", $0)
}

/zskbd_keydesc_/ {
	mapname = substr($0, index($0, "zskbd_keydesc_") + length("zskbd_keydesc_"))
	sub("\\[\\].*", "", mapname)
	sub("\\).*", "", mapname)
	shortname = mapname
	sub("_nodead", "", shortname)	# _nodead ok if main layout ok
	if (shortname != "be" &&
	    shortname != "de" &&
	    shortname != "dk" &&
	    shortname != "es" &&
	    shortname != "fi" &&	# missing from PS/2 source...
	    shortname != "fr" &&
	    shortname != "gr" &&	# missing from PS/2 source...
	    shortname != "it" &&
	    shortname != "nl" &&
	    shortname != "no" &&
	    shortname != "pt" &&
	    shortname != "sf" &&
	    shortname != "sg" &&
	    shortname != "sv" &&
	    shortname != "uk" &&
	    shortname != "us") {
		nolayout = 1
	}
}

/zskbd_keydesc_.*\[\]/ {
	if (nolayout)
		printf("/* %s not applicable */\n", mapname)
}

/KC/ {
	if (ignore)
		next

	if (nolayout)
		next

	haskeys = 1

	sidx = substr($1, 4, length($1) - 5)
	orig = int(sidx)
	id = conv[orig]

	if (id == -1) {
		# printf("/* initially KC(%d),", orig)
		# for (f = 2; f <= NF; f++) {
		# 	if ($f != "/*" && $f != "*/")
		# 		printf("\t%s", $f)
		# }
		# printf("\t*/\n")
	} else {
		lines[id] = sprintf("    KC(%d),\t", id)
		#
		# This makes sure that the non-comment part of the output
		# ends up with a trailing comma. This is necessary since
		# the last line of an input block might not have a trailing
		# comma, but might not be the last line of an output block
		# due to sorting.
		#
		comma = 0
		for (f = 2; f <= NF; f++) {
			l = length($f)
			if ($f == "/*")
				comma++
			if (comma == 0 && substr($f, l) != ",") {
				lines[id] = sprintf("%s%s,", lines[id], $f)
				l++
			} else {
				lines[id] = sprintf("%s%s", lines[id], $f)
			}
			if (comma == 0 && f != NF) {
				if (l < 2 * 8)
					lines[id] = lines[id] "\t"
				if (l < 8)
					lines[id] = lines[id] "\t"
			}
			if ($f == "*/")
				comma--
		}
	}

	next
}
/};/ {
	if (ignore)
		next

	if (nolayout) {
		nolayout = 0
		next
	}

	if (haskeys) {
		for (i = 0; i < 256; i++)
			if (lines[i]) {
				print lines[i]
				lines[i] = ""
			}

		haskeys = 0
	}
}
/KBD_MAP/ {
	summary = 1
}
# hack to eat two line KBD_MAP() - we want to ignore all of them, and
# the second line will get rejected because ``nolayout'' will be set.
/KBD_MAP[^)]*,$/ { next }

{
	if (ignore)
		next
	if (nolayout) {
		if (summary)
			nolayout = 0
		next
	}
	print $0
}


code:
/*	$OpenBSD: panel.c,v 1.3 2014/07/11 08:18:31 guenther Exp $	*/

/*
 * Copyright (c) 2012 Miodrag Vallat.
 *
 * Permission to use, copy, modify, and distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <sys/proc.h>
#include <sys/signalvar.h>
#include <sys/timeout.h>

#include <machine/autoconf.h>
#include <mips64/archtype.h>
#include <machine/bus.h>

#include <sgi/hpc/iocreg.h>
#include <sgi/hpc/hpcreg.h>
#include <sgi/hpc/hpcvar.h>

#include <sgi/sgi/ip22.h>

#include "audio.h"
#include "wskbd.h"
extern int wskbd_set_mixervolume(long, long);

struct panel_softc {
	struct device		 sc_dev;
	bus_space_tag_t		 sc_iot;
	bus_space_handle_t	 sc_ioh;
	int			 sc_irq;		/* irq number */
	void			*sc_ih;			/* irq handler cookie */
	struct timeout		 sc_repeat_tmo;		/* polling timeout */
};

/* Repeat delays for volume buttons. */
#define	PANEL_REPEAT_FIRST	400
#define	PANEL_REPEAT_NEXT	100

int	panel_match(struct device *, void *, void *);
void	panel_attach(struct device *, struct device *, void *);

struct cfdriver panel_cd = {
	NULL, "panel", DV_DULL
};

const struct cfattach panel_ca = {
	sizeof(struct panel_softc), panel_match, panel_attach
};

int	panel_intr(void *);
void	panel_repeat(void *);
#if NAUDIO > 0 && NWSKBD > 0
void	panel_volume_adjust(struct panel_softc *, uint8_t);
#endif

int
panel_match(struct device *parent, void *vcf, void *aux)
{
	struct cfdata *cf = vcf;
	struct hpc_attach_args *ha = aux;

	if (strcmp(ha->ha_name, cf->cf_driver->cd_name) != 0)
		return 0;

	if (sys_config.system_type == SGI_IP20)
		return 0;

	return 1;
}

void
panel_attach(struct device *parent, struct device *self, void *aux)
{
	struct panel_softc *sc = (struct panel_softc *)self;
	struct hpc_attach_args *haa = aux;

	sc->sc_iot = haa->ha_st;
	if (bus_space_subregion(haa->ha_st, haa->ha_sh, haa->ha_devoff + 3, 1,
	    &sc->sc_ioh)) {
		printf(": can't map registers\n");
		return;
	}

	sc->sc_irq = haa->ha_irq;
	sc->sc_ih = hpc_intr_establish(sc->sc_irq, IPL_BIO, panel_intr, sc,
	    sc->sc_dev.dv_xname);
	if (sc->sc_ih == NULL) {
		printf(": can't establish interrupt\n");
		return;
	}

	if (sys_config.system_subtype == IP22_INDY)
		printf(": power and volume buttons\n");
	else
		printf(": power button\n");

	timeout_set(&sc->sc_repeat_tmo, panel_repeat, sc);
}

int
panel_intr(void *v)
{
	struct panel_softc *sc = (struct panel_softc *)v;
	uint8_t reg, ack;
	extern int allowpowerdown;

	reg = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 0);

	ack = IOC_PANEL_POWER_STATE;
	if (sys_config.system_subtype == IP22_INDIGO2 ||
	    (reg & IOC_PANEL_POWER_IRQ) == 0)
		ack |= IOC_PANEL_POWER_IRQ;
	if (sys_config.system_subtype == IP22_INDY) {
		if ((reg & IOC_PANEL_VDOWN_IRQ) == 0)
			ack |= IOC_PANEL_VDOWN_IRQ;
		if ((reg & IOC_PANEL_VUP_IRQ) == 0)
			ack |= IOC_PANEL_VUP_IRQ;
	}
	bus_space_write_1(sc->sc_iot, sc->sc_ioh, 0, ack);
	bus_space_barrier(sc->sc_iot, sc->sc_ioh, 0, 1,
	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);

	/*
	 * Panel interrupts are latched for about 300 msec after being
	 * acked, and not until all buttons are depressed.
	 * We need to temporary disable the interrupt and switch to polling,
	 * until the interrupt can be enabled again.
	 */
	hpc_intr_disable(sc->sc_ih);

	/*
	 * If the power button is down, try and issue a shutdown immediately
	 * (if allowed).
	 */
	if (sys_config.system_subtype == IP22_INDIGO2 ||
	    (reg & IOC_PANEL_POWER_IRQ) == 0) {
		if (allowpowerdown == 1) {
			allowpowerdown = 0;
			prsignal(initprocess, SIGUSR2);
		}
	}

#if NAUDIO > 0 && NWSKBD > 0
	/*
	 * If any of the volume buttons is down, update volume.
	 */
	if (sys_config.system_subtype == IP22_INDY)
		panel_volume_adjust(sc, reg);
#endif

	timeout_add_msec(&sc->sc_repeat_tmo, PANEL_REPEAT_FIRST);

	return 1;
}

void
panel_repeat(void *v)
{
	struct panel_softc *sc = (struct panel_softc *)v;
	uint8_t reg;

	reg = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 0);

#if NAUDIO > 0 && NWSKBD > 0
	/*
	 * Volume button autorepeat.
	 */
	if (sys_config.system_subtype == IP22_INDY)
		panel_volume_adjust(sc, reg);
#endif

	if (hpc_is_intr_pending(sc->sc_irq)) {
		/*
		 * Keep acking everything to get the interrupt finally
		 * unlatched.
		 */
		bus_space_write_1(sc->sc_iot, sc->sc_ioh, 0,
		    IOC_PANEL_POWER_STATE | IOC_PANEL_POWER_IRQ |
		    IOC_PANEL_VDOWN_IRQ | IOC_PANEL_VDOWN_HOLD |
		    IOC_PANEL_VUP_IRQ | IOC_PANEL_VUP_HOLD);
		bus_space_barrier(sc->sc_iot, sc->sc_ioh, 0, 1,
		    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);

		timeout_add_msec(&sc->sc_repeat_tmo, PANEL_REPEAT_NEXT);
	} else {
		hpc_intr_enable(sc->sc_ih);
	}
}

#if NAUDIO > 0 && NWSKBD > 0
void
panel_volume_adjust(struct panel_softc *sc, uint8_t reg)
{
	long adjust;

	switch (reg & (IOC_PANEL_VDOWN_IRQ | IOC_PANEL_VUP_IRQ)) {
	case 0:				/* both buttons pressed: mute */
		adjust = 0;
		break;
	case IOC_PANEL_VDOWN_IRQ:	/* up button pressed */
		adjust = 1;
		break;
	case IOC_PANEL_VDUP_IRQ:	/* down button pressed */
		adjust = -1;
		break;
	case IOC_PANEL_VDOWN_IRQ | IOC_PANEL_VDUP_IRQ:
		return;
	}

	wskbd_set_mixervolume(adjust, 1);
}
#endif


code:
/*	$OpenBSD: pckbc_hpc.c,v 1.4 2015/05/24 10:57:47 miod Exp $	*/
/* $NetBSD: pckbc_hpc.c,v 1.9 2008/03/15 13:23:24 cube Exp $	 */

/*
 * Copyright (c) 2003 Christopher SEKIYA
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *          This product includes software developed for the
 *          NetBSD Project.  See http://www.NetBSD.org/ for
 *          information about NetBSD.
 * 4. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/malloc.h>

#include <machine/autoconf.h>
#include <machine/bus.h>

#include <sgi/hpc/hpcreg.h>
#include <sgi/hpc/hpcvar.h>
#include <sgi/sgi/ip22.h>

#include <dev/ic/i8042reg.h>
#include <dev/ic/pckbcvar.h>

int      pckbc_hpc_match(struct device *, void *, void *);
void     pckbc_hpc_attach(struct device *, struct device *, void *);

const struct cfattach pckbc_hpc_ca = {
	sizeof(struct pckbc_softc), pckbc_hpc_match, pckbc_hpc_attach
};

int
pckbc_hpc_match(struct device *parent, void *vcf, void *aux)
{
	struct cfdata *cf = vcf;
	struct hpc_attach_args *ha = aux;

	/* keyboard controller is not wired on Challenge S */
	if (sys_config.system_subtype == IP22_CHALLS)
		return 0;

	if (strcmp(ha->ha_name, cf->cf_driver->cd_name) == 0)
		return 1;

	return 0;
}

void
pckbc_hpc_attach(struct device *parent, struct device * self, void *aux)
{
	struct pckbc_softc *sc = (struct pckbc_softc *)self;
	struct hpc_attach_args *haa = aux;
	struct pckbc_internal *t = NULL;
	bus_space_handle_t ioh_d, ioh_c;
	int console;

	if (hpc_intr_establish(haa->ha_irq, IPL_TTY, pckbcintr, sc,
	    sc->sc_dv.dv_xname) == NULL) {
		printf(": unable to establish interrupt\n");
		return;
	}

	console = pckbc_is_console(haa->ha_st,
	    XKPHYS_TO_PHYS(haa->ha_sh + haa->ha_devoff + 3));

	if (console) {
		/* pckbc_cnattach() has already been called */
		t = &pckbc_consdata;
		pckbc_console_attached = 1;
	} else {
		if (bus_space_subregion(haa->ha_st, haa->ha_sh,
		    haa->ha_devoff + 3 + KBDATAP, 1, &ioh_d) ||
		    bus_space_subregion(haa->ha_st, haa->ha_sh,
		    haa->ha_devoff + 3 + KBCMDP, 1, &ioh_c)) {
			printf(": couldn't map registers\n");
			return;
		}

		t = malloc(sizeof(*t), M_DEVBUF, M_NOWAIT | M_ZERO);
		t->t_iot = haa->ha_st;
		t->t_ioh_c = ioh_c;
		t->t_ioh_d = ioh_d;
	}

	t->t_cmdbyte = KC8_CPU;
	t->t_sc = sc;
	sc->id = t;

	printf("\n");
	pckbc_attach(sc, 0);
}


code:
/*	$OpenBSD: wdsc.c,v 1.5 2014/06/27 17:51:08 miod Exp $	*/
/*	$NetBSD: wdsc.c,v 1.32 2011/07/01 18:53:47 dyoung Exp $	*/

/*
 * Copyright (c) 2001 Wayne Knowles
 * All rights reserved.
 *
 * This code is derived from software contributed to The NetBSD Foundation
 * by Wayne Knowles
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *        This product includes software developed by the NetBSD
 *        Foundation, Inc. and its contributors.
 * 4. Neither the name of The NetBSD Foundation nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/device.h>
#include <sys/buf.h>
#include <sys/timeout.h>

#include <scsi/scsi_all.h>
#include <scsi/scsiconf.h>

#include <machine/bus.h>
#include <machine/cpu.h>

#include <sgi/hpc/hpcreg.h>
#include <sgi/hpc/hpcvar.h>
#include <sgi/hpc/hpcdma.h>

#include <dev/ic/wd33c93reg.h>
#include <dev/ic/wd33c93var.h>

struct wdsc_softc {
	struct wd33c93_softc	sc_wd33c93; /* Must be first */
	bus_dma_tag_t		sc_dmat;
	bus_dmamap_t		sc_dmamap;
	int			sc_flags;
#define	WDSC_DMA_ACTIVE			0x1
#define	WDSC_DMA_MAPLOADED		0x2
	struct hpc_dma_softc	sc_hpcdma;
};

int	wdsc_match(struct device *, void *, void *);
void	wdsc_attach(struct device *, struct device *, void *);

const struct cfattach wdsc_ca = {
	sizeof(struct wdsc_softc), wdsc_match, wdsc_attach
};

struct cfdriver wdsc_cd = {
	NULL, "wdsc", DV_DULL
};

int	wdsc_dmasetup(struct wd33c93_softc *, void **, ssize_t *, int,
	    ssize_t *);
int	wdsc_dmago(struct wd33c93_softc *);
void	wdsc_dmastop(struct wd33c93_softc *);
void	wdsc_reset(struct wd33c93_softc *);

struct scsi_adapter wdsc_switch = {
	wd33c93_scsi_cmd,
	scsi_minphys,
	NULL,
	NULL,
};

/*
 * Match for SCSI devices on the onboard and GIO32 adapter WD33C93 chips
 */
int
wdsc_match(struct device *parent, void *vcf, void *aux)
{
	struct hpc_attach_args *haa = aux;
	struct cfdata *cf = vcf;
	vaddr_t reset, asr;
	uint32_t dummy;
	uint8_t reg;

	if (strcmp(haa->ha_name, cf->cf_driver->cd_name) != 0)
		return 0;

	reset = PHYS_TO_XKPHYS(haa->ha_sh + haa->ha_dmaoff +
	    haa->hpc_regs->scsi0_ctl, CCA_NC);
	if (guarded_read_4(reset, &dummy) != 0)
		return 0;
	*(volatile uint32_t *)reset = haa->hpc_regs->scsi_dmactl_reset;
	delay(1000);
	*(volatile uint32_t *)reset = 0x0;
	delay(1000);

	asr = PHYS_TO_XKPHYS(haa->ha_sh + haa->ha_devoff + 3, CCA_NC);
	if (guarded_read_1(asr, &reg) != 0)
		return 0;
	if ((reg & 0xff) != SBIC_ASR_INT)
		return 0;

	return 1;
}

/*
 * Attach the wdsc driver
 */
void
wdsc_attach(struct device *parent, struct device *self, void *aux)
{
	struct wdsc_softc *wsc = (struct wdsc_softc *)self;
	struct wd33c93_softc *sc = &wsc->sc_wd33c93;
	struct hpc_attach_args *haa = aux;
	int err;

	sc->sc_regt = haa->ha_st;
	wsc->sc_dmat = haa->ha_dmat;

	wsc->sc_hpcdma.hpc = haa->hpc_regs;

	if ((err = bus_space_subregion(haa->ha_st, haa->ha_sh,
	    haa->ha_devoff + 3, 1, &sc->sc_asr_regh)) != 0) {
		printf(": unable to map asr reg, err=%d\n", err);
		return;
	}

	if ((err = bus_space_subregion(haa->ha_st, haa->ha_sh,
	    haa->ha_devoff + 3 + 4,  1, &sc->sc_data_regh)) != 0) {
		printf(": unable to map data reg, err=%d\n", err);
		return;
	}

	if (bus_dmamap_create(wsc->sc_dmat, MAXPHYS,
	    wsc->sc_hpcdma.hpc->scsi_dma_segs,
	    wsc->sc_hpcdma.hpc->scsi_dma_segs_size,
	    wsc->sc_hpcdma.hpc->scsi_dma_segs_size,
	    BUS_DMA_WAITOK, &wsc->sc_dmamap) != 0) {
		printf(": failed to create dmamap\n");
		return;
	}

	sc->sc_dmasetup = wdsc_dmasetup;
	sc->sc_dmago    = wdsc_dmago;
	sc->sc_dmastop  = wdsc_dmastop;
	sc->sc_reset	= wdsc_reset;

	sc->sc_id = 0;					/* Host ID = 0 */
	sc->sc_clkfreq = 200;				/* 20MHz */
	sc->sc_dmamode = SBIC_CTL_BURST_DMA;

	if (hpc_intr_establish(haa->ha_irq, IPL_BIO,
	     wd33c93_intr, wsc, self->dv_xname) == NULL) {
		printf(": unable to establish interrupt!\n");
		return;
	}

	hpcdma_init(haa, &wsc->sc_hpcdma, wsc->sc_hpcdma.hpc->scsi_dma_segs);
	wd33c93_attach(sc, &wdsc_switch);
}

/*
 * Prime the hardware for a DMA transfer
 *
 * Requires splbio() interrupts to be disabled by the caller
 */
int
wdsc_dmasetup(struct wd33c93_softc *sc, void **addr, ssize_t *len, int datain,
    ssize_t *dmasize)
{
	struct wdsc_softc *wsc = (struct wdsc_softc *)sc;
	struct hpc_dma_softc *dsc = &wsc->sc_hpcdma;
	ssize_t count;
	int err;
	void *vaddr;

	KASSERT((wsc->sc_flags & WDSC_DMA_ACTIVE) == 0);

	vaddr = *addr;
	dsc->sc_dlen = count = *len;
	if (count) {
		KASSERT((wsc->sc_flags & WDSC_DMA_MAPLOADED) == 0);

		/* Build list of physical addresses for this transfer */
		if ((err = bus_dmamap_load(wsc->sc_dmat, wsc->sc_dmamap,
		    vaddr, count, NULL /* kernel address */,
		    BUS_DMA_NOWAIT)) != 0)
			panic("%s: bus_dmamap_load err=%d",
			    sc->sc_dev.dv_xname, err);

		hpcdma_sglist_create(dsc, wsc->sc_dmamap);
		wsc->sc_flags |= WDSC_DMA_MAPLOADED;

		if (datain) {
			dsc->sc_dmacmd =
			    wsc->sc_hpcdma.hpc->scsi_dma_datain_cmd;
			dsc->sc_flags |= HPCDMA_READ;
		} else {
			dsc->sc_dmacmd =
			    wsc->sc_hpcdma.hpc->scsi_dma_dataout_cmd;
			dsc->sc_flags &= ~HPCDMA_READ;
		}
	}
	return count;
}

/*
 * Prime the hardware for the next DMA transfer
 */
int
wdsc_dmago(struct wd33c93_softc *sc)
{
	struct wdsc_softc *wsc = (struct wdsc_softc *)sc;
	struct hpc_dma_softc *dsc = &wsc->sc_hpcdma;

	if (dsc->sc_dlen == 0)
		return 0;

	KASSERT((wsc->sc_flags & WDSC_DMA_ACTIVE) == 0);
	KASSERT((wsc->sc_flags & WDSC_DMA_MAPLOADED));

	wsc->sc_flags |= WDSC_DMA_ACTIVE;

	bus_dmamap_sync(wsc->sc_dmat, wsc->sc_dmamap,
	    0, wsc->sc_dmamap->dm_mapsize,
	    (dsc->sc_flags & HPCDMA_READ) ?
	    BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);

	hpcdma_cntl(dsc, dsc->sc_dmacmd);	/* Thunderbirds are go! */

	return wsc->sc_dmamap->dm_mapsize;
}

/*
 * Stop DMA and unload active DMA maps
 */
void
wdsc_dmastop(struct wd33c93_softc *sc)
{
	struct wdsc_softc *wsc = (struct wdsc_softc *)sc;
	struct hpc_dma_softc *dsc = &wsc->sc_hpcdma;

	if (wsc->sc_flags & WDSC_DMA_ACTIVE) {
		if (dsc->sc_flags & HPCDMA_READ)
			hpcdma_flush(dsc);
		hpcdma_cntl(dsc, 0);	/* Stop DMA */
		bus_dmamap_sync(wsc->sc_dmat, wsc->sc_dmamap,
		    0, wsc->sc_dmamap->dm_mapsize,
		    (dsc->sc_flags & HPCDMA_READ) ?
		    BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
	}
	if (wsc->sc_flags & WDSC_DMA_MAPLOADED)
		bus_dmamap_unload(wsc->sc_dmat, wsc->sc_dmamap);
	wsc->sc_flags &= ~(WDSC_DMA_ACTIVE | WDSC_DMA_MAPLOADED);
}

/*
 * Reset the controller.
 */
void
wdsc_reset(struct wd33c93_softc *sc)
{
	struct wdsc_softc *wsc = (struct wdsc_softc *)sc;
	struct hpc_dma_softc *dsc = &wsc->sc_hpcdma;

	hpcdma_reset(dsc);
}


code:
/*	$OpenBSD: wskbdmap_sgi.c,v 1.2 2014/05/22 19:39:54 miod Exp $	*/

/*
 * THIS FILE IS AUTOMAGICALLY GENERATED.  DO NOT EDIT.
 *
 * generated by:
 *	OpenBSD: makemap.awk,v 1.1 2014/05/22 19:39:37 miod Exp
 * generated from:
 */
/*	OpenBSD: wskbdmap_mfii.c,v 1.43 2013/04/14 19:32:52 miod Exp  */
/*	$NetBSD: wskbdmap_mfii.c,v 1.15 2000/05/19 16:40:04 drochner Exp $	*/

/*
 * PLEASE DO NOT FORGET TO REGEN
 *	sys/dev/usb/ukbdmap.c
 * AFTER ANY CHANGES TO THIS FILE!
 */

/*-
 * Copyright (c) 1997 The NetBSD Foundation, Inc.
 * All rights reserved.
 *
 * This code is derived from software contributed to The NetBSD Foundation
 * by Juergen Hannken-Illjes.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

#include <sys/types.h>
#include <dev/wscons/wsksymdef.h>
#include <dev/wscons/wsksymvar.h>

#define KC(n) KS_KEYCODE(n)

static const keysym_t zskbd_keydesc_us[] = {
/*  pos      command		normal		shifted */
    KC(2),	KS_Cmd1,	KS_Control_L,
    KC(3),	KS_Caps_Lock,
    KC(4),	KS_Shift_R,
    KC(5),	KS_Shift_L,
    KC(6),	KS_Cmd_Debugger,KS_Escape,
    KC(7),	KS_1,		KS_exclam,
    KC(8),	KS_Tab,
    KC(9),	KS_q,
    KC(10),	KS_a,
    KC(11),	KS_s,
    KC(13),	KS_2,		KS_at,
    KC(14),	KS_3,		KS_numbersign,
    KC(15),	KS_w,
    KC(16),	KS_e,
    KC(17),	KS_d,
    KC(18),	KS_f,
    KC(19),	KS_z,
    KC(20),	KS_x,
    KC(21),	KS_4,		KS_dollar,
    KC(22),	KS_5,		KS_percent,
    KC(23),	KS_r,
    KC(24),	KS_t,
    KC(25),	KS_g,
    KC(26),	KS_h,
    KC(27),	KS_c,
    KC(28),	KS_v,
    KC(29),	KS_6,		KS_asciicircum,
    KC(30),	KS_7,		KS_ampersand,
    KC(31),	KS_y,
    KC(32),	KS_u,
    KC(33),	KS_j,
    KC(34),	KS_k,
    KC(35),	KS_b,
    KC(36),	KS_n,
    KC(37),	KS_8,		KS_asterisk,
    KC(38),	KS_9,		KS_parenleft,
    KC(39),	KS_i,
    KC(40),	KS_o,
    KC(41),	KS_l,
    KC(42),	KS_semicolon,	KS_colon,
    KC(43),	KS_m,
    KC(44),	KS_comma,	KS_less,
    KC(45),	KS_0,		KS_parenright,
    KC(46),	KS_minus,	KS_underscore,
    KC(47),	KS_p,
    KC(48),	KS_bracketleft,	KS_braceleft,
    KC(49),	KS_apostrophe,	KS_quotedbl,
    KC(50),	KS_Return,
    KC(51),	KS_period,	KS_greater,
    KC(52),	KS_slash,	KS_question,
    KC(53),	KS_equal,	KS_plus,
    KC(54),	KS_grave,	KS_asciitilde,
    KC(55),	KS_bracketright,KS_braceright,
    KC(56),	KS_backslash,	KS_bar,
    KC(57),	KS_KP_End,	KS_KP_1,
    KC(58),	KS_KP_Insert,	KS_KP_0,
    KC(60),	KS_Cmd_ResetEmul,KS_Delete,
    KC(61),	KS_Cmd_KbdReset,KS_KP_Delete,
    KC(62),	KS_KP_Left,	KS_KP_4,
    KC(63),	KS_KP_Down,	KS_KP_2,
    KC(64),	KS_KP_Next,	KS_KP_3,
    KC(65),	KS_KP_Delete,	KS_KP_Decimal,
    KC(66),	KS_KP_Home,	KS_KP_7,
    KC(67),	KS_KP_Up,	KS_KP_8,
    KC(68),	KS_KP_Begin,	KS_KP_5,
    KC(69),	KS_KP_Right,	KS_KP_6,
    KC(72),	KS_Left,
    KC(73),	KS_Down,
    KC(74),	KS_KP_Prior,	KS_KP_9,
    KC(75),	KS_KP_Subtract,
    KC(79),	KS_Right,
    KC(80),	KS_Up,
    KC(81),	KS_KP_Enter,
    KC(82),	KS_space,
    KC(83),	KS_Cmd2,	KS_Alt_L,
    KC(84),	KS_Cmd2,	KS_Alt_R,	KS_Multi_key,
    KC(85),	KS_Cmd1,	KS_Control_R,
    KC(86),	KS_Cmd_Screen0,	KS_f1,
    KC(87),	KS_Cmd_Screen1,	KS_f2,
    KC(88),	KS_Cmd_Screen2,	KS_f3,
    KC(89),	KS_Cmd_Screen3,	KS_f4,
    KC(90),	KS_Cmd_Screen4,	KS_f5,
    KC(91),	KS_Cmd_Screen5,	KS_f6,
    KC(92),	KS_Cmd_Screen6,	KS_f7,
    KC(93),	KS_Cmd_Screen7,	KS_f8,
    KC(94),	KS_Cmd_Screen8,	KS_f9,
    KC(95),	KS_Cmd_Screen9,	KS_f10,
    KC(96),	KS_Cmd_Screen10,KS_f11,
    KC(97),	KS_Cmd_Screen11,KS_f12,
    KC(98),	KS_Print_Screen,
    KC(99),	KS_Hold_Screen,
    KC(100),	KS_Pause,	/*Break*/
    KC(101),	KS_Insert,
    KC(102),	KS_Home,
    KC(103),	KS_Cmd_ScrollBack,KS_Prior,
    KC(104),	KS_End,
    KC(105),	KS_Cmd_ScrollFwd,KS_Next,
    KC(106),	KS_Num_Lock,
    KC(107),	KS_KP_Divide,
    KC(108),	KS_KP_Multiply,
    KC(109),	KS_KP_Add,
};

#if !defined(WSKBD_NO_INTL_LAYOUTS)

static const keysym_t zskbd_keydesc_de[] = {
/*  pos      normal		shifted		altgr		shift-altgr */
    KC(9),	KS_q,		KS_Q,		KS_at,
    KC(13),	KS_2,		KS_quotedbl,	KS_twosuperior,
    KC(14),	KS_3,		KS_section,	KS_threesuperior,
    KC(19),	KS_y,
    KC(29),	KS_6,		KS_ampersand,
    KC(30),	KS_7,		KS_slash,	KS_braceleft,
    KC(31),	KS_z,
    KC(37),	KS_8,		KS_parenleft,	KS_bracketleft,
    KC(38),	KS_9,		KS_parenright,	KS_bracketright,
    KC(42),	KS_odiaeresis,
    KC(43),	KS_m,		KS_M,		KS_mu,
    KC(44),	KS_comma,	KS_semicolon,
    KC(45),	KS_0,		KS_equal,	KS_braceright,
    KC(46),	KS_ssharp,	KS_question,	KS_backslash,
    KC(48),	KS_udiaeresis,
    KC(49),	KS_adiaeresis,
    KC(51),	KS_period,	KS_colon,
    KC(52),	KS_minus,	KS_underscore,
    KC(53),	KS_dead_acute,	KS_dead_grave,
    KC(54),	KS_dead_circumflex,KS_dead_abovering,
    KC(55),	KS_plus,	KS_asterisk,	KS_dead_tilde,
    KC(56),	KS_numbersign,	KS_apostrophe,
    KC(84),	KS_Mode_switch,	KS_Multi_key,
    KC(111),	KS_less,	KS_greater,	KS_bar,		KS_brokenbar,
};

static const keysym_t zskbd_keydesc_de_nodead[] = {
/*  pos      normal		shifted		altgr		shift-altgr */
    KC(53),	KS_apostrophe,	KS_grave,
    KC(54),	KS_asciicircum,	KS_degree,
    KC(55),	KS_plus,	KS_asterisk,	KS_asciitilde,
};

static const keysym_t zskbd_keydesc_dk[] = {
/*  pos      normal		shifted		altgr		shift-altgr */
    KC(13),	KS_2,		KS_quotedbl,	KS_at,
    KC(14),	KS_3,		KS_numbersign,	KS_sterling,
    KC(21),	KS_4,		KS_currency,	KS_dollar,
    KC(29),	KS_6,		KS_ampersand,
    KC(30),	KS_7,		KS_slash,	KS_braceleft,
    KC(37),	KS_8,		KS_parenleft,	KS_bracketleft,
    KC(38),	KS_9,		KS_parenright,	KS_bracketright,
    KC(42),	KS_ae,
    KC(44),	KS_comma,	KS_semicolon,
    KC(45),	KS_0,		KS_equal,	KS_braceright,
    KC(46),	KS_plus,	KS_question,
    KC(48),	KS_aring,
    KC(49),	KS_oslash,
    KC(51),	KS_period,	KS_colon,
    KC(52),	KS_minus,	KS_underscore,
    KC(53),	KS_dead_acute,	KS_dead_grave,	KS_bar,
    KC(54),	KS_onehalf,	KS_paragraph,
    KC(55),	KS_dead_diaeresis,KS_dead_circumflex,KS_dead_tilde,
    KC(56),	KS_apostrophe,	KS_asterisk,
    KC(84),	KS_Mode_switch,	KS_Multi_key,
    KC(111),	KS_less,	KS_greater,	KS_backslash,
};

static const keysym_t zskbd_keydesc_dk_nodead[] = {
/*  pos      normal		shifted		altgr		shift-altgr */
    KC(53),	KS_apostrophe,	KS_grave,	KS_bar,
    KC(55),	KS_diaeresis,	KS_asciicircum,	KS_asciitilde,
};

static const keysym_t zskbd_keydesc_sv[] = {
/*  pos      normal		shifted		altgr		shift-altgr */
    KC(42),	KS_odiaeresis,
    KC(46),	KS_plus,	KS_question,	KS_backslash,
    KC(49),	KS_adiaeresis,
    KC(54),	KS_section,	KS_onehalf,
    KC(55),	KS_dead_diaeresis,KS_dead_circumflex,KS_dead_tilde,
    KC(84),	KS_Mode_switch,	KS_Multi_key,
    KC(111),	KS_less,	KS_greater,	KS_bar,
};

static const keysym_t zskbd_keydesc_sv_nodead[] = {
/*  pos      normal		shifted		altgr		shift-altgr */
    KC(53),	KS_apostrophe,	KS_grave,	KS_bar,
    KC(55),	KS_diaeresis,	KS_asciicircum,	KS_asciitilde,
};

static const keysym_t zskbd_keydesc_no[] = {
/*  pos      normal		shifted		altgr		shift-altgr */
    KC(42),	KS_oslash,
    KC(49),	KS_ae,
    KC(53),	KS_backslash,	KS_dead_grave,	KS_dead_acute,
    KC(54),	KS_bar,		KS_paragraph,
    KC(55),	KS_dead_diaeresis,KS_dead_circumflex,KS_dead_tilde,
    KC(111),	KS_less,	KS_greater,
};

static const keysym_t zskbd_keydesc_no_nodead[] = {
/*  pos      normal		shifted		altgr		shift-altgr */
    KC(53),	KS_backslash,	KS_grave,	KS_acute,
    KC(55),	KS_diaeresis,	KS_asciicircum,	KS_asciitilde,
};

static const keysym_t zskbd_keydesc_fr[] = {
/*  pos	     normal		shifted		altgr		shift-altgr */
    KC(7),	KS_ampersand,	KS_1,
    KC(9),	KS_a,
    KC(10),	KS_q,
    KC(13),	KS_eacute,	KS_2,		KS_asciitilde,
    KC(14),	KS_quotedbl,	KS_3,		KS_numbersign,
    KC(15),	KS_z,
    KC(19),	KS_w,
    KC(21),	KS_apostrophe,	KS_4,		KS_braceleft,
    KC(22),	KS_parenleft,	KS_5,		KS_bracketleft,
    KC(29),	KS_minus,	KS_6,		KS_bar,
    KC(30),	KS_egrave,	KS_7,		KS_grave,
    KC(37),	KS_underscore,	KS_8,		KS_backslash,
    KC(38),	KS_ccedilla,	KS_9,		KS_asciicircum,
    KC(42),	KS_m,
    KC(43),	KS_comma,	KS_question,
    KC(44),	KS_semicolon,	KS_period,
    KC(45),	KS_agrave,	KS_0,		KS_at,
    KC(46),	KS_parenright,	KS_degree,	KS_bracketright,
    KC(48),	KS_dead_circumflex,KS_dead_diaeresis,
    KC(49),	KS_ugrave,	KS_percent,
    KC(51),	KS_colon,	KS_slash,
    KC(52),	KS_exclam,	KS_section,
    KC(53),	KS_equal,	KS_plus,	KS_braceright,
    KC(54),	KS_twosuperior,
    KC(55),	KS_dollar,	KS_sterling,	KS_currency,
    KC(56),	KS_asterisk,	KS_mu,
    KC(84),	KS_Mode_switch,	KS_Multi_key,
    KC(111),	KS_less,	KS_greater,
};

/*
 * fr-dvorak-be'po layout, simplified map, per http://www.clavier-dvorak.org/
 * (the complete map is still a moving target)
 */
/* fr_dvorak_bepo not applicable */

static const keysym_t zskbd_keydesc_it[] = {
/*  pos      normal		shifted		altgr		shift-altgr */
    KC(13),	KS_2,		KS_quotedbl,	KS_twosuperior,
    KC(14),	KS_3,		KS_sterling,	KS_threesuperior,
    KC(22),	KS_5,		KS_percent,
    KC(29),	KS_6,		KS_ampersand,
    KC(30),	KS_7,		KS_slash,
    KC(37),	KS_8,		KS_parenleft,
    KC(38),	KS_9,		KS_parenright,
    KC(42),	KS_ograve,	KS_Ccedilla,	KS_at,
    KC(44),	KS_comma,	KS_semicolon,
    KC(45),	KS_0,		KS_equal,
    KC(46),	KS_apostrophe,	KS_question,
    KC(48),	KS_egrave,	KS_eacute,	KS_braceleft,	KS_bracketleft,
    KC(49),	KS_agrave,	KS_degree,	KS_numbersign,
    KC(51),	KS_period,	KS_colon,
    KC(52),	KS_minus,	KS_underscore,
    KC(53),	KS_igrave,	KS_asciicircum,
    KC(54),	KS_backslash,	KS_bar,
    KC(55),	KS_plus,	KS_asterisk,	KS_braceright,	KS_bracketright,
    KC(56),	KS_ugrave,	KS_section,
    KC(84),	KS_Mode_switch,	KS_Multi_key,
    KC(111),	KS_less,	KS_greater,
};

static const keysym_t zskbd_keydesc_uk[] = {
/*  pos      normal		shifted		altgr		shift-altgr */
    KC(7),	KS_1,		KS_exclam,	KS_plusminus,	KS_exclamdown,
    KC(13),	KS_2,		KS_quotedbl,	KS_twosuperior,	KS_cent,
    KC(14),	KS_3,		KS_sterling,	KS_threesuperior,
    KC(21),	KS_4,		KS_dollar,	KS_acute,	KS_currency,
    KC(22),	KS_5,		KS_percent,	KS_mu,		KS_yen,
    KC(29),	KS_6,		KS_asciicircum,	KS_paragraph,
    KC(30),	KS_7,		KS_ampersand,	KS_periodcentered,KS_brokenbar,
    KC(37),	KS_8,		KS_asterisk,	KS_cedilla,	KS_ordfeminine,
    KC(38),	KS_9,		KS_parenleft,	KS_onesuperior,	KS_diaeresis,
    KC(45),	KS_0,		KS_parenright,	KS_masculine,	KS_copyright,
    KC(46),	KS_minus,	KS_underscore,	KS_hyphen,	KS_ssharp,
    KC(49),	KS_apostrophe,	KS_at,		KS_section,	KS_Agrave,
    KC(53),	KS_equal,	KS_plus,	KS_onehalf,	KS_guillemotleft,
    KC(54),	KS_grave,	KS_grave,	KS_agrave,	KS_agrave,
    KC(56),	KS_numbersign,	KS_asciitilde,	KS_sterling,	KS_thorn,
    KC(111),	KS_backslash,	KS_bar,		KS_Udiaeresis,
};

/* jp not applicable */

static const keysym_t zskbd_keydesc_es[] = {
/*  pos      normal		shifted		altgr		shift-altgr */
    KC(7),	KS_1,		KS_exclam,	KS_bar,
    KC(13),	KS_2,		KS_quotedbl,	KS_at,
    KC(14),	KS_3,		KS_periodcentered,KS_numbersign,
    KC(21),	KS_4,		KS_dollar,	KS_asciitilde,
    KC(29),	KS_6,		KS_ampersand,
    KC(30),	KS_7,		KS_slash,
    KC(37),	KS_8,		KS_parenleft,
    KC(38),	KS_9,		KS_parenright,
    KC(42),	KS_ntilde,
    KC(44),	KS_comma,	KS_semicolon,
    KC(45),	KS_0,		KS_equal,
    KC(46),	KS_apostrophe,	KS_question,
    KC(48),	KS_dead_grave,	KS_dead_circumflex,KS_bracketleft,
    KC(49),	KS_dead_acute,	KS_dead_diaeresis,KS_braceleft,
    KC(51),	KS_period,	KS_colon,
    KC(52),	KS_minus,	KS_underscore,
    KC(53),	KS_exclamdown,	KS_questiondown,
    KC(54),	KS_degree,	KS_ordfeminine,	KS_backslash,
    KC(55),	KS_plus,	KS_asterisk,	KS_bracketright,
    KC(56),	KS_ccedilla,	KS_Ccedilla,	KS_braceright,
    KC(84),	KS_Mode_switch,	KS_Multi_key,
    KC(111),	KS_less,	KS_greater,
};

/* lt not applicable */

static const keysym_t zskbd_keydesc_be[] = {
/*  pos      normal		shifted		altgr		shift-altgr */
    KC(7),	KS_ampersand,	KS_1,		KS_bar,
    KC(9),	KS_a,
    KC(10),	KS_q,
    KC(13),	KS_eacute,	KS_2,		KS_at,
    KC(14),	KS_quotedbl,	KS_3,		KS_numbersign,
    KC(15),	KS_z,
    KC(19),	KS_w,
    KC(21),	KS_apostrophe,	KS_4,
    KC(22),	KS_parenleft,	KS_5,
    KC(29),	KS_section,	KS_6,		KS_asciicircum,
    KC(30),	KS_egrave,	KS_7,
    KC(37),	KS_exclam,	KS_8,
    KC(38),	KS_ccedilla,	KS_9,		KS_braceleft,
    KC(42),	KS_m,
    KC(43),	KS_comma,	KS_question,
    KC(44),	KS_semicolon,	KS_period,
    KC(45),	KS_agrave,	KS_0,		KS_braceright,
    KC(46),	KS_parenright,	KS_degree,
    KC(48),	KS_dead_circumflex,KS_dead_diaeresis,KS_bracketleft,
    KC(49),	KS_ugrave,	KS_percent,	KS_acute,
    KC(51),	KS_colon,	KS_slash,
    KC(52),	KS_equal,	KS_plus,	KS_asciitilde,
    KC(53),	KS_minus,	KS_underscore,
    KC(54),	KS_twosuperior,	KS_threesuperior,
    KC(55),	KS_dollar,	KS_asterisk,	KS_bracketright,
    KC(56),	KS_mu,		KS_sterling,	KS_grave,
    KC(84),	KS_Mode_switch,	KS_Multi_key,
    KC(111),	KS_less,	KS_greater,	KS_backslash,
};

/* us_declk not applicable */

/* us_dvorak not applicable */

/* swapctrlcaps not applicable */

/* iopener not applicable */

/* ru not applicable */

/* ua not applicable */

static const keysym_t zskbd_keydesc_sg[] = {
/*  pos      normal		shifted		altgr		shift-altgr */
    KC(7),	KS_1,		KS_plus,	KS_bar,
    KC(13),	KS_2,		KS_quotedbl,	KS_at,
    KC(14),	KS_3,		KS_asterisk,	KS_numbersign,
    KC(16),	KS_e,		KS_E,		KS_currency,
    KC(19),	KS_y,
    KC(21),	KS_4,		KS_ccedilla,
    KC(29),	KS_6,		KS_ampersand,	KS_notsign,
    KC(30),	KS_7,		KS_slash,	KS_brokenbar,
    KC(31),	KS_z,
    KC(37),	KS_8,		KS_parenleft,	KS_cent,
    KC(38),	KS_9,		KS_parenright,
    KC(42),	KS_odiaeresis,	KS_eacute,
    KC(44),	KS_comma,	KS_semicolon,
    KC(45),	KS_0,		KS_equal,
    KC(46),	KS_apostrophe,	KS_question,	KS_dead_acute,
    KC(48),	KS_udiaeresis,	KS_egrave,	KS_bracketleft,
    KC(49),	KS_adiaeresis,	KS_agrave,	KS_braceleft,
    KC(51),	KS_period,	KS_colon,
    KC(52),	KS_minus,	KS_underscore,
    KC(53),	KS_dead_circumflex,KS_dead_grave,KS_dead_tilde,
    KC(54),	KS_section,	KS_degree,	KS_dead_abovering,
    KC(55),	KS_dead_diaeresis,KS_exclam,	KS_bracketright,
    KC(56),	KS_dollar,	KS_sterling,	KS_braceright,
    KC(84),	KS_Mode_switch,	KS_Multi_key,
    KC(111),	KS_less,	KS_greater,	KS_backslash,
};

static const keysym_t zskbd_keydesc_sg_nodead[] = {
/*  pos      normal		shifted		altgr		shift-altgr */
    KC(46),	KS_apostrophe,	KS_question,	KS_acute,
    KC(53),	KS_asciicircum,	KS_grave,	KS_asciitilde,
    KC(55),	KS_diaeresis,	KS_exclam,	KS_bracketright,
};

static const keysym_t zskbd_keydesc_sf[] = {
/*  pos      normal		shifted		altgr		shift-altgr */
    KC(42),	KS_eacute,	KS_odiaeresis,
    KC(48),	KS_egrave,	KS_udiaeresis,	KS_bracketleft,
    KC(49),	KS_agrave,	KS_adiaeresis,	KS_braceleft,
};

static const keysym_t zskbd_keydesc_pt[] = {
/*  pos      normal		shifted		altgr		shift-altgr */
    KC(13),	KS_2,		KS_quotedbl,	KS_at,
    KC(14),	KS_3,		KS_numbersign,	KS_sterling,
    KC(29),	KS_6,		KS_ampersand,
    KC(30),	KS_7,		KS_slash,	KS_braceleft,
    KC(37),	KS_8,		KS_parenleft,	KS_bracketleft,
    KC(38),	KS_9,		KS_parenright,	KS_bracketright,
    KC(42),	KS_ccedilla,	KS_Ccedilla,
    KC(44),	KS_comma,	KS_semicolon,
    KC(45),	KS_0,		KS_equal,	KS_braceright,
    KC(46),	KS_apostrophe,	KS_question,
    KC(48),	KS_plus,	KS_asterisk,
    KC(49),	KS_masculine,	KS_ordfeminine,
    KC(51),	KS_period,	KS_colon,
    KC(52),	KS_minus,	KS_underscore,
    KC(53),	KS_less,	KS_greater,
    KC(54),	KS_backslash,	KS_bar,
    KC(55),	KS_dead_acute,	KS_dead_grave,
    KC(56),	KS_dead_tilde,	KS_dead_circumflex,
    KC(84),	KS_Mode_switch,	KS_Multi_key,
    KC(111),	KS_less,	KS_greater,
};

/* la not applicable */

/* br not applicable */

/* tr not applicable */

/* tr_nodead not applicable */

/* pl not applicable */

/* hu not applicable */

/* si not applicable */

/* cf not applicable */

/* cf_nodead not applicable */

/* lv not applicable */

static const keysym_t zskbd_keydesc_nl[] = {
/*  pos      normal		shifted		altgr		shift-altgr */
    KC(7),	KS_1,		KS_exclam,	KS_onesuperior,
    KC(11),	KS_s,		KS_S,		KS_ssharp,
    KC(13),	KS_2,		KS_quotedbl,	KS_twosuperior,
    KC(14),	KS_3,		KS_numbersign,	KS_threesuperior,
    KC(19),	KS_z,		KS_Z,		KS_guillemotleft,
    KC(20),	KS_x,		KS_X,		KS_guillemotright,
    KC(21),	KS_4,		KS_dollar,	KS_onequarter,
    KC(22),	KS_5,		KS_percent,	KS_onehalf,
    KC(23),	KS_r,		KS_R,		KS_paragraph,
    KC(27),	KS_c,		KS_C,		KS_cent,
    KC(29),	KS_6,		KS_ampersand,	KS_threequarters,
    KC(30),	KS_7,		KS_underscore,	KS_sterling,
    KC(37),	KS_8,		KS_parenleft,	KS_braceleft,
    KC(38),	KS_9,		KS_parenright,	KS_braceright,
    KC(42),	KS_plus,	KS_plusminus,
    KC(43),	KS_m,		KS_M,		KS_mu,
    KC(44),	KS_comma,	KS_semicolon,
    KC(45),	KS_0,		KS_apostrophe,
    KC(46),	KS_slash,	KS_question,	KS_backslash,
    KC(48),	KS_dead_diaeresis,KS_dead_circumflex,
    KC(49),	KS_dead_acute,	KS_dead_grave,
    KC(51),	KS_period,	KS_colon,	KS_periodcentered,
    KC(52),	KS_minus,	KS_equal,
    KC(53),	KS_degree,	KS_dead_tilde,	KS_dead_cedilla,
    KC(54),	KS_at,		KS_section,	KS_notsign,
    KC(55),	KS_asterisk,	KS_bar,
    KC(56),	KS_less,	KS_greater,
    KC(84),	KS_Mode_switch,	KS_Multi_key,
    KC(111),	KS_bracketright,KS_bracketleft,	KS_brokenbar,
};

static const keysym_t zskbd_keydesc_nl_nodead[] = {
/*  pos      normal		shifted		altgr		shift-altgr */
    KC(48),	KS_quotedbl,	KS_asciicircum,
    KC(49),	KS_apostrophe,	KS_grave,
    KC(53),	KS_degree,	KS_asciitilde,	KS_cedilla,
};

/* is not applicable */

/* is_nodead not applicable */

#endif	/* WSKBD_NO_INTL_LAYOUTS */

#define KBD_MAP(name, base, map) \
			{ name, base, sizeof(map)/sizeof(keysym_t), map }

const struct wscons_keydesc wssgi_keydesctab[] = {
	KBD_MAP(KB_US,			0,	zskbd_keydesc_us),
#if !defined(WSKBD_NO_INTL_LAYOUTS)
	KBD_MAP(KB_DE,			KB_US,	zskbd_keydesc_de),
	KBD_MAP(KB_DE | KB_NODEAD,	KB_DE,	zskbd_keydesc_de_nodead),
	KBD_MAP(KB_FR,			KB_US,	zskbd_keydesc_fr),
	KBD_MAP(KB_DK,			KB_US,	zskbd_keydesc_dk),
	KBD_MAP(KB_DK | KB_NODEAD,	KB_DK,	zskbd_keydesc_dk_nodead),
	KBD_MAP(KB_IT,			KB_US,	zskbd_keydesc_it),
	KBD_MAP(KB_UK,			KB_US,	zskbd_keydesc_uk),
	KBD_MAP(KB_SV,			KB_DK,	zskbd_keydesc_sv),
	KBD_MAP(KB_SV | KB_NODEAD,	KB_SV,	zskbd_keydesc_sv_nodead),
	KBD_MAP(KB_NO,			KB_DK,	zskbd_keydesc_no),
	KBD_MAP(KB_NO | KB_NODEAD,	KB_NO,	zskbd_keydesc_no_nodead),
	KBD_MAP(KB_ES,			KB_US,	zskbd_keydesc_es),
	KBD_MAP(KB_BE,			KB_US,	zskbd_keydesc_be),
	KBD_MAP(KB_SG,			KB_US,	zskbd_keydesc_sg),
	KBD_MAP(KB_SG | KB_NODEAD,	KB_SG,	zskbd_keydesc_sg_nodead),
	KBD_MAP(KB_SF,			KB_SG,	zskbd_keydesc_sf),
	KBD_MAP(KB_SF | KB_NODEAD,	KB_SF,	zskbd_keydesc_sg_nodead),
	KBD_MAP(KB_PT,			KB_US,	zskbd_keydesc_pt),
	KBD_MAP(KB_NL,			KB_US, 	zskbd_keydesc_nl),
	KBD_MAP(KB_NL | KB_NODEAD,	KB_NL,	zskbd_keydesc_nl_nodead),
#endif	/* WSKBD_NO_INTL_LAYOUTS */
	{0, 0, 0, 0}
};

#undef KBD_MAP
#undef KC