code:
/*	$OpenBSD: kcore.h,v 1.3 2005/09/06 19:28:22 miod Exp $	*/

/*
 * Copyright (c) 2001 Miodrag Vallat.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef	_M88K_KCORE_H_
#define	_M88K_KCORE_H_

/* Keep this define consistent with VM_PHYSSEG_MAX in <machine/vmparam.h> */
#define	NPHYS_RAM_SEGS	1

typedef struct cpu_kcore_hdr {
	int		cputype;	/* cpu type: 88100, 88110 */
	phys_ram_seg_t	ram_segs[NPHYS_RAM_SEGS];
} cpu_kcore_hdr_t;

#endif	/* _M88K_KCORE_H_ */


code:
/*	$OpenBSD: limits.h,v 1.7 2015/04/30 13:42:08 millert Exp $ */
/*
 * Copyright (c) 1988, 1993
 *	The Regents of the University of California.  All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of the University nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 *	from: @(#)limits.h	8.3 (Berkeley) 1/4/94
 */

#ifndef _M88K_LIMITS_H_
#define _M88K_LIMITS_H_

#include <sys/cdefs.h>

#if __POSIX_VISIBLE || __XPG_VISIBLE
#define	SSIZE_MAX	LONG_MAX	/* max value for a ssize_t */
#endif

#if __BSD_VISIBLE
#define	SIZE_T_MAX	ULONG_MAX	/* max value for a size_t (historic) */

/* GCC requires that quad constants be written as expressions. */
#define	UQUAD_MAX	((u_quad_t)0-1)	/* max value for a uquad_t */
					/* max value for a quad_t */
#define	QUAD_MAX	((quad_t)(UQUAD_MAX >> 1))
#define	QUAD_MIN	(-QUAD_MAX-1)	/* min value for a quad_t */
#endif /* __BSD_VISIBLE */

#endif /* _M88K_LIMITS_H_ */

license: unknown


code:
#ifndef	_M88K_LOCK_H_
#define	_M88K_LOCK_H_
/*	$OpenBSD: lock.h,v 1.11 2015/02/11 00:14:11 dlg Exp $	*/

/*
 * Copyright (c) 2005, Miodrag Vallat.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

#include <m88k/asm.h>

typedef volatile u_int	__cpu_simple_lock_t;

/* do not change these - code below assumes r0 == __SIMPLELOCK_UNLOCKED */
#define	__SIMPLELOCK_LOCKED	1
#define	__SIMPLELOCK_UNLOCKED	0

static __inline__ void
__cpu_simple_lock_init(__cpu_simple_lock_t *l)
{
	*l = __SIMPLELOCK_UNLOCKED;
}

static __inline__ int
__cpu_simple_lock_try(__cpu_simple_lock_t *l)
{
	/*
	 * The local __cpu_simple_lock_t is not declared volatile, so that
	 * there are not pipeline synchronization around stores to it.
	 * xmem will do the right thing regardless of the volatile qualifier.
	 */
	u_int old = __SIMPLELOCK_LOCKED;

	__asm__ volatile
	    ("xmem %0, %2, %%r0" : "+r"(old), "+m"(*l) : "r"(l));

	return (old == __SIMPLELOCK_UNLOCKED);
}

static __inline__ void
__cpu_simple_lock(__cpu_simple_lock_t *l)
{
	for (;;) {
		if (__cpu_simple_lock_try(l) != 0)
			break;
		while (*l != __SIMPLELOCK_UNLOCKED)
			;	/* spin without exclusive bus access */
	}
}

static __inline__ void
__cpu_simple_unlock(__cpu_simple_lock_t *l)
{
	*l = __SIMPLELOCK_UNLOCKED;
}

#endif	/* _M88K_LOCK_H_ */


code:
/*	$OpenBSD: m88100.h,v 1.9 2014/05/31 11:19:06 miod Exp $ */
/*
 * Mach Operating System
 * Copyright (c) 1993-1992 Carnegie Mellon University
 * All Rights Reserved.
 *
 * Permission to use, copy, modify and distribute this software and its
 * documentation is hereby granted, provided that both the copyright
 * notice and this permission notice appear in all copies of the
 * software, derivative works or modified versions, and any portions
 * thereof, and that both notices appear in supporting documentation.
 *
 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
 * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
 *
 * Carnegie Mellon requests users of this software to return to
 *
 *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
 *  School of Computer Science
 *  Carnegie Mellon University
 *  Pittsburgh PA 15213-3890
 *
 * any improvements or extensions that they make and grant Carnegie Mellon
 * the rights to redistribute these changes.
 */

#ifndef _M88K_M88100_H_
#define _M88K_M88100_H_

/*
 *	88100 RISC definitions
 */

/*
 * DMT0, DMT1, DMT2 layout
 */
#define DMT_BO		0x00008000	/* Byte-Ordering */
#define DMT_DAS		0x00004000	/* Data Access Space */
#define DMT_DOUB1	0x00002000	/* Double Word */
#define DMT_LOCKBAR	0x00001000	/* Bud Lock */
#define DMT_DREG	0x00000F80	/* Destination Registers 5bits */
#define DMT_SIGNED	0x00000040	/* Sign-Extended Bit */
#define DMT_EN		0x0000003C	/* Byte Enable Bit */
#define DMT_WRITE	0x00000002	/* Read/Write Transaction Bit */
#define	DMT_VALID	0x00000001	/* Valid Transaction Bit */

#define	DMT_DREGSHIFT	7
#define	DMT_ENSHIFT	2

#define	DMT_DREGBITS(x)	(((x) & DMT_DREG) >> DMT_DREGSHIFT)
#define	DMT_ENBITS(x)	(((x) & DMT_EN) >> DMT_ENSHIFT)

#if defined(_KERNEL) && !defined(_LOCORE)

void	dae_print(u_int *);
void	data_access_emulation(u_int *);

u_int32_t do_load_word(vaddr_t, int);
u_int32_t do_load_half(vaddr_t, int);
u_int32_t do_load_byte(vaddr_t, int);
void      do_store_word(vaddr_t, u_int32_t, int);
void      do_store_half(vaddr_t, u_int16_t, int);
void      do_store_byte(vaddr_t, u_int8_t, int);
u_int32_t do_xmem_word(vaddr_t, u_int32_t, int);
u_int8_t  do_xmem_byte(vaddr_t, u_int8_t, int);

void	m88100_apply_patches(void);
void	m88100_smp_setup(struct cpu_info *);

/* rewind one instruction */
static __inline__ void
m88100_rewind_insn(struct reg *regs)
{
	regs->sfip = regs->snip;
	regs->snip = regs->sxip;
}

#endif

#endif /* _M88K_M88100_H_ */


code:
/*	$OpenBSD: m8820x.h,v 1.10 2013/05/17 22:33:25 miod Exp $ */
/*
 * Copyright (c) 2004, Miodrag Vallat.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */
/*
 * Mach Operating System
 * Copyright (c) 1993-1992 Carnegie Mellon University
 * All Rights Reserved.
 *
 * Permission to use, copy, modify and distribute this software and its
 * documentation is hereby granted, provided that both the copyright
 * notice and this permission notice appear in all copies of the
 * software, derivative works or modified versions, and any portions
 * thereof, and that both notices appear in supporting documentation.
 *
 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
 * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
 *
 * Carnegie Mellon requests users of this software to return to
 *
 *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
 *  School of Computer Science
 *  Carnegie Mellon University
 *  Pittsburgh PA 15213-3890
 *
 * any improvements or extensions that they make and grant Carnegie Mellon
 * the rights to redistribute these changes.
 */

#ifndef	_M88K_M8820X_H_
#define	_M88K_M8820X_H_

/*
 * 8820x CMMU definitions
 */

/* CMMU registers */
#define CMMU_IDR	(0x000 / 4)	/* CMMU id register */
#define CMMU_SCR	(0x004 / 4)	/* system command register */
#define CMMU_SSR	(0x008 / 4)	/* system status register */
#define CMMU_SAR	(0x00c / 4)	/* system address register */
#define CMMU_SCTR	(0x104 / 4)	/* system control register */
#define CMMU_PFSR	(0x108 / 4)	/* P bus fault status register */
#define CMMU_PFAR	(0x10c / 4)	/* P bus fault address register */
#define CMMU_SAPR	(0x200 / 4)	/* supervisor area pointer register */
#define CMMU_UAPR	(0x204 / 4)	/* user area pointer register */
#define CMMU_BWP0	(0x400 / 4)	/* block ATC writer port 0 */
#define CMMU_BWP1	(0x404 / 4)	/* block ATC writer port 1 */
#define CMMU_BWP2	(0x408 / 4)	/* block ATC writer port 2 */
#define CMMU_BWP3	(0x40c / 4)	/* block ATC writer port 3 */
#define CMMU_BWP4	(0x410 / 4)	/* block ATC writer port 4 */
#define CMMU_BWP5	(0x414 / 4)	/* block ATC writer port 5 */
#define CMMU_BWP6	(0x418 / 4)	/* block ATC writer port 6 */
#define CMMU_BWP7	(0x41c / 4)	/* block ATC writer port 7 */
#define CMMU_BWP(n)	(CMMU_BWP0 + (n))
#define CMMU_CDP0	(0x800 / 4)	/* cache data port 0 */
#define CMMU_CDP1	(0x804 / 4)	/* cache data port 1 */
#define CMMU_CDP2	(0x808 / 4)	/* cache data port 2 */
#define CMMU_CDP3	(0x80c / 4)	/* cache data port 3 */
#define CMMU_CTP0	(0x840 / 4)	/* cache tag port 0 */
#define CMMU_CTP1	(0x844 / 4)	/* cache tag port 1 */
#define CMMU_CTP2	(0x848 / 4)	/* cache tag port 2 */
#define CMMU_CTP3	(0x84c / 4)	/* cache tag port 3 */
#define CMMU_CSSP0	(0x880 / 4)	/* cache set status register */
#define CMMU_CSSP(n)	((0x880 + (n * 0x10)) / 4)
/* the following only exist on 88204 */
#define CMMU_CSSP1	(0x890 / 4)	/* cache set status register */
#define CMMU_CSSP2	(0x8a0 / 4)	/* cache set status register */
#define CMMU_CSSP3	(0x8b0 / 4)	/* cache set status register */

/* system commands */
#define CMMU_FLUSH_CACHE_INV_LINE	0x14	/* data cache invalidate */
#define CMMU_FLUSH_CACHE_INV_PAGE	0x15
#define CMMU_FLUSH_CACHE_INV_SEGMENT	0x16
#define CMMU_FLUSH_CACHE_INV_ALL	0x17
#define CMMU_FLUSH_CACHE_CB_LINE	0x18	/* data cache copyback */
#define CMMU_FLUSH_CACHE_CB_PAGE	0x19
#define CMMU_FLUSH_CACHE_CB_SEGMENT	0x1a
#define CMMU_FLUSH_CACHE_CB_ALL		0x1b
#define CMMU_FLUSH_CACHE_CBI_LINE	0x1c	/* copyback and invalidate */
#define CMMU_FLUSH_CACHE_CBI_PAGE	0x1d
#define CMMU_FLUSH_CACHE_CBI_SEGMENT	0x1e
#define CMMU_FLUSH_CACHE_CBI_ALL	0x1f
#define CMMU_PROBE_USER			0x20	/* probe user address */
#define CMMU_PROBE_SUPER		0x24	/* probe supervisor address */
#define CMMU_FLUSH_USER_LINE		0x30	/* flush PATC */
#define CMMU_FLUSH_USER_PAGE		0x31
#define CMMU_FLUSH_USER_SEGMENT		0x32
#define CMMU_FLUSH_USER_ALL		0x33
#define CMMU_FLUSH_SUPER_LINE		0x34
#define CMMU_FLUSH_SUPER_PAGE		0x35
#define CMMU_FLUSH_SUPER_SEGMENT	0x36
#define CMMU_FLUSH_SUPER_ALL		0x37

/* system control values */
#define CMMU_SCTR_PE	0x00008000	/* parity enable */
#define CMMU_SCTR_SE	0x00004000	/* snoop enable */
#define CMMU_SCTR_PR	0x00002000	/* priority arbitration */

/* P bus fault status */
#define	CMMU_PFSR_FAULT(pfsr)	(((pfsr) >> 16) & 0x07)
#define CMMU_PFSR_SUCCESS	0	/* no fault */
#define CMMU_PFSR_BERROR	3	/* bus error */
#define CMMU_PFSR_SFAULT	4	/* segment fault */
#define CMMU_PFSR_PFAULT	5	/* page fault */
#define CMMU_PFSR_SUPER		6	/* supervisor violation */
#define CMMU_PFSR_WRITE		7	/* writer violation */

/* CSSP values */
#define	CMMU_CSSP_L5		0x20000000
#define	CMMU_CSSP_L4		0x10000000
#define	CMMU_CSSP_L3		0x08000000
#define	CMMU_CSSP_L2		0x04000000
#define	CMMU_CSSP_L1		0x02000000
#define	CMMU_CSSP_L0		0x01000000
#define	CMMU_CSSP_D3		0x00800000
#define	CMMU_CSSP_D2		0x00400000
#define	CMMU_CSSP_D1		0x00200000
#define	CMMU_CSSP_D0		0x00100000
#define	CMMU_CSSP_VV(n,v)	(((v) & 0x03) << (12 + 2 * (n)))
#define	CMMU_VV_EXCLUSIVE	0x00
#define	CMMU_VV_MODIFIED	0x01
#define	CMMU_VV_SHARED		0x02
#define	CMMU_VV_INVALID		0x03

/* IDR values */
#define	CMMU_ID(idr)		((idr) >> 24)
#define	CMMU_TYPE(idr)		(((idr) >> 21) & 0x07)
#define	CMMU_VERSION(idr)	(((idr) >> 16) & 0x1f)
#define	M88200_ID		5
#define	M88204_ID		6

/* SSR values */
#define	CMMU_SSR_CE		0x00008000	/* copyback error */
#define	CMMU_SSR_BE		0x00004000	/* bus error */
#define	CMMU_SSR_SO		0x00000100
#define	CMMU_SSR_M		0x00000010
#define	CMMU_SSR_U		0x00000008
#define	CMMU_SSR_PROT		0x00000004
#define	CMMU_SSR_BH		0x00000002	/* probe BATC hit */
#define	CMMU_SSR_V		0x00000001

/*
 * Cache line information
 */

#define	MC88200_CACHE_SHIFT	4
#define	MC88200_CACHE_LINE	(1 << MC88200_CACHE_SHIFT)

/*
 * Hardwired BATC information
 */

#define	BATC8			0xfff7ffb5
#define	BATC9			0xfffffff5

#define	BATC8_VA		0xfff00000
#define	BATC9_VA		0xfff80000

#define NBSG    	(1 << (PDT_BITS + PG_BITS))	/* segment size */

#ifndef _LOCORE

/*
 * CMMU kernel information
 */
struct m8820x_cmmu {
	volatile u_int32_t *cmmu_regs;	/* CMMU "base" area */
	u_int32_t	cmmu_idr;
#ifdef M88200_HAS_SPLIT_ADDRESS
	vaddr_t		cmmu_addr;	/* address range */
	vaddr_t		cmmu_addr_mask;	/* address mask */
#endif
};

#define	INST_CMMU	0x00	/* even number */
#define	DATA_CMMU	0x01	/* odd number */
#define	CMMU_MODE(num)	((num) & 1)

#ifdef	M88200_HAS_ASYMMETRICAL_ASSOCIATION
#define MAX_CMMUS	16		/* maximum cmmus on the board */
#else
#define MAX_CMMUS	8		/* maximum cmmus on the board */
#endif
extern struct m8820x_cmmu m8820x_cmmu[MAX_CMMUS];
extern u_int cmmu_shift;
extern u_int max_cmmus;

void	m8820x_setup_board_config(void);
cpuid_t	m8820x_cpu_number(void);

extern const struct cmmu_p cmmu8820x;

#endif	/* _LOCORE */
#endif	/* _M88K_M8820X_H_ */


code:
/*	$OpenBSD: mmu.h,v 1.16 2014/03/29 18:09:29 guenther Exp $ */

/*
 * This file bears almost no resemblance to the original m68k file,
 * so the following copyright notice is questionable, but we are
 * nice people.
 */

/*
 * Copyright (c) 1988 University of Utah.
 * Copyright (c) 1982, 1986, 1990, 1993
 *	The Regents of the University of California.  All rights reserved.
 *
 * This code is derived from software contributed to Berkeley by
 * the Systems Programming Group of the University of Utah Computer
 * Science Department.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of the University nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 * from: Utah $Hdr: pte.h 1.13 92/01/20$
 *
 *	@(#)pte.h	8.1 (Berkeley) 6/10/93
 */

#ifndef	_M88K_MMU_H_
#define	_M88K_MMU_H_

/*
 * Parameters which determine the 'geometry' of the m88K page tables in memory.
 */

#define SDT_BITS	10		/* M88K segment table size bits */
#define PDT_BITS	10		/* M88K page table size bits */
#define PG_BITS		PAGE_SHIFT	/* M88K hardware page size bits */

/*
 * Common fields for APR, SDT and PTE
 */

/* address frame */
#define	PG_FRAME	0xfffff000
#define	PG_SHIFT	PG_BITS
#define	PG_PFNUM(x)	(((x) & PG_FRAME) >> PG_SHIFT)

/* cache control bits */
#define	CACHE_DFL	0x00000000
#define	CACHE_INH	0x00000040	/* cache inhibit */
#define	CACHE_GLOBAL	0x00000080	/* global scope */
#define	CACHE_WT	0x00000200	/* write through */

#define	CACHE_MASK	(CACHE_INH | CACHE_GLOBAL | CACHE_WT)

/*
 * Area descriptors
 */

typedef	uint32_t	apr_t;

#define	APR_V		0x00000001	/* valid bit */

/*
 * 88200 PATC (TLB)
 */

#define PATC_ENTRIES	56

/*
 * Segment table entries
 */

typedef uint32_t	sdt_entry_t;

#define	SG_V		0x00000001
#define	SG_NV		0x00000000
#define	SG_PROT		0x00000004
#define	SG_RO		0x00000004
#define	SG_RW		0x00000000
#define	SG_SO		0x00000100

#define	SDT_VALID(sdt)	(*(sdt) & SG_V)
#define	SDT_SUP(sdt)	(*(sdt) & SG_SO)
#define	SDT_WP(sdt)	(*(sdt) & SG_PROT)

/*
 * Page table entries
 */

typedef uint32_t	pt_entry_t;

#define	PG_V		0x00000001
#define	PG_NV		0x00000000
#define	PG_PROT		0x00000004
#define	PG_U		0x00000008
#define	PG_M		0x00000010
#define	PG_M_U		0x00000018
#define	PG_RO		0x00000004
#define	PG_RW		0x00000000
#define	PG_SO		0x00000100
#define	PG_W		0x00000020	/* XXX unused but reserved field */
#define	PG_U0		0x00000400	/* U0 bit for M88110 */
#define	PG_U1		0x00000800	/* U1 bit for M88110 */

#define	PDT_VALID(pte)	(*(pte) & PG_V)
#define	PDT_SUP(pte)	(*(pte) & PG_SO)
#define	PDT_WP(pte)	(*(pte) & PG_PROT)

/*
 * Number of entries in a page table.
 */

#define	SDT_ENTRIES	(1<<(SDT_BITS))
#define PDT_ENTRIES	(1<<(PDT_BITS))

/*
 * Size in bytes of a single page table.
 */

#define SDT_SIZE	(sizeof(sdt_entry_t) * SDT_ENTRIES)
#define PDT_SIZE	(sizeof(pt_entry_t) * PDT_ENTRIES)

/*
 * Shifts and masks
 */

#define SDT_SHIFT	(PDT_BITS + PG_BITS)
#define PDT_SHIFT	(PG_BITS)

#define SDT_MASK	(((1 << SDT_BITS) - 1) << SDT_SHIFT)
#define PDT_MASK	(((1 << PDT_BITS) - 1) << PDT_SHIFT)

#define	SDTIDX(va)	(((va) & SDT_MASK) >> SDT_SHIFT)
#define	PDTIDX(va)	(((va) & PDT_MASK) >> PDT_SHIFT)

/*
 * BATC entries
 */

#define	BATC_V		0x00000001
#define	BATC_PROT	0x00000002
#define	BATC_INH	0x00000004
#define	BATC_GLOBAL	0x00000008
#define	BATC_WT		0x00000010
#define	BATC_SO		0x00000020

typedef uint32_t	batc_t;

/* 8820x fixed size BATC */
#define	BATC_BLKSHIFT	19
#define	BATC_BLKBYTES	(1 << BATC_BLKSHIFT)
#define	BATC_BLKMASK	(BATC_BLKBYTES-1)
/* number of programmable BATC entries */
#define	BATC_MAX	8

/* physical and logical block address */
#define	BATC_PSHIFT	6
#define	BATC_VSHIFT	19

#define	trunc_batc(a)	((a) & ~BATC_BLKMASK)
#define	round_batc(a)	trunc_batc((a) + BATC_BLKBYTES - 1)

static pt_entry_t invalidate_pte(pt_entry_t *);
static __inline__ pt_entry_t
invalidate_pte(pt_entry_t *pte)
{
	pt_entry_t oldpte;

	oldpte = PG_NV;
	__asm__ volatile
	    ("xmem %0, %2, %%r0" : "+r"(oldpte), "+m"(*pte) : "r"(pte));
	return oldpte;
}

#endif /* __M88K_MMU_H__ */


code:
/*	$OpenBSD: mplock.h,v 1.2 2011/03/23 16:54:35 pirofti Exp $	*/

/*
 * Copyright (c) 2004 Niklas Hallqvist.  All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef _M88K_MPLOCK_H_
#define _M88K_MPLOCK_H_

#ifndef _LOCORE

/*
 * Really simple spinlock implementation with recursive capabilities.
 * Correctness is paramount, no fancyness allowed.
 */

struct __mp_lock {
	__cpu_simple_lock_t mpl_lock;
	volatile struct cpu_info *mpl_cpu;
	volatile int mpl_count;
};

static __inline void
__mp_lock_init(struct __mp_lock *mpl)
{
	__cpu_simple_lock_init(&mpl->mpl_lock);
	mpl->mpl_cpu = NULL;
	mpl->mpl_count = 0;
}

void	__mp_lock(struct __mp_lock *);
void	__mp_unlock(struct __mp_lock *);
int	__mp_release_all(struct __mp_lock *);
int	__mp_release_all_but_one(struct __mp_lock *);

static __inline__ void
__mp_acquire_count(struct __mp_lock *mpl, int count)
{
	while (count--)
		__mp_lock(mpl);
}

static __inline__ int
__mp_lock_held(struct __mp_lock *mpl)
{
	return mpl->mpl_cpu == curcpu();
}

#endif

#endif /* !_MACHINE_MPLOCK_H */


code:
#ifndef _M88K_MUTEX_H_
#define _M88K_MUTEX_H_
/*	$OpenBSD: mutex.h,v 1.4 2015/07/03 15:12:49 miod Exp $	*/

/*
 * Copyright (c) 2005, Miodrag Vallat.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

struct mutex {
	volatile int mtx_lock;	/* mutex.S relies upon this field being first */
	int mtx_wantipl;
	int mtx_oldipl;
	void *mtx_owner;
};

/*
 * To prevent lock ordering problems with the kernel lock, we need to
 * make sure we block all interrupts that can grab the kernel lock.
 * The simplest way to achieve this is to make sure mutexes always
 * raise the interrupt priority level to the highest level that has
 * interrupts that grab the kernel lock.
 */
#ifdef MULTIPROCESSOR
#define __MUTEX_IPL(ipl) \
    (((ipl) > IPL_NONE && (ipl) < IPL_TTY) ? IPL_TTY : (ipl))
#else
#define __MUTEX_IPL(ipl) (ipl)
#endif

#define	MUTEX_INITIALIZER(ipl)	{ 0, __MUTEX_IPL((ipl)), IPL_NONE, NULL }

void __mtx_init(struct mutex *, int);
#define mtx_init(mtx, ipl) __mtx_init((mtx), __MUTEX_IPL((ipl)))

#ifdef DIAGNOSTIC

#define MUTEX_ASSERT_LOCKED(mtx) do {					\
	if ((mtx)->mtx_owner != curcpu())				\
		panic("mutex %p not held in %s", (mtx), __func__);	\
} while (0)

#define MUTEX_ASSERT_UNLOCKED(mtx) do {					\
	if ((mtx)->mtx_owner == curcpu())				\
		panic("mutex %p held in %s", (mtx), __func__);		\
} while (0)

#else

#define	MUTEX_ASSERT_LOCKED(mtx)	do { /* nothing */ } while (0)
#define	MUTEX_ASSERT_UNLOCKED(mtx)	do { /* nothing */ } while (0)

#endif

#define MUTEX_OLDIPL(mtx)	(mtx)->mtx_oldipl

#endif	/* _M88K_MUTEX_H_ */


code:
/*	$OpenBSD: param.h,v 1.19 2013/04/01 12:52:24 miod Exp $ */

/*
 * Copyright (c) 1999 Steve Murphree, Jr.
 * Copyright (c) 1988 University of Utah.
 * Copyright (c) 1982, 1986, 1990 The Regents of the University of California.
 * All rights reserved.
 *
 * This code is derived from software contributed to Berkeley by
 * the Systems Programming Group of the University of Utah Computer
 * Science Department.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of the University nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */

#ifndef	_M88K_PARAM_H_
#define	_M88K_PARAM_H_

#ifdef _KERNEL
#ifndef _LOCORE
#include <machine/cpu.h>
#endif	/* _LOCORE */
#endif

#define	_MACHINE_ARCH  m88k
#define	MACHINE_ARCH   "m88k"
#define	MID_MACHINE    MID_M88K

#define	PAGE_SHIFT	12
#define	PAGE_SIZE	(1 << PAGE_SHIFT)
#define	PAGE_MASK	(PAGE_SIZE - 1)

#define	NPTEPG		(PAGE_SIZE / (sizeof(pt_entry_t)))

#ifdef _KERNEL

#define	NBPG		PAGE_SIZE
#define	PGSHIFT		PAGE_SHIFT
#define	PGOFSET		PAGE_MASK

#define	UPAGES		2			/* pages of u-area */
#define	USPACE		(UPAGES * PAGE_SIZE)	/* total size of u-area */
#define	USPACE_ALIGN	0			/* u-area alignment 0-none */

#define	NMBCLUSTERS	4096		/* map size, max cluster allocation */

#ifndef MSGBUFSIZE
#define	MSGBUFSIZE	PAGE_SIZE
#endif

/*
 * Mmaximum size of the kernel malloc arena in PAGE_SIZE-sized
 * logical pages.
 */
#define	NKMEMPAGES_MAX_DEFAULT	((64 * 1024 * 1024) >> PAGE_SHIFT)

/*
 * Get interrupt glue.
 */
#include <machine/intr.h>

#define	DELAY(x)	delay(x)

#if !defined(_LOCORE)
extern void delay(int);
extern int cputyp;
#endif

/*
 * Values for the cputyp variable.
 */
#define CPU_88100	0x00
#define CPU_88110	0x01

#ifdef M88100
#ifdef M88110
#define	CPU_IS88100	(cputyp == CPU_88100)
#define	CPU_IS88110	(cputyp != CPU_88100)
#else
#define	CPU_IS88100	1
#define	CPU_IS88110	0
#endif
#else
#define	CPU_IS88100	0
#define	CPU_IS88110	1
#endif

#endif	/* _KERNEL */

#endif /* _M88K_PARAM_H_ */


code:
/*	$OpenBSD: pcb.h,v 1.7 2015/05/05 02:13:46 guenther Exp $ */
/*
 * Copyright (c) 1996 Nivas Madhur
 * Mach Operating System
 * Copyright (c) 1993-1992 Carnegie Mellon University
 * All Rights Reserved.
 *
 * Permission to use, copy, modify and distribute this software and its
 * documentation is hereby granted, provided that both the copyright
 * notice and this permission notice appear in all copies of the
 * software, derivative works or modified versions, and any portions
 * thereof, and that both notices appear in supporting documentation.
 *
 * CARNEGIE MELLON AND OMRON ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS IS"
 * CONDITION.  CARNEGIE MELLON AND OMRON DISCLAIM ANY LIABILITY OF ANY KIND
 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
 *
 * Carnegie Mellon requests users of this software to return to
 *
 *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
 *  School of Computer Science
 *  Carnegie Mellon University
 *  Pittsburgh PA 15213-3890
 *
 * any improvements or extensions that they make and grant Carnegie Mellon
 * the rights to redistribute these changes.
 */
/*
 * Motorola 88100 pcb definitions
 *
 */
/*
 */
#ifndef _M88K_PCB_H_
#define _M88K_PCB_H_

#include <machine/frame.h>

/*
 * Our PCB is the regular PCB+Save area for kernel frame.
 * Upon entering kernel mode from user land, save the user context
 * in the saved_state area - this is passed as the exception frame.
 * On a context switch, only registers that need to be saved by the
 * C calling convention and few other regs (pc, psr etc) are saved
 * in the kernel_state part of the PCB. Typically, trap frames are
 * saved on the stack (by low level handlers or by hardware) but,
 * we just decided to do it in the PCB.
 */

struct m88100_pcb {
	unsigned long pcb_pc;	/* address to return */
	unsigned long :32;
	unsigned long pcb_r14;
	unsigned long pcb_r15;
	unsigned long pcb_r16;
	unsigned long pcb_r17;
	unsigned long pcb_r18;
	unsigned long pcb_r19;
	unsigned long pcb_r20;
	unsigned long pcb_r21;
	unsigned long pcb_r22;
	unsigned long pcb_r23;
	unsigned long pcb_r24;
	unsigned long pcb_r25;
	unsigned long pcb_r26;
	unsigned long pcb_r27;
	unsigned long pcb_r28;
	unsigned long pcb_r29;
	unsigned long pcb_r30;
	unsigned long pcb_sp; 	/* kernel stack pointer */
	/* floating-point state */
	unsigned long pcb_fcr62;
	unsigned long pcb_fcr63;
};

struct pcb
{
	struct m88100_pcb	kernel_state;
	struct trapframe	user_state;
	int			pcb_onfault;
};

/*
 *	Location of saved user registers for the proc.
 */
#define	USER_REGS(p) \
	(((struct reg *)(&((p)->p_addr->u_pcb.user_state))))

#endif /* _M88K_PCB_H_ */


code:
/*	$OpenBSD: pmap.h,v 1.26 2015/07/25 20:45:05 miod Exp $	*/
/*
 * Mach Operating System
 * Copyright (c) 1991 Carnegie Mellon University
 * Copyright (c) 1991 OMRON Corporation
 * All Rights Reserved.
 *
 * Permission to use, copy, modify and distribute this software and its
 * documentation is hereby granted, provided that both the copyright
 * notice and this permission notice appear in all copies of the
 * software, derivative works or modified versions, and any portions
 * thereof, and that both notices appear in supporting documentation.
 *
 */
#ifndef _M88K_PMAP_H_
#define _M88K_PMAP_H_

#ifdef	_KERNEL

#include <machine/mmu.h>

/*
 * PMAP structure
 */

struct pmap {
	sdt_entry_t		*pm_stab;	/* virtual pointer to sdt */
	apr_t			 pm_apr;
	int			 pm_count;	/* reference count */
	struct pmap_statistics	pm_stats;	/* pmap statistics */
};

/* 	The PV (Physical to virtual) List.
 *
 * For each vm_page_t, pmap keeps a list of all currently valid virtual
 * mappings of that page. An entry is a pv_entry_t; the list is the
 * pv_head_table. This is used by things like pmap_remove, when we must
 * find and remove all mappings for a particular physical page.
 */
/* XXX - struct pv_entry moved to vmparam.h because of include ordering issues */

typedef struct pmap *pmap_t;
typedef struct pv_entry *pv_entry_t;

extern	pmap_t		kernel_pmap;
extern	struct pmap	kernel_pmap_store;
extern	caddr_t		vmmap;
extern	apr_t		kernel_apr, userland_apr;

#define	pmap_kernel()			(&kernel_pmap_store)
#define pmap_resident_count(pmap)	((pmap)->pm_stats.resident_count)
#define	pmap_wired_count(pmap)		((pmap)->pm_stats.wired_count)

#define pmap_copy(dp,sp,d,l,s)		do { /* nothing */ } while (0)
#define pmap_update(pmap)		do { /* nothing */ } while (0)

#define	pmap_clear_modify(pg)		pmap_unsetbit(pg, PG_M)
#define	pmap_clear_reference(pg)	pmap_unsetbit(pg, PG_U)

void	pmap_bootstrap(paddr_t, paddr_t);
void	pmap_bootstrap_cpu(cpuid_t);
void	pmap_cache_ctrl(vaddr_t, vaddr_t, u_int);
void	pmap_page_uncache(paddr_t);
int	pmap_set_modify(pmap_t, vaddr_t);
void	pmap_unmap_firmware(void);
boolean_t pmap_unsetbit(struct vm_page *, int);

#define pmap_unuse_final(p)		/* nothing */
#define	pmap_remove_holes(vm)		do { /* nothing */ } while (0)

int	pmap_translation_info(pmap_t, vaddr_t, paddr_t *, uint32_t *);
/*
 * pmap_translation_info() return values
 */
#define	PTI_INVALID	0
#define	PTI_PTE		1
#define	PTI_BATC	2

#define	pmap_map_direct(pg)		((vaddr_t)VM_PAGE_TO_PHYS(pg))
#define	pmap_unmap_direct(va)		PHYS_TO_VM_PAGE((paddr_t)va)
#define	__HAVE_PMAP_DIRECT
#define	PMAP_STEAL_MEMORY

#endif	/* _KERNEL */

#ifndef _LOCORE
struct pv_entry {
	struct pv_entry	*pv_next;	/* next pv_entry */
	struct pmap	*pv_pmap;	/* pmap where mapping lies */
	vaddr_t		pv_va;		/* virtual address for mapping */
};

struct vm_page_md {
	struct pv_entry pv_ent;
	int		pv_flags;
};

#define	VM_MDPAGE_INIT(pg)						\
do {									\
	(pg)->mdpage.pv_ent.pv_next = NULL;				\
	(pg)->mdpage.pv_ent.pv_pmap = NULL;				\
	(pg)->mdpage.pv_ent.pv_va = 0;					\
	(pg)->mdpage.pv_flags = 0;					\
} while (0)

#endif /* _LOCORE */

#endif /* _M88K_PMAP_H_ */


code:
/*	$OpenBSD: pmap_table.h,v 1.5 2013/11/16 18:45:20 miod Exp $	*/
/*
 * Mach Operating System
 * Copyright (c) 1992 Carnegie Mellon University
 * All Rights Reserved.
 *
 * Permission to use, copy, modify and distribute this software and its
 * documentation is hereby granted, provided that both the copyright
 * notice and this permission notice appear in all copies of the
 * software, derivative works or modified versions, and any portions
 * thereof, and that both notices appear in supporting documentation.
 *
 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
 * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
 *
 * Carnegie Mellon requests users of this software to return to
 *
 *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
 *  School of Computer Science
 *  Carnegie Mellon University
 *  Pittsburgh PA 15213-3890
 *
 * any improvements or extensions that they make and grant Carnegie Mellon
 * the rights to redistribute these changes.
 */

#ifndef _M88K_PMAP_TABLE_H_
#define _M88K_PMAP_TABLE_H_

/*
 * Built-in mappings list.
 * An entry is considered invalid if size = 0, and
 * end of list is indicated by size 0xffffffff
 */
struct pmap_table {
	paddr_t		start;
	psize_t		size;
	vm_prot_t	prot;
	unsigned int	cacheability;
	boolean_t	may_use_batc;
};

const struct pmap_table *pmap_table_build(void);

#endif	/* _M88K_PMAP_TABLE_H_ */


code:
/*	$OpenBSD: proc.h,v 1.7 2014/03/18 22:36:34 miod Exp $ */
/*
 * Copyright (c) 1992, 1993
 *	The Regents of the University of California.  All rights reserved.
 *
 * This software was developed by the Computer Systems Engineering group
 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
 * contributed to Berkeley.
 *
 * All advertising materials mentioning features or use of this software
 * must display the following acknowledgement:
 *	This product includes software developed by the University of
 *	California, Lawrence Berkeley Laboratory.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of the University nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 *	@(#)proc.h	8.1 (Berkeley) 6/11/93
 *
 * from: Header: proc.h,v 1.6 92/11/26 02:04:41 torek Exp  (LBL)
 */

#ifndef _M88K_PROC_H_
#define _M88K_PROC_H_

struct trapframe;

/*
 * Machine-dependent part of the proc structure for m88k.
 */
struct mdproc {
	struct trapframe *md_tf;	/* trap/syscall registers */
	volatile int md_astpending;	/* AST pending for this process */

        /*
         * Single stepping is done by moving two breakpoints in the
         * process' code:
         * - one breakpoint for regular flow (i.e. the immediately following
         *   instruction)
         * - one breakpoint for potential branches.
         * Using two breakpoints allows us to not worry about the delay slots.
         */
	vaddr_t	md_bp0va;
	u_int	md_bp0save;
	vaddr_t	md_bp1va;
	u_int	md_bp1save;
};

#define __HAVE_MD_TCB

#endif /* _M88K_PROC_H_ */


code:
#ifndef _M88K_PROFILE_H_
#define _M88K_PROFILE_H_
/*	$OpenBSD: profile.h,v 1.7 2013/02/14 05:56:02 miod Exp $ */
/*
 * Copyright (c) 2004, Miodrag Vallat.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

#define	_MCOUNT_DECL void _mcount

/*
 * On OpenBSD, calls to the function profiler save r2-r9 on stack. The
 * monitor point is found in r2. The function's return address is taken
 * from the stack frame pointed to by r30, and needs to be restored as
 * r1 hasn't have had a chance to be saved yet.
 */

#ifdef __PIC__
#define	MCOUNT_SYMBOL	"_mcount#plt"
#else
#define	MCOUNT_SYMBOL	"_mcount"
#endif

#define MCOUNT								\
__asm__ (".text;"							\
	 ".align 3;"							\
	 ".globl __mcount;"						\
	 ".type  __mcount,@function;"					\
	 "__mcount:"							\
	 "	subu	%r31, %r31, 16;"				\
	 "	st	%r1,  %r31, 4;"					\
	 "	bsr.n	" MCOUNT_SYMBOL ";"				\
	 "	 ld	%r3,  %r30, 4;"	/* function return address */	\
	 "	ld	%r2,  %r31, 4;"					\
	 "	addu	%r31, %r31, 16;"				\
	 "	jmp.n	%r2;"						\
	 "	 ld	%r1,  %r30, 4;"	/* restore r1 */		\
	 ".size	__mcount, .-__mcount");

#ifdef _KERNEL
#define	MCOUNT_ENTER	do { s = get_psr(); set_psr(s | PSR_IND); } while (0)
#define	MCOUNT_EXIT	set_psr(s)
#endif /* _KERNEL */

#endif /* _M88K_PROFILE_H_ */


code:
/*	$OpenBSD: psl.h,v 1.8 2013/05/17 22:28:21 miod Exp $ */
/*
 * Copyright (c) 1996 Nivas Madhur
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *      This product includes software developed by Nivas Madhur.
 * 4. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */
/*
 * Mach Operating System
 * Copyright (c) 1991 Carnegie Mellon University
 * Copyright (c) 1991 OMRON Corporation
 * All Rights Reserved.
 *
 * Permission to use, copy, modify and distribute this software and its
 * documentation is hereby granted, provided that both the copyright
 * notice and this permission notice appear in all copies of the
 * software, derivative works or modified versions, and any portions
 * thereof, and that both notices appear in supporting documentation.
 *
 */

#ifndef _M88K_PSL_H_
#define _M88K_PSL_H_

/*
 * 881x0 control registers
 */

/*
 * processor identification register (PID)
 */
#define PID_ARN		0x0000ff00	/* architectural revision number */
#define	ARN_SHIFT		8
#define	ARN_88100		0x00
#define	ARN_88110		0x01
#define PID_VN		0x000000fe	/* version number */
#define	VN_SHIFT		1
#define PID_MC		0x00000001	/* 88100 master/checker mode */

/*
 * processor status register
 */

#define PSR_MODE	0x80000000	/* supervisor/user mode */
#define PSR_BO		0x40000000	/* byte-ordering 0:big 1:little */
#define PSR_SER		0x20000000	/* serial mode */
#define PSR_C		0x10000000	/* carry */
#define PSR_SGN		0x04000000	/* 88110 Signed Immediate mode */
#define PSR_SRM		0x02000000	/* 88110 Serialize Memory */
#define PSR_TRACE	0x00800000	/* 88110 hardware trace */
#define PSR_SFD		0x000003e0	/* SFU disable */
#define PSR_SFD2	0x00000010	/* 88110 SFU2 (Graphics) disable */
#define PSR_SFD1	0x00000008	/* SFU1 (FPU) disable */
#define PSR_MXM		0x00000004	/* misaligned access enable */
#define PSR_IND		0x00000002	/* interrupt disable */
#define PSR_SFRZ	0x00000001	/* shadow freeze */

/* bits userland is not allowed to change */
#define	PSR_USERSTATIC	(PSR_MODE | PSR_BO | PSR_SER | PSR_SGN | PSR_SRM | \
			 PSR_SFD | PSR_MXM | PSR_IND | PSR_SFRZ)

#define FIP_V		0x00000002	/* valid */
#define FIP_E		0x00000001	/* exception */
#define FIP_ADDR	0xfffffffc	/* address mask */
#define NIP_V		0x00000002	/* valid */
#define NIP_E		0x00000001	/* exception */
#define NIP_ADDR	0xfffffffc	/* address mask */
#define XIP_V		0x00000002	/* valid */
#define XIP_E		0x00000001	/* exception */
#define XIP_ADDR	0xfffffffc	/* address mask */

#endif /* _M88K_PSL_H_ */


code:
/*	$OpenBSD: ptrace.h,v 1.4 2011/03/23 16:54:35 pirofti Exp $ */
/*
 * Copyright (c) 1999, Steve Murphree, Jr.
 * Copyright (c) 1992, 1993
 *	The Regents of the University of California.  All rights reserved.
 *
 * This software was developed by the Computer Systems Engineering group
 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
 * contributed to Berkeley.
 *
 * All advertising materials mentioning features or use of this software
 * must display the following acknowledgement:
 *	This product includes software developed by the University of
 *	California, Lawrence Berkeley Laboratory.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of the University nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 *	@(#)ptrace.h	8.1 (Berkeley) 6/11/93
 *
 * from: Header: ptrace.h,v 1.6 92/11/26 02:04:43 torek Exp  (LBL)
 */

/*
 * m88k-dependent ptrace definitions.
 */

#ifndef _M88K_PTRACE_H_
#define _M88K_PTRACE_H_

#define	PT_STEP		(PT_FIRSTMACH + 0)
#define	PT_GETREGS	(PT_FIRSTMACH + 1)
#define	PT_SETREGS	(PT_FIRSTMACH + 2)

#endif /* _M88K_PTRACE_H_ */


code:
/*	$OpenBSD: reg.h,v 1.3 2013/07/17 19:19:30 miod Exp $ */
/*
 * Copyright (c) 1999 Steve Murphree, Jr.
 * Copyright (c) 1996 Nivas Madhur
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *      This product includes software developed by Nivas Madhur.
 * 4. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */

#ifndef _M88K_REG_H_
#define _M88K_REG_H_

struct reg {
	unsigned long	r[32];
	unsigned long	epsr;
	unsigned long	fpsr;
	unsigned long	fpcr;
	unsigned long	sxip;
#define exip sxip	/* mc88110 */
	unsigned long	snip;
#define enip snip	/* mc88110 */
	unsigned long	sfip;
	unsigned long	ssbr;
#define duap ssbr	/* mc88110 */
	unsigned long	dmt0;
#define dsr dmt0	/* mc88110 */
	unsigned long	dmd0;
#define dlar dmd0	/* mc88110 */
	unsigned long	dma0;
#define dpar dma0	/* mc88110 */
	unsigned long	dmt1;
#define isr dmt1	/* mc88110 */
	unsigned long	dmd1;
#define ilar dmd1	/* mc88110 */
	unsigned long	dma1;
#define ipar dma1	/* mc88110 */
	unsigned long	dmt2;
#define isap dmt2	/* mc88110 */
	unsigned long	dmd2;
#define dsap dmd2	/* mc88110 */
	unsigned long	dma2;
#define iuap dma2	/* mc88110 */
	unsigned long	fpecr;
	unsigned long	fphs1;
	unsigned long	fpls1;
	unsigned long	fphs2;
	unsigned long	fpls2;
	unsigned long	fppt;
	unsigned long	fprh;
	unsigned long	fprl;
	unsigned long	fpit;
};

#endif /* _M88K_REG_H_ */


code:
/*	$OpenBSD: reloc.h,v 1.1 2013/01/05 11:20:56 miod Exp $	*/

/* public domain */

#ifndef	_M88K_RELOC_H_
#define	_M88K_RELOC_H_

#define	RELOC_NONE		0
#define	RELOC_COPY		1
#define	RELOC_GOTP_ENT		2
#define	RELOC_8			4
#define	RELOC_8S		5
#define	RELOC_16S		7
#define	RELOC_DISP16		8
#define	RELOC_DISP26		10
#define	RELOC_PLT_DISP26	14
#define	RELOC_BBASED_32		16
#define	RELOC_BBASED_32UA	17
#define	RELOC_BBASED_16H	18
#define	RELOC_BBASED_16L	19
#define	RELOC_ABDIFF_32		24
#define	RELOC_ABDIFF_32UA	25
#define	RELOC_ABDIFF_16H	26
#define	RELOC_ABDIFF_16L	27
#define	RELOC_ABDIFF_16		28
#define	RELOC_32		32
#define	RELOC_32UA		33
#define	RELOC_16H		34
#define	RELOC_16L		35
#define	RELOC_16		36
#define	RELOC_GOT_32		40
#define	RELOC_GOT_32UA		41
#define	RELOC_GOT_16H		42
#define	RELOC_GOT_16L		43
#define	RELOC_GOT_16		44
#define	RELOC_GOTP_32		48
#define	RELOC_GOTP_32UA		49
#define	RELOC_GOTP_16H		50
#define	RELOC_GOTP_16L		51
#define	RELOC_GOTP_16		52
#define	RELOC_PLT_32		56
#define	RELOC_PLT_32UA		57
#define	RELOC_PLT_16H		58
#define	RELOC_PLT_16L		59
#define	RELOC_PLT_16		60
#define	RELOC_ABREL_32		64
#define	RELOC_ABREL_32UA	65
#define	RELOC_ABREL_16H		66
#define	RELOC_ABREL_16L		67
#define	RELOC_ABREL_16		68
#define	RELOC_GOT_ABREL_32	72
#define	RELOC_GOT_ABREL_32UA	73
#define	RELOC_GOT_ABREL_16H	74
#define	RELOC_GOT_ABREL_16L	75
#define	RELOC_GOT_ABREL_16	76
#define	RELOC_GOTP_ABREL_32	80
#define	RELOC_GOTP_ABREL_32UA	81
#define	RELOC_GOTP_ABREL_16H	82
#define	RELOC_GOTP_ABREL_16L	83
#define	RELOC_GOTP_ABREL_16	84
#define	RELOC_PLT_ABREL_32	88
#define	RELOC_PLT_ABREL_32UA	89
#define	RELOC_PLT_ABREL_16H	90
#define	RELOC_PLT_ABREL_16L	91
#define	RELOC_PLT_ABREL_16	92
#define	RELOC_SREL_32		96
#define	RELOC_SREL_32UA		97
#define	RELOC_SREL_16H		98
#define	RELOC_SREL_16L		99

#endif	/* _M88K_RELOC_H_ */


code:
/*	$OpenBSD: setjmp.h,v 1.2 2011/03/23 16:54:35 pirofti Exp $	*/

/*
 * machine/setjmp.h: machine dependent setjmp-related information.
 */
#ifndef _M88K_SETJMP_H_
#define _M88K_SETJMP_H_
#define	_JBLEN	21		/* size, in longs, of a jmp_buf */
#endif /* _M88K_SETJMP_H_ */


code:
/*	$OpenBSD: signal.h,v 1.7 2012/12/02 07:03:31 guenther Exp $ */
/*
 * Copyright (c) 1996 Nivas Madhur
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *      This product includes software developed by Nivas Madhur.
 * 4. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */

#ifndef _M88K_SIGNAL_H_
#define _M88K_SIGNAL_H_

#include <sys/cdefs.h>

typedef int sig_atomic_t;

#if __BSD_VISIBLE || __XPG_VISIBLE >= 420

/*
 * Information pushed on stack when a signal is delivered.
 * This is used by the kernel to restore state following
 * execution of the signal handler. It is also made available
 * to the handler to allow it to restore state properly if
 * a non-standard exit is performed.
 */
struct  sigcontext {
        int     __sc_unused;
        int     sc_mask;                /* signal mask to restore */
	/* begin machine dependent portion */
	unsigned int sc_regs[32 + 25];
};
#endif /* __BSD_VISIBLE || __XPG_VISIBLE >= 420 */
#endif /* _M88K_SIGNAL_H_ */


code:
/*	$OpenBSD: spinlock.h,v 1.2 2013/06/01 20:47:40 tedu Exp $	*/

#ifndef _M88K_SPINLOCK_H_
#define _M88K_SPINLOCK_H_

#define _ATOMIC_LOCK_UNLOCKED	(0)
#define _ATOMIC_LOCK_LOCKED	(1)
typedef int _atomic_lock_t;

#ifndef _KERNEL
int _atomic_lock(volatile _atomic_lock_t *);
#endif

#endif


code:
/*	$OpenBSD: stdarg.h,v 1.3 2011/03/23 16:54:35 pirofti Exp $	*/

#ifndef _M88K_STDARG_H_
#define _M88K_STDARG_H_

#include <machine/_types.h>

#ifndef	_STDARG_H
#define	_STDARG_H
#endif

#include <machine/va-m88k.h>

typedef	__va_list	va_list;

#endif	/* _M88K_STDARG_H_ */


code:
/*	$OpenBSD: tcb.h,v 1.3 2014/03/29 18:09:29 guenther Exp $	*/

/*
 * Copyright (c) 2011 Philip Guenther <guenther@openbsd.org>
 *
 * Permission to use, copy, modify, and distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#ifndef _MACHINE_TCB_H_
#define _MACHINE_TCB_H_

/*
 * In userspace, register %r27 contains the address of the thread's TCB,
 * and register %r26 contains the address of the thread's errno.
 * It is the responsibility of the kernel to set %r27 to the proper value
 * when creating the thread, while initialization of %r26 is done in
 * userland within libpthread on a needed basis.
 */

#ifdef _KERNEL

#include <machine/reg.h>

#define TCB_GET(p)		\
	((void *)(p)->p_md.md_tf->tf_r[27])
#define TCB_SET(p, addr)	\
	((p)->p_md.md_tf->tf_r[27] = (register_t)(addr))

#else /* _KERNEL */

/*
 * It is unknown whether the m88k ELF ABI mentions TLS. On m88k, since only
 * unsigned offsets in (register + immediate offset) addressing is supported
 * on all processors, it makes sense to use a small TCB, with static TLS data
 * after it.
 */
#define TLS_VARIANT	1

#if defined(__GNUC__) && __GNUC__ > 4

struct thread_control_block;
__register__ struct thread_control_block *__tcb __asm__ ("%r27");
#define	TCB_GET()	(__tcb)
#define	TCB_SET(tcb)	((__tcb) = (tcb))
#define	TCB_GET_MEMBER(member)	((void *)(__tcb->member))

#else /* __GNUC__ > 4 */

#include <stddef.h>		/* for offsetof */

/* Get a pointer to the TCB itself */
static inline void *
__m88k_get_tcb(void)
{
	void *val;
	__asm__ ("or %0,%%r27,%%r0" : "=r" (val));
	return val;
}

/* Get the value of a specific member in the TCB */
static inline void *
__m88k_read_tcb(size_t offset)
{
	void	*val;
	/* XXX the `offset' constraint ought to be "I" but this causes a warning */
	__asm__ ("ld %0,%%r27,%1" : "=r" (val) : "r" (offset));
	return val;
}

#define TCB_GET()	__m88k_get_tcb()
#define TCB_SET(tcb)	__asm volatile("or %%r27,%0,%r0" : : "r" (tcb))

#define TCB_GET_MEMBER(member)	\
	__m88k_read_tcb(offsetof(struct thread_control_block, member))

#endif /* __GNUC__ > 4 */

#endif /* _KERNEL */

#endif /* _MACHINE_TCB_H_ */


code:
/*	$OpenBSD: trap.h,v 1.11 2013/09/05 20:40:32 miod Exp $ */
/*
 * Mach Operating System
 * Copyright (c) 1992 Carnegie Mellon University
 * All Rights Reserved.
 *
 * Permission to use, copy, modify and distribute this software and its
 * documentation is hereby granted, provided that both the copyright
 * notice and this permission notice appear in all copies of the
 * software, derivative works or modified versions, and any portions
 * thereof, and that both notices appear in supporting documentation.
 *
 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
 * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
 *
 * Carnegie Mellon requests users of this software to return to
 *
 *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
 *  School of Computer Science
 *  Carnegie Mellon University
 *  Pittsburgh PA 15213-3890
 *
 * any improvements or extensions that they make and grant Carnegie Mellon
 * the rights to redistribute these changes.
 */
#ifndef _M88K_TRAP_H_
#define _M88K_TRAP_H_

/*
 * Trap type values. These have no relation to the trap vector offsets in
 * the VBR page.
 */
#define	T_PRIVINFLT	0	/* privileged instruction fault */
#define	T_INSTFLT	1	/* instruction access exception */
#define	T_DATAFLT	2	/* data access exception */
#define	T_MISALGNFLT	3	/* misaligned access exception */
#define	T_ILLFLT	4	/* unimplemented opcode exception */
#define	T_BNDFLT	5	/* bounds check violation exception */
#define	T_ZERODIV	6	/* illegal divide exception */
#define	T_OVFFLT	7	/* integer overflow exception */
#define	T_FPEPFLT	8	/* floating point precise exception */
#define	T_FPEIFLT	9	/* floating point imprecise exception (88100) */
#define	T_KDB_ENTRY	10	/* force entry to kernel debugger */
#define	T_KDB_BREAK	11	/* break point hit */
#define	T_KDB_TRACE	12	/* trace */
#define	T_UNKNOWNFLT	13	/* unknown exception */
#define	T_SIGSYS	14	/* generate SIGSYS */
#define	T_STEPBPT	15	/* special breakpoint for single step */
#define	T_USERBPT	16	/* user set breakpoint (for debugger) */
#define	T_110_DRM	17	/* 88110 data read miss (sw table walk) */
#define	T_110_DWM	18	/* 88110 data write miss (sw table walk) */
#define	T_110_IAM	19	/* 88110 inst ATC miss (sw table walk) */

#define	T_USER		20	/* added to trap code if user mode fault */

#ifndef _LOCORE

void	ast(struct trapframe *);
void	cache_flush(struct trapframe *);
void	interrupt(struct trapframe *);
int	nmi(struct trapframe *);
void	nmi_wrapup(struct trapframe *);

void	m88100_syscall(register_t, struct trapframe *);
void	m88100_trap(u_int, struct trapframe *);
void	m88110_syscall(register_t, struct trapframe *);
void	m88110_trap(u_int, struct trapframe *);

void	m88100_fpu_imprecise_exception(struct trapframe *);
void	m88100_fpu_precise_exception(struct trapframe *);
void	m88110_fpu_exception(struct trapframe *);

#endif /* _LOCORE */

#endif /* _M88K_TRAP_H_ */


code:
/*	$OpenBSD: varargs.h,v 1.2 2006/01/06 18:53:05 millert Exp $	*/

#ifndef _M88K_VARARGS_H_
#define _M88K_VARARGS_H_

#define	_VARARGS_H

#include <machine/_types.h>
#include <machine/va-m88k.h>

typedef	__va_list	va_list;

#endif	/* _M88K_VARARGS_H_ */


code:
/*	$OpenBSD: vmparam.h,v 1.19 2015/02/10 10:02:55 tedu Exp $ */
/*
 * Mach Operating System
 * Copyright (c) 1992 Carnegie Mellon University
 * All Rights Reserved.
 *
 * Permission to use, copy, modify and distribute this software and its
 * documentation is hereby granted, provided that both the copyright
 * notice and this permission notice appear in all copies of the
 * software, derivative works or modified versions, and any portions
 * thereof, and that both notices appear in supporting documentation.
 *
 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
 * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
 *
 * Carnegie Mellon requests users of this software to return to
 *
 *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
 *  School of Computer Science
 *  Carnegie Mellon University
 *  Pittsburgh PA 15213-3890
 *
 * any improvements or extensions that they make and grant Carnegie Mellon
 * the rights to redistribute these changes.
 */

/*
 *	machine dependent virtual memory parameters.
 */

#ifndef	_MACHINE_VM_PARAM_
#define _MACHINE_VM_PARAM_

/*
 * USRTEXT is the start of the user text/data space, while USRSTACK
 * is the top (end) of the user stack.
 */
#define	USRTEXT		0x1000			/* Start of user text */
#define	USRSTACK	VM_MAXUSER_ADDRESS	/* Start of user stack */

/*
 * Virtual memory related constants, all in bytes
 */
#ifndef MAXTSIZ
#define	MAXTSIZ		(32*1024*1024)		/* max text size */
#endif
#ifndef DFLDSIZ
#define	DFLDSIZ		(64*1024*1024)		/* initial data size limit */
#endif
#ifndef MAXDSIZ
#define	MAXDSIZ		(256*1024*1024)		/* max data size */
#endif
#ifndef BRKSIZ
#define	BRKSIZ		MAXDSIZ			/* heap gap size */
#endif
#ifndef	DFLSSIZ
#define	DFLSSIZ		(2*1024*1024)		/* initial stack size limit */
#endif
#ifndef	MAXSSIZ
#define	MAXSSIZ		(32*1024*1024)		/* max stack size */
#endif

#define STACKGAP_RANDOM	256*1024

/*
 * Size of shared memory map
 */
#ifndef SHMMAXPGS
#define SHMMAXPGS	1024
#endif

#define	VM_MIN_ADDRESS		((vaddr_t)PAGE_SIZE)
#define	VM_MAX_ADDRESS		((vaddr_t)0xfffff000)
#define VM_MAXUSER_ADDRESS	VM_MAX_ADDRESS

/* virtual sizes (bytes) for various kernel submaps */
#define VM_PHYS_SIZE		(1 * NPTEPG * PAGE_SIZE)

/*
 * Constants which control the way the VM system deals with memory segments.
 * All m88k systems so far only have one physical memory segment.
 */
#define	VM_PHYSSEG_MAX		1
#define	VM_PHYSSEG_STRAT	VM_PSTRAT_RANDOM
#define	VM_PHYSSEG_NOADD

#endif /* _MACHINE_VM_PARAM_ */


code:
/*	$OpenBSD: atomic.S,v 1.6 2014/07/15 16:26:28 miod Exp $	*/

/*
 * Copyright (c) 2009 Miodrag Vallat.
 *
 * Permission to use, copy, modify, and distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include <machine/asm.h>

#ifdef M88110
#define	CACHE_LINE	32
#else
#define	CACHE_LINE	16
#endif
	.data

/*
 * A __cpu_simple_lock_t used to provide the inter-processor interlock,
 * alone on its cache line.
 */
	.balign	CACHE_LINE
ASLOCAL(__atomic_interlock)
	.word	0
	.balign	CACHE_LINE

	.text

/*
 * Register usage in this file:
 *
 * r2 data address
 * r3 bits to set or clear
 * r4 argument / scratch
 * r5 return address
 * r6 interlock address
 * r7 psr upon entry
 * r8 active psr
 * r9 scratch
 */

ENTRY(atomic_setbits_int)
	or	%r5, %r1, %r0		/* save return address */
	bsr	_C_LABEL(__atomic_lock)

	ld	%r4, %r2, %r0
	or	%r4, %r4, %r3
	st	%r4, %r2, %r0

	br	_C_LABEL(__atomic_unlock)

ENTRY(atomic_clearbits_int)
	or	%r5, %r1, %r0		/* save return address */
	bsr	_C_LABEL(__atomic_lock)

	ld	%r4, %r2, %r0
	or	%r4, %r4, %r3
	xor	%r4, %r4, %r3		/* r4 &= ~r3 */
	st	%r4, %r2, %r0

	br	_C_LABEL(__atomic_unlock)

ENTRY(atomic_add_int_nv_mp)
	or	%r5, %r1, %r0		/* save return address */
	bsr	_C_LABEL(__atomic_lock)

	or	%r9, %r2, %r0
	ld	%r2, %r9, %r0
	addu	%r2, %r2, %r3
	st	%r2, %r9, %r0

	br	_C_LABEL(__atomic_unlock)

ENTRY(atomic_sub_int_nv_mp)
	or	%r5, %r1, %r0		/* save return address */
	bsr	_C_LABEL(__atomic_lock)

	or	%r9, %r2, %r0
	ld	%r2, %r9, %r0
	subu	%r2, %r2, %r3
	st	%r2, %r9, %r0

	br	_C_LABEL(__atomic_unlock)

ENTRY(atomic_cas_uint_mp)
	or	%r5, %r1, %r0		/* save return address */
	bsr	_C_LABEL(__atomic_lock)

	ld	%r9, %r2, %r0
	cmp	%r3, %r3, %r9
	bb0	eq,  %r3, 1f
	st	%r4, %r2, %r0
1:
	or	%r2, %r9, %r0

	br	_C_LABEL(__atomic_unlock)

ENTRY(atomic_swap_uint_mp)
	or	%r5, %r1, %r0		/* save return address */
	bsr	_C_LABEL(__atomic_lock)

	ld	%r4, %r2, %r0
	st	%r3, %r2, %r0
	or	%r2, %r4, %r0

	br	_C_LABEL(__atomic_unlock)

GLOBAL(__atomic_lock)

/*
 * If running a kernel with support for both 88100 and 88110 compiled-in
 * on a 88100 machine, the 88100 code (shorter) will be copied over in
 * vector_init().
 */

#ifdef M88110
ASLOCAL(__atomic_lock_88110)
	/*
	 * This is the 88110 version: disable shadowing and interrupts,
	 * then grab the interlock.
	 */

	or.u	%r6, %r0, %hi16(_ASM_LABEL(__atomic_interlock))
	or	%r6, %r6, %lo16(_ASM_LABEL(__atomic_interlock))

	ldcr	%r7, PSR
	set	%r8, %r7, 1<PSR_INTERRUPT_DISABLE_BIT>
	set	%r8, %r8, 1<PSR_SHADOW_FREEZE_BIT>
	stcr	%r8, PSR
	FLUSH_PIPELINE
1:
	or	%r9, %r0, 1	/* __SIMPLELOCK_LOCKED */
	xmem	%r9, %r6, %r0
	bcnd	eq0, %r9, 3f
2:
	ld	%r9, %r6, %r0
	bcnd	eq0, %r9, 1b
	br	2b
3:
	jmp	%r1
#endif

#ifdef M88100
GLOBAL(__atomic_lock_88100)
	/*
	 * This is the 88100 version: disable interrupts, then grab
	 * the interlock.
	 */

	or.u	%r6, %r0, %hi16(_ASM_LABEL(__atomic_interlock))
	or	%r6, %r6, %lo16(_ASM_LABEL(__atomic_interlock))

	ldcr	%r7, PSR
	set	%r8, %r7, 1<PSR_INTERRUPT_DISABLE_BIT>
	stcr	%r8, PSR
	FLUSH_PIPELINE

1:
	or	%r9, %r0, 1	/* __SIMPLELOCK_LOCKED */
	xmem	%r9, %r6, %r0
	bcnd	eq0, %r9, 3f
2:
	ld	%r9, %r6, %r0
	bcnd	eq0, %r9, 1b
	br	2b
3:
	jmp	%r1
GLOBAL(__atomic_lock_88100_end)
#endif

GLOBAL(__atomic_unlock)

/*
 * If running a kernel with support for both 88100 and 88110 compiled-in
 * on a 88100 machine, the 88100 code (shorter) will be copied over in
 * vector_init().
 */

#ifdef M88110
ASLOCAL(__atomic_unlock_88110)
	/*
	 * This is the 88110 version: release the interlock, set up
	 * exception registers to return to our caller with initial
	 * psr restored.
	 */

	st	%r0, %r6, %r0	/* release interlock */

	stcr	%r5, EXIP	/* return address */
	stcr	%r7, EPSR	/* original PSR */

	/*
	 * No need to workaround errata #18 (see m88110_user_rte in
	 * eh_common.S), as we are not returning to user mode.
	 */
	RTE
#endif

#ifdef M88100
GLOBAL(__atomic_unlock_88100)
	/*
	 * This is the 88100 version: release the interlock,
	 * restore psr and return to the caller.
	 */

	st	%r0, %r6, %r0	/* release interlock */

	stcr	%r7, PSR
	FLUSH_PIPELINE

	jmp	%r5
GLOBAL(__atomic_unlock_88100_end)
#endif


code:
/*	$OpenBSD: db_disasm.c,v 1.9 2007/10/27 20:31:19 miod Exp $	*/
/*
 * Copyright (c) 2006, Miodrag Vallat
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */
/*
 * Mach Operating System
 * Copyright (c) 1993-1991 Carnegie Mellon University
 * Copyright (c) 1991 OMRON Corporation
 * All Rights Reserved.
 *
 * Permission to use, copy, modify and distribute this software and its
 * documentation is hereby granted, provided that both the copyright
 * notice and this permission notice appear in all copies of the
 * software, derivative works or modified versions, and any portions
 * thereof, and that both notices appear in supporting documentation.
 *
 * CARNEGIE MELLON AND OMRON ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS IS"
 * CONDITION.  CARNEGIE MELLON AND OMRON DISCLAIM ANY LIABILITY OF ANY KIND
 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
 *
 * Carnegie Mellon requests users of this software to return to
 *
 *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
 *  School of Computer Science
 *  Carnegie Mellon University
 *  Pittsburgh PA 15213-3890
 *
 * any improvements or extensions that they make and grant Carnegie the
 * rights to redistribute these changes.
 */

/*
 * m88k disassembler for use in ddb
 */

#include <sys/param.h>
#include <sys/systm.h>

#include <machine/db_machdep.h>

#include <ddb/db_sym.h>		/* DB_STGY_PROC, db_printsym() */
#include <ddb/db_access.h>	/* db_get_value() */
#include <ddb/db_output.h>	/* db_printf() */
#include <ddb/db_interface.h>

int	oimmed(int, u_int32_t, const char *, vaddr_t);
int	ctrlregs(int, u_int32_t, const char *, vaddr_t);
int	sindou(int, u_int32_t, const char *, vaddr_t);
int	jump(int, u_int32_t, const char *, vaddr_t);
int	instset(int, u_int32_t, const char *, vaddr_t);
int	obranch(int, u_int32_t, const char *, vaddr_t);
int	brcond(int, u_int32_t, const char *, vaddr_t);
int	otrap(int, u_int32_t, const char *, vaddr_t);
int	obit(int, u_int32_t, const char *, vaddr_t);
int	bitman(int, u_int32_t, const char *, vaddr_t);
int	immem(int, u_int32_t, const char *, vaddr_t);
int	nimmem(int, u_int32_t, const char *, vaddr_t);
int	lognim(int, u_int32_t, const char *, vaddr_t);
int	onimmed(int, u_int32_t, const char *, vaddr_t);
int	pinst(int, u_int32_t, const char *, vaddr_t);

void	printcmp(int, u_int);
void	symofset(u_int, u_int, vaddr_t);
const char *cregname(int, u_int, u_int);

/*
 * Common instruction modifiers
 */

static const char *instwidth[] = {
	".d", "  ", ".h", ".b", ".x"	/* see nimmem() for use of last value */
};
static const char *xinstwidth[4] = {
	".d", "  ", ".x", ".?"
};
static const char *cmpname[0x20] = {
	NULL,
	NULL,
	"eq",
	"ne",
	"gt",
	"le",
	"lt",
	"ge",
	"hi",
	"ls",
	"lo",
	"hs",
	"be",
	"nb",
	"he",
	"nh"
};
static const char *condname[0x20] = {
	NULL,
	"gt",	/* 00001 */
	"eq",	/* 00010 */
	"ge",	/* 00011 */
	NULL,
	NULL,
	NULL,
	NULL,
	NULL,
	NULL,
	NULL,
	NULL,
	"lt",	/* 01100 */
	"ne",	/* 01101 */
	"le"	/* 01110 */
};
static const char sodname[4] = "sdx?";

/*
 * Descriptive control register names
 */

static const char *m88100_ctrlreg[2][64] = {
	{	/* main unit */
		"PID",
		"PSR",
		"EPSR",
		"SSBR",
		"SXIP",
		"SNIP",
		"SFIP",
		"VBR",
		"DMT0",
		"DMD0",
		"DMA0",
		"DMT1",
		"DMD1",
		"DMA1",
		"DMT2",
		"DMD2",
		"DMA2",
		"SR0",
		"SR1",
		"SR2",
		"SR3",
	},
	{	/* SFU1 = FPU */
		"FPECR",
		"FPHS1",
		"FPLS1",
		"FPHS2",
		"FPLS2",
		"FPPT",
		"FPRH",
		"FPRL",
		"FPIT",
		NULL, NULL,
		NULL, NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL, NULL,
		NULL,
		"FPSR",
		"FPCR"
	}
};

static const char *m88110_ctrlreg[2][64] = {
	{	/* main unit */
		"PID",
		"PSR",
		"EPSR",
		NULL,
		"EXIP",
		"ENIP",
		NULL,
		"VBR",
		NULL,
		NULL,
		NULL,
		NULL,
		NULL,
		NULL,
		"RES1",
		"RES2",
		"SRX",
		"SR0",
		"SR1",
		"SR2",
		"SR3",
		NULL,
		NULL,
		NULL,
		NULL,
		"ICMD",
		"ICTL",
		"ISAR",
		"ISAP",
		"IUAP",
		"IIR",
		"IBP",
		"IPPU",
		"IPPL",
		"ISR",
		"ILAR",
		"IPAR",
		NULL,
		NULL,
		NULL,
		"DCMD",
		"DCTL",
		"DSAR",
		"DSAP",
		"DUAP",
		"DIR",
		"DBP",
		"DPPU",
		"DPPL",
		"DSR",
		"DLAR",
		"DPAR",
	},
	{	/* SFU1 = FPU */
		"FPECR",
		NULL, NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL, NULL,
		NULL,
		"FPSR",
		"FPCR"
	}
};

/* print a comparison code */		/* XXX favors cmp vs fcmp or pcmp */
void
printcmp(int cpu, u_int code)
{
	const char *cmp;

	if (cpu == CPU_88100 && code > 11)
		cmp = NULL;
	else
		cmp = cmpname[code];
	if (cmp != NULL)
		db_printf("%s(%d)", cmp, code);
	else
		db_printf("%d", code);
}

const char *
cregname(int cpu, u_int sfu, u_int regno)
{
	static char regbuf[20];
	const char *regname;

	switch (sfu) {
	case 0:	/* main unit */
	case 1:	/* SFU1 = FPU */
		regname = cpu != CPU_88100 ?
		    m88110_ctrlreg[sfu][regno] : m88100_ctrlreg[sfu][regno];
		if (regname == NULL)
			snprintf(regbuf, sizeof regbuf,
			    sfu == 0 ? "cr%d" : "fcr%d", regno);
		else
			snprintf(regbuf, sizeof regbuf,
			    sfu == 0 ? "cr%d (%s)" : "fcr%d (%s)",
			    regno, regname);
		break;
	default:	/* can't happen */
		snprintf(regbuf, sizeof regbuf, "sfu%dcr%d", sfu, regno);
		break;
	}

	return (regbuf);
}

void
symofset(u_int disp, u_int bit, vaddr_t iadr)
{
	vaddr_t addr;

	if (disp & (1 << (bit - 1))) {
		/* negative value */
		addr = iadr + ((disp << 2) | (~0U << bit));
	} else {
		addr = iadr + (disp << 2);
	}
	db_printsym(addr, DB_STGY_PROC, db_printf);
}

/* Handles immediate integer arithmetic instructions */
int
oimmed(int cpu, u_int32_t inst, const char *opcode, vaddr_t iadr)
{
	int32_t Linst = inst & 0xffff;
	u_int32_t H6inst = inst >> 26;
	u_int32_t rs1 = (inst >> 16) & 0x1f;
	u_int32_t rd = (inst >> 21) & 0x1f;

	switch (H6inst) {
	case 0x11:	/* and.u */
	case 0x13:	/* mask.u */
	case 0x15:	/* xor.u */
	case 0x17:	/* or.u */
		db_printf("\t%s.u", opcode);
		break;
	default:
		db_printf("\t%s  ", opcode);
		break;
	}
	db_printf("\t\tr%d, r%d, 0x%04x", rd, rs1, Linst);

	return (1);
}

/* Handles instructions dealing with control registers */
int
ctrlregs(int cpu, u_int32_t inst, const char *opcode, vaddr_t iadr)
{
	u_int32_t dir = (inst >> 14) & 0x03;
	u_int32_t sfu = (inst >> 11) & 0x07;
	u_int32_t creg = (inst >> 5) & 0x3f;
	u_int32_t rd = (inst >> 21) & 0x1f;
	u_int32_t rs1 = (inst >> 16) & 0x1f;
	u_int32_t rs2 = (inst >> 0) & 0x1f;

	/* s1 and s2 must match on {,f}{st,x}cr instructions */
	if (rs1 != rs2 && (dir == 0x02 || dir == 0x03))
		return (0);

	db_printf("\t%s\t\t", opcode);

	switch (dir) {
	case 0x01:	/* ldcr, fldcr */
		db_printf("r%d, %s", rd, cregname(cpu, sfu, creg));
		break;
	case 0x02:	/* stcr, fstcr */
		db_printf("r%d, %s", rs1, cregname(cpu, sfu, creg));
		break;
	default:
	case 0x03:	/* xcr, fxcr */
		db_printf("r%d, r%d, %s",
		    rd, rs1, cregname(cpu, sfu, creg));
		break;
	}

	return (1);
}

/* Handles floating point instructions */
int
sindou(int cpu, u_int32_t inst, const char *opcode, vaddr_t iadr)
{
	u_int32_t rs2 = inst & 0x1f;
	u_int32_t td = (inst >> 5) & 0x03;
	u_int32_t t2 = (inst >> 7) & 0x03;
	u_int32_t t1 = (inst >> 9) & 0x03;
	u_int32_t rs1 = (inst >> 16) & 0x1f;
	u_int32_t rd = (inst >> 21) & 0x1f;
	u_int32_t checkbits = (inst >> 11) & 0x0f;
	u_int32_t rf = (inst >> 15) & 0x01;

	/* do not display a specific fcmpu.s encoding as non-existing fcmpu.d */
	if (checkbits == 0x07)
		td = 0;

	/* do not display dot modifiers for mov.x */
	if (checkbits == 0x08) {
		db_printf("\t%s", opcode);
	} else {
		db_printf("\t%s.%c", opcode, sodname[td]);
	}

	switch (checkbits) {
	default:
	case 0x00:	/* fmul */
	case 0x05:	/* fadd */
	case 0x06:	/* fsub */
	case 0x0e:	/* fdiv */
		db_printf("%c%c\t\t", sodname[t1], sodname[t2]);
		if (rf != 0)
			db_printf("x%d,x%d,x%d", rd, rs1, rs2);
		else
			db_printf("r%d,r%d,r%d", rd, rs1, rs2);
		break;
	case 0x01:	/* fcvt */
	case 0x0f:	/* fsqrt */
		db_printf("%c \t\t", sodname[t2]);
		if (rf != 0)
			db_printf("x%d, x%d", rd, rs2);
		else
			db_printf("r%d, r%d", rd, rs2);
		break;
	case 0x04:	/* flt */
		db_printf("%c \t\t", sodname[t2]);
		if ((inst & 0x200) != 0)	/* does not use the RF bit... */
			db_printf("x%d, x%d", rd, rs2);
		else
			db_printf("r%d, r%d", rd, rs2);
		break;
	case 0x07:	/* fcmp, fcmpu */
		db_printf("%c%c\t\t", sodname[t1], sodname[t2]);
		db_printf("r%d, ", rd);
		if (rf != 0)
			db_printf("x%d, x%d", rs1, rs2);
		else
			db_printf("r%d, r%d", rs1, rs2);
		break;
	case 0x08:	/* mov */
		if (rf != 0 && t1 == 0x01) {	/* mov.x, displayed as mov */
			db_printf("   \t\t");
			db_printf("x%d, x%d", rd, rs2);
		} else {
			db_printf(".%c \t\t", sodname[t2]);

			if (t1 == 0)
				db_printf("r%d, x%d", rd, rs2);
			else
				db_printf("x%d, r%d", rd, rs2);
		}
		break;
	case 0x09:	/* int */
	case 0x0a:	/* nint */
	case 0x0b:	/* trnc */
		db_printf("%c \t\t", sodname[t2]);
		if (rf != 0)
			db_printf("r%d, x%d", rd, rs2);
		else
			db_printf("r%d, r%d", rd, rs2);
		break;
	}

	return (1);
}

int
jump(int cpu, u_int32_t inst, const char *opcode, vaddr_t iadr)
{
	u_int32_t rs2 = inst & 0x1f;

	db_printf("\t%s", opcode);
	if ((inst & (1 << 10)) != 0)
		db_printf(".n");
	else
		db_printf("  ");
	db_printf("\t\tr%d", rs2);

	return (1);
}

/* Handles ff1, ff0, tbnd and rte instructions */
int
instset(int cpu, u_int32_t inst, const char *opcode, vaddr_t iadr)
{
	u_int32_t rs2 = inst & 0x1f;
	u_int32_t rs1 = (inst >> 16) & 0x1f;
	u_int32_t rd = (inst >> 21) & 0x1f;
	u_int32_t checkbits = (inst >> 10) & 0x3f;
	u_int32_t H6inst = (inst >> 26) & 0x3f;

	db_printf("\t%s", opcode);
	if (H6inst == 0x3e) { /* tbnd with imm16 */
		db_printf("\t\tr%d, 0x%04x", rs1, inst & 0xffff);
	} else {
		switch (checkbits) {
		case 0x3a:	/* ff1 */
		case 0x3b:	/* ff0 */
			db_printf("\t\tr%d,r%d", rd, rs2);
			break;
		case 0x3e:	/* tbnd */
			db_printf("\t\tr%d,r%d", rs1, rs2);
			break;
		case 0x3f:	/* rte, illop */
			if (rs2 != 0)
				db_printf("%d", rs2);
			break;
		}
	}

	return (1);
}

/* Handles unconditionnal branches */
int
obranch(int cpu, u_int32_t inst, const char *opcode, vaddr_t iadr)
{
	u_int32_t disp = inst & 0x3ffffff;

	db_printf("\t%s", opcode);
	if ((inst & (1 << 26)) != 0)
		db_printf(".n");
	else
		db_printf("  ");
	db_printf("\t\t");
	symofset(disp, 26, iadr);

	return (1);
}

/* Handles branch on conditions instructions */
int
brcond(int cpu, u_int32_t inst, const char *opcode, vaddr_t iadr)
{
	u_int32_t match = (inst >> 21) & 0x1f;
	u_int32_t rs = (inst >> 16) & 0x1f;
	u_int32_t disp = inst & 0xffff;
	int bcnd = ((inst >> 27) & 0x03) == 1;

	/* skip invalid conditions if bcnd */
	if (bcnd && condname[match] == NULL)
		return (0);

	db_printf("\t%s", opcode);
	if ((inst & (1 << 26)) != 0)
		db_printf(".n");
	else
		db_printf("  ");
	db_printf("\t\t");

	if (bcnd)
		db_printf("%s0", condname[match]);
	else
		printcmp(cpu, match);

	db_printf(", r%d, ", rs);
	symofset(disp, 16, iadr);

	return (1);
}

/* Handles trap instructions */
int
otrap(int cpu, u_int32_t inst, const char *opcode, vaddr_t iadr)
{
	u_int32_t vecno = inst & 0x1ff;
	u_int32_t match = (inst >> 21) & 0x1f;
	u_int32_t rs = (inst >> 16) & 0x1f;
	int tcnd = ((inst >> 12) & 0x0f) == 0xe;

	/* skip invalid conditions if tcnd */
	if (tcnd && condname[match] == NULL)
		return (0);

	db_printf("\t%s\t", opcode);
	if (tcnd)
		db_printf("%s0", condname[match]);
	else
		printcmp(cpu, match);
	db_printf(", r%d, 0x%x", rs, vecno);

	return (1);
}

/* Handles 10 bit immediate bit field operations */
int
obit(int cpu, u_int32_t inst, const char *opcode, vaddr_t iadr)
{
	u_int32_t rs = (inst >> 16) & 0x1f;
	u_int32_t rd = (inst >> 21) & 0x1f;
	u_int32_t width = (inst >> 5) & 0x1f;
	u_int32_t offset = inst & 0x1f;

	db_printf("\t%s\t\tr%d, r%d, ", opcode, rd, rs);
	if (((inst >> 10) & 0x3f) != 0x2a)	/* rot */
		db_printf("%d", width);
	db_printf("<%d>", offset);

	return (1);
}

/* Handles triadic mode bit field instructions */
int
bitman(int cpu, u_int32_t inst, const char *opcode, vaddr_t iadr)
{
	u_int32_t rs1 = (inst >> 16) & 0x1f;
	u_int32_t rd = (inst >> 21) & 0x1f;
	u_int32_t rs2 = inst & 0x1f;

	db_printf("\t%s\t\tr%d, r%d, r%d", opcode, rd, rs1, rs2);

	return (1);
}

/* Handles immediate load/store/exchange instructions */
int
immem(int cpu, u_int32_t inst, const char *opcode, vaddr_t iadr)
{
	u_int32_t rd = (inst >> 21) & 0x1f;
	u_int32_t rs = (inst >> 16) & 0x1f;
	u_int32_t st_lda = (inst >> 28) & 0x03;
	u_int32_t aryno = (inst >> 26) & 0x03;
	int rf = 0;
	char c = ' ';

	switch (st_lda) {
	case 0x00:
		if ((aryno & 0x02) != 0) {	/* 0x02, 0x03: ld.hu, ld.bu */
			opcode = "ld";
			c = 'u';
		} else {
			if (cpu == CPU_88100) {
				opcode = "xmem";
				if (aryno == 0) {	/* xmem.bu */
					aryno = 3;
					c = 'u';
				}
			} else {
				/* opcode = "ld"; */
				rf = 1;
			}
		}
		break;

	case 0x03:
		if (cpu != CPU_88100) {
			rf = 1;
			switch (st_lda) {
			case 0x00:		/* ld.x */
				aryno = 2;
				break;
			case 0x03:		/* st, st.d, st.x */
				break;
			}
		}
		break;
	}

	db_printf("\t%s%s%c\t\t", opcode,
	    rf != 0 ? xinstwidth[aryno] : instwidth[aryno], c);
	if (rf != 0)
		db_printf("x%d, r%d, ", rd, rs);
	else
		db_printf("r%d, r%d, ", rd, rs);
	db_printf("0x%x", inst & 0xffff);

	return (1);
}

/* Handles triadic mode load/store/exchange instructions */
int
nimmem(int cpu, u_int32_t inst, const char *opcode, vaddr_t iadr)
{
	u_int32_t scaled = (inst >> 9) & 0x01;
	u_int32_t rd = (inst >> 21) & 0x1f;
	u_int32_t rs1 = (inst >> 16) & 0x1f;
	u_int32_t rs2 = inst & 0x1f;
	u_int32_t st_lda = (inst >> 12) & 0x03;
	u_int32_t aryno = (inst >> 10) & 0x03;
	char c = ' ';
	int rf = 0, wt = 0, usr = 0;

	switch (st_lda) {
	case 0x00:
		switch (aryno) {
		case 0x00:			/* xmem.bu */
			aryno = 3;
			c = 'u';
			/* FALLTHROUGH */
		case 0x01:			/* xmem */
			opcode = "xmem";
			break;
		default:
		case 0x02:			/* ld.hu */
		case 0x03:			/* ld.bu */
			opcode = "ld";
			c = 'u';
			break;
		}
		break;
	case 0x01:
		opcode = "ld";
		if (cpu != CPU_88100) {
			if ((inst & (1 << 26)) == 0)
				rf = 1;
		}
		break;
	case 0x02:	/* st */
		if (cpu != CPU_88100) {
			if ((inst & (1 << 26)) == 0)
				rf = 1;
			if ((inst & (1 << 7)) != 0)
				wt = 1;
		}
		break;
	case 0x03:
		if (cpu != CPU_88100) {
			/* cheat instwidth for lda.x */
			if (aryno == 3)
				aryno = 4;
		}
		break;
	}

	if (st_lda != 0x03 && (inst & (1 << 8)) != 0)
		usr = 1;

	db_printf("\t%s%s%c%s%s\t",
	    opcode, rf != 0 ? xinstwidth[aryno] : instwidth[aryno], c,
	    usr != 0 ? ".usr" : "    ", wt != 0 ? ".wt" : "   ");
	if (rf != 0)
		db_printf("x%d, r%d", rd, rs1);
	else
		db_printf("r%d, r%d", rd, rs1);

	if (scaled != 0)
		db_printf("[r%d]", rs2);
	else
		db_printf(", r%d", rs2);

	return (1);
}

/* Handles triadic mode logical instructions */
int
lognim(int cpu, u_int32_t inst, const char *opcode, vaddr_t iadr)
{
	u_int32_t rd = (inst >> 21) & 0x1f;
	u_int32_t rs1 = (inst >> 16) & 0x1f;
	u_int32_t rs2 = inst & 0x1f;

	db_printf("\t%s", opcode);
	if ((inst & (1 << 10)) != 0)
		db_printf(".c");

	db_printf("\t\tr%d, r%d, r%d", rd, rs1, rs2);

	return (1);
}

/* Handles triadic mode arithmetic instructions */
int
onimmed(int cpu, u_int32_t inst, const char *opcode, vaddr_t iadr)
{
	u_int32_t rd = (inst >> 21) & 0x1f;
	u_int32_t rs1 = (inst >> 16) & 0x1f;
	u_int32_t rs2 = inst & 0x1f;
	u_int32_t carry = (inst >> 8) & 0x03;

	db_printf("\t%s", opcode);

	if ((inst & (1 << 11)) == 0) {
		switch (carry) {
		case 0x01:
			db_printf(".co");
			break;
		case 0x02:
			db_printf(".ci");
			break;
		case 0x03:
			db_printf(".cio");
			break;
		}
	} else {
		if (cpu != CPU_88100 && carry == 0x01)
			db_printf(".d");
	}

	db_printf("\tr%d, r%d, r%d", rd, rs1, rs2);

	return (1);
}

/* Handles 88110 SFU2 instructions */
int
pinst(int cpu, u_int32_t inst, const char *opcode, vaddr_t iadr)
{
	u_int32_t rd = (inst >> 21) & 0x1f;
	u_int32_t rs1 = (inst >> 16) & 0x1f;
	u_int32_t rs2 = inst & 0x1f;
	u_int32_t tfield = (inst >> 5) & 0x03;
	u_int32_t pfunc = (inst >> 11) & 0x1f;
	const char *saturation[] = { NULL, ".u", ".us", ".s" };

	db_printf("\t%s", opcode);

	switch (pfunc) {
	case 0x0c:	/* ppack */
		db_printf(".%d", (inst >> 5) & 0x3c);
		break;
	case 0x0e:	/* prot */
		break;
	default:	/* other instructions have an S field or zero */
	    {
		u_int32_t sfield = (inst >> 7) & 0x03;

		if (sfield != 0)
			db_printf("%s", saturation[sfield]);
	    }
		break;
	}

	if (tfield != 0 || pfunc == 0x0d /* punpk */) {
		if (tfield != 3)
			db_printf(".%c", "nbh"[tfield]);
	}

	switch (pfunc) {
	case 0x0d:	/* punpk */
		db_printf("\tr%d, r%d", rd, rs1);
		break;
	case 0x0e:	/* prot with immediate */
		db_printf("\tr%d, r%d, %d", rd, rs1, (inst >> 5) & 0x3f);
		break;
	default:
		db_printf("\tr%d, r%d, r%d", rd, rs1, rs2);
		break;
	}

	return (1);
}

static const struct opdesc {
	u_int32_t mask, match;
	int (*opfun)(int, u_int32_t, const char *, vaddr_t);
	const char *opcode;
} opdecode_88100[] = {
	/* ORDER IS IMPORTANT BELOW */
	{ 0xf0000000,	0x00000000,	immem,		NULL },	/* xmem/ld */
	{ 0xf0000000,	0x10000000,	immem,		"ld" },
	{ 0xf0000000,	0x20000000,	immem,		"st" },
	{ 0xf0000000,	0x30000000,	immem,		"lda" },

	{ 0xf8000000,	0x40000000,	oimmed,		"and" },
	{ 0xf8000000,	0x48000000,	oimmed,		"mask" },
	{ 0xf8000000,	0x50000000,	oimmed,		"xor" },
	{ 0xf8000000,	0x58000000,	oimmed,		"or" },
	{ 0xfc000000,	0x60000000,	oimmed,		"addu" },
	{ 0xfc000000,	0x64000000,	oimmed,		"subu" },
	{ 0xfc000000,	0x68000000,	oimmed,		"divu" },
	{ 0xfc000000,	0x6c000000,	oimmed,		"mul" },
	{ 0xfc000000,	0x70000000,	oimmed,		"add" },
	{ 0xfc000000,	0x74000000,	oimmed,		"sub" },
	{ 0xfc000000,	0x78000000,	oimmed,		"div" },
	{ 0xfc000000,	0x7c000000,	oimmed,		"cmp" },

	{ 0xfc00f800,	0x80004000,	ctrlregs,	"ldcr" },
	{ 0xfc00f800,	0x80004800,	ctrlregs,	"fldcr" },
	{ 0xfc00f800,	0x80008000,	ctrlregs,	"stcr" },
	{ 0xfc00f800,	0x80008800,	ctrlregs,	"fstcr" },
	{ 0xfc00f800,	0x8000c000,	ctrlregs,	"xcr" },
	{ 0xfc00f800,	0x8000c800,	ctrlregs,	"fxcr" },

	{ 0xfc00f800,	0x84000000,	sindou,		"fmul" },
	{ 0xfc1fff80,	0x84002000,	sindou,		"flt" },
	{ 0xfc00f800,	0x84002800,	sindou,		"fadd" },
	{ 0xfc00f800,	0x84003000,	sindou,		"fsub" },
	{ 0xfc00f860,	0x84003800,	sindou,		"fcmp" },
	{ 0xfc1ffe60,	0x84004800,	sindou,		"int" },
	{ 0xfc1ffe60,	0x84005000,	sindou,		"nint" },
	{ 0xfc1ffe60,	0x84005800,	sindou,		"trnc" },
	{ 0xfc00f800,	0x84007000,	sindou,		"fdiv" },

	{ 0xf8000000,	0xc0000000,	obranch,	"br" },
	{ 0xf8000000,	0xc8000000,	obranch,	"bsr" },

	{ 0xf8000000,	0xd0000000,	brcond,		"bb0" },
	{ 0xf8000000,	0xd8000000,	brcond,		"bb1" },
	{ 0xf8000000,	0xe8000000,	brcond,		"bcnd" },

	{ 0xfc00fc00,	0xf0008000,	obit,		"clr" },
	{ 0xfc00fc00,	0xf0008800,	obit,		"set" },
	{ 0xfc00fc00,	0xf0009000,	obit,		"ext" },
	{ 0xfc00fc00,	0xf0009800,	obit,		"extu" },
	{ 0xfc00fc00,	0xf000a000,	obit,		"mak" },
	{ 0xfc00fc00,	0xf000a800,	obit,		"rot" },

	{ 0xfc00fe00,	0xf000d000,	otrap,		"tb0" },
	{ 0xfc00fe00,	0xf000d800,	otrap,		"tb1" },
	{ 0xfc00fe00,	0xf000e800,	otrap,		"tcnd" },

	{ 0xfc00f0e0,	0xf4000000,	nimmem,		NULL },	/* xmem/ld */
	{ 0xfc00f0e0,	0xf4001000,	nimmem,		"ld" },
	{ 0xfc00f0e0,	0xf4002000,	nimmem,		"st" },
	{ 0xfc00f0e0,	0xf4003000,	nimmem,		"lda" },

	{ 0xfc00fbe0,	0xf4004000,	lognim,		"and" },
	{ 0xfc00fbe0,	0xf4005000,	lognim,		"xor" },
	{ 0xfc00fbe0,	0xf4005800,	lognim,		"or" },

	{ 0xfc00fce0,	0xf4006000,	onimmed,	"addu" },
	{ 0xfc00fce0,	0xf4006400,	onimmed,	"subu" },
	{ 0xfc00fce0,	0xf4006800,	onimmed,	"divu" },
	{ 0xfc00fce0,	0xf4006c00,	onimmed,	"mul" },
	{ 0xfc00fce0,	0xf4007000,	onimmed,	"add" },
	{ 0xfc00fce0,	0xf4007400,	onimmed,	"sub" },
	{ 0xfc00fce0,	0xf4007800,	onimmed,	"div" },
	{ 0xfc00fce0,	0xf4007c00,	onimmed,	"cmp" },

	{ 0xfc00ffe0,	0xf4008000,	bitman,		"clr" },
	{ 0xfc00ffe0,	0xf4008800,	bitman,		"set" },
	{ 0xfc00ffe0,	0xf4009000,	bitman,		"ext" },
	{ 0xfc00ffe0,	0xf4009800,	bitman,		"extu" },
	{ 0xfc00ffe0,	0xf400a000,	bitman,		"mak" },
	{ 0xfc00ffe0,	0xf400a800,	bitman,		"rot" },

	{ 0xfc00fbe0,	0xf400c000,	jump,		"jmp" },
	{ 0xfc00fbe0,	0xf400c800,	jump,		"jsr" },

	{ 0xfc00ffe0,	0xf400e800,	instset,	"ff1" },
	{ 0xfc00ffe0,	0xf400ec00,	instset,	"ff0" },
	{ 0xfc00ffe0,	0xf400f800,	instset,	"tbnd" },
	{ 0xfc00ffe0,	0xf400fc00,	instset,	"rte" },
	{ 0xfc000000,	0xf8000000,	instset,	"tbnd" },
	{ 0,		0,		NULL,		NULL }
}, opdecode_88110[] = {
	/* ORDER IS IMPORTANT BELOW */
	{ 0xe0000000,	0x00000000,	immem,		"ld" },
	{ 0xf0000000,	0x20000000,	immem,		"st" },
	{ 0xfc000000,	0x3c000000,	immem,		"ld" },
	{ 0xf0000000,	0x30000000,	immem,		"st" },

	{ 0xf8000000,	0x40000000,	oimmed,		"and" },
	{ 0xf8000000,	0x48000000,	oimmed,		"mask" },
	{ 0xf8000000,	0x50000000,	oimmed,		"xor" },
	{ 0xf8000000,	0x58000000,	oimmed,		"or" },
	{ 0xfc000000,	0x60000000,	oimmed,		"addu" },
	{ 0xfc000000,	0x64000000,	oimmed,		"subu" },
	{ 0xfc000000,	0x68000000,	oimmed,		"divu" },
	{ 0xfc000000,	0x6c000000,	oimmed,		"mulu" },
	{ 0xfc000000,	0x70000000,	oimmed,		"add" },
	{ 0xfc000000,	0x74000000,	oimmed,		"sub" },
	{ 0xfc000000,	0x78000000,	oimmed,		"divs" },
	{ 0xfc000000,	0x7c000000,	oimmed,		"cmp" },

	{ 0xfc1ff81f,	0x80004000,	ctrlregs,	"ldcr" },
	{ 0xfc1ff81f,	0x80004800,	ctrlregs,	"fldcr" },
	{ 0xffe0f800,	0x80008000,	ctrlregs,	"stcr" },
	{ 0xffe0f800,	0x80008800,	ctrlregs,	"fstcr" },
	{ 0xfc00f800,	0x8000c000,	ctrlregs,	"xcr" },
	{ 0xfc00f800,	0x8000c800,	ctrlregs,	"fxcr" },

	{ 0xfc007800,	0x84000000,	sindou,		"fmul" },
	{ 0xfc1f7e00,	0x84000800,	sindou,		"fcvt" },
	{ 0xfc1ffd80,	0x84002000,	sindou,		"flt" },
	{ 0xfc007800,	0x84002800,	sindou,		"fadd" },
	{ 0xfc007800,	0x84003000,	sindou,		"fsub" },
	{ 0xfc007860,	0x84003800,	sindou,		"fcmp" },
	{ 0xfc007860,	0x84003820,	sindou,		"fcmpu" },
	{ 0xfc1ffe60,	0x8400c000,	sindou,		"mov" },
	{ 0xfc17fe60,	0x84004200,	sindou,		"mov" },
	{ 0xfc1f7e60,	0x84004800,	sindou,		"int" },
	{ 0xfc1f7e60,	0x84005000,	sindou,		"nint" },
	{ 0xfc1f7e60,	0x84005800,	sindou,		"trnc" },
	{ 0xfc007800,	0x84007000,	sindou,		"fdiv" },
	{ 0xfc1f7e00,	0x84007800,	sindou,		"fsqrt" },

	{ 0xfc00ffe0,	0x88000000,	pinst,		"pmul" },
	{ 0xfc00ff80,	0x88002000,	pinst,		"padd" },
	{ 0xfc00fe00,	0x88002000,	pinst,		"padds" },
	{ 0xfc00ff80,	0x88003000,	pinst,		"psub" },
	{ 0xfc00fe00,	0x88003000,	pinst,		"psubs" },
	{ 0xfc00ffe0,	0x88003860,	pinst,		"pcmp" },
	{ 0xfc00f800,	0x88006000,	pinst,		"ppack" },
	{ 0xfc00ff9f,	0x88006800,	pinst,		"punpk" },
	{ 0xfc00f87f,	0x88007000,	pinst,		"prot" },
	{ 0xfc00ffe0,	0x88007800,	pinst,		"prot" },

	{ 0xf8000000,	0xc0000000,	obranch,	"br" },
	{ 0xf8000000,	0xc8000000,	obranch,	"bsr" },

	{ 0xf8000000,	0xd0000000,	brcond,		"bb0" },
	{ 0xf8000000,	0xd8000000,	brcond,		"bb1" },
	{ 0xf8000000,	0xe8000000,	brcond,		"bcnd" },

	{ 0xfc00fc00,	0xf0008000,	obit,		"clr" },
	{ 0xfc00fc00,	0xf0008800,	obit,		"set" },
	{ 0xfc00fc00,	0xf0009000,	obit,		"ext" },
	{ 0xfc00fc00,	0xf0009800,	obit,		"extu" },
	{ 0xfc00fc00,	0xf000a000,	obit,		"mak" },
	{ 0xfc00ffe0,	0xf000a800,	obit,		"rot" },

	{ 0xfc00fe00,	0xf000d000,	otrap,		"tb0" },
	{ 0xfc00fe00,	0xf000d800,	otrap,		"tb1" },
	{ 0xfc00fe00,	0xf000e800,	otrap,		"tcnd" },

	{ 0xfc00f0e0,	0xf4000000,	nimmem,		NULL },	/* ld/xmem */
	{ 0xf800f0e0,	0xf0001000,	nimmem,		"ld" },
	{ 0xf800f060,	0xf0002000,	nimmem,		"st" },
	{ 0xfc00f2e0,	0xf4003200,	nimmem,		"lda" },

	{ 0xfc00fbe0,	0xf4004000,	lognim,		"and" },
	{ 0xfc00fbe0,	0xf4005000,	lognim,		"xor" },
	{ 0xfc00fbe0,	0xf4005800,	lognim,		"or" },

	{ 0xfc00fce0,	0xf4006000,	onimmed,	"addu" },
	{ 0xfc00fce0,	0xf4006400,	onimmed,	"subu" },
	{ 0xfc00fee0,	0xf4006800,	onimmed,	"divu" },
	{ 0xfc00fee0,	0xf4006c00,	onimmed,	"mulu" },
	{ 0xfc00ffe0,	0xf4006e00,	onimmed,	"muls" },
	{ 0xfc00fce0,	0xf4007000,	onimmed,	"add" },
	{ 0xfc00fce0,	0xf4007400,	onimmed,	"sub" },
	{ 0xfc00ffe0,	0xf4007800,	onimmed,	"divs" },
	{ 0xfc00ffe0,	0xf4007c00,	onimmed,	"cmp" },

	{ 0xfc00ffe0,	0xf4008000,	bitman,		"clr" },
	{ 0xfc00ffe0,	0xf4008800,	bitman,		"set" },
	{ 0xfc00ffe0,	0xf4009000,	bitman,		"ext" },
	{ 0xfc00ffe0,	0xf4009800,	bitman,		"extu" },
	{ 0xfc00ffe0,	0xf400a000,	bitman,		"mak" },
	{ 0xfc00ffe0,	0xf400a800,	bitman,		"rot" },

	{ 0xfffffbe0,	0xf400c000,	jump,		"jmp" },
	{ 0xfffffbe0,	0xf400c800,	jump,		"jsr" },

	{ 0xfc1fffe0,	0xf400e800,	instset,	"ff1" },
	{ 0xfc1fffe0,	0xf400ec00,	instset,	"ff0" },
	{ 0xffe0ffe0,	0xf400f800,	instset,	"tbnd" },
	{ 0xffffffff,	0xf400fc00,	instset,	"rte" },
	{ 0xfffffffc,	0xf400fc00,	instset,	"illop" },
	{ 0xffe00000,	0xf8000000,	instset,	"tbnd" },
	{ 0,		0,		NULL,		NULL }
};

void
m88k_print_instruction(int cpu, u_int iadr, u_int32_t inst)
{
	const struct opdesc *p;

	/*
	 * This messes up "or.b" instructions ever so slightly,
	 * but keeps us in sync between routines...
	 */
	if (inst == 0) {
		db_printf("\t.word\t0\n");
	} else {
		p = cpu != CPU_88100 ? opdecode_88110 : opdecode_88100;
		while (p->mask != 0) {
			if ((inst & p->mask) == p->match) {
				if ((*p->opfun)(cpu, inst, p->opcode, iadr)) {
					db_printf("\n");
					return;
				}
				break;
			}
			p++;
		}
		db_printf("\t.word\t0x%x\n", inst);
	}
}

db_addr_t
db_disasm(db_addr_t loc, boolean_t altfmt)
{
	int cpu;

	if (altfmt)
		cpu = CPU_IS88100 ? CPU_88110 : CPU_88100;
	else
		cpu = cputyp;

	m88k_print_instruction(cpu, loc, db_get_value(loc, 4, FALSE));
	return (loc + 4);
}