code:
/*	$OpenBSD: astro.c,v 1.17 2014/11/16 12:30:57 deraadt Exp $	*/

/*
 * Copyright (c) 2007 Mark Kettenis
 *
 * Permission to use, copy, modify, and distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <sys/extent.h>
#include <sys/malloc.h>
#include <sys/mutex.h>
#include <sys/reboot.h>
#include <sys/tree.h>

#include <uvm/uvm_extern.h>

#include <machine/iomod.h>
#include <machine/autoconf.h>

#include <hppa/dev/cpudevs.h>

struct astro_regs {
	u_int32_t	rid;
	u_int32_t	pad0000;
	u_int32_t	ioc_ctrl;
	u_int32_t	pad0008;
	u_int8_t	resv1[0x0300 - 0x0010];
	u_int64_t	lmmio_direct0_base;
	u_int64_t	lmmio_direct0_mask;
	u_int64_t	lmmio_direct0_route;
	u_int64_t	lmmio_direct1_base;
	u_int64_t	lmmio_direct1_mask;
	u_int64_t	lmmio_direct1_route;
	u_int64_t	lmmio_direct2_base;
	u_int64_t	lmmio_direct2_mask;
	u_int64_t	lmmio_direct2_route;
	u_int64_t	lmmio_direct3_base;
	u_int64_t	lmmio_direct3_mask;
	u_int64_t	lmmio_direct3_route;
	u_int64_t	lmmio_dist_base;
	u_int64_t	lmmio_dist_mask;
	u_int64_t	lmmio_dist_route;
	u_int64_t	gmmio_dist_base;
	u_int64_t	gmmio_dist_mask;
	u_int64_t	gmmio_dist_route;
	u_int64_t	ios_dist_base;
	u_int64_t	ios_dist_mask;
	u_int64_t	ios_dist_route;
	u_int8_t	resv2[0x03c0 - 0x03a8];
	u_int64_t	ios_direct_base;
	u_int64_t	ios_direct_mask;
	u_int64_t	ios_direct_route;
	u_int8_t	resv3[0x22000 - 0x03d8];
	u_int64_t	func_id;
	u_int64_t	func_class;
	u_int8_t	resv4[0x22040 - 0x22010];
	u_int64_t	rope_config;
	u_int8_t	resv5[0x22050 - 0x22048];
	u_int64_t	rope_debug;
	u_int8_t	resv6[0x22200 - 0x22058];
	u_int64_t	rope0_control;
	u_int64_t	rope1_control;
	u_int64_t	rope2_control;
	u_int64_t	rope3_control;
	u_int64_t	rope4_control;
	u_int64_t	rope5_control;
	u_int64_t	rope6_control;
	u_int64_t	rope7_control;
	u_int8_t	resv7[0x22300 - 0x22240];
	u_int32_t	tlb_ibase;
	u_int32_t	pad22300;
	u_int32_t	tlb_imask;
	u_int32_t	pad22308;
	u_int32_t	tlb_pcom;
	u_int32_t	pad22310;
	u_int32_t	tlb_tcnfg;
	u_int32_t	pad22318;
	u_int64_t	tlb_pdir_base;
};

#define ASTRO_IOC_CTRL_TE	0x0001	/* TOC Enable */
#define ASTRO_IOC_CTRL_CE	0x0002	/* Coalesce Enable */
#define ASTRO_IOC_CTRL_DE	0x0004	/* Dillon Enable */
#define ASTRO_IOC_CTRL_IE	0x0008	/* IOS Enable */
#define ASTRO_IOC_CTRL_OS	0x0010	/* Outbound Synchronous */
#define ASTRO_IOC_CTRL_IS	0x0020	/* Inbound Synchronous */
#define ASTRO_IOC_CTRL_RC	0x0040	/* Read Current Enable */
#define ASTRO_IOC_CTRL_L0	0x0080	/* 0-length Read Enable */
#define ASTRO_IOC_CTRL_RM	0x0100	/* Real Mode */
#define ASTRO_IOC_CTRL_NC	0x0200	/* Non-coherent Mode */
#define ASTRO_IOC_CTRL_ID	0x0400	/* Interrupt Disable */
#define ASTRO_IOC_CTRL_D4	0x0800	/* Disable 4-byte Coalescing */
#define ASTRO_IOC_CTRL_CC	0x1000	/* Increase Coalescing counter value */
#define ASTRO_IOC_CTRL_DD	0x2000	/* Disable distr. range coalescing */
#define ASTRO_IOC_CTRL_DC	0x4000	/* Disable the coalescing counter */

#define IOTTE_V		0x8000000000000000LL	/* Entry valid */
#define IOTTE_PAMASK	0x000000fffffff000LL
#define IOTTE_CI	0x00000000000000ffLL	/* Coherent index */

struct astro_softc {
	struct device sc_dv;

	bus_dma_tag_t sc_dmat;
	struct astro_regs volatile *sc_regs;
	u_int64_t *sc_pdir;

	char sc_dvmamapname[20];
	struct extent *sc_dvmamap;
	struct mutex sc_dvmamtx;

	struct hppa_bus_dma_tag sc_dmatag;
};

/*
 * per-map DVMA page table
 */
struct iommu_page_entry {
	SPLAY_ENTRY(iommu_page_entry) ipe_node;
	paddr_t	ipe_pa;
	vaddr_t	ipe_va;
	bus_addr_t ipe_dva;
};

struct iommu_page_map {
	SPLAY_HEAD(iommu_page_tree, iommu_page_entry) ipm_tree;
	int ipm_maxpage;	/* Size of allocated page map */
	int ipm_pagecnt;	/* Number of entries in use */
	struct iommu_page_entry	ipm_map[1];
};

/*
 * per-map IOMMU state
 */
struct iommu_map_state {
	struct astro_softc *ims_sc;
	bus_addr_t ims_dvmastart;
	bus_size_t ims_dvmasize;
	struct extent_region ims_er;
	struct iommu_page_map ims_map;	/* map must be last (array at end) */
};

int	astro_match(struct device *, void *, void *);
void	astro_attach(struct device *, struct device *, void *);

struct cfattach astro_ca = {
	sizeof(struct astro_softc), astro_match, astro_attach
};

struct cfdriver astro_cd = {
	NULL, "astro", DV_DULL
};

int	iommu_dvmamap_create(void *, bus_size_t, int, bus_size_t, bus_size_t,
	    int, bus_dmamap_t *);
void	iommu_dvmamap_destroy(void *, bus_dmamap_t);
int	iommu_dvmamap_load(void *, bus_dmamap_t, void *, bus_size_t,
	    struct proc *, int);
int	iommu_iomap_load_map(struct astro_softc *, bus_dmamap_t, int);
int	iommu_dvmamap_load_mbuf(void *, bus_dmamap_t, struct mbuf *, int);
int	iommu_dvmamap_load_uio(void *, bus_dmamap_t, struct uio *, int);
int	iommu_dvmamap_load_raw(void *, bus_dmamap_t, bus_dma_segment_t *,
	    int, bus_size_t, int);
void	iommu_dvmamap_unload(void *, bus_dmamap_t);
void	iommu_dvmamap_sync(void *, bus_dmamap_t, bus_addr_t, bus_size_t, int);
int	iommu_dvmamem_alloc(void *, bus_size_t, bus_size_t, bus_size_t,
	    bus_dma_segment_t *, int, int *, int);
void	iommu_dvmamem_free(void *, bus_dma_segment_t *, int);
int	iommu_dvmamem_map(void *, bus_dma_segment_t *, int, size_t,
	    caddr_t *, int);
void	iommu_dvmamem_unmap(void *, caddr_t, size_t);
paddr_t	iommu_dvmamem_mmap(void *, bus_dma_segment_t *, int, off_t, int, int);

void	iommu_enter(struct astro_softc *, bus_addr_t, paddr_t, vaddr_t, int);
void	iommu_remove(struct astro_softc *, bus_addr_t);

struct iommu_map_state *iommu_iomap_create(int);
void	iommu_iomap_destroy(struct iommu_map_state *);
int	iommu_iomap_insert_page(struct iommu_map_state *, vaddr_t, paddr_t);
bus_addr_t iommu_iomap_translate(struct iommu_map_state *, paddr_t);
void	iommu_iomap_clear_pages(struct iommu_map_state *);

const struct hppa_bus_dma_tag astro_dmat = {
	NULL,
	iommu_dvmamap_create, iommu_dvmamap_destroy,
	iommu_dvmamap_load, iommu_dvmamap_load_mbuf,
	iommu_dvmamap_load_uio, iommu_dvmamap_load_raw,
	iommu_dvmamap_unload, iommu_dvmamap_sync,

	iommu_dvmamem_alloc, iommu_dvmamem_free, iommu_dvmamem_map,
	iommu_dvmamem_unmap, iommu_dvmamem_mmap
};

int
astro_match(struct device *parent, void *cfdata, void *aux)
{
	struct confargs *ca = aux;

	/* Astro is a U-Turn variant. */
	if (ca->ca_type.iodc_type != HPPA_TYPE_IOA ||
	    ca->ca_type.iodc_sv_model != HPPA_IOA_UTURN)
		return 0;

	if (ca->ca_type.iodc_model == 0x58 &&
	    ca->ca_type.iodc_revision >= 0x20)
		return 1;

	return 0;
}

void
astro_attach(struct device *parent, struct device *self, void *aux)
{
	struct confargs *ca = aux, nca;
	struct astro_softc *sc = (struct astro_softc *)self;
	volatile struct astro_regs *r;
	bus_space_handle_t ioh;
	u_int32_t rid, ioc_ctrl;
	psize_t size;
	vaddr_t va;
	paddr_t pa;
	struct vm_page *m;
	struct pglist mlist;
	int iova_bits;

	sc->sc_dmat = ca->ca_dmatag;
	if (bus_space_map(ca->ca_iot, ca->ca_hpa, sizeof(struct astro_regs),
	    0, &ioh)) {
		printf(": can't map IO space\n");
		return;
	}
	sc->sc_regs = r = (struct astro_regs *)ca->ca_hpa;

	rid = letoh32(r->rid);
	printf(": Astro rev %d.%d\n", (rid & 7) + 1, (rid >> 3) & 3);

	ioc_ctrl = letoh32(r->ioc_ctrl);
	ioc_ctrl &= ~ASTRO_IOC_CTRL_CE;
	ioc_ctrl &= ~ASTRO_IOC_CTRL_RM;
	ioc_ctrl &= ~ASTRO_IOC_CTRL_NC;
	r->ioc_ctrl = htole32(ioc_ctrl);

	/*
	 * Setup the iommu.
	 */

	/* XXX This gives us 256MB of iova space. */
	iova_bits = 28;

	r->tlb_ibase = htole32(0);
	r->tlb_imask = htole32(0xffffffff << iova_bits);

	/* Page size is 4K. */
	r->tlb_tcnfg = htole32(0);

	/* Flush TLB. */
	r->tlb_pcom = htole32(31);

	/*
	 * Allocate memory for I/O pagetables.  They need to be physically
	 * contiguous.
	 */

	size = (1 << (iova_bits - PAGE_SHIFT)) * sizeof(u_int64_t);
	TAILQ_INIT(&mlist);
	if (uvm_pglistalloc(size, 0, -1, PAGE_SIZE, 0, &mlist,
	    1, UVM_PLA_NOWAIT) != 0)
		panic("astrottach: no memory");

	va = (vaddr_t)km_alloc(size, &kv_any, &kp_none, &kd_nowait);
	if (va == 0)
		panic("astroattach: no memory");
	sc->sc_pdir = (u_int64_t *)va;

	m = TAILQ_FIRST(&mlist);
	r->tlb_pdir_base = htole64(VM_PAGE_TO_PHYS(m));

	/* Map the pages. */
	for (; m != NULL; m = TAILQ_NEXT(m, pageq)) {
		pa = VM_PAGE_TO_PHYS(m);
		pmap_enter(pmap_kernel(), va, pa,
		    PROT_READ | PROT_WRITE, PMAP_WIRED);
		va += PAGE_SIZE;
	}
	pmap_update(pmap_kernel());
	memset(sc->sc_pdir, 0, size);

	/*
	 * The PDC might have set up some devices to do DMA.  It will do
	 * this for the onboard USB controller if an USB keyboard is used
	 * for console input.  In that case, bad things will happen if we
	 * enable iova space.  So reset the PDC devices before we do that.
	 * Don't do this if we're using a serial console though, since it
	 * will stop working if we do.  This is fine since the serial port
	 * doesn't do DMA.
	 */
	if (PAGE0->mem_cons.pz_class != PCL_DUPLEX)
		pdc_call((iodcio_t)pdc, 0, PDC_IO, PDC_IO_RESET_DEVICES);

	/* Enable iova space. */
	r->tlb_ibase = htole32(1);

        /*
         * Now all the hardware's working we need to allocate a dvma map.
         */
	snprintf(sc->sc_dvmamapname, sizeof(sc->sc_dvmamapname),
	    "%s_dvma", sc->sc_dv.dv_xname);
	sc->sc_dvmamap = extent_create(sc->sc_dvmamapname, 0, (1 << iova_bits),
	    M_DEVBUF, NULL, 0, EX_NOWAIT | EX_NOCOALESCE);
	KASSERT(sc->sc_dvmamap);
	mtx_init(&sc->sc_dvmamtx, IPL_HIGH);

	sc->sc_dmatag = astro_dmat;
	sc->sc_dmatag._cookie = sc;

	nca = *ca;	/* clone from us */
	nca.ca_hpamask = HPPA_IOBEGIN;
	nca.ca_dmatag = &sc->sc_dmatag;
	pdc_scanbus(self, &nca, MAXMODBUS, 0, 0);
}

int
iommu_dvmamap_create(void *v, bus_size_t size, int nsegments,
    bus_size_t maxsegsz, bus_size_t boundary, int flags, bus_dmamap_t *dmamap)
{
	struct astro_softc *sc = v;
	bus_dmamap_t map;
	struct iommu_map_state *ims;
	int error;

	error = bus_dmamap_create(sc->sc_dmat, size, nsegments, maxsegsz,
	    boundary, flags, &map);
	if (error)
		return (error);

	ims = iommu_iomap_create(atop(round_page(size)));
	if (ims == NULL) {
		bus_dmamap_destroy(sc->sc_dmat, map);
		return (ENOMEM);
	}

	ims->ims_sc = sc;
	map->_dm_cookie = ims;
	*dmamap = map;

	return (0);
}

void
iommu_dvmamap_destroy(void *v, bus_dmamap_t map)
{
	struct astro_softc *sc = v;

	/*
	 * The specification (man page) requires a loaded
	 * map to be unloaded before it is destroyed.
	 */
	if (map->dm_nsegs)
		iommu_dvmamap_unload(sc, map);

        if (map->_dm_cookie)
                iommu_iomap_destroy(map->_dm_cookie);
	map->_dm_cookie = NULL;

	bus_dmamap_destroy(sc->sc_dmat, map);
}

int
iommu_iomap_load_map(struct astro_softc *sc, bus_dmamap_t map, int flags)
{
	struct iommu_map_state *ims = map->_dm_cookie;
	struct iommu_page_map *ipm = &ims->ims_map;
	struct iommu_page_entry *e;
	int err, seg;
	paddr_t pa, paend;
	vaddr_t va;
	bus_size_t sgsize;
	bus_size_t align, boundary;
	u_long dvmaddr;
	bus_addr_t dva;
	int i;

	/* XXX */
	boundary = map->_dm_boundary;
	align = PAGE_SIZE;

	iommu_iomap_clear_pages(ims);

	for (seg = 0; seg < map->dm_nsegs; seg++) {
		struct hppa_bus_dma_segment *ds = &map->dm_segs[seg];

		paend = round_page(ds->ds_addr + ds->ds_len);
		for (pa = trunc_page(ds->ds_addr), va = trunc_page(ds->_ds_va);
		     pa < paend; pa += PAGE_SIZE, va += PAGE_SIZE) {
			err = iommu_iomap_insert_page(ims, va, pa);
			if (err) {
                               printf("iomap insert error: %d for "
                                    "va 0x%lx pa 0x%lx\n", err, va, pa);
				bus_dmamap_unload(sc->sc_dmat, map);
				iommu_iomap_clear_pages(ims);
			}
		}
	}

	sgsize = ims->ims_map.ipm_pagecnt * PAGE_SIZE;
	mtx_enter(&sc->sc_dvmamtx);
	err = extent_alloc_with_descr(sc->sc_dvmamap, sgsize, align, 0,
	    boundary, EX_NOWAIT | EX_BOUNDZERO, &ims->ims_er, &dvmaddr);
	mtx_leave(&sc->sc_dvmamtx);
	if (err)
		return (err);

	ims->ims_dvmastart = dvmaddr;
	ims->ims_dvmasize = sgsize;

	dva = dvmaddr;
	for (i = 0, e = ipm->ipm_map; i < ipm->ipm_pagecnt; ++i, ++e) {
		e->ipe_dva = dva;
		iommu_enter(sc, e->ipe_dva, e->ipe_pa, e->ipe_va, flags);
		dva += PAGE_SIZE;
	}

	for (seg = 0; seg < map->dm_nsegs; seg++) {
		struct hppa_bus_dma_segment *ds = &map->dm_segs[seg];
		ds->ds_addr = iommu_iomap_translate(ims, ds->ds_addr);
	}

	return (0);
}

int
iommu_dvmamap_load(void *v, bus_dmamap_t map, void *addr, bus_size_t size,
    struct proc *p, int flags)
{
	struct astro_softc *sc = v;
	int err;

	err = bus_dmamap_load(sc->sc_dmat, map, addr, size, p, flags);
	if (err)
		return (err);

	return iommu_iomap_load_map(sc, map, flags);
}

int
iommu_dvmamap_load_mbuf(void *v, bus_dmamap_t map, struct mbuf *m, int flags)
{
	struct astro_softc *sc = v;
	int err;

	err = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, flags);
	if (err)
		return (err);

	return iommu_iomap_load_map(sc, map, flags);
}

int
iommu_dvmamap_load_uio(void *v, bus_dmamap_t map, struct uio *uio, int flags)
{
	struct astro_softc *sc = v;

	printf("load_uio\n");

	return (bus_dmamap_load_uio(sc->sc_dmat, map, uio, flags));
}

int
iommu_dvmamap_load_raw(void *v, bus_dmamap_t map, bus_dma_segment_t *segs,
    int nsegs, bus_size_t size, int flags)
{
	struct astro_softc *sc = v;

	printf("load_raw\n");

	return (bus_dmamap_load_raw(sc->sc_dmat, map, segs, nsegs, size, flags));
}

void
iommu_dvmamap_unload(void *v, bus_dmamap_t map)
{
	struct astro_softc *sc = v;
	struct iommu_map_state *ims = map->_dm_cookie;
	struct iommu_page_map *ipm = &ims->ims_map;
	struct iommu_page_entry *e;
	int err, i;

	/* Remove the IOMMU entries. */
	for (i = 0, e = ipm->ipm_map; i < ipm->ipm_pagecnt; ++i, ++e)
		iommu_remove(sc, e->ipe_dva);

	/* Clear the iomap. */
	iommu_iomap_clear_pages(ims);

	bus_dmamap_unload(sc->sc_dmat, map);

	mtx_enter(&sc->sc_dvmamtx);
	err = extent_free(sc->sc_dvmamap, ims->ims_dvmastart,
	    ims->ims_dvmasize, EX_NOWAIT);
	ims->ims_dvmastart = 0;
	ims->ims_dvmasize = 0;
	mtx_leave(&sc->sc_dvmamtx);
	if (err)
		printf("warning: %ld of DVMA space lost\n", ims->ims_dvmasize);
}

void
iommu_dvmamap_sync(void *v, bus_dmamap_t map, bus_addr_t off,
    bus_size_t len, int ops)
{
	/* Nothing to do; DMA is cache-coherent. */
}

int
iommu_dvmamem_alloc(void *v, bus_size_t size, bus_size_t alignment,
    bus_size_t boundary, bus_dma_segment_t *segs,
    int nsegs, int *rsegs, int flags)
{
	struct astro_softc *sc = v;

	return (bus_dmamem_alloc(sc->sc_dmat, size, alignment, boundary,
	    segs, nsegs, rsegs, flags));
}

void
iommu_dvmamem_free(void *v, bus_dma_segment_t *segs, int nsegs)
{
	struct astro_softc *sc = v;

	bus_dmamem_free(sc->sc_dmat, segs, nsegs);
}

int
iommu_dvmamem_map(void *v, bus_dma_segment_t *segs, int nsegs, size_t size,
    caddr_t *kvap, int flags)
{
	struct astro_softc *sc = v;

	return (bus_dmamem_map(sc->sc_dmat, segs, nsegs, size, kvap, flags));
}

void
iommu_dvmamem_unmap(void *v, caddr_t kva, size_t size)
{
	struct astro_softc *sc = v;

	bus_dmamem_unmap(sc->sc_dmat, kva, size);
}

paddr_t
iommu_dvmamem_mmap(void *v, bus_dma_segment_t *segs, int nsegs, off_t off,
    int prot, int flags)
{
	struct astro_softc *sc = v;

	return (bus_dmamem_mmap(sc->sc_dmat, segs, nsegs, off, prot, flags));
}

/*
 * Utility function used by splay tree to order page entries by pa.
 */
static inline int
iomap_compare(struct iommu_page_entry *a, struct iommu_page_entry *b)
{
	return ((a->ipe_pa > b->ipe_pa) ? 1 :
		(a->ipe_pa < b->ipe_pa) ? -1 : 0);
}

SPLAY_PROTOTYPE(iommu_page_tree, iommu_page_entry, ipe_node, iomap_compare);

SPLAY_GENERATE(iommu_page_tree, iommu_page_entry, ipe_node, iomap_compare);

/*
 * Create a new iomap.
 */
struct iommu_map_state *
iommu_iomap_create(int n)
{
	struct iommu_map_state *ims;

	/* Safety for heavily fragmented data, such as mbufs */
	n += 4;
	if (n < 16)
		n = 16;

	ims = malloc(sizeof(*ims) + (n - 1) * sizeof(ims->ims_map.ipm_map[0]),
	    M_DEVBUF, M_NOWAIT | M_ZERO);
	if (ims == NULL)
		return (NULL);

	/* Initialize the map. */
	ims->ims_map.ipm_maxpage = n;
	SPLAY_INIT(&ims->ims_map.ipm_tree);

	return (ims);
}

/*
 * Destroy an iomap.
 */
void
iommu_iomap_destroy(struct iommu_map_state *ims)
{
#ifdef DIAGNOSTIC
	if (ims->ims_map.ipm_pagecnt > 0)
		printf("iommu_iomap_destroy: %d page entries in use\n",
		    ims->ims_map.ipm_pagecnt);
#endif

	free(ims, M_DEVBUF, 0);
}

/*
 * Insert a pa entry in the iomap.
 */
int
iommu_iomap_insert_page(struct iommu_map_state *ims, vaddr_t va, paddr_t pa)
{
	struct iommu_page_map *ipm = &ims->ims_map;
	struct iommu_page_entry *e;

	if (ipm->ipm_pagecnt >= ipm->ipm_maxpage) {
		struct iommu_page_entry ipe;

		ipe.ipe_pa = pa;
		if (SPLAY_FIND(iommu_page_tree, &ipm->ipm_tree, &ipe))
			return (0);

		return (ENOMEM);
	}

	e = &ipm->ipm_map[ipm->ipm_pagecnt];

	e->ipe_pa = pa;
	e->ipe_va = va;
	e->ipe_dva = 0;

	e = SPLAY_INSERT(iommu_page_tree, &ipm->ipm_tree, e);

	/* Duplicates are okay, but only count them once. */
	if (e)
		return (0);

	++ipm->ipm_pagecnt;

	return (0);
}

/*
 * Translate a physical address (pa) into a DVMA address.
 */
bus_addr_t
iommu_iomap_translate(struct iommu_map_state *ims, paddr_t pa)
{
	struct iommu_page_map *ipm = &ims->ims_map;
	struct iommu_page_entry *e;
	struct iommu_page_entry pe;
	paddr_t offset = pa & PAGE_MASK;

	pe.ipe_pa = trunc_page(pa);

	e = SPLAY_FIND(iommu_page_tree, &ipm->ipm_tree, &pe);

	if (e == NULL) {
		panic("couldn't find pa %lx", pa);
		return 0;
	}

	return (e->ipe_dva | offset);
}

/*
 * Clear the iomap table and tree.
 */
void
iommu_iomap_clear_pages(struct iommu_map_state *ims)
{
        ims->ims_map.ipm_pagecnt = 0;
        SPLAY_INIT(&ims->ims_map.ipm_tree);
}

/*
 * Add an entry to the IOMMU table.
 */
void
iommu_enter(struct astro_softc *sc, bus_addr_t dva, paddr_t pa, vaddr_t va,
    int flags)
{
	volatile u_int64_t *tte_ptr = &sc->sc_pdir[dva >> PAGE_SHIFT];
	u_int64_t tte;
	u_int32_t ci;

#ifdef DEBUG
	printf("iommu_enter dva %lx, pa %lx, va %lx\n", dva, pa, va);
#endif

#ifdef DIAGNOSTIC
	tte = letoh64(*tte_ptr);

	if (tte & IOTTE_V) {
		printf("Overwriting valid tte entry (dva %lx pa %lx "
		    "&tte %p tte %llx)\n", dva, pa, tte_ptr, tte);
		extent_print(sc->sc_dvmamap);
		panic("IOMMU overwrite");
	}
#endif

	mtsp(HPPA_SID_KERNEL, 1);
	__asm volatile("lci 0(%%sr1, %1), %0" : "=r" (ci) : "r" (va));

	tte = (pa & IOTTE_PAMASK) | ((ci >> 12) & IOTTE_CI);
	tte |= IOTTE_V;

	*tte_ptr = htole64(tte);
	__asm volatile("fdc 0(%%sr1, %0)\n\tsync" : : "r" (tte_ptr));
}

/*
 * Remove an entry from the IOMMU table.
 */
void
iommu_remove(struct astro_softc *sc, bus_addr_t dva)
{
	volatile struct astro_regs *r = sc->sc_regs;
	u_int64_t *tte_ptr = &sc->sc_pdir[dva >> PAGE_SHIFT];
	u_int64_t tte;

#ifdef DIAGNOSTIC
	if (dva != trunc_page(dva)) {
		printf("iommu_remove: unaligned dva: %lx\n", dva);
		dva = trunc_page(dva);
	}
#endif

	tte = letoh64(*tte_ptr);

#ifdef DIAGNOSTIC
	if ((tte & IOTTE_V) == 0) {
		printf("Removing invalid tte entry (dva %lx &tte %p "
		    "tte %llx)\n", dva, tte_ptr, tte);
		extent_print(sc->sc_dvmamap);
		panic("IOMMU remove overwrite");
	}
#endif

	*tte_ptr = htole64(tte & ~IOTTE_V);

	/* Flush IOMMU. */
	r->tlb_pcom = htole32(dva | PAGE_SHIFT);
}


code:
/*	$OpenBSD: clock.c,v 1.29 2014/03/29 18:09:29 guenther Exp $	*/

/*
 * Copyright (c) 1998-2003 Michael Shalayeff
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
 * THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/timetc.h>

#include <dev/clock_subr.h>

#include <machine/pdc.h>
#include <machine/iomod.h>
#include <machine/psl.h>
#include <machine/intr.h>
#include <machine/reg.h>
#include <machine/cpufunc.h>
#include <machine/autoconf.h>

u_long	cpu_hzticks;
int	timeset;

int	cpu_hardclock(void *);
u_int	itmr_get_timecount(struct timecounter *);

struct timecounter itmr_timecounter = {
	itmr_get_timecount, NULL, 0xffffffff, 0, "itmr", 0, NULL
};

void
cpu_initclocks(void)
{
	struct cpu_info *ci = curcpu();
	u_long __itmr;

	cpu_hzticks = (PAGE0->mem_10msec * 100) / hz;

	itmr_timecounter.tc_frequency = PAGE0->mem_10msec * 100;
	tc_init(&itmr_timecounter);

	mfctl(CR_ITMR, __itmr);
	ci->ci_itmr = __itmr;
	__itmr += cpu_hzticks;
	mtctl(__itmr, CR_ITMR);
}

int
cpu_hardclock(void *v)
{
	struct cpu_info *ci = curcpu();
	u_long __itmr, delta, eta;
	int wrap;
	register_t eiem;

	/*
	 * Invoke hardclock as many times as there has been cpu_hzticks
	 * ticks since the last interrupt.
	 */
	for (;;) {
		mfctl(CR_ITMR, __itmr);
		delta = __itmr - ci->ci_itmr;
		if (delta >= cpu_hzticks) {
			hardclock(v);
			ci->ci_itmr += cpu_hzticks;
		} else
			break;
	}

	/*
	 * Program the next clock interrupt, making sure it will
	 * indeed happen in the future. This is done with interrupts
	 * disabled to avoid a possible race.
	 */
	eta = ci->ci_itmr + cpu_hzticks;
	wrap = eta < ci->ci_itmr;	/* watch out for a wraparound */
	__asm volatile("mfctl	%%cr15, %0": "=r" (eiem));
	__asm volatile("mtctl	%r0, %cr15");
	mtctl(eta, CR_ITMR);
	mfctl(CR_ITMR, __itmr);
	/*
	 * If we were close enough to the next tick interrupt
	 * value, by the time we have programmed itmr, it might
	 * have passed the value, which would cause a complete
	 * cycle until the next interrupt occurs. On slow
	 * models, this would be a disaster (a complete cycle
	 * taking over two minutes on a 715/33).
	 *
	 * We expect that it will only be necessary to postpone
	 * the interrupt once. Thus, there are two cases:
	 * - We are expecting a wraparound: eta < cpu_itmr.
	 *   itmr is in tracks if either >= cpu_itmr or < eta.
	 * - We are not wrapping: eta > cpu_itmr.
	 *   itmr is in tracks if >= cpu_itmr and < eta (we need
	 *   to keep the >= cpu_itmr test because itmr might wrap
	 *   before eta does).
	 */
	if ((wrap && !(eta > __itmr || __itmr >= ci->ci_itmr)) ||
	    (!wrap && !(eta > __itmr && __itmr >= ci->ci_itmr))) {
		eta += cpu_hzticks;
		mtctl(eta, CR_ITMR);
	}
	__asm volatile("mtctl	%0, %%cr15":: "r" (eiem));

	return (1);
}

/*
 * initialize the system time from the time of day clock
 */
void
inittodr(time_t t)
{
	struct pdc_tod tod PDC_ALIGNMENT;
	int 	error, tbad = 0;
	struct timespec ts;

	if (t < 12*SECYR) {
		printf ("WARNING: preposterous time in file system");
		t = 6*SECYR + 186*SECDAY + SECDAY/2;
		tbad = 1;
	}

	if ((error = pdc_call((iodcio_t)pdc,
	    1, PDC_TOD, PDC_TOD_READ, &tod, 0, 0, 0, 0, 0)))
		printf("clock: failed to fetch (%d)\n", error);

	ts.tv_sec = tod.sec;
	ts.tv_nsec = tod.usec * 1000;
	tc_setclock(&ts);
	timeset = 1;

	if (!tbad) {
		u_long	dt;

		dt = (tod.sec < t)?  t - tod.sec : tod.sec - t;

		if (dt < 2 * SECDAY)
			return;
		printf("WARNING: clock %s %ld days",
		    tod.sec < t? "lost" : "gained", dt / SECDAY);
	}

	printf (" -- CHECK AND RESET THE DATE!\n");
}

/*
 * reset the time of day clock to the value in time
 */
void
resettodr()
{
	struct timeval tv;
	int error;

	/*
	 * We might have been called by boot() due to a crash early
	 * on.  Don't reset the clock chip in this case.
	 */
	if (!timeset)
		return;

	microtime(&tv);

	if ((error = pdc_call((iodcio_t)pdc, 1, PDC_TOD, PDC_TOD_WRITE,
	    tv.tv_sec, tv.tv_usec)))
		printf("clock: failed to save (%d)\n", error);
}

void
setstatclockrate(int newhz)
{
	/* nothing we can do */
}

u_int
itmr_get_timecount(struct timecounter *tc)
{
	u_long __itmr;

	mfctl(CR_ITMR, __itmr);
	return (__itmr);
}

license: unknown


code:
/*	$OpenBSD: com_dino.c,v 1.4 2007/07/15 19:25:49 kettenis Exp $	*/

/*
 * Copyright (c) 2004 Michael Shalayeff
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
 * THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <sys/tty.h>

#include <machine/bus.h>
#include <machine/intr.h>
#include <machine/iomod.h>
#include <machine/autoconf.h>

#include <dev/ic/comreg.h>
#include <dev/ic/comvar.h>

#include <hppa/dev/cpudevs.h>

void *dino_intr_establish(void *sc, int irq, int pri,
    int (*handler)(void *v), void *arg, const char *name);

#define	COM_DINO_FREQ	7272700

struct com_dino_regs {
	u_int8_t	reset;
	u_int8_t	pad0[3];
	u_int8_t	test;
#define	COM_DINO_PAR_LOOP	0x01
#define	COM_DINO_CLK_SEL	0x02
	u_int8_t	pad1[3];
	u_int32_t	iodc;
	u_int8_t	pad2[0x54];
	u_int8_t	dither;
};

int	com_dino_match(struct device *, void *, void *);
void	com_dino_attach(struct device *, struct device *, void *);

struct cfattach com_dino_ca = {
	sizeof(struct com_softc), com_dino_match, com_dino_attach
};

int
com_dino_match(parent, match, aux)
	struct device *parent;
	void *match, *aux;
{
	struct confargs *ca = aux;

	if (ca->ca_type.iodc_type != HPPA_TYPE_FIO ||
	    ca->ca_type.iodc_sv_model != HPPA_FIO_GRS232)
		return (0);

	return (1);
	/* HOZER comprobe1(ca->ca_iot, ca->ca_hpa + IOMOD_DEVOFFSET); */
}

void
com_dino_attach(parent, self, aux)
	struct device *parent, *self;
	void *aux;
{
	struct com_softc *sc = (void *)self;
	struct confargs *ca = aux;
	struct com_dino_regs *regs = (struct com_dino_regs *)ca->ca_hpa;

	sc->sc_iot = ca->ca_iot;
	sc->sc_iobase = (bus_addr_t)ca->ca_hpa + IOMOD_DEVOFFSET;

	if (bus_space_map(sc->sc_iot, sc->sc_iobase, COM_NPORTS,
	    0, &sc->sc_ioh)) {
		printf(": cannot map io space\n");
		return;
	}

	if (PAGE0->mem_cons.pz_class == PCL_DUPLEX &&
	    PAGE0->mem_cons.pz_hpa == ca->ca_hpa) {
		bus_space_unmap(sc->sc_iot, sc->sc_ioh, COM_NPORTS);
		comcnattach(sc->sc_iot, sc->sc_iobase, comdefaultrate,
		    COM_DINO_FREQ, comconscflag);
	}

	/* select clock freq */
	regs->test = COM_DINO_CLK_SEL;
	sc->sc_frequency = COM_DINO_FREQ;

	com_attach_subr(sc);

	sc->sc_ih = dino_intr_establish(parent, ca->ca_irq, IPL_TTY,
	    comintr, sc, sc->sc_dev.dv_xname);
}


code:
/*	$OpenBSD: com_ssio.c,v 1.2 2007/06/24 16:28:39 kettenis Exp $	*/

/*
 * Copyright (c) 2007 Mark Kettenis
 *
 * Permission to use, copy, modify, and distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <sys/tty.h>

#include <machine/bus.h>
#include <machine/iomod.h>

#include <dev/ic/comreg.h>
#include <dev/ic/comvar.h>

#include <hppa/dev/ssiovar.h>

#define COM_SSIO_FREQ	1843200

int com_ssio_match(struct device *, void *, void *);
void com_ssio_attach(struct device *, struct device *, void *);

struct cfattach com_ssio_ca = {
	sizeof(struct com_softc), com_ssio_match, com_ssio_attach
};

int
com_ssio_match(struct device *parent, void *match, void *aux)
{
	struct cfdata *cf = match;
	struct ssio_attach_args *saa = aux;

	if (strcmp(saa->saa_name, "com") != 0)
		return (0);

	/* Check locators. */
	if (cf->ssiocf_irq != SSIO_UNK_IRQ && cf->ssiocf_irq != saa->saa_irq)
		return (0);

	return (1);
}

void
com_ssio_attach(struct device *parent, struct device *self, void *aux)
{
	struct com_softc *sc = (void *)self;
	struct ssio_attach_args *saa = aux;

	sc->sc_iot = saa->saa_iot;
	sc->sc_iobase = saa->saa_iobase;
	if (bus_space_map(sc->sc_iot, sc->sc_iobase, COM_NPORTS,
	    0, &sc->sc_ioh)) {
		printf(": cannot map io space\n");
		return;
	}

	if (PAGE0->mem_cons.pz_class == PCL_DUPLEX &&
	    PAGE0->mem_cons.pz_hpa == sc->sc_ioh) {
		bus_space_unmap(sc->sc_iot, sc->sc_ioh, COM_NPORTS);
		comcnattach(sc->sc_iot, sc->sc_iobase, comdefaultrate,
		    COM_SSIO_FREQ, comconscflag);
	}

	sc->sc_frequency = COM_SSIO_FREQ;
	com_attach_subr(sc);

	sc->sc_ih = ssio_intr_establish(IPL_TTY, saa->saa_irq,
	    comintr, sc, sc->sc_dev.dv_xname);
}


code:
/*	$OpenBSD: cpu.c,v 1.41 2014/01/19 12:45:35 deraadt Exp $	*/

/*
 * Copyright (c) 1998-2003 Michael Shalayeff
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
 * THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <sys/proc.h>
#include <sys/reboot.h>
#include <dev/rndvar.h>

#include <uvm/uvm_extern.h>

#include <machine/cpufunc.h>
#include <machine/pdc.h>
#include <machine/reg.h>
#include <machine/iomod.h>
#include <machine/autoconf.h>

#include <hppa/dev/cpudevs.h>

struct cpu_softc {
	struct  device sc_dev;
};

#ifdef MULTIPROCESSOR
struct cpu_info *cpu_hatch_info;
static volatile int start_secondary_cpu;
#endif

int	cpumatch(struct device *, void *, void *);
void	cpuattach(struct device *, struct device *, void *);

struct cfattach cpu_ca = {
	sizeof(struct cpu_softc), cpumatch, cpuattach
};

struct cfdriver cpu_cd = {
	NULL, "cpu", DV_DULL
};

int
cpumatch(struct device *parent, void *cfdata, void *aux)
{
	struct cfdata *cf = cfdata;
	struct confargs *ca = aux;

	/* probe any 1.0, 1.1 or 2.0 */
	if (ca->ca_type.iodc_type != HPPA_TYPE_NPROC ||
	    ca->ca_type.iodc_sv_model != HPPA_NPROC_HPPA)
		return 0;

	if (cf->cf_unit >= MAXCPUS)
		return 0;

	return 1;
}

void
cpuattach(struct device *parent, struct device *self, void *aux)
{
	/* machdep.c */
	extern struct pdc_model pdc_model;
	extern struct pdc_cache pdc_cache;
	extern struct pdc_btlb pdc_btlb;
	extern u_int cpu_ticksnum, cpu_ticksdenom;
	extern u_int fpu_enable;
	/* clock.c */
	extern int cpu_hardclock(void *);
	/* ipi.c */
	extern int hppa_ipi_intr(void *);

	struct confargs *ca = (struct confargs *)aux;
	struct cpu_info *ci;
	u_int mhz = 100 * cpu_ticksnum / cpu_ticksdenom;
	int cpuno = self->dv_unit;
	struct pglist mlist;
	struct vm_page *m;
	const char *p;
	int error;

	ci = &cpu_info[cpuno];
	ci->ci_dev = self;
	ci->ci_cpuid = cpuno;
	ci->ci_hpa = ca->ca_hpa;

	/* Allocate stack for spin up and FPU emulation. */
	TAILQ_INIT(&mlist);
	error = uvm_pglistalloc(PAGE_SIZE, 0, -1L, 0, 0, &mlist, 1,
	    UVM_PLA_NOWAIT);
	if (error) {
		printf(": unable to allocate CPU stack!\n");
		return;
	}
	m = TAILQ_FIRST(&mlist);
	ci->ci_stack = VM_PAGE_TO_PHYS(m);

	printf (": %s ", cpu_typename);
	if (pdc_model.hvers) {
		static const char lvls[4][4] = { "0", "1", "1.5", "2" };

		printf("L%s-%c ", lvls[pdc_model.pa_lvl], "AB"[pdc_model.mc]);
	}

	printf ("%d", mhz / 100);
	if (mhz % 100 > 9)
		printf(".%02d", mhz % 100);
	printf("MHz");

	if (fpu_enable) {
		extern u_int fpu_version;
		u_int32_t ver[2];

		mtctl(fpu_enable, CR_CCR);
		__asm volatile(
		    "fstds   %%fr0,0(%0)\n\t"
		    "copr,0,0\n\t"
		    "fstds   %%fr0,0(%0)"
		    :: "r" (&ver) : "memory");
		mtctl(0, CR_CCR);
		fpu_version = HPPA_FPUVER(ver[0]);
		printf(", FPU %s rev %d",
		    hppa_mod_info(HPPA_TYPE_FPU, fpu_version >> 5),
		    fpu_version & 0x1f);
	}

	printf("\n%s: ", self->dv_xname);
	p = "";
	if (!pdc_cache.dc_conf.cc_sh) {
		printf("%uK(%db/l) Icache, ",
		    pdc_cache.ic_size / 1024, pdc_cache.ic_conf.cc_line * 16);
		p = "D";
	}

	printf("%uK(%db/l) wr-%s %scache, ",
	    pdc_cache.dc_size / 1024, pdc_cache.dc_conf.cc_line * 16,
	    pdc_cache.dc_conf.cc_wt? "thru" : "back", p);

	p = "";
	if (!pdc_cache.dt_conf.tc_sh) {
		printf("%u ITLB, ", pdc_cache.it_size);
		p = "D";
	}
	printf("%u %scoherent %sTLB",
	    pdc_cache.dt_size, pdc_cache.dt_conf.tc_cst? "" : "in", p);

	if (pdc_btlb.finfo.num_c)
		printf(", %u BTLB", pdc_btlb.finfo.num_c);
	else if (pdc_btlb.finfo.num_i || pdc_btlb.finfo.num_d)
		printf(", %u/%u D/I BTLBs",
		    pdc_btlb.finfo.num_i, pdc_btlb.finfo.num_d);

	cpu_intr_establish(IPL_CLOCK, 31, cpu_hardclock, NULL, "clock");
#ifdef MULTIPROCESSOR
	cpu_intr_establish(IPL_IPI, 30, hppa_ipi_intr, NULL, "ipi");
#endif

	printf("\n");
}

#ifdef MULTIPROCESSOR
void
cpu_boot_secondary_processors(void)
{
	struct cpu_info *ci;
	struct iomod *cpu;
	int i, j;

	/* Initialise primary CPU. */
	ci = curcpu();
	ci->ci_flags |= CPUF_RUNNING;
	hppa_ipi_init(ci);

	for (i = 0; i < HPPA_MAXCPUS; i++) {

		ci = &cpu_info[i];
		if (ci->ci_cpuid == 0)
			continue;

		ci->ci_randseed = (arc4random() & 0x7fffffff) + 1;

		sched_init_cpu(ci);

		/* Release the specified CPU by triggering an EIR{0}. */
		cpu_hatch_info = ci;
		cpu = (struct iomod *)(ci->ci_hpa);
		cpu->io_eir = 0;
		asm volatile ("sync" ::: "memory");

		/* Wait for CPU to wake up... */
		j = 0;
		while (!(ci->ci_flags & CPUF_RUNNING) && j++ < 10000)
			delay(1000);
		if (!(ci->ci_flags & CPUF_RUNNING))
			printf("failed to hatch cpu %i!\n", ci->ci_cpuid);
	}

	/* Release secondary CPUs. */
	start_secondary_cpu = 1;
	asm volatile ("sync" ::: "memory");
}

void
cpu_hw_init(void)
{
	struct cpu_info *ci = curcpu();

	/* Purge TLB and flush caches. */
	ptlball();
	ficacheall();
	fdcacheall();

	/* Enable address translations. */
	ci->ci_psw = PSL_I | PSL_Q | PSL_P | PSL_C | PSL_D;
	ci->ci_psw |= (cpu_info[0].ci_psw & PSL_O);
}

void
cpu_hatch(void)
{
	struct cpu_info *ci = curcpu();
	extern u_long cpu_hzticks;
	u_long itmr;
	int s;

	/* Initialise IPIs. */
	hppa_ipi_init(ci);

	/* Initialise clock. */
	mtctl((1U << 31), CR_EIRR);
	mfctl(CR_ITMR, itmr);
	ci->ci_itmr = itmr;
	itmr += cpu_hzticks;
	mtctl(itmr, CR_ITMR);
	ci->ci_mask |= (1U << 31);

	/* Enable interrupts. */
	mtctl(ci->ci_mask, CR_EIEM);

	ncpus++;
	ci->ci_flags |= CPUF_RUNNING;

	/* Wait for additional CPUs to spinup. */
	while (!start_secondary_cpu)
		;

	SCHED_LOCK(s);
	cpu_switchto(NULL, sched_chooseproc());
}

void
cpu_unidle(struct cpu_info *ci)
{
	if (ci != curcpu())
		hppa_ipi_send(ci, HPPA_IPI_NOP);
}
#endif

void
need_resched(struct cpu_info *ci)
{
	ci->ci_want_resched = 1;

	/* There's a risk we'll be called before the idle threads start */
	if (ci->ci_curproc) {
		setsoftast(ci->ci_curproc);
		cpu_unidle(ci);
	}
}


code:
$OpenBSD: cpudevs,v 1.44 2007/05/18 15:57:35 kettenis Exp $

/*
 * Copyright (c) 1998-2004 Michael Shalayeff
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
 * THE POSSIBILITY OF SUCH DAMAGE.
 */

type	nproc	0x00	native processor
type	memory	0x01	memory
type	bdma	0x02	Type-B DMA (NIO Transit, Parallel, ... )
type	bdirect	0x03	Type-B Direct (obsolete)
type	adma	0x04	Type-A DMA (NIO HPIB, LAN, ... )
type	adirect	0x05	Type-A Direct (RS232, HIL, ... )
type	other	0x06	other (obsolete)
type	bcport	0x07	Bus Converter Port
type	cio	0x08	CIO adapter
type	console	0x09	console
type	fio	0x0a	foreign I/O module
type	bha	0x0b	bus host adaptor
type	ioa	0x0c	IO Adapter
type	bridge	0x0d	Bus Bridge to Foreign Bus
type	fabric	0x0e	Fabric Components
#		0x0f	-
#		0x1e	reserved
type	faulty	0x1f	broken
#			pseudo-types
type	board	0x80	system board
type	cpu	0x81	CPU chips
type	fpu	0x82	FPU chips
type	bus	0x83	Main Busses

board	HP840		0x004	840/930 (Indigo)
board	HP825		0x008	825/925 (FireFox)
board	HP835		0x00a	83[45]/[69]35 (TopGun)
board	HP845		0x00b	845/645 (Technical ShoGun)
board	HP850		0x00C	850/950 (Cheetah)
board	HP949		0x00f	949 (Commercial ShoGun)

board	HP950S		0x080	950S (Cheetah)
board	HP855		0x081	855/955 (Jaguar)
board	HP860		0x082	860/960 (Cougar)
board	HP870		0x083	865/870/980 (Panther)

board	HP810		0x100	810 (Burgundy)
board	HP822		0x101	822/922 (SilverFox Low)
board	HP832		0x102	832/932 (SilverFox High)
board	HP808		0x103	808/815/920 (Lego, SilverLite)
board	HP842		0x104	842/948 (SilverBullet Low)
board	HP852		0x105	852/958 (SilverBullet High)
board	HPOBOE		0x106	(Oboe)

board	HPDRAGON	0x180	(Dragon)
board	HP890		0x181	890/990/992 (Chimera)
board	HP891		0x182	891/T500 (TNT 100)
board	HP892		0x183	892/T520 (TNT 120)
board	HP893_T540	0x184	893/T540/T600 (Jade 180 U)

board	HPHXPROC	0x1ff	Hitachi X Processor

board	HP720		0x200	720 (Cobra)
board	HP750_66	0x201	750/66 (Coral)
board	HP730_66	0x202	730/66 (King Cobra)
board	HP735_99	0x203	735/99 (Hardball)
board	HP755_99	0x204	755/99 (Coral II)
board	HP755_125	0x205	755/125 (Coral II)
#board	HP755_125E	0x205	755/125 (Snake Eagle, opt 91)
board	HP735_130	0x206	735/130 (Snake Cheetah)

board	HP817		0x280	817/827/957/957LX/FH20 (Nova Low)
board	HP837		0x281	837/847/857/967/967LX/FGHI30 (Nova High)
board	HP807		0x282	807/917/917LX/927/927LX/937/937LX/947/947LX/F10 (Nova8)
board	HP867		0x283	867/877/977/GHI40 (Nova64)
board	HP887T		0x284	887/897/987/GHI50 (TNova)
#board	HP		0x285	(TNova64)
#board	HP		0x286	(Hydra64 (Nova))
board	HP887		0x287	887/897/GHI70 (Hydra96 (Nova))
board	HP887T96	0x288	887/897/GHI60 (TNova96)

board	HP710		0x300	710/50 (Bushmaster)
board	HP705		0x302	705/35 (Flounder)

board	HP715_50	0x310	715/50 (Scorpio)
board	HP715_33	0x311	715/33 (Scorpio Jr.)
board	HP715S_50	0x312	715S/50 (Spider-50)
board	HP715S_33	0x313	715S/33 (Spider-33)
board	HP715T_50	0x314	715T/50 (Trailways-50)
board	HP715T_33	0x315	715T/33 (Trailways-33)
board	HP715_75	0x316	715/75 (Scorpio Sr.)
board	HP715_99	0x317	715/99 (Scorpio 100)
board	HP725_50	0x318	725/50 (Spectra)
board	HP725_75	0x319	725/75 (Spectra)
board	HP725_99	0x320	725/99 (Spectra)

board	HP745i_50	0x401	745i/747i/50 (Pace)
board	HP742i_50	0x402	742i/50 (Sidewinder)
board	HP747i_100	0x403	745i/747i/100 (Fast Pace)

board	HPE23		0x480	806/E23 (Orville)
board	HPE25		0x481	806/E25 (Wilbur)
board	HPE35		0x482	816/E35 (Wright Brothers 80)
board	HPE45		0x483	826/E45 (Wright Brothers 96)
board	HPD210		0x484	811/D210/D310 (UltraLight L 100)
board	HPD200		0x485	801/D200/D300 (UltraLight L 75)

board	HP778_B132L	0x501	778/B132L (Merlin L2 132)
board	HP778_B160L	0x502	778/B160L (Merlin L2 160)
board	HP778_B132LP	0x503	778/B132L+ (Merlin L2+ 132)
board	HP778_B180L	0x504	778/B180L+ (Merlin L2+ 180)
board	HP779_C132L	0x505	779/C132L (Raven L2 132)
board	HP779_C160L	0x506	779/C160L (Raven L2 160)
board	HP779_C180L	0x507	779/C180L (Raven L2 180)
board	HP779_C160L1	0x508	779/C160L (Raven L2 160)
board	HP712_132L2	0x509	712/132 (L2 Upgrade)
board	HP712_160L2	0x50a	712/160 (L2 Upgrade)
board	HP712_132L21	0x50b	712/132 (L2 Upgrade)
board	HP712_160L21	0x50c	712/160 (L2 Upgrade)
#board	HP		0x50d	(Rocky2 L2 120)
#board	HP		0x50e	(Rocky2 L2 150)
board	HP744_132L	0x50f	744/132L (Anole-132L)
board	HP744_165L	0x510	744/165L (Anole-165L)
#board	HPKIJI132	0x511	(Kiji L2 132)
board	HP803		0x512	803/D220 (UltraLight L2 132)
board	HP813		0x513	813/D320 (UltraLight L2 160)
board	HP778_B132	0x514	778/B132 (Merlin Jr. L2 132)
board	HP800_A132	0x515	800/A132 (Staccato L2 132)
board	HP800_A180C	0x516	800/A180C (Staccato L2 180)

board	HP809		0x580	809/K100 (KittyHawk DC2-100)
board	HP839		0x581	839/K210 (KittyHawk DC3-120)
board	HP829		0x582	829/K400 (KittyHawk DC3-100)
board	HP849		0x583	849/K410 (KittyHawk DC3-120)
board	HP770_J210XC	0x584	770/J210XC (LighteningHawk)
board	HP770_J200	0x585   770/J200 (SkyHawk 100)
board	HP770_J210	0x586   770/J210 (SkyHawk 120)
board	HP841		0x587	841/D210/D410 (UltraLight Proc 1-way T'120)
board	HP851		0x588	851/D210-2/D410-2 (UltraLight Proc 2-way T'120)
board	HP821_1		0x589	821/D200/D400 (UltraLight Proc 1-way T'100)
board	HP831		0x58a	831/D200-2/D400-2 (UltraLight Proc 2-way T'100)
board	HP819		0x58b	819/K200 (KittyHawk DC2 100)
board	HP859		0x58c	859/K220 (ThunderHawk DC3- 120 1M)
board	HP869		0x58d	869/K420 (ThunderHawk DC3 120 1M)
board	HP780_C110	0x58e   780/C110 (Raven 120 T')
board	HP804		0x58f	804/K450 (Mohawk 160 U 1M DC3)
board	HP889		0x590	889/K460 (Mohawk 180 U 1M DC3)
#board	HP889_1		0x591	889/K470 (Mohawk 200 U 1M DC3)
board	HP780_C100	0x592	780/C100 (Raven 100 T')
#board	HP		0x593	(FireHawk 160 U)
board	HP780_J282	0x594	780/J282 (FireHawk 180 U)
#board	HP		0x595	(FireHawk 220 U)
#board	HP		0x596	(FireHawk 240 U)
board	HP800V		0x597	800/V2200/V2500 (SPP2000)
board	HP780_C230	0x598	780/C230 (Raven U 230)
board	HP780_C240	0x599	780/C240 (Raven U 240)
#			0x59a		reserved
board	HP780_C160	0x59b	780/C160 (Raven U 160)
board	HP780_C180XP	0x59c	780/C180XP (Raven U 180)
board	HP780_C200	0x59d	780/C200 (Raven U 200)
#board	HP		0x59e	(ThunderHawk T' 120)
board	HP780_C180P	0x59f	780/C180+ (Raven U 180+)
board	HP841_1		0x5a0	841/D260/D360 (UltraLight 1-way T120 1MB)
board	HP851_1		0x5a1	851/D260/D360 (UltraLight 2-way T120 1MB)
board	HP861		0x5a2	861/D270/D370 (UltraLight 1-way U160 512K)
board	HP871		0x5a3	871/D270/D370 (UltraLight 2-way U160 512K)
board	HP802		0x5a4	802/K250 (MoHawk U160 1M DC3-)
board	HP879		0x5a5	879/K260 (MoHawk U180 1M DC3-)
#board	HP878?		0x5a6	878/K270 (MoHawk U200 1M DC3-)
#board	HP		0x5a7	(UltraLight 1-way U160 1M)
#board	HP		0x5a8	(UltraLight 2-way U160 1M)
board	HP810D		0x5a9	810/D380/R380 (UltraLight 1-way U180 1M)
board	HP820		0x5aa	820/D280 (UltraLight 2-way U180 1M)
#			0x5ab	obsolete
#			0x5ac	obsolete
#board	HP898?		0x5ad	898/K360 (BraveHawk 180 DC3-)
board	HP898		0x5ae	898/K370 (BraveHawk 200 DC3-)
#board	HP		0x5af	(BraveHawk 220 DC3-)
#board	HP899?		0x5b0	899/K560 (BraveHawk 180 DC3)
board	HP899		0x5b1	899/K570 (BraveHawk 200 DC3)
#board	HP		0x5b2	(BraveHawk 220 DC3)
#board	HP		0x5b3	(FireHawk 200)
board	HP800V2		0x5b4	800/V2500 (SPP2500)
board	HP782_J2240	0x5b5	782/J2240 (SummitHawk U+)
board	HP800K		0x5b6	800/K580 (DragonHawk U+ 240 DC3)
#board	HP800K?		0x5b7	800/K380 (DragonHawk U+ 240 DC3-)
#board			0x5b8	SPP2250 240MHz processor
board	HP821		0x5b9	821/D350/R350 (UltraLight 1w U+/240)
board	HP800D		0x5ba	800/D390/R390 (UltraLight 2w U+/240)
board	HP785_C3000	0x5bb	785/C3000 (AllegroHigh W)
board	HP785_B1000	0x5bc	785/B1000 (AllegroLow W)
board	HP785_J5000	0x5bd	785/J5000 (Forte W 2w)
board	HP800_N400036	0x5be	800/N4000-36/rp7400 (Prelude W)
board	HP785_J7000	0x5bf	785/J7000 (Forte W 4w)
#board			0x5c0	(M2250)
#board			0x5c1	(M2500)
#board			0x5c2	(Sonata 440)
#board			0x5c3	(Sonata 360)
board	HP800_L200044	0x5c4	800/L2000-44/rp5450 (Rhapsody 440)
board	HP800_L200036	0x5c5	800/L2000-36/rp5450 (Rhapsody 360)
board	HP785_C360	0x5c6	780/C360 (Raven W 360)
#board			0x5c7	(Halftone W 440)
#board			0x5c8	(Lego 360)
board	HP800_L100044	0x5c9	800/L1000-44/rp5400 (Rhapsody DC-440)
board	HP800_L100036	0x5ca	800/L1000-36/rp5400 (Rhapsody DC-360)
board	HP897_A50044	0x5cb	897/A500-44/rp2450 (Crescendo 440)
board	HP800_N400044	0x5cc	800/N4000-44/rp7400 (Prelude W 440)
#board			0x5cd	SPP2600
#board			0x5ce	M2600
board	HP785_C3600	0x5cf	785/C3600 (Allegro)
board	HP786_B2000	0x5d0	786/B2000 (Kazoo W+)
board	HP785_J5600	0x5d1	785/J5600 (Forte W+ 2w)
board	HP785_J7600	0x5d2	785/J7600 (Forte W+ 4w)
board	HP800_N400055	0x5d3	800/N4000-55/rp7400 (Prelude W+ 550)
board	HP785_J6000	0x5d4	785/J6000 (Duet W+)
board	HP897_A5005X	0x5d5	897/A500-5X/rp2450 (Crescendo 550)
board	HP897_A40044	0x5d6	897/A400-44/rp2400 (Crescendo 440)
board	HP800_N40005X	0x5d7	800/N4000-5X/rp7410 (Keystone W+ 550)
board	HP800_L150044	0x5d8	800/L1500-44/rp5430 (Rhapsody wave 2 W+)
board	HP800_L150036	0x5d9	800/L1500-36/rp5430 (Rhapsody wave 2 W+)
#board			0x5da	(Marcato W+ DC-)
board	HP800_L30005X	0x5db	800/L3000-5X/rp5470 (Marcato W+)
board	HP785_C3700	0x5dc	785/C3700
board	HP785_J6700	0x5dd	785/J6700 (Duet W2)
board	HP785_B2600	0x5de	785/B2600 (Piccolo W+)
#board	HP		0x5df	(Cantata W2)
#board	HP		0x5e0	(Cantata DC- W2)
board	HP897_A4006X	0x5e1	897/A400-6X/rp2430 (Crescendo DC-W2)
board	HP897_A5006X	0x5e2	897/A500-6X/rp2470 (Crescendo 650 W2)
board	HP897_A5007X	0x5e3	897/A500-7X/rp2470 (Crescendo 750 W2)
board	HP800_N40007X	0x5e4	800/N4000-7X/rp7410 (Keystone/Matterhorn W2 750)
#board	HP		0x5e5	(PowerBar W+)
board	HP800_N40006X	0x5e6	800/N4000-6X/rp7410 (Keystone/Matterhorn W2 650)
#board			0x5e7	(Caribe W2 750)
#board			0x5e8	(Pikes Peak W2)

board	HITACHIW	0x5ff	(Hitachi W)

board	HP785_C8000	0x89c	785/C8000

board	HP712_60	0x600	712/60 (Gecko)
board	HP712_80	0x601	712/80 (King Gecko)
board	HP712_100	0x602	712/100 (King Gecko)
board	HP743i_64	0x603	743i/64 (Anole-64)
board	HP743i_100	0x604	743i/100 (Anole-100)
board	HP712_120	0x605	712/120 (King Gecko)
#board	HP		0x606	(Gila 80)
#board	HP		0x607	(Gila 100)
#board	HP		0x608	(Gila 120)
board	HP715_80	0x609	715/80 (Scorpio-L)
board	HP715_64	0x60A	715/64 (Mirage Jr.)
board	HP715_100	0x60B	715/100 (Mirage Sr.)
board	HP715_100XC	0x60C	715/100XC (Turnip)
board	HP725_100	0x60D	725/100 (Electra)
board	HP725_120	0x60E	725/120 (Electra)
board	HP715_100L	0x610	715/100L (Scorpio-L)
board	HP715_120L	0x611	715/120L (Scorpio-L)
board	HP725_80L	0x612	725/80L (Spectra-L)
board	HP725_100L	0x613	725/100L (Spectra-L)
board	HP725_120L	0x614	725/120L (Spectra-L)
#board	HP		0x615	/100 (Piranha 100)
#board	HP		0x616	/120 (Piranha 120)
board	HP743_50	0x617	743/50 (Jason)
board	HP743_100	0x618	743/100 (Jason)
board	HP715_80M	0x619	715/80 (Mirage)
board	HP811		0x61a	811/DX5 (SAIC L-80)
board	HP801		0x61b	801/DX0 (Rocky1 L-80)
board	HP743T		0x61c	743T (Anole T)

board	HITACHIT80	0x67e	(Hitachi Tiny 80)
board	HITACHIT64	0x67f	(Hitachi Tiny 64)

board	NEC		0x700	(NEC Aska)

# IODC_HVERSION[0..4]
bus	MID_BUS	0	MID_BUS
bus	SMB	1	SMB
bus	HPPB	2	HP-PB
bus	SUMMIT	3	Summit
bus	VVSC	4	Viper-VSC
bus	VHPPB	5	Viper-HPPB
bus	K9KSC	6	K9-KSC
bus	SPSSC	7	Spider-SSC
bus	STSSC	8	Stiletto-SSC
bus	GSCHPPB	9	GSC-HPPB
bus	GSCHSC	10	GSC+(HSC)
bus	RUNWAY	11	Runway
bus	GSC	12	GSC
bus	GSCP	13	GSC++
bus	NECSB	14	NEC System Bus
bus	ROPES	15	Ropes
bus	MERCED	16	Merced

cpu	SOFTEMU	0x01	Software Emulation
#cpu	PCXS	0x02	PCXS (Cheetah)
#cpu	PCXT	0x09	PCXT (Thunderbird)
#cpu	HARP	0x0a	HARP-I
cpu	PCXT2	0x0b	PCXT' (Thunderbird')
#cpu	PA50	0x0c	PA-50 (Hitachi)
cpu	PCXL	0x0d	PCXL (Hummingbird)
cpu	PCXU	0x0e	PCXU (Onyx)
cpu	PCXL2	0x0f	PCXL2 (Velociraptor)
cpu	PCXUP	0x10	PCXU+ (Vulcan)
cpu	PCXW	0x11	PCXW (Vulcan)
#cpu	PCXWP	0x??	PCXW+ (Landshark)
cpu	PCXW2	0x13	PCXW2 (Piranha)
#cpu	PCXM	0x??	Mako
#cpu	PCXM2	0x??	Shortfin

fpu	SOFTEMU	0x01	Software Emulation
fpu	INDIGO	0x02	Indigo
fpu	TYCO	0x03	Sterling I MIU (TYCO)
fpu	ROC	0x04	Sterling I MIU (ROC w/Weitek)
fpu	FPCW	0x06	FPC (NMOS-III w/Weitek)
fpu	FPCB	0x07	FPC (NMOS-III w/Bit)
fpu	PCXS	0x08	PCXS (Timex-II)
fpu	PCXT	0x09	PCXT (Rolex - CMOS-26B)
fpu	HARP	0x0a	HARP-I
fpu	PCXT2	0x0b	PCXT' (Tornado)
fpu	PA50	0x0c	PA-50 (Hitachi)
fpu	PCXL	0x0d	PCXL (CMOS-26B)
fpu	PCXU	0x0e	PCXU/PCXU+
fpu	VR	0x0f	VR
fpu	PCXW	0x10	PCXW
fpu	PCXW2	0x13	PCXW2

nproc	HPPA	4	PA-RISC

memory	ARCH	0x008	architected memory module
memory	PDEP	0x009	pdep memory module

bdma	PARALLEL	0x018	Parallel I/O
bdma	PRDB		0x019	Parallel RDB
bdma	MIDBUSPSI	0x020	MID_BUS PSI
bdma	HPPBTPSI	0x02f	HP-PB Transit PSI
bdma	HPPBT8023	0x051	HP-PB Transit 802.3
bdma	HPPBLANCON	0x052	Miura LAN/Console (J2146A)
bdma	HPPB8024	0x058	HP-PB Transit 802.4
bdma	LANCONS		0x060	LAN/Console
bdma	EXERCISER	0x094	GSC+ Exerciser
bdma	HPPBHFI		0x100	HP-PB HF Interface

#bdirect

adma	SCSI	0x039	SCSI
adma	FWSCSI0	0x03b	Wizard FW SCSI
adma	HPIB	0x040	HP-IB
adma	HPPBFL	0x041	HP-PB HP-FL
adma	HPPBIB	0x042	HP-PB LoQuix HP-IB
adma	HPPBCL	0x043	HP-PB Crypt LoQuix
adma	HPPBGPS	0x044	HP-PB Shazam GPIO
adma	HPPBGPL	0x045	HP-PB LoQuix GPIO
adma	2X25	0x046	2-Port X.25 NIO_ACC
adma	4X25	0x047	4-Port X.25 NIO_ACC
adma	NIMBFB	0x04a	Nimbus Frame Buffer
adma	NIMBCL	0x04b	Nimbus Control
adma	MRTI	0x04c	Martian RTI
adma	ACCMUX	0x04d	ACC Mux
adma	L8023	0x050	Lanbrusca 802.3
adma	LQFDDI	0x056	HP-PB LoQuix FDDI
adma	LQFDDI1	0x057	HP-PB LoQuix FDDI (28670A)
adma	GTR	0x05e	TI TokenRing
adma	FWSCSI	0x089	FW SCSI
adma	NETFC	0x091	Net FC
adma	YATM	0x092	GSC+ YLIASTER ATM
adma	MYRI	0x095	Hamlyn GSC+ Network Card
adma	LFEMU	0x098	Lo-fat Emulator
adma	VATM	0x09a	GSC+ Venus ATM
adma	HSCPCI	0x09d	HP HSC-PCI Cards
adma	ATMGSC	0x09e	Alaxis GSC+ ATM
adma	SHUSB	0x09f	SummitHawk 230 USB
adma	SHFETH	0x0a0	SummitHawk 230 100BaseT
adma	MASSFC	0x0a7	Add-on mass FC
adma	IPFC	0x380	Interphase NIO-FC
adma	IPATM	0x381	Interphase NIO-ATM
adma	IP100T	0x382	Interphase NIO-100BaseT
adma	IPNIOVG	0x383	Interphase NIO-100VG

adirect	APMUX	0x00d	AP/MUX
adirect	RS232	0x00e	RS-232
adirect	PEACOCK	0x00f	Peacock Graphics
adirect	HIL	0x014	HIL
adirect	LEONARDO 0x015	Leonardo
adirect	HRM	0x016	HP-PB HRM
adirect	HRC	0x017	HP-PB HRC
adirect	LPT	0x03a	Centronics interface
adirect	ATTDK	0x04e	AT&T DataKit
adirect	HPIB	0x09b	Test&Meas GSC HPIB
adirect	ROCKYKBD 0x0a8	Rocky2 Front Keyboard
adirect	HICONS	0x101	Hitachi Console Module
adirect	HIBOOT	0x102	Hitachi Boot Module

other	MIDBVM	0x030	MID_BUS Verification Master
other	MIDBVS	0x034	MID_BUS Verification Slave
other	MIDBEDU	0x038	MID_BUS Verification EDU
other	SPECFB	0x048	Spectograph frame buffer
other	SPECCTL	0x049	Spectograph control

bcport	PHANTOM	0x000	Phantom Port
bcport	PORT	0x00c	Bus Converter Port

cio	CIO	0x010	CIO

console	CHEETAH	0x01c	Cheetah Console
console	NULL	0x01f	Jason/Anole Null Console

fio	A_X25	0x02e	Armyknife Optional X.25
fio	8x25	0x04f	8-Port X.25 EISA-ACC
fio	SCSI	0x071	NCR 53C700 SCSI
fio	LAN	0x072	Core LAN
fio	HIL	0x073	Core HIL
fio	CENT	0x074	Core Centronics
fio	RS232	0x075	Core RS-232C
fio	SGC	0x077	SGC Graphics
fio	A1	0x07a	Core audio (int.)
fio	A2NB	0x07b	Advanced audio (ext.)
fio	FWSCSI	0x07c	NCR 53C720 FW-SCSI
fio	FDDI	0x07d	Core FDDI
fio	A1NB	0x07e	Core audio (ext.)
fio	A2	0x07f	Advanced audio (int.)
fio	HPIB	0x080	Core HPIB
fio	TR9000	0x086	GSC IBM TokenRing
fio	VMENET	0x088	VME Networking
fio	BOOTROM	0x08f	BOOT ROM
fio	DINOPCK	0x096	Dino PC Keyboard
fio	EISALAN	0x097	Cascade EISA 100VG lan
fio	WHPIB	0x099	Wax/Clark/Dino HPIB
fio	SPPCON	0x0a1	SPP2000 Console TTY
fio	PCILAN	0x0a2	PCI Plug-In LAN
fio	PCIDSK	0x0a3	PCI Plug-In Disk
fio	SPPCORE	0x0a4	SPP2000 Core BA
fio	SONICET	0x0a6	Sonic Ethernet
fio	PCIMISC	0x0a9	Misc PCI Plug-in
fio	METHEUS	0x320	Metheus Frame Buffer
fio	BARCO	0x340	BARCO CX4500 VME Graphics Console
fio	HUGHES	0x360	Hughes TOG VME FDDI

# Gecko section
fio	GSCSI	0x082	NCR 53C710 SCSI
fio	GPCFD	0x083	floppy controller
fio	GPCIO	0x084	PS/2 port
fio	GSGC	0x085	GIO Graphics
fio	GISDN	0x087	Core ISDN
fio	GSCSCSI	0x089	GSC SCSI
fio	GLAN	0x08a	Core LAN
fio	GRS232	0x08c	Core RS-232C
fio	GRJ16	0x08d	Optional RJ-16

bha	DIO	0x003	DIO Bus Adapter
bha	SGC	0x005	SGC Bus Adapter
bha	GSC	0x007	GSC Bus Adapter
bha	ASP	0x070	Core Bus Adapter (ASP)
bha	EISA	0x076	EISA Bus Adapter
bha	VME	0x078	VME Bus Adapter
bha	LASI	0x081	LASI Bus Adapter
bha	PCMCIA	0x08b	PCMCIA Bus Adapter
bha	WAX	0x08e	WAX Bus Adapter
bha	WEISA	0x090	WAX EISA Bus Adapter
bha	TIMI	0x093	TIMI Bus Adapter
bha	EPIC	0x0a5	Epic PCI Bus Adapter

ioa	UTURN	0x00b	U2/UTurn Runway BC Port
ioa	PLUTO	0x00c	Pluto BC Port

bridge	DINO	0x00a	PCI Bridge
bridge	SAGA	0x0a5	Saga PCI Bridge

fabric	DNACA	0x0aa	Halfdome DNA Central Agent
fabric	TOGO	0x0ab	Halfdome TOGO Fabric Crossbar
fabric	SAKURA	0x0ac	Halfdome Sakura Fabric Router

path: sys/arch/hppa/dev/cpudevs


code:
/*
 * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
 * generated from:
 *	OpenBSD: cpudevs,v 1.44 2007/05/18 15:57:35 kettenis Exp
 */

#define	HPPA_TYPE_NPROC	0x00
#define	HPPA_TYPE_MEMORY	0x01
#define	HPPA_TYPE_BDMA	0x02
#define	HPPA_TYPE_BDIRECT	0x03
#define	HPPA_TYPE_ADMA	0x04
#define	HPPA_TYPE_ADIRECT	0x05
#define	HPPA_TYPE_OTHER	0x06
#define	HPPA_TYPE_BCPORT	0x07
#define	HPPA_TYPE_CIO	0x08
#define	HPPA_TYPE_CONSOLE	0x09
#define	HPPA_TYPE_FIO	0x0a
#define	HPPA_TYPE_BHA	0x0b
#define	HPPA_TYPE_IOA	0x0c
#define	HPPA_TYPE_BRIDGE	0x0d
#define	HPPA_TYPE_FABRIC	0x0e
#define	HPPA_TYPE_FAULTY	0x1f
#define	HPPA_TYPE_BOARD	0x80
#define	HPPA_TYPE_CPU	0x81
#define	HPPA_TYPE_FPU	0x82
#define	HPPA_TYPE_BUS	0x83
#define	HPPA_BOARD_HP840	0x004
#define	HPPA_BOARD_HP825	0x008
#define	HPPA_BOARD_HP835	0x00a
#define	HPPA_BOARD_HP845	0x00b
#define	HPPA_BOARD_HP850	0x00C
#define	HPPA_BOARD_HP949	0x00f
#define	HPPA_BOARD_HP950S	0x080
#define	HPPA_BOARD_HP855	0x081
#define	HPPA_BOARD_HP860	0x082
#define	HPPA_BOARD_HP870	0x083
#define	HPPA_BOARD_HP810	0x100
#define	HPPA_BOARD_HP822	0x101
#define	HPPA_BOARD_HP832	0x102
#define	HPPA_BOARD_HP808	0x103
#define	HPPA_BOARD_HP842	0x104
#define	HPPA_BOARD_HP852	0x105
#define	HPPA_BOARD_HPOBOE	0x106
#define	HPPA_BOARD_HPDRAGON	0x180
#define	HPPA_BOARD_HP890	0x181
#define	HPPA_BOARD_HP891	0x182
#define	HPPA_BOARD_HP892	0x183
#define	HPPA_BOARD_HP893_T540	0x184
#define	HPPA_BOARD_HPHXPROC	0x1ff
#define	HPPA_BOARD_HP720	0x200
#define	HPPA_BOARD_HP750_66	0x201
#define	HPPA_BOARD_HP730_66	0x202
#define	HPPA_BOARD_HP735_99	0x203
#define	HPPA_BOARD_HP755_99	0x204
#define	HPPA_BOARD_HP755_125	0x205
#define	HPPA_BOARD_HP735_130	0x206
#define	HPPA_BOARD_HP817	0x280
#define	HPPA_BOARD_HP837	0x281
#define	HPPA_BOARD_HP807	0x282
#define	HPPA_BOARD_HP867	0x283
#define	HPPA_BOARD_HP887T	0x284
#define	HPPA_BOARD_HP887	0x287
#define	HPPA_BOARD_HP887T96	0x288
#define	HPPA_BOARD_HP710	0x300
#define	HPPA_BOARD_HP705	0x302
#define	HPPA_BOARD_HP715_50	0x310
#define	HPPA_BOARD_HP715_33	0x311
#define	HPPA_BOARD_HP715S_50	0x312
#define	HPPA_BOARD_HP715S_33	0x313
#define	HPPA_BOARD_HP715T_50	0x314
#define	HPPA_BOARD_HP715T_33	0x315
#define	HPPA_BOARD_HP715_75	0x316
#define	HPPA_BOARD_HP715_99	0x317
#define	HPPA_BOARD_HP725_50	0x318
#define	HPPA_BOARD_HP725_75	0x319
#define	HPPA_BOARD_HP725_99	0x320
#define	HPPA_BOARD_HP745I_50	0x401
#define	HPPA_BOARD_HP742I_50	0x402
#define	HPPA_BOARD_HP747I_100	0x403
#define	HPPA_BOARD_HPE23	0x480
#define	HPPA_BOARD_HPE25	0x481
#define	HPPA_BOARD_HPE35	0x482
#define	HPPA_BOARD_HPE45	0x483
#define	HPPA_BOARD_HPD210	0x484
#define	HPPA_BOARD_HPD200	0x485
#define	HPPA_BOARD_HP778_B132L	0x501
#define	HPPA_BOARD_HP778_B160L	0x502
#define	HPPA_BOARD_HP778_B132LP	0x503
#define	HPPA_BOARD_HP778_B180L	0x504
#define	HPPA_BOARD_HP779_C132L	0x505
#define	HPPA_BOARD_HP779_C160L	0x506
#define	HPPA_BOARD_HP779_C180L	0x507
#define	HPPA_BOARD_HP779_C160L1	0x508
#define	HPPA_BOARD_HP712_132L2	0x509
#define	HPPA_BOARD_HP712_160L2	0x50a
#define	HPPA_BOARD_HP712_132L21	0x50b
#define	HPPA_BOARD_HP712_160L21	0x50c
#define	HPPA_BOARD_HP744_132L	0x50f
#define	HPPA_BOARD_HP744_165L	0x510
#define	HPPA_BOARD_HP803	0x512
#define	HPPA_BOARD_HP813	0x513
#define	HPPA_BOARD_HP778_B132	0x514
#define	HPPA_BOARD_HP800_A132	0x515
#define	HPPA_BOARD_HP800_A180C	0x516
#define	HPPA_BOARD_HP809	0x580
#define	HPPA_BOARD_HP839	0x581
#define	HPPA_BOARD_HP829	0x582
#define	HPPA_BOARD_HP849	0x583
#define	HPPA_BOARD_HP770_J210XC	0x584
#define	HPPA_BOARD_HP770_J200	0x585
#define	HPPA_BOARD_HP770_J210	0x586
#define	HPPA_BOARD_HP841	0x587
#define	HPPA_BOARD_HP851	0x588
#define	HPPA_BOARD_HP821_1	0x589
#define	HPPA_BOARD_HP831	0x58a
#define	HPPA_BOARD_HP819	0x58b
#define	HPPA_BOARD_HP859	0x58c
#define	HPPA_BOARD_HP869	0x58d
#define	HPPA_BOARD_HP780_C110	0x58e
#define	HPPA_BOARD_HP804	0x58f
#define	HPPA_BOARD_HP889	0x590
#define	HPPA_BOARD_HP780_C100	0x592
#define	HPPA_BOARD_HP780_J282	0x594
#define	HPPA_BOARD_HP800V	0x597
#define	HPPA_BOARD_HP780_C230	0x598
#define	HPPA_BOARD_HP780_C240	0x599
#define	HPPA_BOARD_HP780_C160	0x59b
#define	HPPA_BOARD_HP780_C180XP	0x59c
#define	HPPA_BOARD_HP780_C200	0x59d
#define	HPPA_BOARD_HP780_C180P	0x59f
#define	HPPA_BOARD_HP841_1	0x5a0
#define	HPPA_BOARD_HP851_1	0x5a1
#define	HPPA_BOARD_HP861	0x5a2
#define	HPPA_BOARD_HP871	0x5a3
#define	HPPA_BOARD_HP802	0x5a4
#define	HPPA_BOARD_HP879	0x5a5
#define	HPPA_BOARD_HP810D	0x5a9
#define	HPPA_BOARD_HP820	0x5aa
#define	HPPA_BOARD_HP898	0x5ae
#define	HPPA_BOARD_HP899	0x5b1
#define	HPPA_BOARD_HP800V2	0x5b4
#define	HPPA_BOARD_HP782_J2240	0x5b5
#define	HPPA_BOARD_HP800K	0x5b6
#define	HPPA_BOARD_HP821	0x5b9
#define	HPPA_BOARD_HP800D	0x5ba
#define	HPPA_BOARD_HP785_C3000	0x5bb
#define	HPPA_BOARD_HP785_B1000	0x5bc
#define	HPPA_BOARD_HP785_J5000	0x5bd
#define	HPPA_BOARD_HP800_N400036	0x5be
#define	HPPA_BOARD_HP785_J7000	0x5bf
#define	HPPA_BOARD_HP800_L200044	0x5c4
#define	HPPA_BOARD_HP800_L200036	0x5c5
#define	HPPA_BOARD_HP785_C360	0x5c6
#define	HPPA_BOARD_HP800_L100044	0x5c9
#define	HPPA_BOARD_HP800_L100036	0x5ca
#define	HPPA_BOARD_HP897_A50044	0x5cb
#define	HPPA_BOARD_HP800_N400044	0x5cc
#define	HPPA_BOARD_HP785_C3600	0x5cf
#define	HPPA_BOARD_HP786_B2000	0x5d0
#define	HPPA_BOARD_HP785_J5600	0x5d1
#define	HPPA_BOARD_HP785_J7600	0x5d2
#define	HPPA_BOARD_HP800_N400055	0x5d3
#define	HPPA_BOARD_HP785_J6000	0x5d4
#define	HPPA_BOARD_HP897_A5005X	0x5d5
#define	HPPA_BOARD_HP897_A40044	0x5d6
#define	HPPA_BOARD_HP800_N40005X	0x5d7
#define	HPPA_BOARD_HP800_L150044	0x5d8
#define	HPPA_BOARD_HP800_L150036	0x5d9
#define	HPPA_BOARD_HP800_L30005X	0x5db
#define	HPPA_BOARD_HP785_C3700	0x5dc
#define	HPPA_BOARD_HP785_J6700	0x5dd
#define	HPPA_BOARD_HP785_B2600	0x5de
#define	HPPA_BOARD_HP897_A4006X	0x5e1
#define	HPPA_BOARD_HP897_A5006X	0x5e2
#define	HPPA_BOARD_HP897_A5007X	0x5e3
#define	HPPA_BOARD_HP800_N40007X	0x5e4
#define	HPPA_BOARD_HP800_N40006X	0x5e6
#define	HPPA_BOARD_HITACHIW	0x5ff
#define	HPPA_BOARD_HP785_C8000	0x89c
#define	HPPA_BOARD_HP712_60	0x600
#define	HPPA_BOARD_HP712_80	0x601
#define	HPPA_BOARD_HP712_100	0x602
#define	HPPA_BOARD_HP743I_64	0x603
#define	HPPA_BOARD_HP743I_100	0x604
#define	HPPA_BOARD_HP712_120	0x605
#define	HPPA_BOARD_HP715_80	0x609
#define	HPPA_BOARD_HP715_64	0x60A
#define	HPPA_BOARD_HP715_100	0x60B
#define	HPPA_BOARD_HP715_100XC	0x60C
#define	HPPA_BOARD_HP725_100	0x60D
#define	HPPA_BOARD_HP725_120	0x60E
#define	HPPA_BOARD_HP715_100L	0x610
#define	HPPA_BOARD_HP715_120L	0x611
#define	HPPA_BOARD_HP725_80L	0x612
#define	HPPA_BOARD_HP725_100L	0x613
#define	HPPA_BOARD_HP725_120L	0x614
#define	HPPA_BOARD_HP743_50	0x617
#define	HPPA_BOARD_HP743_100	0x618
#define	HPPA_BOARD_HP715_80M	0x619
#define	HPPA_BOARD_HP811	0x61a
#define	HPPA_BOARD_HP801	0x61b
#define	HPPA_BOARD_HP743T	0x61c
#define	HPPA_BOARD_HITACHIT80	0x67e
#define	HPPA_BOARD_HITACHIT64	0x67f
#define	HPPA_BOARD_NEC	0x700
#define	HPPA_BUS_MID_BUS	0
#define	HPPA_BUS_SMB	1
#define	HPPA_BUS_HPPB	2
#define	HPPA_BUS_SUMMIT	3
#define	HPPA_BUS_VVSC	4
#define	HPPA_BUS_VHPPB	5
#define	HPPA_BUS_K9KSC	6
#define	HPPA_BUS_SPSSC	7
#define	HPPA_BUS_STSSC	8
#define	HPPA_BUS_GSCHPPB	9
#define	HPPA_BUS_GSCHSC	10
#define	HPPA_BUS_RUNWAY	11
#define	HPPA_BUS_GSC	12
#define	HPPA_BUS_GSCP	13
#define	HPPA_BUS_NECSB	14
#define	HPPA_BUS_ROPES	15
#define	HPPA_BUS_MERCED	16
#define	HPPA_CPU_SOFTEMU	0x01
#define	HPPA_CPU_PCXT2	0x0b
#define	HPPA_CPU_PCXL	0x0d
#define	HPPA_CPU_PCXU	0x0e
#define	HPPA_CPU_PCXL2	0x0f
#define	HPPA_CPU_PCXUP	0x10
#define	HPPA_CPU_PCXW	0x11
#define	HPPA_CPU_PCXW2	0x13
#define	HPPA_FPU_SOFTEMU	0x01
#define	HPPA_FPU_INDIGO	0x02
#define	HPPA_FPU_TYCO	0x03
#define	HPPA_FPU_ROC	0x04
#define	HPPA_FPU_FPCW	0x06
#define	HPPA_FPU_FPCB	0x07
#define	HPPA_FPU_PCXS	0x08
#define	HPPA_FPU_PCXT	0x09
#define	HPPA_FPU_HARP	0x0a
#define	HPPA_FPU_PCXT2	0x0b
#define	HPPA_FPU_PA50	0x0c
#define	HPPA_FPU_PCXL	0x0d
#define	HPPA_FPU_PCXU	0x0e
#define	HPPA_FPU_VR	0x0f
#define	HPPA_FPU_PCXW	0x10
#define	HPPA_FPU_PCXW2	0x13
#define	HPPA_NPROC_HPPA	4
#define	HPPA_MEMORY_ARCH	0x008
#define	HPPA_MEMORY_PDEP	0x009
#define	HPPA_BDMA_PARALLEL	0x018
#define	HPPA_BDMA_PRDB	0x019
#define	HPPA_BDMA_MIDBUSPSI	0x020
#define	HPPA_BDMA_HPPBTPSI	0x02f
#define	HPPA_BDMA_HPPBT8023	0x051
#define	HPPA_BDMA_HPPBLANCON	0x052
#define	HPPA_BDMA_HPPB8024	0x058
#define	HPPA_BDMA_LANCONS	0x060
#define	HPPA_BDMA_EXERCISER	0x094
#define	HPPA_BDMA_HPPBHFI	0x100
#define	HPPA_ADMA_SCSI	0x039
#define	HPPA_ADMA_FWSCSI0	0x03b
#define	HPPA_ADMA_HPIB	0x040
#define	HPPA_ADMA_HPPBFL	0x041
#define	HPPA_ADMA_HPPBIB	0x042
#define	HPPA_ADMA_HPPBCL	0x043
#define	HPPA_ADMA_HPPBGPS	0x044
#define	HPPA_ADMA_HPPBGPL	0x045
#define	HPPA_ADMA_2X25	0x046
#define	HPPA_ADMA_4X25	0x047
#define	HPPA_ADMA_NIMBFB	0x04a
#define	HPPA_ADMA_NIMBCL	0x04b
#define	HPPA_ADMA_MRTI	0x04c
#define	HPPA_ADMA_ACCMUX	0x04d
#define	HPPA_ADMA_L8023	0x050
#define	HPPA_ADMA_LQFDDI	0x056
#define	HPPA_ADMA_LQFDDI1	0x057
#define	HPPA_ADMA_GTR	0x05e
#define	HPPA_ADMA_FWSCSI	0x089
#define	HPPA_ADMA_NETFC	0x091
#define	HPPA_ADMA_YATM	0x092
#define	HPPA_ADMA_MYRI	0x095
#define	HPPA_ADMA_LFEMU	0x098
#define	HPPA_ADMA_VATM	0x09a
#define	HPPA_ADMA_HSCPCI	0x09d
#define	HPPA_ADMA_ATMGSC	0x09e
#define	HPPA_ADMA_SHUSB	0x09f
#define	HPPA_ADMA_SHFETH	0x0a0
#define	HPPA_ADMA_MASSFC	0x0a7
#define	HPPA_ADMA_IPFC	0x380
#define	HPPA_ADMA_IPATM	0x381
#define	HPPA_ADMA_IP100T	0x382
#define	HPPA_ADMA_IPNIOVG	0x383
#define	HPPA_ADIRECT_APMUX	0x00d
#define	HPPA_ADIRECT_RS232	0x00e
#define	HPPA_ADIRECT_PEACOCK	0x00f
#define	HPPA_ADIRECT_HIL	0x014
#define	HPPA_ADIRECT_LEONARDO	0x015
#define	HPPA_ADIRECT_HRM	0x016
#define	HPPA_ADIRECT_HRC	0x017
#define	HPPA_ADIRECT_LPT	0x03a
#define	HPPA_ADIRECT_ATTDK	0x04e
#define	HPPA_ADIRECT_HPIB	0x09b
#define	HPPA_ADIRECT_ROCKYKBD	0x0a8
#define	HPPA_ADIRECT_HICONS	0x101
#define	HPPA_ADIRECT_HIBOOT	0x102
#define	HPPA_OTHER_MIDBVM	0x030
#define	HPPA_OTHER_MIDBVS	0x034
#define	HPPA_OTHER_MIDBEDU	0x038
#define	HPPA_OTHER_SPECFB	0x048
#define	HPPA_OTHER_SPECCTL	0x049
#define	HPPA_BCPORT_PHANTOM	0x000
#define	HPPA_BCPORT_PORT	0x00c
#define	HPPA_CIO_CIO	0x010
#define	HPPA_CONSOLE_CHEETAH	0x01c
#define	HPPA_CONSOLE_NULL	0x01f
#define	HPPA_FIO_A_X25	0x02e
#define	HPPA_FIO_8X25	0x04f
#define	HPPA_FIO_SCSI	0x071
#define	HPPA_FIO_LAN	0x072
#define	HPPA_FIO_HIL	0x073
#define	HPPA_FIO_CENT	0x074
#define	HPPA_FIO_RS232	0x075
#define	HPPA_FIO_SGC	0x077
#define	HPPA_FIO_A1	0x07a
#define	HPPA_FIO_A2NB	0x07b
#define	HPPA_FIO_FWSCSI	0x07c
#define	HPPA_FIO_FDDI	0x07d
#define	HPPA_FIO_A1NB	0x07e
#define	HPPA_FIO_A2	0x07f
#define	HPPA_FIO_HPIB	0x080
#define	HPPA_FIO_TR9000	0x086
#define	HPPA_FIO_VMENET	0x088
#define	HPPA_FIO_BOOTROM	0x08f
#define	HPPA_FIO_DINOPCK	0x096
#define	HPPA_FIO_EISALAN	0x097
#define	HPPA_FIO_WHPIB	0x099
#define	HPPA_FIO_SPPCON	0x0a1
#define	HPPA_FIO_PCILAN	0x0a2
#define	HPPA_FIO_PCIDSK	0x0a3
#define	HPPA_FIO_SPPCORE	0x0a4
#define	HPPA_FIO_SONICET	0x0a6
#define	HPPA_FIO_PCIMISC	0x0a9
#define	HPPA_FIO_METHEUS	0x320
#define	HPPA_FIO_BARCO	0x340
#define	HPPA_FIO_HUGHES	0x360
#define	HPPA_FIO_GSCSI	0x082
#define	HPPA_FIO_GPCFD	0x083
#define	HPPA_FIO_GPCIO	0x084
#define	HPPA_FIO_GSGC	0x085
#define	HPPA_FIO_GISDN	0x087
#define	HPPA_FIO_GSCSCSI	0x089
#define	HPPA_FIO_GLAN	0x08a
#define	HPPA_FIO_GRS232	0x08c
#define	HPPA_FIO_GRJ16	0x08d
#define	HPPA_BHA_DIO	0x003
#define	HPPA_BHA_SGC	0x005
#define	HPPA_BHA_GSC	0x007
#define	HPPA_BHA_ASP	0x070
#define	HPPA_BHA_EISA	0x076
#define	HPPA_BHA_VME	0x078
#define	HPPA_BHA_LASI	0x081
#define	HPPA_BHA_PCMCIA	0x08b
#define	HPPA_BHA_WAX	0x08e
#define	HPPA_BHA_WEISA	0x090
#define	HPPA_BHA_TIMI	0x093
#define	HPPA_BHA_EPIC	0x0a5
#define	HPPA_IOA_UTURN	0x00b
#define	HPPA_IOA_PLUTO	0x00c
#define	HPPA_BRIDGE_DINO	0x00a
#define	HPPA_BRIDGE_SAGA	0x0a5
#define	HPPA_FABRIC_DNACA	0x0aa
#define	HPPA_FABRIC_TOGO	0x0ab
#define	HPPA_FABRIC_SAKURA	0x0ac


code:
/*
 * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
 * generated from:
 *	OpenBSD: cpudevs,v 1.44 2007/05/18 15:57:35 kettenis Exp
 */

{HPPA_TYPE_BOARD,	HPPA_BOARD_HP840,	"840/930 (Indigo)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP825,	"825/925 (FireFox)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP835,	"83[45]/[69]35 (TopGun)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP845,	"845/645 (Technical ShoGun)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP850,	"850/950 (Cheetah)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP949,	"949 (Commercial ShoGun)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP950S,	"950S (Cheetah)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP855,	"855/955 (Jaguar)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP860,	"860/960 (Cougar)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP870,	"865/870/980 (Panther)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP810,	"810 (Burgundy)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP822,	"822/922 (SilverFox Low)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP832,	"832/932 (SilverFox High)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP808,	"808/815/920 (Lego, SilverLite)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP842,	"842/948 (SilverBullet Low)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP852,	"852/958 (SilverBullet High)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HPOBOE,	"(Oboe)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HPDRAGON,	"(Dragon)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP890,	"890/990/992 (Chimera)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP891,	"891/T500 (TNT 100)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP892,	"892/T520 (TNT 120)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP893_T540,	"893/T540/T600 (Jade 180 U)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HPHXPROC,	"Hitachi X Processor" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP720,	"720 (Cobra)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP750_66,	"750/66 (Coral)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP730_66,	"730/66 (King Cobra)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP735_99,	"735/99 (Hardball)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP755_99,	"755/99 (Coral II)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP755_125,	"755/125 (Coral II)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP735_130,	"735/130 (Snake Cheetah)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP817,	"817/827/957/957LX/FH20 (Nova Low)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP837,	"837/847/857/967/967LX/FGHI30 (Nova High)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP807,	"807/917/917LX/927/927LX/937/937LX/947/947LX/F10 (Nova8)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP867,	"867/877/977/GHI40 (Nova64)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP887T,	"887/897/987/GHI50 (TNova)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP887,	"887/897/GHI70 (Hydra96 (Nova))" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP887T96,	"887/897/GHI60 (TNova96)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP710,	"710/50 (Bushmaster)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP705,	"705/35 (Flounder)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP715_50,	"715/50 (Scorpio)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP715_33,	"715/33 (Scorpio Jr.)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP715S_50,	"715S/50 (Spider-50)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP715S_33,	"715S/33 (Spider-33)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP715T_50,	"715T/50 (Trailways-50)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP715T_33,	"715T/33 (Trailways-33)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP715_75,	"715/75 (Scorpio Sr.)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP715_99,	"715/99 (Scorpio 100)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP725_50,	"725/50 (Spectra)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP725_75,	"725/75 (Spectra)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP725_99,	"725/99 (Spectra)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP745I_50,	"745i/747i/50 (Pace)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP742I_50,	"742i/50 (Sidewinder)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP747I_100,	"745i/747i/100 (Fast Pace)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HPE23,	"806/E23 (Orville)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HPE25,	"806/E25 (Wilbur)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HPE35,	"816/E35 (Wright Brothers 80)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HPE45,	"826/E45 (Wright Brothers 96)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HPD210,	"811/D210/D310 (UltraLight L 100)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HPD200,	"801/D200/D300 (UltraLight L 75)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP778_B132L,	"778/B132L (Merlin L2 132)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP778_B160L,	"778/B160L (Merlin L2 160)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP778_B132LP,	"778/B132L+ (Merlin L2+ 132)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP778_B180L,	"778/B180L+ (Merlin L2+ 180)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP779_C132L,	"779/C132L (Raven L2 132)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP779_C160L,	"779/C160L (Raven L2 160)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP779_C180L,	"779/C180L (Raven L2 180)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP779_C160L1,	"779/C160L (Raven L2 160)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP712_132L2,	"712/132 (L2 Upgrade)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP712_160L2,	"712/160 (L2 Upgrade)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP712_132L21,	"712/132 (L2 Upgrade)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP712_160L21,	"712/160 (L2 Upgrade)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP744_132L,	"744/132L (Anole-132L)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP744_165L,	"744/165L (Anole-165L)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP803,	"803/D220 (UltraLight L2 132)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP813,	"813/D320 (UltraLight L2 160)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP778_B132,	"778/B132 (Merlin Jr. L2 132)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP800_A132,	"800/A132 (Staccato L2 132)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP800_A180C,	"800/A180C (Staccato L2 180)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP809,	"809/K100 (KittyHawk DC2-100)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP839,	"839/K210 (KittyHawk DC3-120)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP829,	"829/K400 (KittyHawk DC3-100)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP849,	"849/K410 (KittyHawk DC3-120)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP770_J210XC,	"770/J210XC (LighteningHawk)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP770_J200,	"770/J200 (SkyHawk 100)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP770_J210,	"770/J210 (SkyHawk 120)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP841,	"841/D210/D410 (UltraLight Proc 1-way T'120)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP851,	"851/D210-2/D410-2 (UltraLight Proc 2-way T'120)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP821_1,	"821/D200/D400 (UltraLight Proc 1-way T'100)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP831,	"831/D200-2/D400-2 (UltraLight Proc 2-way T'100)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP819,	"819/K200 (KittyHawk DC2 100)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP859,	"859/K220 (ThunderHawk DC3- 120 1M)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP869,	"869/K420 (ThunderHawk DC3 120 1M)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP780_C110,	"780/C110 (Raven 120 T')" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP804,	"804/K450 (Mohawk 160 U 1M DC3)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP889,	"889/K460 (Mohawk 180 U 1M DC3)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP780_C100,	"780/C100 (Raven 100 T')" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP780_J282,	"780/J282 (FireHawk 180 U)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP800V,	"800/V2200/V2500 (SPP2000)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP780_C230,	"780/C230 (Raven U 230)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP780_C240,	"780/C240 (Raven U 240)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP780_C160,	"780/C160 (Raven U 160)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP780_C180XP,	"780/C180XP (Raven U 180)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP780_C200,	"780/C200 (Raven U 200)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP780_C180P,	"780/C180+ (Raven U 180+)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP841_1,	"841/D260/D360 (UltraLight 1-way T120 1MB)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP851_1,	"851/D260/D360 (UltraLight 2-way T120 1MB)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP861,	"861/D270/D370 (UltraLight 1-way U160 512K)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP871,	"871/D270/D370 (UltraLight 2-way U160 512K)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP802,	"802/K250 (MoHawk U160 1M DC3-)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP879,	"879/K260 (MoHawk U180 1M DC3-)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP810D,	"810/D380/R380 (UltraLight 1-way U180 1M)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP820,	"820/D280 (UltraLight 2-way U180 1M)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP898,	"898/K370 (BraveHawk 200 DC3-)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP899,	"899/K570 (BraveHawk 200 DC3)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP800V2,	"800/V2500 (SPP2500)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP782_J2240,	"782/J2240 (SummitHawk U+)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP800K,	"800/K580 (DragonHawk U+ 240 DC3)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP821,	"821/D350/R350 (UltraLight 1w U+/240)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP800D,	"800/D390/R390 (UltraLight 2w U+/240)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP785_C3000,	"785/C3000 (AllegroHigh W)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP785_B1000,	"785/B1000 (AllegroLow W)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP785_J5000,	"785/J5000 (Forte W 2w)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP800_N400036,	"800/N4000-36/rp7400 (Prelude W)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP785_J7000,	"785/J7000 (Forte W 4w)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP800_L200044,	"800/L2000-44/rp5450 (Rhapsody 440)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP800_L200036,	"800/L2000-36/rp5450 (Rhapsody 360)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP785_C360,	"780/C360 (Raven W 360)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP800_L100044,	"800/L1000-44/rp5400 (Rhapsody DC-440)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP800_L100036,	"800/L1000-36/rp5400 (Rhapsody DC-360)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP897_A50044,	"897/A500-44/rp2450 (Crescendo 440)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP800_N400044,	"800/N4000-44/rp7400 (Prelude W 440)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP785_C3600,	"785/C3600 (Allegro)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP786_B2000,	"786/B2000 (Kazoo W+)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP785_J5600,	"785/J5600 (Forte W+ 2w)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP785_J7600,	"785/J7600 (Forte W+ 4w)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP800_N400055,	"800/N4000-55/rp7400 (Prelude W+ 550)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP785_J6000,	"785/J6000 (Duet W+)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP897_A5005X,	"897/A500-5X/rp2450 (Crescendo 550)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP897_A40044,	"897/A400-44/rp2400 (Crescendo 440)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP800_N40005X,	"800/N4000-5X/rp7410 (Keystone W+ 550)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP800_L150044,	"800/L1500-44/rp5430 (Rhapsody wave 2 W+)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP800_L150036,	"800/L1500-36/rp5430 (Rhapsody wave 2 W+)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP800_L30005X,	"800/L3000-5X/rp5470 (Marcato W+)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP785_C3700,	"785/C3700" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP785_J6700,	"785/J6700 (Duet W2)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP785_B2600,	"785/B2600 (Piccolo W+)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP897_A4006X,	"897/A400-6X/rp2430 (Crescendo DC-W2)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP897_A5006X,	"897/A500-6X/rp2470 (Crescendo 650 W2)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP897_A5007X,	"897/A500-7X/rp2470 (Crescendo 750 W2)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP800_N40007X,	"800/N4000-7X/rp7410 (Keystone/Matterhorn W2 750)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP800_N40006X,	"800/N4000-6X/rp7410 (Keystone/Matterhorn W2 650)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HITACHIW,	"(Hitachi W)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP785_C8000,	"785/C8000" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP712_60,	"712/60 (Gecko)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP712_80,	"712/80 (King Gecko)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP712_100,	"712/100 (King Gecko)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP743I_64,	"743i/64 (Anole-64)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP743I_100,	"743i/100 (Anole-100)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP712_120,	"712/120 (King Gecko)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP715_80,	"715/80 (Scorpio-L)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP715_64,	"715/64 (Mirage Jr.)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP715_100,	"715/100 (Mirage Sr.)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP715_100XC,	"715/100XC (Turnip)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP725_100,	"725/100 (Electra)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP725_120,	"725/120 (Electra)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP715_100L,	"715/100L (Scorpio-L)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP715_120L,	"715/120L (Scorpio-L)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP725_80L,	"725/80L (Spectra-L)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP725_100L,	"725/100L (Spectra-L)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP725_120L,	"725/120L (Spectra-L)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP743_50,	"743/50 (Jason)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP743_100,	"743/100 (Jason)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP715_80M,	"715/80 (Mirage)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP811,	"811/DX5 (SAIC L-80)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP801,	"801/DX0 (Rocky1 L-80)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HP743T,	"743T (Anole T)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HITACHIT80,	"(Hitachi Tiny 80)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_HITACHIT64,	"(Hitachi Tiny 64)" },
{HPPA_TYPE_BOARD,	HPPA_BOARD_NEC,	"(NEC Aska)" },
{HPPA_TYPE_BUS,	HPPA_BUS_MID_BUS,	"MID_BUS" },
{HPPA_TYPE_BUS,	HPPA_BUS_SMB,	"SMB" },
{HPPA_TYPE_BUS,	HPPA_BUS_HPPB,	"HP-PB" },
{HPPA_TYPE_BUS,	HPPA_BUS_SUMMIT,	"Summit" },
{HPPA_TYPE_BUS,	HPPA_BUS_VVSC,	"Viper-VSC" },
{HPPA_TYPE_BUS,	HPPA_BUS_VHPPB,	"Viper-HPPB" },
{HPPA_TYPE_BUS,	HPPA_BUS_K9KSC,	"K9-KSC" },
{HPPA_TYPE_BUS,	HPPA_BUS_SPSSC,	"Spider-SSC" },
{HPPA_TYPE_BUS,	HPPA_BUS_STSSC,	"Stiletto-SSC" },
{HPPA_TYPE_BUS,	HPPA_BUS_GSCHPPB,	"GSC-HPPB" },
{HPPA_TYPE_BUS,	HPPA_BUS_GSCHSC,	"GSC+(HSC)" },
{HPPA_TYPE_BUS,	HPPA_BUS_RUNWAY,	"Runway" },
{HPPA_TYPE_BUS,	HPPA_BUS_GSC,	"GSC" },
{HPPA_TYPE_BUS,	HPPA_BUS_GSCP,	"GSC++" },
{HPPA_TYPE_BUS,	HPPA_BUS_NECSB,	"NEC System Bus" },
{HPPA_TYPE_BUS,	HPPA_BUS_ROPES,	"Ropes" },
{HPPA_TYPE_BUS,	HPPA_BUS_MERCED,	"Merced" },
{HPPA_TYPE_CPU,	HPPA_CPU_SOFTEMU,	"Software Emulation" },
{HPPA_TYPE_CPU,	HPPA_CPU_PCXT2,	"PCXT' (Thunderbird')" },
{HPPA_TYPE_CPU,	HPPA_CPU_PCXL,	"PCXL (Hummingbird)" },
{HPPA_TYPE_CPU,	HPPA_CPU_PCXU,	"PCXU (Onyx)" },
{HPPA_TYPE_CPU,	HPPA_CPU_PCXL2,	"PCXL2 (Velociraptor)" },
{HPPA_TYPE_CPU,	HPPA_CPU_PCXUP,	"PCXU+ (Vulcan)" },
{HPPA_TYPE_CPU,	HPPA_CPU_PCXW,	"PCXW (Vulcan)" },
{HPPA_TYPE_CPU,	HPPA_CPU_PCXW2,	"PCXW2 (Piranha)" },
{HPPA_TYPE_FPU,	HPPA_FPU_SOFTEMU,	"Software Emulation" },
{HPPA_TYPE_FPU,	HPPA_FPU_INDIGO,	"Indigo" },
{HPPA_TYPE_FPU,	HPPA_FPU_TYCO,	"Sterling I MIU (TYCO)" },
{HPPA_TYPE_FPU,	HPPA_FPU_ROC,	"Sterling I MIU (ROC w/Weitek)" },
{HPPA_TYPE_FPU,	HPPA_FPU_FPCW,	"FPC (NMOS-III w/Weitek)" },
{HPPA_TYPE_FPU,	HPPA_FPU_FPCB,	"FPC (NMOS-III w/Bit)" },
{HPPA_TYPE_FPU,	HPPA_FPU_PCXS,	"PCXS (Timex-II)" },
{HPPA_TYPE_FPU,	HPPA_FPU_PCXT,	"PCXT (Rolex - CMOS-26B)" },
{HPPA_TYPE_FPU,	HPPA_FPU_HARP,	"HARP-I" },
{HPPA_TYPE_FPU,	HPPA_FPU_PCXT2,	"PCXT' (Tornado)" },
{HPPA_TYPE_FPU,	HPPA_FPU_PA50,	"PA-50 (Hitachi)" },
{HPPA_TYPE_FPU,	HPPA_FPU_PCXL,	"PCXL (CMOS-26B)" },
{HPPA_TYPE_FPU,	HPPA_FPU_PCXU,	"PCXU/PCXU+" },
{HPPA_TYPE_FPU,	HPPA_FPU_VR,	"VR" },
{HPPA_TYPE_FPU,	HPPA_FPU_PCXW,	"PCXW" },
{HPPA_TYPE_FPU,	HPPA_FPU_PCXW2,	"PCXW2" },
{HPPA_TYPE_NPROC,	HPPA_NPROC_HPPA,	"PA-RISC" },
{HPPA_TYPE_MEMORY,	HPPA_MEMORY_ARCH,	"architected memory module" },
{HPPA_TYPE_MEMORY,	HPPA_MEMORY_PDEP,	"pdep memory module" },
{HPPA_TYPE_BDMA,	HPPA_BDMA_PARALLEL,	"Parallel I/O" },
{HPPA_TYPE_BDMA,	HPPA_BDMA_PRDB,	"Parallel RDB" },
{HPPA_TYPE_BDMA,	HPPA_BDMA_MIDBUSPSI,	"MID_BUS PSI" },
{HPPA_TYPE_BDMA,	HPPA_BDMA_HPPBTPSI,	"HP-PB Transit PSI" },
{HPPA_TYPE_BDMA,	HPPA_BDMA_HPPBT8023,	"HP-PB Transit 802.3" },
{HPPA_TYPE_BDMA,	HPPA_BDMA_HPPBLANCON,	"Miura LAN/Console (J2146A)" },
{HPPA_TYPE_BDMA,	HPPA_BDMA_HPPB8024,	"HP-PB Transit 802.4" },
{HPPA_TYPE_BDMA,	HPPA_BDMA_LANCONS,	"LAN/Console" },
{HPPA_TYPE_BDMA,	HPPA_BDMA_EXERCISER,	"GSC+ Exerciser" },
{HPPA_TYPE_BDMA,	HPPA_BDMA_HPPBHFI,	"HP-PB HF Interface" },
{HPPA_TYPE_ADMA,	HPPA_ADMA_SCSI,	"SCSI" },
{HPPA_TYPE_ADMA,	HPPA_ADMA_FWSCSI0,	"Wizard FW SCSI" },
{HPPA_TYPE_ADMA,	HPPA_ADMA_HPIB,	"HP-IB" },
{HPPA_TYPE_ADMA,	HPPA_ADMA_HPPBFL,	"HP-PB HP-FL" },
{HPPA_TYPE_ADMA,	HPPA_ADMA_HPPBIB,	"HP-PB LoQuix HP-IB" },
{HPPA_TYPE_ADMA,	HPPA_ADMA_HPPBCL,	"HP-PB Crypt LoQuix" },
{HPPA_TYPE_ADMA,	HPPA_ADMA_HPPBGPS,	"HP-PB Shazam GPIO" },
{HPPA_TYPE_ADMA,	HPPA_ADMA_HPPBGPL,	"HP-PB LoQuix GPIO" },
{HPPA_TYPE_ADMA,	HPPA_ADMA_2X25,	"2-Port X.25 NIO_ACC" },
{HPPA_TYPE_ADMA,	HPPA_ADMA_4X25,	"4-Port X.25 NIO_ACC" },
{HPPA_TYPE_ADMA,	HPPA_ADMA_NIMBFB,	"Nimbus Frame Buffer" },
{HPPA_TYPE_ADMA,	HPPA_ADMA_NIMBCL,	"Nimbus Control" },
{HPPA_TYPE_ADMA,	HPPA_ADMA_MRTI,	"Martian RTI" },
{HPPA_TYPE_ADMA,	HPPA_ADMA_ACCMUX,	"ACC Mux" },
{HPPA_TYPE_ADMA,	HPPA_ADMA_L8023,	"Lanbrusca 802.3" },
{HPPA_TYPE_ADMA,	HPPA_ADMA_LQFDDI,	"HP-PB LoQuix FDDI" },
{HPPA_TYPE_ADMA,	HPPA_ADMA_LQFDDI1,	"HP-PB LoQuix FDDI (28670A)" },
{HPPA_TYPE_ADMA,	HPPA_ADMA_GTR,	"TI TokenRing" },
{HPPA_TYPE_ADMA,	HPPA_ADMA_FWSCSI,	"FW SCSI" },
{HPPA_TYPE_ADMA,	HPPA_ADMA_NETFC,	"Net FC" },
{HPPA_TYPE_ADMA,	HPPA_ADMA_YATM,	"GSC+ YLIASTER ATM" },
{HPPA_TYPE_ADMA,	HPPA_ADMA_MYRI,	"Hamlyn GSC+ Network Card" },
{HPPA_TYPE_ADMA,	HPPA_ADMA_LFEMU,	"Lo-fat Emulator" },
{HPPA_TYPE_ADMA,	HPPA_ADMA_VATM,	"GSC+ Venus ATM" },
{HPPA_TYPE_ADMA,	HPPA_ADMA_HSCPCI,	"HP HSC-PCI Cards" },
{HPPA_TYPE_ADMA,	HPPA_ADMA_ATMGSC,	"Alaxis GSC+ ATM" },
{HPPA_TYPE_ADMA,	HPPA_ADMA_SHUSB,	"SummitHawk 230 USB" },
{HPPA_TYPE_ADMA,	HPPA_ADMA_SHFETH,	"SummitHawk 230 100BaseT" },
{HPPA_TYPE_ADMA,	HPPA_ADMA_MASSFC,	"Add-on mass FC" },
{HPPA_TYPE_ADMA,	HPPA_ADMA_IPFC,	"Interphase NIO-FC" },
{HPPA_TYPE_ADMA,	HPPA_ADMA_IPATM,	"Interphase NIO-ATM" },
{HPPA_TYPE_ADMA,	HPPA_ADMA_IP100T,	"Interphase NIO-100BaseT" },
{HPPA_TYPE_ADMA,	HPPA_ADMA_IPNIOVG,	"Interphase NIO-100VG" },
{HPPA_TYPE_ADIRECT,	HPPA_ADIRECT_APMUX,	"AP/MUX" },
{HPPA_TYPE_ADIRECT,	HPPA_ADIRECT_RS232,	"RS-232" },
{HPPA_TYPE_ADIRECT,	HPPA_ADIRECT_PEACOCK,	"Peacock Graphics" },
{HPPA_TYPE_ADIRECT,	HPPA_ADIRECT_HIL,	"HIL" },
{HPPA_TYPE_ADIRECT,	HPPA_ADIRECT_LEONARDO,	"Leonardo" },
{HPPA_TYPE_ADIRECT,	HPPA_ADIRECT_HRM,	"HP-PB HRM" },
{HPPA_TYPE_ADIRECT,	HPPA_ADIRECT_HRC,	"HP-PB HRC" },
{HPPA_TYPE_ADIRECT,	HPPA_ADIRECT_LPT,	"Centronics interface" },
{HPPA_TYPE_ADIRECT,	HPPA_ADIRECT_ATTDK,	"AT&T DataKit" },
{HPPA_TYPE_ADIRECT,	HPPA_ADIRECT_HPIB,	"Test&Meas GSC HPIB" },
{HPPA_TYPE_ADIRECT,	HPPA_ADIRECT_ROCKYKBD,	"Rocky2 Front Keyboard" },
{HPPA_TYPE_ADIRECT,	HPPA_ADIRECT_HICONS,	"Hitachi Console Module" },
{HPPA_TYPE_ADIRECT,	HPPA_ADIRECT_HIBOOT,	"Hitachi Boot Module" },
{HPPA_TYPE_OTHER,	HPPA_OTHER_MIDBVM,	"MID_BUS Verification Master" },
{HPPA_TYPE_OTHER,	HPPA_OTHER_MIDBVS,	"MID_BUS Verification Slave" },
{HPPA_TYPE_OTHER,	HPPA_OTHER_MIDBEDU,	"MID_BUS Verification EDU" },
{HPPA_TYPE_OTHER,	HPPA_OTHER_SPECFB,	"Spectograph frame buffer" },
{HPPA_TYPE_OTHER,	HPPA_OTHER_SPECCTL,	"Spectograph control" },
{HPPA_TYPE_BCPORT,	HPPA_BCPORT_PHANTOM,	"Phantom Port" },
{HPPA_TYPE_BCPORT,	HPPA_BCPORT_PORT,	"Bus Converter Port" },
{HPPA_TYPE_CIO,	HPPA_CIO_CIO,	"CIO" },
{HPPA_TYPE_CONSOLE,	HPPA_CONSOLE_CHEETAH,	"Cheetah Console" },
{HPPA_TYPE_CONSOLE,	HPPA_CONSOLE_NULL,	"Jason/Anole Null Console" },
{HPPA_TYPE_FIO,	HPPA_FIO_A_X25,	"Armyknife Optional X.25" },
{HPPA_TYPE_FIO,	HPPA_FIO_8X25,	"8-Port X.25 EISA-ACC" },
{HPPA_TYPE_FIO,	HPPA_FIO_SCSI,	"NCR 53C700 SCSI" },
{HPPA_TYPE_FIO,	HPPA_FIO_LAN,	"Core LAN" },
{HPPA_TYPE_FIO,	HPPA_FIO_HIL,	"Core HIL" },
{HPPA_TYPE_FIO,	HPPA_FIO_CENT,	"Core Centronics" },
{HPPA_TYPE_FIO,	HPPA_FIO_RS232,	"Core RS-232C" },
{HPPA_TYPE_FIO,	HPPA_FIO_SGC,	"SGC Graphics" },
{HPPA_TYPE_FIO,	HPPA_FIO_A1,	"Core audio (int.)" },
{HPPA_TYPE_FIO,	HPPA_FIO_A2NB,	"Advanced audio (ext.)" },
{HPPA_TYPE_FIO,	HPPA_FIO_FWSCSI,	"NCR 53C720 FW-SCSI" },
{HPPA_TYPE_FIO,	HPPA_FIO_FDDI,	"Core FDDI" },
{HPPA_TYPE_FIO,	HPPA_FIO_A1NB,	"Core audio (ext.)" },
{HPPA_TYPE_FIO,	HPPA_FIO_A2,	"Advanced audio (int.)" },
{HPPA_TYPE_FIO,	HPPA_FIO_HPIB,	"Core HPIB" },
{HPPA_TYPE_FIO,	HPPA_FIO_TR9000,	"GSC IBM TokenRing" },
{HPPA_TYPE_FIO,	HPPA_FIO_VMENET,	"VME Networking" },
{HPPA_TYPE_FIO,	HPPA_FIO_BOOTROM,	"BOOT ROM" },
{HPPA_TYPE_FIO,	HPPA_FIO_DINOPCK,	"Dino PC Keyboard" },
{HPPA_TYPE_FIO,	HPPA_FIO_EISALAN,	"Cascade EISA 100VG lan" },
{HPPA_TYPE_FIO,	HPPA_FIO_WHPIB,	"Wax/Clark/Dino HPIB" },
{HPPA_TYPE_FIO,	HPPA_FIO_SPPCON,	"SPP2000 Console TTY" },
{HPPA_TYPE_FIO,	HPPA_FIO_PCILAN,	"PCI Plug-In LAN" },
{HPPA_TYPE_FIO,	HPPA_FIO_PCIDSK,	"PCI Plug-In Disk" },
{HPPA_TYPE_FIO,	HPPA_FIO_SPPCORE,	"SPP2000 Core BA" },
{HPPA_TYPE_FIO,	HPPA_FIO_SONICET,	"Sonic Ethernet" },
{HPPA_TYPE_FIO,	HPPA_FIO_PCIMISC,	"Misc PCI Plug-in" },
{HPPA_TYPE_FIO,	HPPA_FIO_METHEUS,	"Metheus Frame Buffer" },
{HPPA_TYPE_FIO,	HPPA_FIO_BARCO,	"BARCO CX4500 VME Graphics Console" },
{HPPA_TYPE_FIO,	HPPA_FIO_HUGHES,	"Hughes TOG VME FDDI" },
{HPPA_TYPE_FIO,	HPPA_FIO_GSCSI,	"NCR 53C710 SCSI" },
{HPPA_TYPE_FIO,	HPPA_FIO_GPCFD,	"floppy controller" },
{HPPA_TYPE_FIO,	HPPA_FIO_GPCIO,	"PS/2 port" },
{HPPA_TYPE_FIO,	HPPA_FIO_GSGC,	"GIO Graphics" },
{HPPA_TYPE_FIO,	HPPA_FIO_GISDN,	"Core ISDN" },
{HPPA_TYPE_FIO,	HPPA_FIO_GSCSCSI,	"GSC SCSI" },
{HPPA_TYPE_FIO,	HPPA_FIO_GLAN,	"Core LAN" },
{HPPA_TYPE_FIO,	HPPA_FIO_GRS232,	"Core RS-232C" },
{HPPA_TYPE_FIO,	HPPA_FIO_GRJ16,	"Optional RJ-16" },
{HPPA_TYPE_BHA,	HPPA_BHA_DIO,	"DIO Bus Adapter" },
{HPPA_TYPE_BHA,	HPPA_BHA_SGC,	"SGC Bus Adapter" },
{HPPA_TYPE_BHA,	HPPA_BHA_GSC,	"GSC Bus Adapter" },
{HPPA_TYPE_BHA,	HPPA_BHA_ASP,	"Core Bus Adapter (ASP)" },
{HPPA_TYPE_BHA,	HPPA_BHA_EISA,	"EISA Bus Adapter" },
{HPPA_TYPE_BHA,	HPPA_BHA_VME,	"VME Bus Adapter" },
{HPPA_TYPE_BHA,	HPPA_BHA_LASI,	"LASI Bus Adapter" },
{HPPA_TYPE_BHA,	HPPA_BHA_PCMCIA,	"PCMCIA Bus Adapter" },
{HPPA_TYPE_BHA,	HPPA_BHA_WAX,	"WAX Bus Adapter" },
{HPPA_TYPE_BHA,	HPPA_BHA_WEISA,	"WAX EISA Bus Adapter" },
{HPPA_TYPE_BHA,	HPPA_BHA_TIMI,	"TIMI Bus Adapter" },
{HPPA_TYPE_BHA,	HPPA_BHA_EPIC,	"Epic PCI Bus Adapter" },
{HPPA_TYPE_IOA,	HPPA_IOA_UTURN,	"U2/UTurn Runway BC Port" },
{HPPA_TYPE_IOA,	HPPA_IOA_PLUTO,	"Pluto BC Port" },
{HPPA_TYPE_BRIDGE,	HPPA_BRIDGE_DINO,	"PCI Bridge" },
{HPPA_TYPE_BRIDGE,	HPPA_BRIDGE_SAGA,	"Saga PCI Bridge" },
{HPPA_TYPE_FABRIC,	HPPA_FABRIC_DNACA,	"Halfdome DNA Central Agent" },
{HPPA_TYPE_FABRIC,	HPPA_FABRIC_TOGO,	"Halfdome TOGO Fabric Crossbar" },
{HPPA_TYPE_FABRIC,	HPPA_FABRIC_SAKURA,	"Halfdome Sakura Fabric Router" },
{ -1 }


code:
#	$OpenBSD: devlist2h.awk,v 1.6 2004/04/07 18:24:19 mickey Exp $

#
# Copyright (c) 1998-2003 Michael Shalayeff
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
# 1. Redistributions of source code must retain the above copyright
#    notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
#    notice, this list of conditions and the following disclaimer in the
#    documentation and/or other materials provided with the distribution.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
# INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
# SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
# STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
# THE POSSIBILITY OF SUCH DAMAGE.
#

BEGIN	{
	ncpu = 0;
	cpuh="cpudevs.h";
	cpud="cpudevs_data.h";
	SUBSEP = "_";
}

/^[ \t]*$/	{next}

/^[ \t]*\/\*/	{busted++}

/^[ \t]*#/	{next}

busted	{
	cp = match($0, /\*\//);
	if(!cp) {
		next;
	} else if (cp + 1 == length($0)) {
		busted = 0;
		next;
	} else {
		sub(/.*\*\//, "");
		busted = 0;
	}
}

# first line is rcsid, beware
NR == 1	{
	VERSION = $0;
	gsub("\\$", "", VERSION);

	printf("/*\n * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.\n" \
	       " * generated from:\n *\t%s\n */\n\n", VERSION) > cpud;
	printf("/*\n * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.\n" \
	       " * generated from:\n *\t%s\n */\n\n", VERSION) > cpuh;
}

$1 == "type"	{
	printf("#define\tHPPA_TYPE_%s\t%s\n", toupper($2), $3) > cpuh;
	types[tolower($2)] = toupper($2);
	next;
}

NR > 1 {
	if (tolower($1) in types) {
		printf("#define\tHPPA_%s_%s\t%s\n", toupper($1),
		       toupper($2), $3) > cpuh;
		printf("{HPPA_TYPE_%s,\tHPPA_%s_%s,\t\"", toupper($1),
		       toupper($1), toupper($2), $3) > cpud;
		f = 4;
		while (f <= NF) {
			sub(/[ \t]*/, "", $f);
			ep = match($f, /\*\//);
			if (busted && !ep) {
				f++;
				continue;
			}
			if (match($f, /\/\*/)) {
				if (ep) {
					sub(/\/\*/, "", $f);
				} else {
					sub(/\/\*.*$/, "", $f);
					busted++;
				}
			}
			if (ep) {
				gsub(/^.*\*\//, "", $f);
				busted = 0;
			}
			if (length($f)) {
				if (f > 4)
					printf (" ") > cpud;
				printf ("%s", $f) > cpud;
			}
			f++;
		}
		printf("\" },\n") > cpud;
	} else {
		printf("WHA at line %d\n", NR);
		exit(1);
	}
}

END	{
	if (busted) {
		print("unterminated comment at the EOF\n");
		exit(1);
	}
	printf("{ -1 }\n") > cpud;
}