code:
/*	$OpenBSD: asm.h,v 1.12 2013/07/05 21:10:50 miod Exp $ */
/*	$NetBSD: asm.h,v 1.9 1999/01/15 13:31:28 bouyer Exp $ */
/*
 * Copyright (c) 1982, 1993
 *	The Regents of the University of California.  All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of the University nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 *	@(#)DEFS.h	8.1 (Berkeley) 6/4/93
 */

#ifndef _MACHINE_ASM_H_
#define _MACHINE_ASM_H_

#define R0	0x001
#define R1	0x002
#define R2	0x004
#define R3	0x008
#define R4	0x010
#define R5	0x020
#define R6	0x040
#define R7 	0x080
#define R8	0x100
#define R9	0x200
#define R10	0x400
#define R11	0x800

#ifdef __ELF__
# define _C_LABEL(x)	x
#else
# ifdef __STDC__
#  define _C_LABEL(x)	_ ## x
# else
#  define _C_LABEL(x)	_/**/x
# endif
#endif

#define	_ASM_LABEL(x)	x

#ifdef __STDC__
# define __CONCAT(x,y)	x ## y
# define __STRING(x)	#x
#else
# define __CONCAT(x,y)	x/**/y
# define __STRING(x)	"x"
#endif

/* let kernels and others override entrypoint alignment */
#ifndef _ALIGN_TEXT
# define _ALIGN_TEXT .align 2
#endif

#define _ALTENTRY(x) \
	.globl x; .type x,@function; x:
#define	_ENTRY(x, regs) \
	.text; _ALIGN_TEXT; _ALTENTRY(x) .word regs

#if defined(PROF) || defined(GPROF)
# ifdef __ELF__
#  define _PROF_PROLOGUE	\
	.data; 1:; .long 0; .text; moval 1b,r0; jsb _ASM_LABEL(__mcount)
# else
#  define _PROF_PROLOGUE	\
	.data; 1:; .long 0; .text; moval 1b,r0; jsb _ASM_LABEL(mcount)
# endif
#else
# define _PROF_PROLOGUE
#endif

#define ENTRY(x, regs)			_ENTRY(_C_LABEL(x), regs); _PROF_PROLOGUE
#define ENTRY_NOPROFILE(x, regs)	_ENTRY(_C_LABEL(x), regs)
#define NENTRY(x, regs)			_ENTRY(_C_LABEL(x), regs)
#define ASENTRY(x, regs)		_ENTRY(_ASM_LABEL(x), regs); _PROF_PROLOGUE
#define ASENTRY_NOPROFILE(x, regs)	_ENTRY(_ASM_LABEL(x), regs)

#define ALTENTRY(x)		_ALTENTRY(_C_LABEL(x))
#define RCSID(x)		.text; .asciz x

#ifdef	__ELF__
#define	STRONG_ALIAS(alias,sym)						\
	.global alias;							\
	alias = sym
#define	WEAK_ALIAS(alias,sym)						\
	.weak alias;							\
	alias = sym
#else
#define	STRONG_ALIAS(alias,sym)						\
	.global _##alias;						\
	_##alias = _##sym
#define	WEAK_ALIAS(alias,sym)						\
	.weak _##alias;							\
	_##alias = _##sym
#endif

#ifdef __STDC__
#define	WARN_REFERENCES(sym,msg)					\
	.stabs msg ## ,30,0,0,0 ;					\
	.stabs __STRING(_C_LABEL(sym)) ## ,1,0,0,0
#else
#define	WARN_REFERENCES(sym,msg)					\
	.stabs msg,30,0,0,0 ;						\
	.stabs __STRING(_C_LABEL(sym)),1,0,0,0
#endif /* __STDC__ */

#endif /* _MACHINE_ASM_H_ */


code:
/*	$OpenBSD: atomic.h,v 1.9 2014/07/19 05:27:17 dlg Exp $	*/

/* Public Domain */

#ifndef _VAX_ATOMIC_H_
#define _VAX_ATOMIC_H_

#if defined(_KERNEL)

#include <machine/mtpr.h>
#include <machine/intr.h>

static __inline void
atomic_setbits_int(volatile unsigned int *uip, unsigned int v)
{
	int s;

	s = splhigh();
	*uip |= v;
	splx(s);
}

static __inline void
atomic_clearbits_int(volatile unsigned int *uip, unsigned int v)
{
	int s;

	s = splhigh();
	*uip &= ~v;
	splx(s);
}

static __inline unsigned int
atomic_add_int_nv_sp(volatile unsigned int *uip, unsigned int v)
{
	int s;
	unsigned int nv;

	s = splhigh();
	*uip += v;
	nv = *uip;
	splx(s);

	return nv;
}

static __inline unsigned int
atomic_sub_int_nv_sp(volatile unsigned int *uip, unsigned int v)
{
	int s;
	unsigned int nv;

	s = splhigh();
	*uip -= v;
	nv = *uip;
	splx(s);

	return nv;
}

static inline unsigned int
atomic_cas_uint_sp(unsigned int *p, unsigned int o, unsigned int n)
{
	int s;
	unsigned int ov;

	s = splhigh();
	ov = *p;
	if (ov == o)
		*p = n;
	splx(s);

	return ov;
}

static inline unsigned int
atomic_swap_uint_sp(unsigned int *p, unsigned int v)
{
	int s;
	unsigned int ov;

	s = splhigh();
	ov = *p;
	*p = v;
	splx(s);

	return ov;
}

#define	atomic_add_int_nv	atomic_add_int_nv_sp
#define	atomic_sub_int_nv	atomic_sub_int_nv_sp
#define	atomic_cas_uint		atomic_cas_uint_sp
#define	atomic_swap_uint	atomic_swap_uint_sp

#define	atomic_add_long_nv(p,v) \
	((unsigned long)atomic_add_int_nv((unsigned int *)p, (unsigned int)v))
#define	atomic_sub_long_nv(p,v) \
	((unsigned long)atomic_sub_int_nv((unsigned int *)p, (unsigned int)v))

#define	atomic_cas_ulong(p,o,n) \
	((unsigned long)atomic_cas_uint((unsigned int *)p, (unsigned int)o, \
	 (unsigned int)n))
#define	atomic_cas_ptr(p,o,n) \
	((void *)atomic_cas_uint((unsigned int *)p, (unsigned int)o, \
	 (unsigned int)n))

#define	atomic_swap_ulong(p,o) \
	((unsigned long)atomic_swap_uint((unsigned int *)p, (unsigned int)o)
#define	atomic_swap_ptr(p,o) \
	((void *)atomic_swap_uint((unsigned int *)p, (unsigned int)o))

static inline void
__sync_synchronize(void)
{
	__asm__ volatile ("" ::: "memory");
}

#endif /* defined(_KERNEL) */
#endif /* _VAX_ATOMIC_H_ */

license: unknown


code:
/*	$OpenBSD: bus.h,v 1.16 2011/03/23 16:54:37 pirofti Exp $	*/
/*	$NetBSD: bus.h,v 1.14 2000/06/26 04:56:13 simonb Exp $	*/

/*-
 * Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
 * All rights reserved.
 *
 * This code is derived from software contributed to The NetBSD Foundation
 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
 * NASA Ames Research Center.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

/*
 * Copyright (c) 1996 Charles M. Hannum.  All rights reserved.
 * Copyright (c) 1996 Christopher G. Demetriou.  All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *      This product includes software developed by Christopher G. Demetriou
 *	for the NetBSD Project.
 * 4. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef _MACHINE_BUS_H_
#define _MACHINE_BUS_H_

/*
 * Bus address and size types
 */
typedef u_long bus_addr_t;
typedef u_long bus_size_t;

/*
 * Access methods for bus resources and address space.
 */
typedef	struct vax_bus_space *bus_space_tag_t;
typedef	u_long bus_space_handle_t;

struct vax_bus_space {
	/* cookie */
	void		*vbs_cookie;

	/* mapping/unmapping */
	int		(*vbs_map)(void *, bus_addr_t, bus_size_t,
			    int, bus_space_handle_t *);
	void		(*vbs_unmap)(void *, bus_space_handle_t,
			    bus_size_t);
	int		(*vbs_subregion)(void *, bus_space_handle_t,
			    bus_size_t, bus_size_t, bus_space_handle_t *);

	/* allocation/deallocation */
	int		(*vbs_alloc)(void *, bus_addr_t, bus_addr_t,
			    bus_size_t, bus_size_t, bus_size_t, int,
			    bus_addr_t *, bus_space_handle_t *);
	void		(*vbs_free)(void *, bus_space_handle_t,
			    bus_size_t);

	/* get kernel virtual address */
	void *		(*vbs_vaddr)(void *, bus_space_handle_t);
};

/*
 *	int bus_space_map(bus_space_tag_t t, bus_addr_t addr,
 *	    bus_size_t size, int flags, bus_space_handle_t *bshp);
 *
 * Map a region of bus space.
 */

#define	BUS_SPACE_MAP_CACHEABLE		0x01
#define	BUS_SPACE_MAP_LINEAR		0x02
#define	BUS_SPACE_MAP_PREFETCHABLE	0x04

#define	bus_space_map(t, a, s, f, hp)					\
	(*(t)->vbs_map)((t)->vbs_cookie, (a), (s), (f), (hp))

/*
 *	int bus_space_unmap(bus_space_tag_t t,
 *	    bus_space_handle_t bsh, bus_size_t size);
 *
 * Unmap a region of bus space.
 */

#define bus_space_unmap(t, h, s)					\
	(*(t)->vbs_unmap)((t)->vbs_cookie, (h), (s))

/*
 *	int bus_space_subregion(bus_space_tag_t t,
 *	    bus_space_handle_t bsh, bus_size_t offset, bus_size_t size,
 *	    bus_space_handle_t *nbshp);
 *
 * Get a new handle for a subregion of an already-mapped area of bus space.
 */

#define bus_space_subregion(t, h, o, s, nhp)				\
	(*(t)->vbs_subregion)((t)->vbs_cookie, (h), (o), (s), (nhp))

/*
 *	int bus_space_alloc(bus_space_tag_t t, bus_addr_t rstart,
 *	    bus_addr_t rend, bus_size_t size, bus_size_t align,
 *	    bus_size_t boundary, int flags, bus_addr_t *addrp,
 *	    bus_space_handle_t *bshp);
 *
 * Allocate a region of bus space.
 */

#define bus_space_alloc(t, rs, re, s, a, b, f, ap, hp)			\
	(*(t)->vbs_alloc)((t)->vbs_cookie, (rs), (re), (s), (a), (b),   \
	    (f), (ap), (hp))

/*
 *	int bus_space_free(bus_space_tag_t t,
 *	    bus_space_handle_t bsh, bus_size_t size);
 *
 * Free a region of bus space.
 */

#define bus_space_free(t, h, s)						\
	(*(t)->vbs_free)((t)->vbs_cookie, (h), (s))

/*
 *	void *bus_space_vaddr(bus_space_tag_t t, bus_space_handle_t h);
 *
 * Get kernel virtual address.
 */

#define	bus_space_vaddr(t, h)						\
	(*(t)->vbs_vaddr)((t)->vbs_cookie, (h))

/*
 *	u_intN_t bus_space_read_N(bus_space_tag_t tag,
 *	    bus_space_handle_t bsh, bus_size_t offset);
 *
 * Read a 1, 2, 4, or 8 byte quantity from bus space
 * described by tag/handle/offset.
 */

#define	bus_space_read_1(t, h, o)					\
	    (*(volatile u_int8_t *)((h) + (o)))

#define	bus_space_read_2(t, h, o)					\
	    (*(volatile u_int16_t *)((h) + (o)))

#define	bus_space_read_4(t, h, o)					\
	    (*(volatile u_int32_t *)((h) + (o)))

#if 0	/* Cause a link error for bus_space_read_8 */
#define	bus_space_read_8(t, h, o)	!!! bus_space_read_8 unimplemented !!!
#endif

/*
 *	void bus_space_read_multi_N(bus_space_tag_t tag,
 *	    bus_space_handle_t bsh, bus_size_t offset,
 *	    u_intN_t *addr, size_t count);
 *
 * Read `count' 1, 2, 4, or 8 byte quantities from bus space
 * described by tag/handle/offset and copy into buffer provided.
 */
static __inline void vax_mem_read_multi_1(bus_space_tag_t,
	bus_space_handle_t, bus_size_t, u_int8_t *, size_t);
static __inline void vax_mem_read_multi_2(bus_space_tag_t,
	bus_space_handle_t, bus_size_t, u_int16_t *, size_t);
static __inline void vax_mem_read_multi_4(bus_space_tag_t,
	bus_space_handle_t, bus_size_t, u_int32_t *, size_t);

#define	bus_space_read_multi_1(t, h, o, a, c)				\
	vax_mem_read_multi_1((t), (h), (o), (a), (c))

#define bus_space_read_multi_2(t, h, o, a, c)				\
	vax_mem_read_multi_2((t), (h), (o), (a), (c))

#define bus_space_read_multi_4(t, h, o, a, c)				\
	vax_mem_read_multi_4((t), (h), (o), (a), (c))

#if 0	/* Cause a link error for bus_space_read_multi_8 */
#define	bus_space_read_multi_8	!!! bus_space_read_multi_8 unimplemented !!!
#endif

static __inline void
vax_mem_read_multi_1(t, h, o, a, c)
	bus_space_tag_t t;
	bus_space_handle_t h;
	bus_size_t o;
	u_int8_t *a;
	size_t c;
{
	const bus_addr_t addr = h + o;

	for (; c != 0; c--, a++)
		*a = *(volatile u_int8_t *)(addr);
}

static __inline void
vax_mem_read_multi_2(t, h, o, a, c)
	bus_space_tag_t t;
	bus_space_handle_t h;
	bus_size_t o;
	u_int16_t *a;
	size_t c;
{
	const bus_addr_t addr = h + o;

	for (; c != 0; c--, a++)
		*a = *(volatile u_int16_t *)(addr);
}

static __inline void
vax_mem_read_multi_4(t, h, o, a, c)
	bus_space_tag_t t;
	bus_space_handle_t h;
	bus_size_t o;
	u_int32_t *a;
	size_t c;
{
	const bus_addr_t addr = h + o;

	for (; c != 0; c--, a++)
		*a = *(volatile u_int32_t *)(addr);
}

/*
 *	void bus_space_read_region_N(bus_space_tag_t tag,
 *	    bus_space_handle_t bsh, bus_size_t offset,
 *	    u_intN_t *addr, size_t count);
 *
 * Read `count' 1, 2, 4, or 8 byte quantities from bus space
 * described by tag/handle and starting at `offset' and copy into
 * buffer provided.
 */

static __inline void vax_mem_read_region_1(bus_space_tag_t,
	bus_space_handle_t, bus_size_t, u_int8_t *, size_t);
static __inline void vax_mem_read_region_2(bus_space_tag_t,
	bus_space_handle_t, bus_size_t, u_int16_t *, size_t);
static __inline void vax_mem_read_region_4(bus_space_tag_t,
	bus_space_handle_t, bus_size_t, u_int32_t *, size_t);

#define	bus_space_read_region_1(t, h, o, a, c)				\
	vax_mem_read_region_1((t), (h), (o), (a), (c))

#define bus_space_read_region_2(t, h, o, a, c)				\
	vax_mem_read_region_2((t), (h), (o), (a), (c))

#define bus_space_read_region_4(t, h, o, a, c)				\
	vax_mem_read_region_4((t), (h), (o), (a), (c))

#if 0	/* Cause a link error for bus_space_read_region_8 */
#define	bus_space_read_region_8					\
			!!! bus_space_read_region_8 unimplemented !!!
#endif

static __inline void
vax_mem_read_region_1(t, h, o, a, c)
	bus_space_tag_t t;
	bus_space_handle_t h;
	bus_size_t o;
	u_int8_t *a;
	size_t c;
{
	bus_addr_t addr = h + o;

	for (; c != 0; c--, addr++, a++)
		*a = *(volatile u_int8_t *)(addr);
}

static __inline void
vax_mem_read_region_2(t, h, o, a, c)
	bus_space_tag_t t;
	bus_space_handle_t h;
	bus_size_t o;
	u_int16_t *a;
	size_t c;
{
	bus_addr_t addr = h + o;

	for (; c != 0; c--, addr++, a++)
		*a = *(volatile u_int16_t *)(addr);
}

static __inline void
vax_mem_read_region_4(t, h, o, a, c)
	bus_space_tag_t t;
	bus_space_handle_t h;
	bus_size_t o;
	u_int32_t *a;
	size_t c;
{
	bus_addr_t addr = h + o;

	for (; c != 0; c--, addr++, a++)
		*a = *(volatile u_int32_t *)(addr);
}

/*
 *	void bus_space_write_N(bus_space_tag_t tag,
 *	    bus_space_handle_t bsh, bus_size_t offset,
 *	    u_intN_t value);
 *
 * Write the 1, 2, 4, or 8 byte value `value' to bus space
 * described by tag/handle/offset.
 */

#define	bus_space_write_1(t, h, o, v)					\
	((void)(*(volatile u_int8_t *)((h) + (o)) = (v)))

#define	bus_space_write_2(t, h, o, v)					\
	((void)(*(volatile u_int16_t *)((h) + (o)) = (v)))

#define	bus_space_write_4(t, h, o, v)					\
	((void)(*(volatile u_int32_t *)((h) + (o)) = (v)))

#if 0	/* Cause a link error for bus_space_write_8 */
#define	bus_space_write_8	!!! bus_space_write_8 not implemented !!!
#endif

/*
 *	void bus_space_write_multi_N(bus_space_tag_t tag,
 *	    bus_space_handle_t bsh, bus_size_t offset,
 *	    const u_intN_t *addr, size_t count);
 *
 * Write `count' 1, 2, 4, or 8 byte quantities from the buffer
 * provided to bus space described by tag/handle/offset.
 */
static __inline void vax_mem_write_multi_1(bus_space_tag_t,
	bus_space_handle_t, bus_size_t, const u_int8_t *, size_t);
static __inline void vax_mem_write_multi_2(bus_space_tag_t,
	bus_space_handle_t, bus_size_t, const u_int16_t *, size_t);
static __inline void vax_mem_write_multi_4(bus_space_tag_t,
	bus_space_handle_t, bus_size_t, const u_int32_t *, size_t);

#define	bus_space_write_multi_1(t, h, o, a, c)				\
	vax_mem_write_multi_1((t), (h), (o), (a), (c))

#define bus_space_write_multi_2(t, h, o, a, c)				\
	vax_mem_write_multi_2((t), (h), (o), (a), (c))

#define bus_space_write_multi_4(t, h, o, a, c)				\
	vax_mem_write_multi_4((t), (h), (o), (a), (c))

#if 0	/* Cause a link error for bus_space_write_multi_8 */
#define	bus_space_write_multi_8(t, h, o, a, c)				\
			!!! bus_space_write_multi_8 unimplemented !!!
#endif

static __inline void
vax_mem_write_multi_1(t, h, o, a, c)
	bus_space_tag_t t;
	bus_space_handle_t h;
	bus_size_t o;
	const u_int8_t *a;
	size_t c;
{
	const bus_addr_t addr = h + o;

	for (; c != 0; c--, a++)
		*(volatile u_int8_t *)(addr) = *a;
}

static __inline void
vax_mem_write_multi_2(t, h, o, a, c)
	bus_space_tag_t t;
	bus_space_handle_t h;
	bus_size_t o;
	const u_int16_t *a;
	size_t c;
{
	const bus_addr_t addr = h + o;

	for (; c != 0; c--, a++)
		*(volatile u_int16_t *)(addr) = *a;
}

static __inline void
vax_mem_write_multi_4(t, h, o, a, c)
	bus_space_tag_t t;
	bus_space_handle_t h;
	bus_size_t o;
	const u_int32_t *a;
	size_t c;
{
	const bus_addr_t addr = h + o;

	for (; c != 0; c--, a++)
		*(volatile u_int32_t *)(addr) = *a;
}

/*
 *	void bus_space_write_region_N(bus_space_tag_t tag,
 *	    bus_space_handle_t bsh, bus_size_t offset,
 *	    const u_intN_t *addr, size_t count);
 *
 * Write `count' 1, 2, 4, or 8 byte quantities from the buffer provided
 * to bus space described by tag/handle starting at `offset'.
 */
static __inline void vax_mem_write_region_1(bus_space_tag_t,
	bus_space_handle_t, bus_size_t, const u_int8_t *, size_t);
static __inline void vax_mem_write_region_2(bus_space_tag_t,
	bus_space_handle_t, bus_size_t, const u_int16_t *, size_t);
static __inline void vax_mem_write_region_4(bus_space_tag_t,
	bus_space_handle_t, bus_size_t, const u_int32_t *, size_t);

#define	bus_space_write_region_1(t, h, o, a, c)				\
	vax_mem_write_region_1((t), (h), (o), (a), (c))

#define bus_space_write_region_2(t, h, o, a, c)				\
	vax_mem_write_region_2((t), (h), (o), (a), (c))

#define bus_space_write_region_4(t, h, o, a, c)				\
	vax_mem_write_region_4((t), (h), (o), (a), (c))

#if 0	/* Cause a link error for bus_space_write_region_8 */
#define	bus_space_write_region_8					\
			!!! bus_space_write_region_8 unimplemented !!!
#endif

static __inline void
vax_mem_write_region_1(t, h, o, a, c)
	bus_space_tag_t t;
	bus_space_handle_t h;
	bus_size_t o;
	const u_int8_t *a;
	size_t c;
{
	bus_addr_t addr = h + o;

	for (; c != 0; c--, addr++, a++)
		*(volatile u_int8_t *)(addr) = *a;
}

static __inline void
vax_mem_write_region_2(t, h, o, a, c)
	bus_space_tag_t t;
	bus_space_handle_t h;
	bus_size_t o;
	const u_int16_t *a;
	size_t c;
{
	bus_addr_t addr = h + o;

	for (; c != 0; c--, addr++, a++)
		*(volatile u_int16_t *)(addr) = *a;
}

static __inline void
vax_mem_write_region_4(t, h, o, a, c)
	bus_space_tag_t t;
	bus_space_handle_t h;
	bus_size_t o;
	const u_int32_t *a;
	size_t c;
{
	bus_addr_t addr = h + o;

	for (; c != 0; c--, addr++, a++)
		*(volatile u_int32_t *)(addr) = *a;
}

/*
 *	void bus_space_set_multi_N(bus_space_tag_t tag,
 *	    bus_space_handle_t bsh, bus_size_t offset, u_intN_t val,
 *	    size_t count);
 *
 * Write the 1, 2, 4, or 8 byte value `val' to bus space described
 * by tag/handle/offset `count' times.
 */

static __inline void vax_mem_set_multi_1(bus_space_tag_t,
	bus_space_handle_t, bus_size_t, u_int8_t, size_t);
static __inline void vax_mem_set_multi_2(bus_space_tag_t,
	bus_space_handle_t, bus_size_t, u_int16_t, size_t);
static __inline void vax_mem_set_multi_4(bus_space_tag_t,
	bus_space_handle_t, bus_size_t, u_int32_t, size_t);

#define	bus_space_set_multi_1(t, h, o, v, c)				\
	vax_mem_set_multi_1((t), (h), (o), (v), (c))

#define	bus_space_set_multi_2(t, h, o, v, c)				\
	vax_mem_set_multi_2((t), (h), (o), (v), (c))

#define	bus_space_set_multi_4(t, h, o, v, c)				\
	vax_mem_set_multi_4((t), (h), (o), (v), (c))

static __inline void
vax_mem_set_multi_1(t, h, o, v, c)
	bus_space_tag_t t;
	bus_space_handle_t h;
	bus_size_t o;
	u_int8_t v;
	size_t c;
{
	bus_addr_t addr = h + o;

	while (c--)
		*(volatile u_int8_t *)(addr) = v;
}

static __inline void
vax_mem_set_multi_2(t, h, o, v, c)
	bus_space_tag_t t;
	bus_space_handle_t h;
	bus_size_t o;
	u_int16_t v;
	size_t c;
{
	bus_addr_t addr = h + o;

	while (c--)
		*(volatile u_int16_t *)(addr) = v;
}

static __inline void
vax_mem_set_multi_4(t, h, o, v, c)
	bus_space_tag_t t;
	bus_space_handle_t h;
	bus_size_t o;
	u_int32_t v;
	size_t c;
{
	bus_addr_t addr = h + o;

	while (c--)
		*(volatile u_int32_t *)(addr) = v;
}

#if 0	/* Cause a link error for bus_space_set_multi_8 */
#define	bus_space_set_multi_8 !!! bus_space_set_multi_8 unimplemented !!!
#endif

/*
 *	void bus_space_set_region_N(bus_space_tag_t tag,
 *	    bus_space_handle_t bsh, bus_size_t offset, u_intN_t val,
 *	    size_t count);
 *
 * Write `count' 1, 2, 4, or 8 byte value `val' to bus space described
 * by tag/handle starting at `offset'.
 */

static __inline void vax_mem_set_region_1(bus_space_tag_t,
	bus_space_handle_t, bus_size_t, u_int8_t, size_t);
static __inline void vax_mem_set_region_2(bus_space_tag_t,
	bus_space_handle_t, bus_size_t, u_int16_t, size_t);
static __inline void vax_mem_set_region_4(bus_space_tag_t,
	bus_space_handle_t, bus_size_t, u_int32_t, size_t);

#define	bus_space_set_region_1(t, h, o, v, c)				\
	vax_mem_set_region_1((t), (h), (o), (v), (c))

#define	bus_space_set_region_2(t, h, o, v, c)				\
	vax_mem_set_region_2((t), (h), (o), (v), (c))

#define	bus_space_set_region_4(t, h, o, v, c)				\
	vax_mem_set_region_4((t), (h), (o), (v), (c))

static __inline void
vax_mem_set_region_1(t, h, o, v, c)
	bus_space_tag_t t;
	bus_space_handle_t h;
	bus_size_t o;
	u_int8_t v;
	size_t c;
{
	bus_addr_t addr = h + o;

	for (; c != 0; c--, addr++)
		*(volatile u_int8_t *)(addr) = v;
}

static __inline void
vax_mem_set_region_2(t, h, o, v, c)
	bus_space_tag_t t;
	bus_space_handle_t h;
	bus_size_t o;
	u_int16_t v;
	size_t c;
{
	bus_addr_t addr = h + o;

	for (; c != 0; c--, addr += 2)
		*(volatile u_int16_t *)(addr) = v;
}

static __inline void
vax_mem_set_region_4(t, h, o, v, c)
	bus_space_tag_t t;
	bus_space_handle_t h;
	bus_size_t o;
	u_int32_t v;
	size_t c;
{
	bus_addr_t addr = h + o;

	for (; c != 0; c--, addr += 4)
		*(volatile u_int32_t *)(addr) = v;
}

#if 0	/* Cause a link error for bus_space_set_region_8 */
#define	bus_space_set_region_8	!!! bus_space_set_region_8 unimplemented !!!
#endif

/*
 *	void bus_space_copy_N(bus_space_tag_t tag,
 *	    bus_space_handle_t bsh1, bus_size_t off1,
 *	    bus_space_handle_t bsh2, bus_size_t off2,
 *	    size_t count);
 *
 * Copy `count' 1, 2, 4, or 8 byte values from bus space starting
 * at tag/bsh1/off1 to bus space starting at tag/bsh2/off2.
 */

static __inline void vax_mem_copy_1(bus_space_tag_t,
	bus_space_handle_t, bus_size_t, bus_space_handle_t,
	bus_size_t, size_t);
static __inline void vax_mem_copy_2(bus_space_tag_t,
	bus_space_handle_t, bus_size_t, bus_space_handle_t,
	bus_size_t, size_t);
static __inline void vax_mem_copy_4(bus_space_tag_t,
	bus_space_handle_t, bus_size_t, bus_space_handle_t,
	bus_size_t, size_t);

#define	bus_space_copy_1(t, h1, o1, h2, o2, c)				\
	vax_mem_copy_1((t), (h1), (o1), (h2), (o2), (c))

#define	bus_space_copy_2(t, h1, o1, h2, o2, c)				\
	vax_mem_copy_2((t), (h1), (o1), (h2), (o2), (c))

#define	bus_space_copy_4(t, h1, o1, h2, o2, c)				\
	vax_mem_copy_4((t), (h1), (o1), (h2), (o2), (c))

static __inline void
vax_mem_copy_1(t, h1, o1, h2, o2, c)
	bus_space_tag_t t;
	bus_space_handle_t h1;
	bus_size_t o1;
	bus_space_handle_t h2;
	bus_size_t o2;
	size_t c;
{
	bus_addr_t addr1 = h1 + o1;
	bus_addr_t addr2 = h2 + o2;

	if (addr1 >= addr2) {
		/* src after dest: copy forward */
		for (; c != 0; c--, addr1++, addr2++)
			*(volatile u_int8_t *)(addr2) =
			    *(volatile u_int8_t *)(addr1);
	} else {
		/* dest after src: copy backwards */
		for (addr1 += (c - 1), addr2 += (c - 1);
		    c != 0; c--, addr1--, addr2--)
			*(volatile u_int8_t *)(addr2) =
			    *(volatile u_int8_t *)(addr1);
	}
}

static __inline void
vax_mem_copy_2(t, h1, o1, h2, o2, c)
	bus_space_tag_t t;
	bus_space_handle_t h1;
	bus_size_t o1;
	bus_space_handle_t h2;
	bus_size_t o2;
	size_t c;
{
	bus_addr_t addr1 = h1 + o1;
	bus_addr_t addr2 = h2 + o2;

	if (addr1 >= addr2) {
		/* src after dest: copy forward */
		for (; c != 0; c--, addr1 += 2, addr2 += 2)
			*(volatile u_int16_t *)(addr2) =
			    *(volatile u_int16_t *)(addr1);
	} else {
		/* dest after src: copy backwards */
		for (addr1 += 2 * (c - 1), addr2 += 2 * (c - 1);
		    c != 0; c--, addr1 -= 2, addr2 -= 2)
			*(volatile u_int16_t *)(addr2) =
			    *(volatile u_int16_t *)(addr1);
	}
}

static __inline void
vax_mem_copy_4(t, h1, o1, h2, o2, c)
	bus_space_tag_t t;
	bus_space_handle_t h1;
	bus_size_t o1;
	bus_space_handle_t h2;
	bus_size_t o2;
	size_t c;
{
	bus_addr_t addr1 = h1 + o1;
	bus_addr_t addr2 = h2 + o2;

	if (addr1 >= addr2) {
		/* src after dest: copy forward */
		for (; c != 0; c--, addr1 += 4, addr2 += 4)
			*(volatile u_int32_t *)(addr2) =
			    *(volatile u_int32_t *)(addr1);
	} else {
		/* dest after src: copy backwards */
		for (addr1 += 4 * (c - 1), addr2 += 4 * (c - 1);
		    c != 0; c--, addr1 -= 4, addr2 -= 4)
			*(volatile u_int32_t *)(addr2) =
			    *(volatile u_int32_t *)(addr1);
	}
}

#if 0	/* Cause a link error for bus_space_copy_8 */
#define	bus_space_copy_8	!!! bus_space_copy_8 unimplemented !!!
#endif

/*
 * Bus read/write barrier methods.
 *
 *	void bus_space_barrier(bus_space_tag_t tag,
 *	    bus_space_handle_t bsh, bus_size_t offset,
 *	    bus_size_t len, int flags);
 *
 * Note: the vax does not currently require barriers, but we must
 * provide the flags to MI code.
 */
#define	bus_space_barrier(t, h, o, l, f)	\
	((void)((void)(t), (void)(h), (void)(o), (void)(l), (void)(f)))
#define	BUS_SPACE_BARRIER_READ	0x01		/* force read barrier */
#define	BUS_SPACE_BARRIER_WRITE	0x02		/* force write barrier */

/*
 * Flags used in various bus DMA methods.
 */
#define	BUS_DMA_WAITOK		0x000	/* safe to sleep (pseudo-flag) */
#define	BUS_DMA_NOWAIT		0x001	/* not safe to sleep */
#define	BUS_DMA_ALLOCNOW	0x002	/* perform resource allocation now */
#define	BUS_DMA_COHERENT	0x004	/* hint: map memory DMA coherent */
#define	BUS_DMA_BUS1		0x010	/* placeholders for bus functions... */
#define	BUS_DMA_BUS2		0x020
#define	BUS_DMA_BUS3		0x040
#define	BUS_DMA_BUS4		0x080
#define	BUS_DMA_STREAMING	0x100	/* hint: sequential, unidirectional */
#define	BUS_DMA_READ		0x200	/* mapping is device -> memory only */
#define	BUS_DMA_WRITE		0x400	/* mapping is memory -> device only */
#define	BUS_DMA_ZERO		0x800	/* zero memory in dmamem_alloc */

#define	VAX_BUS_DMA_SPILLPAGE	BUS_DMA_BUS1	/* VS4000 kludge */
/*
 * Private flags stored in the DMA map.
 */
#define DMAMAP_HAS_SGMAP	0x80000000	/* sgva/len are valid */

/* Forwards needed by prototypes below. */
struct mbuf;
struct uio;
struct vax_sgmap;

/*
 * Operations performed by bus_dmamap_sync().
 */
#define	BUS_DMASYNC_PREREAD	0x01	/* pre-read synchronization */
#define	BUS_DMASYNC_POSTREAD	0x02	/* post-read synchronization */
#define	BUS_DMASYNC_PREWRITE	0x04	/* pre-write synchronization */
#define	BUS_DMASYNC_POSTWRITE	0x08	/* post-write synchronization */

typedef struct vax_bus_dma_tag	*bus_dma_tag_t;
typedef struct vax_bus_dmamap	*bus_dmamap_t;

/*
 *	bus_dma_segment_t
 *
 *	Describes a single contiguous DMA transaction.  Values
 *	are suitable for programming into DMA registers.
 */
struct vax_bus_dma_segment {
	bus_addr_t	ds_addr;	/* DMA address */
	bus_size_t	ds_len;		/* length of transfer */
};
typedef struct vax_bus_dma_segment	bus_dma_segment_t;

struct proc;

/*
 *	bus_dma_tag_t
 *
 *	A machine-dependent opaque type describing the implementation of
 *	DMA for a given bus.
 */
struct vax_bus_dma_tag {
	void	*_cookie;		/* cookie used in the guts */
	bus_addr_t _wbase;		/* DMA window base */
	bus_size_t _wsize;		/* DMA window size */

	/*
	 * Some chipsets have a built-in boundary constraint, independent
	 * of what the device requests.  This allows that boundary to
	 * be specified.  If the device has a more restrictive contraint,
	 * the map will use that, otherwise this boundary will be used.
	 * This value is ignored if 0.
	 */
	bus_size_t _boundary;

	/*
	 * A bus may have more than one SGMAP window, so SGMAP
	 * windows also get a pointer to their SGMAP state.
	 */
	struct vax_sgmap *_sgmap;

	/*
	 * DMA mapping methods.
	 */
	int	(*_dmamap_create)(bus_dma_tag_t, bus_size_t, int,
		    bus_size_t, bus_size_t, int, bus_dmamap_t *);
	void	(*_dmamap_destroy)(bus_dma_tag_t, bus_dmamap_t);
	int	(*_dmamap_load)(bus_dma_tag_t, bus_dmamap_t, void *,
		    bus_size_t, struct proc *, int);
	int	(*_dmamap_load_mbuf)(bus_dma_tag_t, bus_dmamap_t,
		    struct mbuf *, int);
	int	(*_dmamap_load_uio)(bus_dma_tag_t, bus_dmamap_t,
		    struct uio *, int);
	int	(*_dmamap_load_raw)(bus_dma_tag_t, bus_dmamap_t,
		    bus_dma_segment_t *, int, bus_size_t, int);
	void	(*_dmamap_unload)(bus_dma_tag_t, bus_dmamap_t);
	void	(*_dmamap_sync)(bus_dma_tag_t, bus_dmamap_t,
		    bus_addr_t, bus_size_t, int);

	/*
	 * DMA memory utility functions.
	 */
	int	(*_dmamem_alloc)(bus_dma_tag_t, bus_size_t, bus_size_t,
		    bus_size_t, bus_dma_segment_t *, int, int *, int);
	void	(*_dmamem_free)(bus_dma_tag_t,
		    bus_dma_segment_t *, int);
	int	(*_dmamem_map)(bus_dma_tag_t, bus_dma_segment_t *,
		    int, size_t, caddr_t *, int);
	void	(*_dmamem_unmap)(bus_dma_tag_t, caddr_t, size_t);
	paddr_t	(*_dmamem_mmap)(bus_dma_tag_t, bus_dma_segment_t *,
		    int, off_t, int, int);
};

#define	bus_dmamap_create(t, s, n, m, b, f, p)			\
	(*(t)->_dmamap_create)((t), (s), (n), (m), (b), (f), (p))
#define	bus_dmamap_destroy(t, p)				\
	(*(t)->_dmamap_destroy)((t), (p))
#define	bus_dmamap_load(t, m, b, s, p, f)			\
	(*(t)->_dmamap_load)((t), (m), (b), (s), (p), (f))
#define	bus_dmamap_load_mbuf(t, m, b, f)			\
	(*(t)->_dmamap_load_mbuf)((t), (m), (b), (f))
#define	bus_dmamap_load_uio(t, m, u, f)				\
	(*(t)->_dmamap_load_uio)((t), (m), (u), (f))
#define	bus_dmamap_load_raw(t, m, sg, n, s, f)			\
	(*(t)->_dmamap_load_raw)((t), (m), (sg), (n), (s), (f))
#define	bus_dmamap_unload(t, p)					\
	(*(t)->_dmamap_unload)((t), (p))
#define	bus_dmamap_sync(t, p, o, l, ops)			\
	(*(t)->_dmamap_sync)((t), (p), (o), (l), (ops))
#define	bus_dmamem_alloc(t, s, a, b, sg, n, r, f)		\
	(*(t)->_dmamem_alloc)((t), (s), (a), (b), (sg), (n), (r), (f))
#define	bus_dmamem_free(t, sg, n)				\
	(*(t)->_dmamem_free)((t), (sg), (n))
#define	bus_dmamem_map(t, sg, n, s, k, f)			\
	(*(t)->_dmamem_map)((t), (sg), (n), (s), (k), (f))
#define	bus_dmamem_unmap(t, k, s)				\
	(*(t)->_dmamem_unmap)((t), (k), (s))
#define	bus_dmamem_mmap(t, sg, n, o, p, f)			\
	(*(t)->_dmamem_mmap)((t), (sg), (n), (o), (p), (f))

/*
 *	bus_dmamap_t
 *
 *	Describes a DMA mapping.
 */
struct vax_bus_dmamap {
	/*
	 * PRIVATE MEMBERS: not for use by machine-independent code.
	 */
	bus_size_t	_dm_size;	/* largest DMA transfer mappable */
	int		_dm_segcnt;	/* number of segs this map can map */
	bus_size_t	_dm_maxsegsz;	/* largest possible segment */
	bus_size_t	_dm_boundary;	/* don't cross this */
	int		_dm_flags;	/* misc. flags */

	/*
	 * This is used only for SGMAP-mapped DMA, but we keep it
	 * here to avoid pointless indirection.
	 */
	int		_dm_pteidx;	/* PTE index */
	int		_dm_ptecnt;	/* PTE count */
	u_long		_dm_sgva;	/* allocated sgva */
	bus_size_t	_dm_sgvalen;	/* svga length */

	/*
	 * PUBLIC MEMBERS: these are used by machine-independent code.
	 */
	bus_size_t	dm_mapsize;	/* size of the mapping */
	int		dm_nsegs;	/* # valid segments in mapping */
	bus_dma_segment_t dm_segs[1];	/* segments; variable length */
};

#ifdef _VAX_BUS_DMA_PRIVATE
int	_bus_dmamap_create(bus_dma_tag_t, bus_size_t, int, bus_size_t,
	    bus_size_t, int, bus_dmamap_t *);
void	_bus_dmamap_destroy(bus_dma_tag_t, bus_dmamap_t);

int	_bus_dmamap_load(bus_dma_tag_t, bus_dmamap_t,
	    void *, bus_size_t, struct proc *, int);
int	_bus_dmamap_load_mbuf(bus_dma_tag_t,
	    bus_dmamap_t, struct mbuf *, int);
int	_bus_dmamap_load_uio(bus_dma_tag_t,
	    bus_dmamap_t, struct uio *, int);
int	_bus_dmamap_load_raw(bus_dma_tag_t,
	    bus_dmamap_t, bus_dma_segment_t *, int, bus_size_t, int);

void	_bus_dmamap_unload(bus_dma_tag_t, bus_dmamap_t);
void	_bus_dmamap_sync(bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
	    bus_size_t, int);

int	_bus_dmamem_alloc(bus_dma_tag_t tag, bus_size_t size,
	    bus_size_t alignment, bus_size_t boundary,
	    bus_dma_segment_t *segs, int nsegs, int *rsegs, int flags);
void	_bus_dmamem_free(bus_dma_tag_t tag, bus_dma_segment_t *segs,
	    int nsegs);
int	_bus_dmamem_map(bus_dma_tag_t tag, bus_dma_segment_t *segs,
	    int nsegs, size_t size, caddr_t *kvap, int flags);
void	_bus_dmamem_unmap(bus_dma_tag_t tag, caddr_t kva,
	    size_t size);
paddr_t	_bus_dmamem_mmap(bus_dma_tag_t tag, bus_dma_segment_t *segs,
	    int nsegs, off_t off, int prot, int flags);
#endif /* _VAX_BUS_DMA_PRIVATE */

#endif /* _MACHINE_BUS_H_ */


code:
/*	$OpenBSD: cca.h,v 1.1 2008/08/18 23:25:53 miod Exp $	*/
/*	$NetBSD: cca.h,v 1.2 2008/03/11 05:34:02 matt Exp $	*/

/*
 * Copyright (c) 2008 Miodrag Vallat.
 *
 * Permission to use, copy, modify, and distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */
/*
 * Copyright (c) 2000 Ludd, University of Lule}, Sweden. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *      This product includes software developed at Ludd, University of
 *      Lule}, Sweden and its contributors.
 * 4. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/*
 * Console Communication Area (CCA) layout description.
 *
 * Based on NetBSD/vax <machine/cca.h>, further reconstructed from the
 * description in VAX 6000 Model 600 System Technical User's Guide
 * (660eatm1.pdf)
 */

struct cca {
	struct cca *cca_base;	/* Physical base address of block */
	uint16_t cca_size;	/* Size of this struct */
	uint16_t cca_id;	/* 'CC' */
	uint8_t  cca_nproc;	/* max number of CPUs */
	uint8_t  cca_cksum;	/* Checksum of all earlier bytes */
	uint8_t  cca_flags;
#define	CCAF_BOOTIP		0x01	/* bootstrap in progress */
#define	CCAF_REBOOT		0x10	/* reboot requested */
#define	CCAF_REPROMPT		0x20	/* trigger the prom prompt */
#define	CCAF_DISABLE_SECONDARY	0x40	/* ignore messages from secondaries */
	uint8_t  cca_revision;

	uint64_t cca_ready;	/* Data ready? */
	uint64_t cca_console;	/* Processors in console mode */
	uint64_t cca_enabled;	/* enabled/disabled */
	uint32_t cca_bitmapsz;	/* Size of memory bitmap */
	uint32_t cca_bitmap;	/* Address of memory bitmap */
	uint32_t cca_bmcksum;	/* Bitmap checksum */
	uint8_t	 cca_tknode;	/* TK nodes of boot device */
#define	CCA_TKN_VAXBI_MASK	0x0f
#define	CCA_TKN_VAXBI_SHIFT	0
#define	CCA_TKN_XMI_MASK	0xf0
#define	CCA_TKN_XMI_SHIFT	4
	uint8_t	 cca_pad0[3];
	uint64_t cca_starting;	/* Processors currently starting */
	uint64_t cca_restart;	/* Processors currently restarting */
	uint8_t	 cca_primary;	/* XMI node of boot processor */
	uint8_t	 cca_power;
	uint16_t cca_sernum_ext;
	uint32_t cca_pad1[2];
	uint64_t cca_halted;	/* Processors currently halted by user */
	uint8_t  cca_sernum[8];	/* Serial number */
/* CPU revisions */
	struct {
		uint8_t	 cr_compat;	/* cpu compatibility group */
		uint8_t	 cr_pad0[3];
		uint32_t cr_modulerev;	/* ascii module revision */
	} cca_revs[16];
	uint64_t cca_vecenab;	/* Processors with enabled vector processors */
	uint64_t cca_vecwork;	/* Processors with working vector processors */
	uint32_t cca_vecrevs[16];/* Vector processor revisions */
	uint32_t cca_console_xpgr[16];
	uint32_t cca_entry_xpgr[16];
	uint8_t  cca_pad2[80];	/* pad to VAX_NBPG */
/* Inter-CPU communication structs */
	struct {
		uint8_t	 cc_flags;	/* Status flags */
#define CCACCF_RXRDY	0x01	/* has message in rxbuf */
#define	CCACCF_DEST	0x02	/* currently sending to zdst */
#define	CCACCF_SRC	0x04	/* currently receiving from zsrc */
#define	CCACCF_ALT	0x08	/* unable to communicate through cca */
		uint8_t	 cc_zdst;	/* Node sending to */
		uint8_t	 cc_zsrc;	/* Node sending from */
		uint8_t	 cc_znid;	/* Originating node if not zsrc */
		uint8_t	 cc_txlen;	/* Length of transmit message */
		uint8_t	 cc_rxlen;	/* Length of receive message */
		uint16_t cc_rxcd;
#define	CCACC_RX_DATA_MASK	0x00ff	/* character received */
#define	CCACC_RX_DATA_SHIFT	0
#define	CCACC_RX_NODE_MASK	0x0f00	/* originating node */
#define	CCACC_RX_NODE_SHIFT	8
#define	CCACC_RX_DATA_READY	0x8000	/* rxcd assembled */
		char	 cc_txbuf[80];	/* Transmit buffer */
		char	 cc_rxbuf[80];	/* Receive buffer */
	} cca_cc[16];
};

#ifdef _KERNEL
extern	struct cca *cca;
#endif


code:
/*	$OpenBSD: cdefs.h,v 1.9 2013/07/05 21:10:50 miod Exp $	*/

/*
 * Written by J.T. Conklin <jtc@wimsey.com> 01/17/95.
 * Public domain.
 */

#ifndef	_MACHINE_CDEFS_H_
#define	_MACHINE_CDEFS_H_

#define __warn_references(sym,msg)				\
	__asm__(".section .gnu.warning." __STRING(sym)		\
	    " ; .ascii \"" msg "\" ; .text")
#define __strong_alias(alias,sym)			\
	__asm__(".global " __STRING(alias) " ; " __STRING(alias)	\
	    " = " __STRING(sym))
#define __weak_alias(alias,sym)					\
	__asm__(".weak " __STRING(alias) " ; " __STRING(alias)	\
	    " = " __STRING(sym))

#endif /* !_MACHINE_CDEFS_H_ */


code:
/*	$OpenBSD: clock.h,v 1.10 2015/02/07 00:09:09 miod Exp $ */
/*	$NetBSD: clock.h,v 1.4 1999/09/06 19:52:53 ragge Exp $ */
/*
 * Copyright (c) 1996 Ludd, University of Lule}, Sweden.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *	This product includes software developed at Ludd, University of
 *	Lule}, Sweden and its contributors.
 * 4. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/*
 * Time constants. These are unlikely to change.
 */
#define IS_LEAPYEAR(y) (((y % 4) == 0) && (y % 100))

#define SEC_PER_MIN	(60)
#define SEC_PER_HOUR	(SEC_PER_MIN * 60)
#define SEC_PER_DAY	(SEC_PER_HOUR * 24)
#define DAYSPERYEAR(y)	(IS_LEAPYEAR(y) ? 366 : 365)
#define SECPERYEAR(y)	(DAYSPERYEAR(y) * SEC_PER_DAY)

#define TODRBASE	(1 << 28) /* Rumours say it comes from VMS */

#define	SEC_OFF		0
#define	MIN_OFF		2
#define	HR_OFF		4
#define	WDAY_OFF	6
#define	DAY_OFF		7
#define	MON_OFF		8
#define	YR_OFF		9
#define	CSRA_OFF	10
#define	CSRB_OFF	11
#define	CSRD_OFF	13

#define	CSRA_UIP	0200
#define	CSRB_SET	0200
#define	CSRB_24		0002
#define	CSRB_DM		0004
#define	CSRD_VRT	0200

/* ICCS bits */

#define	ICCS_ERR	0x80000000	/* lost tick */
#define	ICCS_OFLOW	0x00000080	/* icr overflow */
#define	ICCS_INTENA	0x00000040	/* interrupt enable */
#define	ICCS_INCR	0x00000020	/* increment (if not running) */
#define	ICCS_RESET	0x00000010	/* reset to nicr */
#define	ICCS_RUN	0x00000001	/* enable */

/* Var's used when dealing with clock chip */
extern	volatile short *clk_page;
extern	int clk_adrshift, clk_tweak;

/* Prototypes */
void	icr_hardclock(struct clockframe *);
int	generic_clkread(struct timespec *, time_t);
void	generic_clkwrite(void);
int	chip_clkread(struct timespec *, time_t);
void	chip_clkwrite(void);

int	yeartonum(int);
int	numtoyear(int);


code:
/*	$OpenBSD: cpu.h,v 1.48 2015/02/07 00:20:53 miod Exp $	*/
/*	$NetBSD: cpu.h,v 1.41 1999/10/21 20:01:36 ragge Exp $	*/

/*
 * Copyright (c) 1994 Ludd, University of Lule}, Sweden
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *      This product includes software developed at Ludd, University of Lule}
 * 4. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef _MACHINE_CPU_H_
#define _MACHINE_CPU_H_
#ifdef _KERNEL

#include <sys/device.h>
#include <sys/evcount.h>

#include <machine/mtpr.h>
#include <machine/pte.h>
#include <machine/pcb.h>
#include <machine/uvax.h>
#include <machine/psl.h>
#include <machine/trap.h>
#include <machine/intr.h>

#include <sys/sched.h>
struct cpu_info {
	struct proc *ci_curproc;

	struct schedstate_percpu ci_schedstate; /* scheduler state */
	u_int32_t 		ci_randseed;
#ifdef DIAGNOSTIC
	int	ci_mutex_level;
#endif
#ifdef GPROF
	struct gmonparam *ci_gmon;
#endif
};

extern struct cpu_info cpu_info_store;
#define	curcpu()	(&cpu_info_store)
#define cpu_number()	0
#define CPU_IS_PRIMARY(ci)	1
#define CPU_INFO_ITERATOR	int
#define CPU_INFO_FOREACH(cii, ci) \
	for (cii = 0, ci = curcpu(); ci != NULL; ci = NULL)
#define CPU_INFO_UNIT(ci)	0
#define MAXCPUS	1
#define cpu_unidle(ci)

#define CPU_BUSY_CYCLE()	do {} while (0)

struct clockframe {
	int	pc;
	int	ps;
};

/*
 * All cpu-dependent info is kept in this struct. Pointer to the
 * struct for the current cpu is set up in locore.c.
 */
struct	cpu_dep {
	void	(*cpu_init)(void);	/* pmap init before mm is on */
	int	(*cpu_mchk)(caddr_t);	/* Machine check handling */
	void	(*cpu_memerr)(void);	/* Memory subsystem errors */
	void	(*cpu_conf)(void);	/* Autoconfiguration */
	int	(*cpu_clkread)(struct timespec *, time_t); /* Read cpu clock time */
	void	(*cpu_clkwrite)(void);	/* Write system time to cpu */
	short	cpu_vups;	/* speed of cpu */
	short	cpu_scbsz;	/* (estimated) size of system control block */
	void	(*cpu_halt)(void); /* Cpu dependent halt call */
	void	(*cpu_reboot)(int); /* Cpu dependent reboot call */
	void	(*cpu_clrf)(void); /* Clear cold/warm start flags */
	void	(*cpu_hardclock)(struct clockframe *);	/* hardclock handler */
};

extern struct cpu_dep *dep_call; /* Holds pointer to current CPU struct. */

extern struct device *booted_from;
extern int mastercpu;
extern int bootdev;

/*
 * Preempt the current process if in interrupt from user mode,
 * or after the current trap/syscall if in system mode.
 */

#define need_resched(ci){ \
	want_resched++; \
	mtpr(AST_OK,PR_ASTLVL); \
	}
#define clear_resched(ci) 	want_resched = 0

/*
 * Notify the current process (p) that it has a signal pending,
 * process as soon as possible.
 */

#define signotify(p)		mtpr(AST_OK,PR_ASTLVL);

extern	int	want_resched;	/* resched() was called */

/*
 * This is used during profiling to integrate system time.
 */
#define	PROC_PC(p)	(((struct trapframe *)((p)->p_addr->u_pcb.framep))->pc)
#define	PROC_STACK(p)	(((struct trapframe *)((p)->p_addr->u_pcb.framep))->sp)

/*
 * Give a profiling tick to the current process when the user profiling
 * buffer pages are invalid.  On the vax, request an ast to send us
 * through trap, marking the proc as needing a profiling tick.
 */
#define need_proftick(p) mtpr(AST_OK,PR_ASTLVL)

/*
 * Temporarily switching to ipl 1 when the kernel is idle allows SIMH
 * to recognize the system is idle, and relinquish CPU time as well.
 */
#define	cpu_idle_enter()	do { /* nothing */ } while (0)
#define	cpu_idle_leave()	do { /* nothing */ } while (0)
#define	cpu_idle_cycle() \
do { \
	mtpr(0x01, PR_IPL); \
	mtpr(0x00, PR_IPL); \
} while (0)

/*
 * This defines the I/O device register space size in pages.
 */
#define	IOSPSZ	((16*1024) / VAX_NBPG)	/* 16Kb == 32 pages */

struct device;

extern char cpu_model[100];

/* Some low-level prototypes */
int	badaddr(caddr_t, int);
void	dumpconf(void);
void	dumpsys(void);
void	swapconf(void);
void	disk_printtype(int, int);
vaddr_t	vax_map_physmem(paddr_t, int);
void	vax_unmap_physmem(vaddr_t, int);
void	ioaccess(vaddr_t, paddr_t, int);
void	iounaccess(vaddr_t, int);
void	findcpu(void);
#ifdef DDB
int	kdbrint(int);
#endif
#endif /* _KERNEL */

/*
 * CTL_MACHDEP definitions.
 */
#define CPU_CONSDEV		1	/* dev_t: console terminal device */
#define	CPU_LED_BLINK		2	/* int: display led patterns */
#define CPU_MAXID		3	/* number of valid machdep ids */

#define CTL_MACHDEP_NAMES { \
	{ 0, 0 }, \
	{ "console_device", CTLTYPE_STRUCT }, \
	{ "led_blink", CTLTYPE_INT } \
}

#endif /* _MACHINE_CPU_H_ */


code:
/*	$OpenBSD: cvax.h,v 1.2 2011/09/19 20:58:32 miod Exp $	*/
/*	$NetBSD: ka650.h,v 1.6 1997/07/26 10:12:43 ragge Exp $	*/
/*
 * Copyright (c) 1988 The Regents of the University of California.
 * All rights reserved.
 *
 * This code is derived from software contributed to Berkeley by
 * Mt. Xinu.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of the University nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 *	@(#)ka650.h	7.5 (Berkeley) 6/28/90
 */

/*
 *
 * Definitions specific to CVAX processors.
 */

/*
 * CADR: Cache Disable Register (IPR 37)
 */
#define CADR_STMASK	0x000000f0	/* 1st level cache state mask */
#define CADR_SEN2	0x00000080	/* 1st level cache set 2 enabled */
#define CADR_SEN1	0x00000040	/* 1st level cache set 1 enabled */
#define CADR_CENI	0x00000020	/* 1st level I-stream caching enabled */
#define CADR_CEND	0x00000010	/* 1st level D-stream caching enabled */

/*
 * Internal State Info 2: (for mcheck recovery)
 */
#define IS2_VCR		0x00008000	/* VAX Can't Restart flag */

#ifndef _LOCORE

/*
 * System Support Chip (SSC) registers
 */
struct cvax_ssc {
	u_long	ssc_sscbr;	/* SSC Base Addr Register */
	u_long	pad1[3];
	u_long	ssc_ssccr;	/* SSC Configuration Register */
	u_long	pad2[3];
	u_long	ssc_cbtcr;	/* CDAL Bus Timeout Control Register */
	u_long	pad3[18];
	u_long	ssc_todr;	/* TOY Clock Register */
	u_long	pad4[36];
	u_long	ssc_tcr0;	/* timer control reg 0 */
	u_long	ssc_tir0;	/* timer interval reg 0 */
	u_long	ssc_tnir0;	/* timer next interval reg 0 */
	u_long	ssc_tivr0;	/* timer interrupt vector reg 0 */
	u_long	ssc_tcr1;	/* timer control reg 1 */
	u_long	ssc_tir1;	/* timer interval reg 1 */
	u_long	ssc_tnir1;	/* timer next interval reg 1 */
	u_long	ssc_tivr1;	/* timer interrupt vector reg 1 */
	u_long	pad5[184];
	u_char	ssc_cpmbx;	/* Console Program Mail Box: Lang & Hact */
	u_char	ssc_terminfo;	/* TTY info: Video Dev, MCS, CRT & ROM flags */
	u_char	ssc_keyboard;	/* Keyboard code */
};
#define CVAX_SSC	0x20140000

extern struct cvax_ssc *cvax_ssc_ptr;

/*
 * CBTCR: CDAL Bus Timeout Control Register (ssc_cbtcr)
 */
#define CBTCR_BTO	0x80000000	/* r/w unimp IPR or unack intr */
#define CBTCR_RWT	0x40000000	/* CDAL Bus Timeout on CPU or DMA */

/*
 * TCR0/TCR1: Programable Timer Control Registers (ssc_tcr[01])
 * (The rest of the bits are the same as in the standard VAX
 *	Interval timer and are defined in clock.h)
 */
#define TCR_STP		0x00000004	/* Stop after time-out */

/*
 * Flags for Console Program Mail Box
 */
#define CPMB_CVAX_HALTACT	0x03	/* Field for halt action */
#define CPMB_CVAX_RESTART	0x01	/* Restart */
#define CPMB_CVAX_REBOOT	0x02	/* Reboot */
#define CPMB_CVAX_HALT		0x03	/* Halt */
#define CPMB_CVAX_BIP		0x04	/* Bootstrap in progress */
#define CPMB_CVAX_RIP		0x08	/* Restart in progress */
#define	CPMB_CVAX_DOTHIS	0x30	/* Execute sommand */
#define CPMB_CVAX_LANG		0xf0	/* Language field */

/*
 * Machine Check frame
 */
struct cvax_mchk_frame {
	int	cvax_bcnt;		/* byte count == 0x10 */
	int	cvax_summary;		/* summary parameter */
	int	cvax_mrvaddr;		/* most recent vad */
	int	cvax_istate1;		/* internal state */
	int	cvax_istate2;		/* internal state */
	int	cvax_pc;		/* trapped pc */
	int	cvax_psl;		/* trapped psl */
};

const char *cvax_mchk_descr(int);
void	cvax_halt(void);
void	cvax_reboot(int);

#endif /* _LOCORE */


code:
/*	$OpenBSD: db_machdep.h,v 1.17 2014/03/16 20:31:46 guenther Exp $	*/
/*	$NetBSD: db_machdep.h,v 1.6 1998/08/10 14:33:33 ragge Exp $	*/

/*
 * Mach Operating System
 * Copyright (c) 1991,1990 Carnegie Mellon University
 * All Rights Reserved.
 *
 * Permission to use, copy, modify and distribute this software and its
 * documentation is hereby granted, provided that both the copyright
 * notice and this permission notice appear in all copies of the
 * software, derivative works or modified versions, and any portions
 * thereof, and that both notices appear in supporting documentation.
 *
 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
 * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
 *
 * Carnegie Mellon requests users of this software to return to
 *
 *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
 *  School of Computer Science
 *  Carnegie Mellon University
 *  Pittsburgh PA 15213-3890
 *
 * any improvements or extensions that they make and grant Carnegie Mellon
 * the rights to redistribute these changes.
 */

#ifndef	_MACHINE_DB_MACHDEP_H_
#define	_MACHINE_DB_MACHDEP_H_

/*
 * Machine-dependent defines for new kernel debugger.
 * Modified for vax out of i386 code.
 */

#include <sys/param.h>
#include <uvm/uvm_extern.h>
#include <machine/trap.h>
#include <machine/psl.h>

typedef	vaddr_t	db_addr_t;		/* address - unsigned */
typedef	long		db_expr_t;	/* expression - signed */

typedef struct trapframe db_regs_t;
extern db_regs_t	ddb_regs;	/* register state */
#define	DDB_REGS	(&ddb_regs)

#define	PC_REGS(regs)	((db_addr_t)(regs)->pc)
#define	SET_PC_REGS(regs, value)	(regs)->pc = (long)(value)

#define	BKPT_INST	0x03		/* breakpoint instruction */
#define	BKPT_SIZE	(1)		/* size of breakpoint inst */
#define	BKPT_SET(inst)	(BKPT_INST)

#define	FIXUP_PC_AFTER_BREAK(regs)	((regs)->pc -= BKPT_SIZE)

#define	db_clear_single_step(regs)	((regs)->psl &= ~PSL_T)
#define	db_set_single_step(regs)	((regs)->psl |=  PSL_T)

#define	IS_BREAKPOINT_TRAP(type, code)	((type) == T_BPTFLT)
#define IS_WATCHPOINT_TRAP(type, code)	((type) == T_TRCTRAP)

#define	I_CALL		0xfb
#define	I_RET		0x04
#define	I_IRET		0x02

#define	inst_trap_return(ins)	(((ins)&0xff) == I_IRET)
#define	inst_return(ins)	(((ins)&0xff) == I_RET)
#define	inst_call(ins)		(((ins)&0xff) == I_CALL)

/* Prototypes */
void	kdb_trap(struct trapframe *);

#endif	/* _MACHINE_DB_MACHDEP_H_ */


code:
/*	$OpenBSD: disklabel.h,v 1.9 2007/06/20 18:15:45 deraadt Exp $	*/

/*
 * Copyright (c) 1994 Christopher G. Demetriou
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *      This product includes software developed by Christopher G. Demetriou.
 * 4. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef _MACHINE_DISKLABEL_H_
#define _MACHINE_DISKLABEL_H_

#define	LABELSECTOR	0			/* sector containing label */
#define	LABELOFFSET	64			/* offset of label in sector */
#define	MAXPARTITIONS	16			/* number of partitions */

#endif /* _MACHINE_DISKLABEL_H_ */


code:
/*	$OpenBSD: endian.h,v 1.17 2014/07/12 16:25:09 guenther Exp $	*/

/*-
 * Copyright (c) 1997 Niklas Hallqvist.  All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef _MACHINE_ENDIAN_H_
#define _MACHINE_ENDIAN_H_

#ifdef	__GNUC__

#define	__swap64md	__swap64gen

#define	__swap32md(x) __statement({					\
	__uint32_t __swap32md_y, __swap32md_x = (x);			\
									\
	__asm ("rotl $-8, %1, %0; insv %0, $16, $8, %0; "		\
	    "rotl $8, %1, %%r1; movb %%r1, %0" :			\
	    "&=r" (__swap32md_y) : "r" (__swap32md_x) : "r1", "cc");	\
	__swap32md_y;							\
})

#define __swap16md(x) __statement({					\
	__uint16_t __swap16md_y, __swap16md_x = (x);			\
									\
	__asm ("rotl $8, %1, %0; rotl $-8, %1, %%r1; movb %%r1, %0; "	\
	    "movzwl %0, %0" :						\
	    "&=r" (__swap16md_y) : "r" (__swap16md_x) : "r1", "cc");	\
	__swap16md_y;							\
})

/* Tell sys/endian.h we have MD variants of the swap macros.  */
#ifdef notyet
#define __HAVE_MD_SWAP
#endif

#endif /* __GNUC__ */

#define _BYTE_ORDER _LITTLE_ENDIAN

#ifndef __FROM_SYS__ENDIAN
#include <sys/endian.h>
#endif

#endif /* _MACHINE_ENDIAN_H_ */


code:
/*	$OpenBSD: exec.h,v 1.11 2014/03/18 19:23:42 guenther Exp $	*/
/*	$NetBSD: exec.h,v 1.4 1995/09/23 14:57:40 ragge Exp $	*/

/*
 * Copyright (c) 1993 Christopher G. Demetriou
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef _MACHINE_EXEC_H_
#define _MACHINE_EXEC_H_

#define __LDPGSZ	4096

#define _NLIST_DO_ELF
#define _KERN_DO_ELF

#define ARCH_ELFSIZE		32

#define ELF_TARG_CLASS		ELFCLASS32
#define ELF_TARG_DATA		ELFDATA2LSB
#define ELF_TARG_MACH		EM_VAX

#endif  /* _MACHINE_EXEC_H_ */


code:
/*	$OpenBSD: frame.h,v 1.4 2011/03/23 16:54:37 pirofti Exp $ */
/*	$NetBSD: frame.h,v 1.2 2000/06/04 19:30:15 matt Exp $ */
/*
 * Copyright (c) 1995 Ludd, University of Lule}, Sweden.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *      This product includes software developed at Ludd, University of
 *      Lule}, Sweden and its contributors.
 * 4. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef _MACHINE_FRAME_H_
#define	_MACHINE_FRAME_H_

/*
 * Description of calls frame on stack. This is the
 * standard way of making procedure calls on vax systems.
 */
struct callsframe {
	unsigned int	ca_cond;	/* condition handler */
	unsigned int	ca_maskpsw;	/* register mask and saved psw */
	unsigned int	ca_ap;		/* argument pointer */
	unsigned int	ca_fp;		/* frame pointer */
	unsigned int	ca_pc;		/* program counter */
	unsigned int	ca_argno;	/* argument count on stack */
	unsigned int	ca_arg1;	/* first arg on stack */
	/* This can be followed by more arguments */
};

struct icallsframe {
	struct callsframe ica_frame;	/* std call frame */
	unsigned int	ica_r0;		/* interrupt saved r0 */
	unsigned int	ica_r1;		/* interrupt saved r1 */
	unsigned int	ica_r2;		/* interrupt saved r2 */
	unsigned int	ica_r3;		/* interrupt saved r3 */
	unsigned int	ica_r4;		/* interrupt saved r4 */
	unsigned int	ica_r5;		/* interrupt saved r5 */
	unsigned int	ica_pc;		/* interrupt saved pc */
	unsigned int	ica_psl;	/* interrupt saved psl */
};

#endif /* _VAX_FRAME_H */


code:
/*	$OpenBSD: intr.h,v 1.18 2014/03/29 18:09:30 guenther Exp $	*/
/* 	$NetBSD: intr.h,v 1.1 1998/08/18 23:55:00 matt Exp $	*/

/*
 * Copyright (c) 1998 Matt Thomas.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. The name of the company nor the name of the author may be used to
 *    endorse or promote products derived from this software without specific
 *    prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */

#ifndef _MACHINE_INTR_H_
#define _MACHINE_INTR_H_

/* Define the various Interrupt Priority Levels */

/* Interrupt Priority Levels are not mutually exclusive. */

#define IPL_NONE	0x00
#define	IPL_SOFT	0x08
#define	IPL_SOFTCLOCK	0x09
#define	IPL_SOFTNET	0x0a
#define	IPL_SOFTTTY	0x0b
#define IPL_BIO		0x15	/* block I/O */
#define IPL_NET		0x15	/* network */
#define IPL_TTY		0x16	/* terminal */
#define IPL_VM		0x17	/* memory allocation */
#define	IPL_AUDIO	0x15	/* audio */
#define IPL_CLOCK	0x18	/* clock */
#define IPL_STATCLOCK	0x18	/* statclock */
#define	IPL_SCHED	0x1f
#define	IPL_HIGH	0x1f

#define	IPL_MPSAFE	0	/* no "mpsafe" interrupts */

#define	IST_UNUSABLE	-1	/* interrupt cannot be used */
#define	IST_NONE	0	/* none (dummy) */
#define	IST_PULSE	1	/* pulsed */
#define	IST_EDGE	2	/* edge-triggered */
#define	IST_LEVEL	3	/* level-triggered */

#define _splset(reg)						\
({								\
	register int val;					\
	__asm volatile ("mfpr $0x12,%0;mtpr %1,$0x12"		\
				: "=&g" (val)			\
				: "g" (reg));			\
	val;							\
})

#define	_splraise(reg)						\
({								\
	register int val;					\
	__asm volatile ("mfpr $0x12,%0"				\
				: "=&g" (val)			\
				: );				\
	if ((reg) > val) {					\
		__asm volatile ("mtpr %0,$0x12"			\
				:				\
				: "g" (reg));			\
	}							\
	val;							\
})

#define	splx(reg)						\
	__asm volatile ("mtpr %0,$0x12" : : "g" (reg))

#define	spl0()		_splset(IPL_NONE)
#define splsoftclock()	_splraise(IPL_SOFTCLOCK)
#define splsoftnet()	_splraise(IPL_SOFTNET)
#define splbio()	_splraise(IPL_BIO)
#define splnet()	_splraise(IPL_NET)
#define spltty()	_splraise(IPL_TTY)
#define splvm()		_splraise(IPL_VM)
#define splaudio()	_splraise(IPL_AUDIO)
#define splclock()	_splraise(IPL_CLOCK)
#define splstatclock()	_splraise(IPL_STATCLOCK)
#define splhigh()	_splset(IPL_HIGH)
#define	splsched()	splhigh()

/* These are better to use when playing with VAX buses */
#define	spl4()		_splraise(0x14)
#define	spl5()		_splraise(0x15)
#define	spl6()		_splraise(0x16)
#define	spl7()		_splraise(0x17)

/* SPL asserts */
#ifdef DIAGNOSTIC
/*
 * Although this function is implemented in MI code, it must be in this MD
 * header because we don't want this header to include MI includes.
 */
void splassert_fail(int, int, const char *);
extern int splassert_ctl;
void splassert_check(int, const char *);
#define splassert(__wantipl) do {			\
	if (splassert_ctl > 0) {			\
		splassert_check(__wantipl, __func__);	\
	}						\
} while (0)
#define splsoftassert(wantipl) splassert(wantipl)
#else
#define	splassert(wantipl)	do { /* nothing */ } while (0)
#define	splsoftassert(wantipl)	do { /* nothing */ } while (0)
#endif

#define	SI_SOFT			0	/* for IPL_SOFT */
#define	SI_SOFTCLOCK		1	/* for IPL_SOFTCLOCK */
#define	SI_SOFTNET		2	/* for IPL_SOFTNET */
#define	SI_SOFTTTY		3	/* for IPL_SOFTTTY */

#define	SI_NQUEUES		4

#ifndef _LOCORE

#include <machine/mutex.h>
#include <sys/queue.h>

struct soft_intrhand {
	TAILQ_ENTRY(soft_intrhand) sih_list;
	void (*sih_func)(void *);
	void *sih_arg;
	struct soft_intrq *sih_siq;
	int sih_pending;
};

struct soft_intrq {
	TAILQ_HEAD(, soft_intrhand) siq_list;
	int siq_si;
	struct mutex siq_mtx;
};

void	 softintr_disestablish(void *);
void	*softintr_establish(int, void (*)(void *), void *);
void	 softintr_init(void);
void	 softintr_schedule(void *);

#endif	/* _LOCORE */

#endif	/* _VAX_INTR_H */


code:
/*	$OpenBSD: ka410.h,v 1.7 2011/09/11 19:29:01 miod Exp $ */
/*	$NetBSD: ka410.h,v 1.2 1997/02/19 10:06:05 ragge Exp $ */
/*
 * Copyright (c) 1996 Ludd, University of Lule}, Sweden.
 * All rights reserved.
 *
 * This code is derived from software contributed to Ludd by Bertram Barth.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *      This product includes software developed at Ludd, University of
 *      Lule}, Sweden and its contributors.
 * 4. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/*
 * Definition for  I/O addresses of
 *
 *	MicroVAX 2000	(TeamMate)
 *	VAXstation 2000 (VAXstar)
 */

#define KA410_SIDEX	0x20040004	/* SID extension register */

#define KA410_CFGTST	0x20020000	/* Configuration and Test register */
#define KA410_IORESET	0x20020000	/* I/O Reset register */

#define KA410_ROM_BASE	0x20040000	/* System module ROM */
#define KA410_ROM_END	0x2007FFFF
#define KA410_ROM_SIZE	   0x40000

#define KA410_IVN_BASE	0x20040020	/* Interrupt Vector Numbers */
#define KA410_IVN_END	0x2004003F
#define KA410_IVN_SIZE	      0x20

#define KA410_HLTCOD	0x20080000	/* Halt Code Register */
#define KA410_MSER	0x20080004	/* Memory System Error register */
#define KA410_MEAR	0x20080008	/* Memory Error Address register */
#define KA410_INTMSK	0x2008000C	/* Interrupt Mask register */
#define KA410_VDCORG	0x2008000D	/* Video Controller Origin Register */
#define KA410_VDCSEL	0x2008000E	/* Video Controller Select Register */
#define KA410_INTREQ	0x2008000F	/* Interrupt Request register */
#define KA410_INTCLR	0x2008000F	/* Interrupt Request clear register */

/*
 * Other fixed addresses which should be mapped
 */
#define KA410_NWA_BASE	0x20090000	/* Network Address ROM */
#define KA410_NWA_END	0x2009007F
#define KA410_NWA_SIZE	      0x80
#define KA410_SER_BASE	0x200A0000	/* Serial line controller */
#define KA410_SER_END	0x200A000F
#define KA410_SER_SIZE        0x10
#define KA410_WAT_BASE	0x200B0000	/* TOY clock */
#define KA410_WAT_END	0x200B00FF
#define KA410_WAT_SIZE	     0x100
#define KA410_DKC_BASE	0x200C0000	/* Disk Controller Ports */
#define KA410_DKC_END	0x200C0007
#define KA410_DKC_SIZE	      0x08
#define KA410_SCS_BASE	0x200C0080	/* Tape (SCSI) Controller Chip */
#define KA410_SCS_END	0x200C009F
#define KA410_SCS_SIZE	      0x20
#define KA410_DMA_BASE	0x200D0000	/* Disk Data buffer RAM */
#define KA410_DMA_END	0x200D3FFF
#define KA410_DMA_SIZE	    0x4000
#define KA410_LAN_BASE	0x200E0000	/* LANCE chip registers */
#define KA410_LAN_END	0x200E0007
#define KA410_LAN_SIZE	      0x08
#define KA410_CUR_BASE	0x200F0000	/* Monochrome video cursor chip */
#define KA410_CUR_END	0x200F003F
#define KA410_CUR_SIZE	      0x40

#define KA410_SCS_DADR	0x200C00A0	/* Tape(SCSI) DMA address register */
#define KA410_SCS_DCNT	0x200C00C0	/* Tape(SCSI) DMA byte count reg. */
#define KA410_SCS_DDIR	0x200C00C4	/* Tape(SCSI) DMA transfer direction */

/*
 * Definitions for the Configuration and Test Register
 */
#define KA410_CFG_MULTU		0x80	/* MicroVAX or VAXstation */
#define KA410_CFG_NETOPT	0x40	/* Network option present */
#define KA410_CFG_L3CON		0x20	/* Console on line #3 of dc */
#define KA410_CFG_CURTEST	0x10	/* Cursor Test (monochrom) */
#define KA410_CFG_VIDOPT	0x08	/* Video option present */
#define KA410_CFG_MEMSZ		0x07	/* Memory option type/size */

#define KA410_CFG_0MB		0x00	/* No additional Memory board */
#define KA410_CFG_1MB		0x01
#define KA410_CFG_2MB		0x02
#define KA410_CFG_4MB		0x03
#define KA410_CFG_6MB		0x04
#define KA410_CFG_8MB		0x05
#define KA410_CFG_12MB		0x06
#define KA410_CFG_14MB		0x07

/*
 * interrupt request-, clear-, and mask register
 */
extern volatile unsigned char *ka410_intreq;
extern volatile unsigned char *ka410_intclr;
extern volatile unsigned char *ka410_intmsk;

#define INTR_SR	(1<<7)	/* Serial line receiver or silo full */
#define INTR_ST	(1<<6)	/* Serial line transmitter done */
#define INTR_NP	(1<<5)	/* Network controller primary */
#define INTR_NS	(1<<4)	/* Network controller secondary */
#define INTR_VF	(1<<3)	/* Video end of frame */
#define INTR_VS	(1<<2)	/* Video secondary */
#define INTR_SC	(1<<1)	/* SCSI controller */
#define INTR_DC	(1<<0)	/* Disk controller */

/*
 * Clock-Chip data in NVRAM
 */
#define KA410_CPMBX	0x200B0038	/* Console Mailbox (1 byte) */
#define KA410_CPFLG	0x200B003C	/* Console Program Flags (1 byte) */
#define KA410_LK201_ID	0x200B0040	/* Keyboard Variation (1 byte) */
#define KA410_CONS_ID	0x200B0044	/* Console Device Type (1 byte) */
#define KA410_SCR	0x200B0048	/* Console Scratch RAM */
#define KA410_TEMP	0x200B0058	/* Used by System Firmware */
#define KA410_BAT_CHK	0x200B0088	/* Battery Check Data */
#define KA410_BOOTDEV	0x200B0098	/* Default Boot Device (4 bytes) */
#define KA410_BOOTFLG	0x200B00A8	/* Default Boot Flags (4 bytes) */
#define KA410_SCRLEN	0x200B00B8	/* Number of pages of SCR (1 byte) */
#define KA410_SCSIPORT	0x200B00BC	/* Tape Controller Port Data */
#define KA410_RESERVED	0x200B00C0	/* Reserved (16 bytes) */

/*
 * KA410 uses bits 2-9 of longwords to store single bytes in NVRAM,
 * thus we declare the clock as an struct of bit-fields, so that the
 * generic clock-routines work for KA410...
 */
struct ka410_clock {
	u_long  :2;	u_long	sec	:8;	u_long  :22;
	u_long  :2;	u_long	secalrm :8;	u_long  :22;
	u_long  :2;	u_long	min	:8;	u_long  :22;
	u_long  :2;	u_long	minalrm	:8;	u_long  :22;
	u_long  :2;	u_long	hr	:8;	u_long  :22;
	u_long  :2;	u_long	hralrm	:8;	u_long  :22;
	u_long  :2;	u_long	dayofwk	:8;	u_long  :22;
	u_long  :2;	u_long	day	:8;	u_long  :22;
	u_long  :2;	u_long	mon	:8;	u_long  :22;
	u_long  :2;	u_long	yr	:8;	u_long  :22;
	u_long  :2;	u_long	csr0	:8;	u_long  :22;
	u_long  :2;	u_long	csr1	:8;	u_long  :22;
	u_long  :2;	u_long	csr2	:8;	u_long  :22;
	u_long  :2;	u_long	csr3	:8;	u_long  :22;
	u_long  :2;	u_long	cpmbx	:8;	u_long  :22;
};


code:
/*	$OpenBSD: ka420.h,v 1.5 2008/08/18 23:07:24 miod Exp $ */
/*	$NetBSD: ka420.h,v 1.2 1998/06/07 18:34:09 ragge Exp $ */
/*
 * Copyright (c) 1996 Ludd, University of Lule}, Sweden.
 * All rights reserved.
 *
 * This code is derived from software contributed to Ludd by Bertram Barth.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *      This product includes software developed at Ludd, University of
 *      Lule}, Sweden and its contributors.
 * 4. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/*
 * Definitions for I/O addresses of
 *
 *	VAXstation 3100 models 30, 40	(PVAX)
 *	MicroVAX 3100 models 10, 20	(Teammate II)
 *	MicroVAX 3100 models 10e, 20e	(Teammate II)
 *	VAXstation 3100 models 38, 48	(PVAX rev#7)
 */

#define KA420_SIDEX	0x20040004	/* SID extension register */

#define KA420_CH2_BASE	0x10000000	/* 2nd level cache data area */
#define KA420_CH2_END	0x10007FFF
#define KA420_CH2_SIZE	    0x8000
#define KA420_CT2_BASE	0x10010000	/* 2nd level cache tag area */
#define KA420_CT2_END	0x10017FFF
#define KA420_CT2_SIZE	    0x8000
#define KA420_CH2_CREG	0x20084000	/* 2nd level cache control register */

#define KA420_CFGTST	0x20020000	/* Configuration and Test register */
#define KA420_IORESET	0x20020000	/* I/O Reset register */

#define KA420_ROM_BASE	0x20040000	/* System module ROM */
#define KA420_ROM_END	0x2007FFFF
#define KA420_ROM_SIZE	   0x40000	/* ??? */

#define KA420_IVN_BASE	0x20040020	/* Interrupt Vector Numbers */
#define KA420_IVN_END	0x2004003F
#define KA420_IVN_SIZE	      0x20

#define KA420_HLTCOD	0x20080000	/* Halt Code Register */
#define KA420_MSER	0x20080004	/* Memory System Error register */
#define KA420_MEAR	0x20080008	/* Memory Error Address register */
#define KA420_INTMSK	0x2008000C	/* Interrupt Mask register */
#define KA420_VDCORG	0x2008000D	/* Video Controller Origin Register */
#define KA420_VDCSEL	0x2008000E	/* Video Controller Select Register */
#define KA420_INTREQ	0x2008000F	/* Interrupt Request register */
#define KA420_INTCLR	0x2008000F	/* Interrupt Request clear register */

#define KA420_CACR	0x20084000	/* L2 cache ctrl reg */

/*
 * Other fixed addresses which should be mapped
 */
#define KA420_NWA_BASE	0x20090000	/* Network Address ROM */
#define KA420_NWA_END	0x2009007F
#define KA420_NWA_SIZE	      0x80
#define KA420_SER_BASE	0x200A0000	/* Serial line controller */
#define KA420_SER_END	0x200A000F
#define KA420_SER_SIZE        0x10
#define KA420_WAT_BASE	0x200B0000	/* TOY clock and NV-RAM */
#define KA420_WAT_END	0x200B00FF
#define KA420_WAT_SIZE	     0x100
#define KA420_DKC_BASE	0x200C0000	/* Disk Controller Ports */
#define KA420_DKC_END	0x200C0007
#define KA420_DKC_SIZE	      0x08
#define KA420_SCS_BASE	0x200C0080	/* Tape (SCSI) Controller Chip */
#define KA420_SCS_END	0x200C009F
#define KA420_SCS_SIZE	      0x20
#define KA420_D16_BASE	0x200D0000	/* 16KB (compatibility) Data Buffer */
#define KA420_D16_END	0x200D3FFF
#define KA420_D16_SIZE	    0x4000
#define KA420_LAN_BASE	0x200E0000	/* LANCE chip registers */
#define KA420_LAN_END	0x200E0007
#define KA420_LAN_SIZE	      0x08
#define KA420_CUR_BASE	0x200F0000	/* Monochrome video cursor chip */
#define KA420_CUR_END	0x200F003F
#define KA420_CUR_SIZE	      0x40
#define KA420_DMA_BASE	0x202D0000	/* 128KB Data Buffer */
#define KA420_DMA_END	0x202EFFFF
#define KA420_DMA_SIZE     0x20000

#define KA420_SCD_DADR	0x200C00A0	/* Tape(SCSI) DMA address register */
#define KA420_SCD_DCNT	0x200C00C0	/* Tape(SCSI) DMA byte count reg. */
#define KA420_SCD_DDIR	0x200C00C4	/* Tape(SCSI) DMA transfer direction */

#define KA420_STC_MODE	0x200C00E0	/* Storage Controller Mode register */

/*
 * Clock-Chip data in NVRAM
 */
#define KA420_CPMBX	0x200B0038	/* Console Mailbox (1 byte) */
#define KA420_CPFLG	0x200B003C	/* Console Program Flags (1 byte) */
#define KA420_LK201_ID	0x200B0040	/* Keyboard Variation (1 byte) */
#define KA420_CONS_ID	0x200B0044	/* Console Device Type (1 byte) */
#define KA420_SCR	0x200B0048	/* Console Scratch RAM */
#define KA420_TEMP	0x200B0058	/* Used by System Firmware */
#define KA420_BAT_CHK	0x200B0088	/* Battery Check Data */
#define KA420_BOOTDEV	0x200B0098	/* Default Boot Device (4 bytes) */
#define KA420_BOOTFLG	0x200B00A8	/* Default Boot Flags (4 bytes) */
#define KA420_SCRLEN	0x200B00B8	/* Number of pages of SCR (1 byte) */
#define KA420_SCSIPORT	0x200B00BC	/* Tape Controller Port Data */
#define KA420_RESERVED	0x200B00C0	/* Reserved (16 bytes) */

/* Used bits in the CFGTST (20020000) register */
#define	KA420_CFG_STCMSK	0xc000	/* Storage controller mask */
#define	KA420_CFG_RB		0x0000	/* RB (ST506/SCSI) present */
#define	KA420_CFG_RD		0x4000	/* RD (SCSI/SCSI) present */
#define	KA420_CFG_NONE		0xc000	/* No storage ctlr present */
#define	KA420_CFG_MULTU		0x80	/* MicroVAX or VAXstation */
#define	KA420_CFG_CACHPR	0x40	/* Secondary cache present */
#define	KA420_CFG_L3CON		0x20	/* Console on line #3 of dc */
#define	KA420_CFG_CURTEST	0x10	/* Cursor Test (monochrom) */
#define	KA420_CFG_VIDOPT	0x08	/* Video option present */

/* Secondary cache bits (CACR, 20084000) */
#define	KA420_CACR_CP3		0x80000000	/* last parity read */
#define	KA420_CACR_CP2		0x40000000	/* last parity read */
#define	KA420_CACR_CP1		0x20000000	/* last parity read */
#define	KA420_CACR_CP0		0x10000000	/* last parity read */
#define	KA420_CACR_TPP		0x00100000	/* tag predicted parity */
#define	KA420_CACR_TGP		0x00080000	/* tag parity read */
#define	KA420_CACR_TGV		0x00040000	/* valid flag */
#define	KA420_CACR_TPE		0x00000020	/* tag parity error */
#define	KA420_CACR_CEN		0x00000010	/* cache enable */


code:
/*	$OpenBSD: ka43.h,v 1.6 2011/09/13 21:25:23 miod Exp $ */
/*	$NetBSD: ka43.h,v 1.6 2005/01/14 11:47:43 ragge Exp $ */
/*
 * Copyright (c) 1996 Ludd, University of Lule}, Sweden.
 * All rights reserved.
 *
 * This code is derived from software contributed to Ludd by Bertram Barth.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *      This product includes software developed at Ludd, University of
 *      Lule}, Sweden and its contributors.
 * 4. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/*
 * Definitions for I/O addresses of
 *
 *	VAXstation 3100 model 76	(RigelMAX)
 */

#define KA43_SIDEX	0x20040004	/* SID extension register */

#define KA43_CFGTST	0x20020000	/* Configuration and Test register */
#define KA43_IORESET	0x20020000	/* I/O Reset register */

#define KA43_ROMGETC	0x20040044
#define KA43_ROMPUTC	0x20040058
#define KA43_ROMPUTS	0x2004004C

#define KA43_CH2_BASE	0x10000000	/* 2nd level cache data area */
#define KA43_CH2_END	0x1FFFFFFF
#define KA43_CH2_SIZE	0x10000000
#define KA43_CT2_BASE	0x21000000	/* 2nd level cache tag area */
#define KA43_CT2_END	0x2101FFFF
#define KA43_CT2_SIZE	   0x20000
#define KA43_CH2_CREG	0x21100000	/* 2nd level cache control register */

#define KA43_ROM_BASE	0x20040000	/* System module ROM */
#define KA43_ROM_END	0x2007FFFF
#define KA43_ROM_SIZE	   0x40000	/* ??? */

#define KA43_IVN_BASE	0x20040020	/* Interrupt Vector Numbers */
#define KA43_IVN_END	0x2004003F
#define KA43_IVN_SIZE	      0x20

#define KA43_HLTCOD	0x20080000	/* Halt Code Register */
/* #define KA43_MSER	0x20080004 */	/* Memory System Error register */
/* #define KA43_MEAR	0x20080008 */	/* Memory Error Address register */
#define KA43_INTMSK	0x2008000C	/* Interrupt Mask register */
#define KA43_VDCORG	0x2008000D	/* Video Controller Origin Register */
#define KA43_VDCSEL	0x2008000E	/* Video Controller Select Register */
#define KA43_INTREQ	0x2008000F	/* Interrupt Request register */
#define KA43_INTCLR	0x2008000F	/* Interrupt Request clear register */
#define KA43_DIAGDSP	0x20080010	/* Diagnostic display register */
#define KA43_PARCTL	0x20080014	/* Parity Control Register */
#define KA43_DIAGTME	0x2008001E	/* diagnostic time register */

#define KA43_PCTL_DPEN	0x00000001	/* DMA parity enable (bit 0) */
#define KA43_PCTL_CPEN	0x00000002	/* CPU Parity enable (bit 1) */
#define KA43_PCTL_DMA	0x01000000	/* LANCE DMA control (bit 24) */

/*
 * "CH2" and "SESR" are two common names related to Secondary Cache
 */
#define KA43_SESR	0x21100000	/* same as KA43_CH2_CREG */

#define KA43_SESR_CENB	0x00000001	/* Cache Enable */
#define KA43_SESR_SERR  0x00000002
#define KA43_SESR_LERR	0x00000004
#define KA43_SESR_CERR	0x00000008
#define KA43_SESR_DIRTY	0x00000010
#define KA43_SESR_MISS	0x00000020
#define KA43_SESR_DPE	0x00000040	/* Dal Parity Error */
#define KA43_SESR_TPE	0x00000080	/* Tag Parity Error */
#define KA43_SESR_WSB	0x00010000
#define KA43_SESR_CIEA	0x7FFC0000

#define KA43_SESR_BITS \
	"\020\010TPE\007DPE\006MISS\005DIRTY\004CERR\003LERR\002SERR\001ENABLE"

/*
 * The following values refer to bits/bitfields within the 4 internal
 * registers controlling primary cache:
 * PR_PCTAG(124, tag-register)		PR_PCIDX(125, index-register)
 * PR_PCERR(126, error-register)	PR_PCSTS(127, status-register)
 */
#define KA43_PCTAG_TAG		0x1FFFF800	/* bits 11-29 */
#define KA43_PCTAG_PARITY	0x40000000
#define KA43_PCTAG_VALID	0x80000000

#define KA43_PCIDX_INDEX	0x000007F8	/* 0x100 Q-word entries */

#define KA43_PCERR_ADDR		0x3FFFFFFF

#define KA43_PCS_FORCEHIT	0x00000001	/* Force hit */
#define KA43_PCS_ENABLE		0x00000002	/* Enable primary cache */
#define KA43_PCS_FLUSH		0x00000004	/* Flush cache */
#define KA43_PCS_REFRESH	0x00000008	/* Enable refresh */
#define KA43_PCS_HIT		0x00000010	/* Cache hit */
#define KA43_PCS_INTERRUPT	0x00000020	/* Interrupt pending */
#define KA43_PCS_TRAP2		0x00000040	/* Trap while trap */
#define KA43_PCS_TRAP1		0x00000080	/* Micro trap/machine check */
#define KA43_PCS_TPERR		0x00000100	/* Tag parity error */
#define KA43_PCS_DPERR		0x00000200	/* Dal data parity error */
#define KA43_PCS_PPERR		0x00000400	/* P data parity error */
#define KA43_PCS_BUSERR		0x00000800	/* Bus error */
#define KA43_PCS_BCHIT		0x00001000	/* B cache hit */

#define KA43_PCSTS_BITS \
	"\020\015BCHIT\014BUSERR\013PPERR\012DPERR\011TPERR\010TRAP1" \
	"\007TRAP2\006INTR\005HIT\004REFRESH\003FLUSH\002ENABLE\001FORCEHIT"

/*
 * Bits in PR_ACCS (Floating Point Accelerator Register)
 */
#define KA43_ACCS_VECTOR	(1<<0)	/* Vector Unit Present */
#define KA43_ACCS_FCHIP		(1<<1)	/* FPU chip present */
#define KA43_ACCS_WEP		(1<<31)	/* Write Even Parity */

/*
 * Other fixed addresses which should be mapped
 */
#define KA43_CPU_BASE	0x20080000	/* so called "CPU registers" */
#define KA43_CPU_END	0x200800FF
#define KA43_CPU_SIZE	     0x100
#define KA43_NWA_BASE	0x20090000	/* Network Address ROM */
#define KA43_NWA_END	0x2009007F
#define KA43_NWA_SIZE	      0x80
#define KA43_SER_BASE	0x200A0000	/* Serial line controller */
#define KA43_SER_END	0x200A000F
#define KA43_SER_SIZE         0x10
#define KA43_WAT_BASE	0x200B0000	/* TOY clock and NV-RAM */
#define KA43_WAT_END	0x200B00FF
#define KA43_WAT_SIZE	     0x100
#define KA43_SC1_BASE	0x200C0080	/* 1st SCSI Controller Chip */
#define KA43_SC1_END	0x200C009F
#define KA43_SC1_SIZE	      0x20
#define KA43_SC2_BASE	0x200C0180	/* 2nd SCSI Controller Chip */
#define KA43_SC2_END	0x200C019F
#define KA43_SC2_SIZE	      0x20
#define KA43_SCS_BASE	0x200C0000	/* area occupied by SCSI 1+2 */
#define KA43_SCS_END	0x200C01FF
#define KA43_SCS_SIZE	     0x200
#define KA43_LAN_BASE	0x200E0000	/* LANCE chip registers */
#define KA43_LAN_END	0x200E0007
#define KA43_LAN_SIZE	      0x08
#define KA43_CUR_BASE	0x200F0000	/* Monochrome video cursor chip */
#define KA43_CUR_END	0x200F003C
#define KA43_CUR_SIZE	      0x40
#define KA43_DMA_BASE	0x202D0000	/* 128KB Data Buffer */
#define KA43_DMA_END	0x202EFFFF
#define KA43_DMA_SIZE      0x20000
#define KA43_VME_BASE	0x30000000
#define KA43_VME_END	0x3003FFFF
#define KA43_VME_SIZE	   0x40000

#define KA43_DIAGMEM	0x28000000	/* start of diagnostic memory */

#define KA43_SC1_DADR	0x200C00A0	/* (1st SCSI) DMA address register */
#define KA43_SC1_DCNT	0x200C00C0	/* (1st SCSI) DMA byte count reg. */
#define KA43_SC1_DDIR	0x200C00C4	/* (1st SCSI) DMA transfer direction */
#define KA43_SC2_DADR	0x200C01A0
#define KA43_SC2_DCNT	0x200C01C0
#define KA43_SC2_DDIR	0x200C01C4

/*
 * Clock-Chip data in NVRAM
 */
#define KA43_CPMBX	0x200B0038	/* Console Mailbox (1 byte) */
#define KA43_CPFLG	0x200B003C	/* Console Program Flags (1 byte) */
#define KA43_LK201_ID	0x200B0040	/* Keyboard Variation (1 byte) */
#define KA43_CONS_ID	0x200B0044	/* Console Device Type (1 byte) */
#define KA43_SCR	0x200B0048	/* Console Scratch RAM */
#define KA43_TEMP	0x200B0058	/* Used by System Firmware */
#define KA43_BAT_CHK	0x200B0088	/* Battery Check Data */
#define KA43_PASSWD	0x200B0098	/* ??? */
#define KA43_BOOTFLG	0x200B00A8	/* Default Boot Flags (4 bytes) */
#define KA43_SCRLEN	0x200B00B8	/* Number of pages of SCR (1 byte) */
#define KA43_SCSIPORT	0x200B00BC	/* Tape Controller Port Data */
#define KA43_RESERVED	0x200B00C0	/* Reserved (16 bytes) */

struct ka43_cpu {
	u_long  hltcod;		/* Halt Code Register */
	u_long  pad2;
	u_long  pad3;
	u_char  intreg[4];	/* Four 1-byte registers */
	u_short	diagdsp;	/* Diagnostic display register */
	u_short pad4;
	u_long	parctl;		/* Parity Control Register */
	u_short pad5;
	u_short pad6;
	u_short pad7;
	u_short	diagtme;	/* Diagnostic time register */
};

struct ka43_clock {
	u_long  :2;	u_long	sec	:8;	u_long  :22;
	u_long  :2;	u_long	secalrm :8;	u_long  :22;
	u_long  :2;	u_long	min	:8;	u_long  :22;
	u_long  :2;	u_long	minalrm	:8;	u_long  :22;
	u_long  :2;	u_long	hr	:8;	u_long  :22;
	u_long  :2;	u_long	hralrm	:8;	u_long  :22;
	u_long  :2;	u_long	dayofwk	:8;	u_long  :22;
	u_long  :2;	u_long	day	:8;	u_long  :22;
	u_long  :2;	u_long	mon	:8;	u_long  :22;
	u_long  :2;	u_long	yr	:8;	u_long  :22;
	u_long  :2;	u_long	csr0	:8;	u_long  :22;
	u_long  :2;	u_long	csr1	:8;	u_long  :22;
	u_long  :2;	u_long	csr2	:8;	u_long  :22;
	u_long  :2;	u_long	csr3	:8;	u_long  :22;
	u_long  :2;	u_long	req	:4;
			u_long	halt	:4;	u_long  :22;
};


code:
/*	$OpenBSD: ka46.h,v 1.1 2000/04/26 06:08:27 bjc Exp $	*/
/*	$NetBSD: ka46.h,v 1.2 1998/08/11 17:52:58 ragge Exp $ */
/*
 * Copyright (c) 1998 Ludd, University of Lule}, Sweden.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *      This product includes software developed at Ludd, University of
 *      Lule}, Sweden and its contributors.
 * 4. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/*
 * KA46 (VS4000/60) specific definitions.
 */

/* IPR bits definitions */
#define	PCSTS_FLUSH		 4
#define	PCSTS_ENABLE		 2
#define	PCTAG_PARITY	0x80000000
#define	PCTAG_VALID		 1

/* memory addresses of interest */
#define	KA46_INVFLT	0x20200000
#define	KA46_INVFLTSZ	32768
#define	KA46_CCR	0x23000000
#define	KA46_TAGST	0x2d000000
#define	KA46_TAGSZ	32768

#define	CCR_CENA	0x00000001
#define	CCR_SPECIO	0x00000010

#define	KA46_BWF0	0x20080014
#define	BWF0_FEN	0x01000000