code:
/*	$OpenBSD: pxa2x0_mmc.c,v 1.11 2012/08/22 13:37:04 jsg Exp $	*/

/*
 * Copyright (c) 2007 Uwe Stuehler <uwe@openbsd.org>
 *
 * Permission to use, copy, modify, and distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

/*
 * MMC/SD/SDIO controller driver for Intel PXA27x processors
 *
 * Power management is beyond control of the processor's SD/SDIO/MMC
 * block, so this driver depends on the attachment driver to provide
 * us with some callback functions via the "tag" member in our softc.
 * Bus power management calls are then dispatched to the attachment
 * driver.
 */

#include <sys/param.h>
#include <sys/device.h>
#include <sys/kernel.h>
#include <sys/proc.h>
#include <sys/systm.h>

#include <machine/bus.h>

#include <arch/arm/xscale/pxa2x0_gpio.h>
#include <arch/arm/xscale/pxa2x0reg.h>
#include <arch/arm/xscale/pxa2x0var.h>
#include <arch/arm/xscale/pxammcvar.h>

#include <dev/sdmmc/sdmmcchip.h>
#include <dev/sdmmc/sdmmcreg.h>
#include <dev/sdmmc/sdmmcvar.h>

/* GPIO pins */
#define PXAMMC_MMCLK		32
#define PXAMMC_MMCMD		112
#define PXAMMC_MMDAT0		92
#define PXAMMC_MMDAT1		109
#define PXAMMC_MMDAT2		110
#define PXAMMC_MMDAT3		111

int	pxammc_host_reset(sdmmc_chipset_handle_t);
u_int32_t pxammc_host_ocr(sdmmc_chipset_handle_t);
int	pxammc_host_maxblklen(sdmmc_chipset_handle_t);
int	pxammc_card_detect(sdmmc_chipset_handle_t);
int	pxammc_bus_power(sdmmc_chipset_handle_t, u_int32_t);
int	pxammc_bus_clock(sdmmc_chipset_handle_t, int);
void	pxammc_exec_command(sdmmc_chipset_handle_t, struct sdmmc_command *);
void	pxammc_clock_stop(struct pxammc_softc *);
void	pxammc_clock_start(struct pxammc_softc *);
int	pxammc_card_intr(void *);
int	pxammc_intr(void *);
static inline void	pxammc_intr_cmd(struct pxammc_softc *);
static inline void	pxammc_intr_data(struct pxammc_softc *);
void	pxammc_intr_done(struct pxammc_softc *);

#define CSR_READ_1(sc, reg) \
	bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg))
#define CSR_WRITE_1(sc, reg, val) \
	bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
#define CSR_READ_4(sc, reg) \
	bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))
#define CSR_WRITE_4(sc, reg, val) \
	bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
#define CSR_SET_4(sc, reg, bits) \
	CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) | (bits))
#define CSR_CLR_4(sc, reg, bits) \
	CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) & ~(bits))

struct sdmmc_chip_functions pxammc_functions = {
	/* host controller reset */
	pxammc_host_reset,
	/* host controller capabilities */
	pxammc_host_ocr,
	pxammc_host_maxblklen,
	/* card detection */
	pxammc_card_detect,
	/* bus power and clock frequency */
	pxammc_bus_power,
	pxammc_bus_clock,
	/* command execution */
	pxammc_exec_command
};

struct cfdriver pxammc_cd = {
	NULL, "pxammc", DV_DULL
};

#ifdef SDMMC_DEBUG
int sdhcdebug = 0;	/* XXX must be named sdhcdebug for sdmmc.c */
#define DPRINTF(n,s)	do { if ((n) <= sdhcdebug) printf s; } while (0)
#else
#define DPRINTF(n,s)	do {} while (0)
#endif

int
pxammc_match(void)
{
	return (cputype & ~CPU_ID_XSCALE_COREREV_MASK) == CPU_ID_PXA27X;
}

void
pxammc_attach(struct pxammc_softc *sc, void *aux)
{
	struct pxaip_attach_args *pxa = aux;
	struct sdmmcbus_attach_args saa;
	int s;

	/* Enable the clocks to the MMC controller. */
	pxa2x0_clkman_config(CKEN_MMC, 1);

	sc->sc_iot = pxa->pxa_sa.sa_iot;
	if (bus_space_map(sc->sc_iot, PXA2X0_MMC_BASE, PXA2X0_MMC_SIZE, 0,
	    &sc->sc_ioh) != 0) {
		printf(": can't map regs\n");
		goto fail;
	}

	/*
	 * Establish the card detection and MMC interrupt handlers and
	 * mask all interrupts until we are prepared to handle them.
	 */
	s = splsdmmc();

	pxa2x0_gpio_set_function(sc->sc_gpio_detect, GPIO_IN);
	sc->sc_card_ih = pxa2x0_gpio_intr_establish(sc->sc_gpio_detect,
	    IST_EDGE_BOTH, IPL_SDMMC, pxammc_card_intr, sc, "mmccd");
	if (sc->sc_card_ih == NULL) {
		splx(s);
		printf(": can't establish card interrupt\n");
		goto fail;
	}
	pxa2x0_gpio_intr_mask(sc->sc_card_ih);

	sc->sc_ih = pxa2x0_intr_establish(PXA2X0_INT_MMC, IPL_SDMMC,
	    pxammc_intr, sc, sc->sc_dev.dv_xname);
	if (sc->sc_ih == NULL) {
		splx(s);
		printf(": can't establish MMC interrupt\n");
		goto fail;
	}
	CSR_WRITE_4(sc, MMC_I_MASK, 0xffffffff);

	splx(s);

	printf(": MMC/SD/SDIO controller\n");

	/*
	 * Configure the GPIO pins.  In SD/MMC mode, all pins except
	 * MMCLK are bidirectional and the direction is controlled in
	 * hardware without our assistence.
	 */
	pxa2x0_gpio_set_function(PXAMMC_MMCLK, GPIO_ALT_FN_2_OUT);
	pxa2x0_gpio_set_function(PXAMMC_MMCMD, GPIO_ALT_FN_1_IN);
	pxa2x0_gpio_set_function(PXAMMC_MMDAT0, GPIO_ALT_FN_1_IN);
	pxa2x0_gpio_set_function(PXAMMC_MMDAT1, GPIO_ALT_FN_1_IN);
	pxa2x0_gpio_set_function(PXAMMC_MMDAT2, GPIO_ALT_FN_1_IN);
	pxa2x0_gpio_set_function(PXAMMC_MMDAT3, GPIO_ALT_FN_1_IN);

	/*
	 * Reset the host controller and unmask normal interrupts.
	 */
	(void)pxammc_host_reset(sc);

	/*
	 * Attach the generic sdmmc bus driver.
	 */
	bzero(&saa, sizeof saa);
	saa.saa_busname = "sdmmc";
	saa.sct = &pxammc_functions;
	saa.sch = sc;
	saa.flags = SMF_STOP_AFTER_MULTIPLE;
	saa.max_xfer = 1;

	sc->sc_sdmmc = config_found(&sc->sc_dev, &saa, NULL);
	if (sc->sc_sdmmc == NULL) {
		printf("%s: can't attach bus\n", sc->sc_dev.dv_xname);
		goto fail;
	}

	/* Enable card detection interrupt. */
	pxa2x0_gpio_intr_unmask(sc->sc_card_ih);
	return;

fail:
	if (sc->sc_ih != NULL) {
		pxa2x0_intr_disestablish(sc->sc_ih);
		sc->sc_ih = NULL;
	}
	if (sc->sc_card_ih != NULL) {
		pxa2x0_gpio_intr_disestablish(sc->sc_card_ih);
		sc->sc_card_ih = NULL;
	}
	if (sc->sc_ioh != 0) {
		bus_space_unmap(sc->sc_iot, sc->sc_ioh, PXA2X0_MMC_SIZE);
		sc->sc_ioh = 0;
	}
	pxa2x0_clkman_config(CKEN_MMC, 0);
}

int
pxammc_host_reset(sdmmc_chipset_handle_t sch)
{
	struct pxammc_softc *sc = sch;
	int s = splsdmmc();

	/* Make sure to initialize the card before the next command. */
	CLR(sc->sc_flags, PMF_CARD_INITED);

	/* Disable SPI mode (we don't support SPI). */
	CSR_WRITE_4(sc, MMC_SPI, 0);

	/* Set response timeout to maximum. */
	CSR_WRITE_4(sc, MMC_RESTO, 0x7f);

	/* Enable all interrupts. */
	CSR_WRITE_4(sc, MMC_I_MASK, 0);

	splx(s);
	return 0;
}

int
pxammc_host_maxblklen(sdmmc_chipset_handle_t sch)
{
	return 2048;
}

u_int32_t
pxammc_host_ocr(sdmmc_chipset_handle_t sch)
{
	struct pxammc_softc *sc = sch;

	if (sc->tag.get_ocr != NULL)
		return sc->tag.get_ocr(sc->tag.cookie);

	DPRINTF(0,("%s: driver lacks get_ocr() function\n",
	    sc->sc_dev.dv_xname));
	return ENXIO;
}

int
pxammc_card_detect(sdmmc_chipset_handle_t sch)
{
	struct pxammc_softc *sc = sch;
	return !pxa2x0_gpio_get_bit(sc->sc_gpio_detect);
}

int
pxammc_bus_power(sdmmc_chipset_handle_t sch, u_int32_t ocr)
{
	struct pxammc_softc *sc = sch;

	/*
	 * Bus power management is beyond control of the SD/SDIO/MMC
	 * block of the PXA2xx processors, so we have to hand this
	 * task off to the attachment driver.
	 */
	if (sc->tag.set_power != NULL)
		return sc->tag.set_power(sc->tag.cookie, ocr);

	DPRINTF(0,("%s: driver lacks set_power() function\n",
	    sc->sc_dev.dv_xname));
	return ENXIO;
}

int
pxammc_bus_clock(sdmmc_chipset_handle_t sch, int freq)
{
	struct pxammc_softc *sc = sch;
	int actfreq = 19500; /* KHz */
	int div = 0;
	int s;

	s = splsdmmc();

	/* Stop the clock and wait for the interrupt. */
	pxammc_clock_stop(sc);

	/* Just stop the clock. */
	if (freq == 0) {
		splx(s);
		return 0;
	}

	/*
	 * PXA27x Errata...
	 *
	 * <snip>
	 * E40. SDIO: SDIO Devices Not Working at 19.5 Mbps
	 *
	 * SD/SDIO controller can only support up to 9.75 Mbps data
	 * transfer rate for SDIO card.
	 * </snip>
	 *
	 * If we don't limit the frequency, CRC errors will be
	 * reported by the controller after we set the bus speed.
	 * XXX slow down incrementally.
	 */
	if (freq > 9750)
		freq = 9750;

	/*
	 * Pick the smallest divider that produces a frequency not
	 * more than `freq' KHz.
	 */
	while (div < 7) {
		if (actfreq <= freq)
			break;
		actfreq /= 2;
		div++;
	}
	if (div == 7) {
		splx(s);
		printf("%s: unsupported bus frequency of %d KHz\n",
		    sc->sc_dev.dv_xname, freq);
		return -1;
	}

	DPRINTF(1,("pxammc_bus_clock freq=%d actfreq=%d div=%d\n",
	    freq, actfreq, div));
	sc->sc_clkdiv = div;
	pxammc_clock_start(sc);
	splx(s);
	return 0;
}

void
pxammc_exec_command(sdmmc_chipset_handle_t sch,
    struct sdmmc_command *cmd)
{
	struct pxammc_softc *sc = sch;
	u_int32_t cmdat;
	int timo;
	int s;

	DPRINTF(1,("%s: cmd %u arg=%#x data=%#x dlen=%d flags=%#x "
	    "proc=\"%s\"\n", sc->sc_dev.dv_xname, cmd->c_opcode,
	    cmd->c_arg, cmd->c_data, cmd->c_datalen, cmd->c_flags,
	    curproc ? curproc->p_comm : ""));

	s = splsdmmc();

	/* Stop the bus clock (MMCLK). [15.8.3] */
	pxammc_clock_stop(sc);

	/* Set the command and argument. */
	CSR_WRITE_4(sc, MMC_CMD, cmd->c_opcode);
	CSR_WRITE_4(sc, MMC_ARGH, (cmd->c_arg >> 16) & 0xffff);
	CSR_WRITE_4(sc, MMC_ARGL, cmd->c_arg & 0xffff);

	/* Set response characteristics for this command. */
	if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT))
		cmdat = CMDAT_RESPONSE_FORMAT_NO;
	else if (ISSET(cmd->c_flags, SCF_RSP_136))
		cmdat = CMDAT_RESPONSE_FORMAT_R2;
	else if (!ISSET(cmd->c_flags, SCF_RSP_CRC))
		cmdat = CMDAT_RESPONSE_FORMAT_R3;
	else
		cmdat = CMDAT_RESPONSE_FORMAT_R1;

	if (ISSET(cmd->c_flags, SCF_RSP_BSY))
		cmdat |= CMDAT_BUSY;

	if (!ISSET(cmd->c_flags, SCF_CMD_READ))
		cmdat |= CMDAT_WRITE;

	/* Fragment the data into proper blocks. */
	if (cmd->c_datalen > 0) {
		int blklen = MIN(cmd->c_datalen, cmd->c_blklen);
		int numblk = cmd->c_datalen / blklen;

		if (cmd->c_datalen % blklen > 0) {
			/* XXX: Split this command. (1.7.4) */
			printf("%s: data not a multiple of %d bytes\n",
			    sc->sc_dev.dv_xname, blklen);
			cmd->c_error = EINVAL;
			splx(s);
			return;
		}

		CSR_WRITE_4(sc, MMC_BLKLEN, blklen);
		CSR_WRITE_4(sc, MMC_NUMBLK, numblk);

		/* Enable data interrupts. */
		CSR_CLR_4(sc, MMC_I_MASK,
		    MMC_I_RXFIFO_RD_REQ | MMC_I_TXFIFO_WR_REQ |
		    MMC_I_DAT_ERR);

		cmd->c_resid = cmd->c_datalen;
		cmd->c_buf = cmd->c_data;

		cmdat |= CMDAT_DATA_EN;
	} else {
		cmd->c_resid = 0;
		cmd->c_buf = NULL;
	}

	/*
	 * "After reset, the MMC card must be initialized by sending
	 * 80 clocks to it on the MMCLK signal." [15.4.3.2]
	 */
	if (!ISSET(sc->sc_flags, PMF_CARD_INITED)) {
		DPRINTF(1,("%s: first command\n", sc->sc_dev.dv_xname));
		cmdat |= CMDAT_INIT;
		SET(sc->sc_flags, PMF_CARD_INITED);
	}

	/* Begin the transfer and start the bus clock. */
	CSR_WRITE_4(sc, MMC_CMDAT, cmdat);
	pxammc_clock_start(sc);

	/* Wait for it to complete (in no more than 2 seconds). */
	CSR_CLR_4(sc, MMC_I_MASK, MMC_I_END_CMD_RES | MMC_I_RES_ERR);
	timo = 2;
	sc->sc_cmd = cmd;
	do { tsleep(sc, PWAIT, "mmcmd", hz); }
	while (sc->sc_cmd == cmd && timo-- > 0);

	/* If it completed in time, SCF_ITSDONE is already set. */
	if (sc->sc_cmd == cmd) {
		sc->sc_cmd = NULL;
		cmd->c_error = ETIMEDOUT;
		SET(cmd->c_flags, SCF_ITSDONE);
	}
	splx(s);
}

void
pxammc_clock_stop(struct pxammc_softc *sc)
{
	if (ISSET(CSR_READ_4(sc, MMC_STAT), STAT_CLK_EN)) {
		CSR_CLR_4(sc, MMC_I_MASK, MMC_I_CLK_IS_OFF);
		CSR_WRITE_4(sc, MMC_STRPCL, STRPCL_STOP);
		while (ISSET(CSR_READ_4(sc, MMC_STAT), STAT_CLK_EN))
			tsleep(sc, PWAIT, "mmclk", 0);
	}
}

void
pxammc_clock_start(struct pxammc_softc *sc)
{
	CSR_WRITE_4(sc, MMC_CLKRT, sc->sc_clkdiv);
	CSR_WRITE_4(sc, MMC_STRPCL, STRPCL_START);
}

int
pxammc_card_intr(void *arg)
{
	struct pxammc_softc *sc = arg;

	DPRINTF(1,("%s: card intr\n", sc->sc_dev.dv_xname));

	/* Scan for inserted or removed cards. */
	sdmmc_needs_discover(sc->sc_sdmmc);

	return 1;
}

int
pxammc_intr(void *arg)
{
	struct pxammc_softc *sc = arg;
	int status;
#ifdef DIAGNOSTIC
	int wstatus;
#endif

#define MMC_I_REG_STR	"\20\001DATADONE\002PRGDONE\003ENDCMDRES"	\
			"\004STOPCMD\005CLKISOFF\006RXFIFO\007TXFIFO"	\
			"\011DATERR\012RESERR\014SDIO"

#ifdef DIAGNOSTIC
	wstatus =
#endif
	status = CSR_READ_4(sc, MMC_I_REG) & ~CSR_READ_4(sc, MMC_I_MASK);
	DPRINTF(1,("%s: intr %b\n", sc->sc_dev.dv_xname, status,
	    MMC_I_REG_STR));

	/*
	 * Notify the process waiting in pxammc_clock_stop() when
	 * the clock has really stopped.
	 */
	if (ISSET(status, MMC_I_CLK_IS_OFF)) {
		DPRINTF(2,("%s: clock is now off\n", sc->sc_dev.dv_xname));
		wakeup(sc);
		CSR_SET_4(sc, MMC_I_MASK, MMC_I_CLK_IS_OFF);
		CLR(status, MMC_I_CLK_IS_OFF);
	}

	if (sc->sc_cmd == NULL)
		goto end;

	if (ISSET(status, MMC_I_RES_ERR)) {
		CSR_SET_4(sc, MMC_I_MASK, MMC_I_RES_ERR);
		CLR(status, MMC_I_RES_ERR | MMC_I_END_CMD_RES);
		sc->sc_cmd->c_error = ENOEXEC;
		pxammc_intr_done(sc);
		goto end;
	}

	if (ISSET(status, MMC_I_END_CMD_RES)) {
		pxammc_intr_cmd(sc);
		CSR_SET_4(sc, MMC_I_MASK, MMC_I_END_CMD_RES);
		CLR(status, MMC_I_END_CMD_RES);
		/* ignore programming done condition */
		if (ISSET(status, MMC_I_PRG_DONE)) {
			CSR_SET_4(sc, MMC_I_MASK, MMC_I_PRG_DONE);
			CLR(status, MMC_I_PRG_DONE);
		}
		if (sc->sc_cmd == NULL)
			goto end;
	}

	if (ISSET(status, MMC_I_DAT_ERR)) {
		sc->sc_cmd->c_error = EIO;
		pxammc_intr_done(sc);
		CSR_SET_4(sc, MMC_I_MASK, MMC_I_DAT_ERR);
		CLR(status, MMC_I_DAT_ERR);
		/* ignore transmission done condition */
		if (ISSET(status, MMC_I_DATA_TRAN_DONE)) {
			CSR_SET_4(sc, MMC_I_MASK, MMC_I_DATA_TRAN_DONE);
			CLR(status, MMC_I_DATA_TRAN_DONE);
		}
		goto end;
	}

	if (ISSET(status, MMC_I_DATA_TRAN_DONE)) {
		pxammc_intr_done(sc);
		CSR_SET_4(sc, MMC_I_MASK, MMC_I_DATA_TRAN_DONE);
		CLR(status, MMC_I_DATA_TRAN_DONE);
	}

	if (ISSET(status, MMC_I_TXFIFO_WR_REQ | MMC_I_RXFIFO_RD_REQ)) {
		pxammc_intr_data(sc);
		CLR(status, MMC_I_TXFIFO_WR_REQ | MMC_I_RXFIFO_RD_REQ);
	}

end:
	/* Avoid further unhandled interrupts. */
	if (status != 0) {
#ifdef DIAGNOSTIC
		printf("%s: unhandled interrupt %b out of %b\n",
		    sc->sc_dev.dv_xname, status, MMC_I_REG_STR,
		    wstatus, MMC_I_REG_STR);
#endif
		CSR_SET_4(sc, MMC_I_MASK, status);
	}

	return 1;
}

static inline void
pxammc_intr_cmd(struct pxammc_softc *sc)
{
	struct sdmmc_command *cmd = sc->sc_cmd;
	u_int32_t status;
	int i;

#define MMC_STAT_STR	"\20\001READ_TIME_OUT\002TIMEOUT_RESPONSE"	\
			"\003CRC_WRITE_ERROR\004CRC_READ_ERROR"		\
			"\005SPI_READ_ERROR_TOKEN\006RES_CRC_ERR"	\
			"\007XMIT_FIFO_EMPTY\010RECV_FIFO_FULL"		\
			"\011CLK_EN\012FLASH_ERR\013SPI_WR_ERR"		\
			"\014DATA_TRAN_DONE\015PRG_DONE\016END_CMD_RES"	\
			"\017RD_STALLED\020SDIO_INT\021SDIO_SUSPEND_ACK"

#define STAT_ERR	(STAT_READ_TIME_OUT | STAT_TIMEOUT_RESPONSE |	\
			 STAT_CRC_WRITE_ERROR | STAT_CRC_READ_ERROR |	\
			 STAT_SPI_READ_ERROR_TOKEN | STAT_RES_CRC_ERR)

	if (ISSET(cmd->c_flags, SCF_RSP_136)) {
		for (i = 3; i >= 0; i--) {
			u_int32_t h = CSR_READ_4(sc, MMC_RES) & 0xffff;
			u_int32_t l = CSR_READ_4(sc, MMC_RES) & 0xffff;
			cmd->c_resp[i] = (h << 16) | l;
		}
		cmd->c_error = 0;
	} else if (ISSET(cmd->c_flags, SCF_RSP_PRESENT)) {
		/*
		 * Grrr... The processor manual is not clear about
		 * the layout of the response FIFO.  It just states
		 * that the FIFO is 16 bits wide, has a depth of 8,
		 * and that the CRC is not copied into the FIFO.
		 *
		 * A 16-bit word in the FIFO is filled from highest
		 * to lowest bit as the response comes in.  The two
		 * start bits and the 6 command index bits are thus
		 * stored in the upper 8 bits of the first 16-bit
		 * word that we read back from the FIFO.
		 *
		 * Since the sdmmc(4) framework expects the host
		 * controller to discard the first 8 bits of the
		 * response, what we must do is discard the upper
		 * byte of the first 16-bit word.
		 */
		u_int32_t h = CSR_READ_4(sc, MMC_RES) & 0xffff;
		u_int32_t m = CSR_READ_4(sc, MMC_RES) & 0xffff;
		u_int32_t l = CSR_READ_4(sc, MMC_RES) & 0xffff;
		cmd->c_resp[0] = h << 24 | m << 8 | l >> 8;
		for (i = 1; i < 4; i++)
			cmd->c_resp[i] = 0;
		cmd->c_error = 0;
	}

	status = CSR_READ_4(sc, MMC_STAT);

	if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT))
		status &= ~STAT_TIMEOUT_RESPONSE;

	/* XXX only for R6, not for R2 */
	if (!ISSET(cmd->c_flags, SCF_RSP_IDX))
		status &= ~STAT_RES_CRC_ERR;

	if (ISSET(status, STAT_TIMEOUT_RESPONSE))
		cmd->c_error = ETIMEDOUT;
	else if (ISSET(status, STAT_ERR))
		cmd->c_error = EIO;

	if (cmd->c_error || cmd->c_datalen < 1)
		pxammc_intr_done(sc);
}

static inline void
pxammc_intr_data(struct pxammc_softc *sc)
{
	struct sdmmc_command *cmd = sc->sc_cmd;
	int n;

	n = MIN(32, cmd->c_resid);
	cmd->c_resid -= n;

	DPRINTF(2,("%s: cmd %p resid %d\n", sc->sc_dev.dv_xname,
	    cmd, cmd->c_resid));

	if (ISSET(cmd->c_flags, SCF_CMD_READ)) {
		while (n-- > 0)
			*cmd->c_buf++ = CSR_READ_1(sc, MMC_RXFIFO);

		if (cmd->c_resid > 0)
			CSR_CLR_4(sc, MMC_I_MASK, MMC_I_RXFIFO_RD_REQ);
		else {
			CSR_SET_4(sc, MMC_I_MASK, MMC_I_RXFIFO_RD_REQ);
			CSR_CLR_4(sc, MMC_I_MASK, MMC_I_DATA_TRAN_DONE);
		}
	} else {
		int short_xfer = (n != 0 && n != 32);

		while (n-- > 0)
			CSR_WRITE_1(sc, MMC_TXFIFO, *cmd->c_buf++);
		if (short_xfer)
			CSR_WRITE_4(sc, MMC_PRTBUF, 1);

		if (cmd->c_resid > 0)
			CSR_CLR_4(sc, MMC_I_MASK, MMC_I_TXFIFO_WR_REQ);
		else {
			CSR_SET_4(sc, MMC_I_MASK, MMC_I_TXFIFO_WR_REQ);
			CSR_CLR_4(sc, MMC_I_MASK, MMC_I_DATA_TRAN_DONE);
		}
	}
}

/*
 * Wake up the process sleeping in pxammc_exec_command().
 */
void
pxammc_intr_done(struct pxammc_softc *sc)
{
	DPRINTF(1,("%s: status %b\n", sc->sc_dev.dv_xname,
	    CSR_READ_4(sc, MMC_STAT), MMC_STAT_STR));

	CSR_SET_4(sc, MMC_I_MASK, MMC_I_TXFIFO_WR_REQ |
	    MMC_I_RXFIFO_RD_REQ | MMC_I_DATA_TRAN_DONE |
	    MMC_I_END_CMD_RES | MMC_I_RES_ERR | MMC_I_DAT_ERR);

	SET(sc->sc_cmd->c_flags, SCF_ITSDONE);
	sc->sc_cmd = NULL;
	wakeup(sc);
}


code:
/*	$OpenBSD: pxa2x0_mutex.c,v 1.2 2009/08/13 13:24:55 weingart Exp $	*/

/*
 * Copyright (c) 2004 Artur Grabowski <art@openbsd.org>
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
 * THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL  DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <sys/param.h>
#include <sys/mutex.h>
#include <sys/systm.h>

#include <machine/intr.h>

#ifdef MULTIPROCESSOR
#error This code needs work
#endif

/*
 * Single processor systems don't need any mutexes, but they need the spl
 * raising semantics of the mutexes.
 */
void
mtx_init(struct mutex *mtx, int wantipl)
{
	mtx->mtx_oldipl = 0;
	mtx->mtx_wantipl = wantipl;
	mtx->mtx_lock = 0;
}

void
mtx_enter(struct mutex *mtx)
{
	if (mtx->mtx_wantipl != IPL_NONE)
		mtx->mtx_oldipl = _splraise(mtx->mtx_wantipl);

	MUTEX_ASSERT_UNLOCKED(mtx);
	mtx->mtx_lock = 1;
}

int
mtx_enter_try(struct mutex *mtx)
{
	if (mtx->mtx_wantipl != IPL_NONE)
		mtx->mtx_oldipl = _splraise(mtx->mtx_wantipl);

	MUTEX_ASSERT_UNLOCKED(mtx);
	mtx->mtx_lock = 1;
	return 1;
}

void
mtx_leave(struct mutex *mtx)
{
	MUTEX_ASSERT_LOCKED(mtx);
	mtx->mtx_lock = 0;
	if (mtx->mtx_wantipl != IPL_NONE)
		splx(mtx->mtx_oldipl);
}

license: unknown


code:
/*	$OpenBSD: pxa2x0_ohci.c,v 1.26 2014/05/19 13:11:31 mpi Exp $ */

/*
 * Copyright (c) 2005 David Gwynne <dlg@openbsd.org>
 *
 * Permission to use, copy, modify, and distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <sys/kernel.h>
#include <sys/timeout.h>

#include <machine/intr.h>
#include <machine/bus.h>

#include <arm/xscale/pxa2x0reg.h>
#include <arm/xscale/pxa2x0var.h>
#include <arm/xscale/pxa2x0_gpio.h>

#include <dev/usb/usb.h>
#include <dev/usb/usbdi.h>
#include <dev/usb/usbdivar.h>
#include <dev/usb/usb_mem.h>

#include <dev/usb/ohcireg.h>
#include <dev/usb/ohcivar.h>

int	pxaohci_match(struct device *, void *, void *);
void	pxaohci_attach(struct device *, struct device *, void *);
int	pxaohci_detach(struct device *, int);
int	pxaohci_activate(struct device *, int);

struct pxaohci_softc {
	struct ohci_softc	sc;
	void			*sc_ih;
};

void	pxaohci_enable(struct pxaohci_softc *);
void	pxaohci_disable(struct pxaohci_softc *);

struct cfattach pxaohci_ca = {
        sizeof (struct pxaohci_softc), pxaohci_match, pxaohci_attach,
	pxaohci_detach, ohci_activate
};

int
pxaohci_match(struct device *parent, void *match, void *aux)
{
	if ((cputype & ~CPU_ID_XSCALE_COREREV_MASK) != CPU_ID_PXA27X)
		return (0);

	return (1);
}

void
pxaohci_attach(struct device *parent, struct device *self, void *aux)
{
	struct pxaohci_softc		*sc = (struct pxaohci_softc *)self;
	struct pxaip_attach_args	*pxa = aux;
	usbd_status			r;

	sc->sc.iot = pxa->pxa_iot;
	sc->sc.sc_bus.dmatag = pxa->pxa_dmat;
	sc->sc_ih = NULL;
	sc->sc.sc_size = 0;

	/* Map I/O space */
	if (bus_space_map(sc->sc.iot, PXA2X0_USBHC_BASE, PXA2X0_USBHC_SIZE, 0,
	    &sc->sc.ioh)) {
		printf(": cannot map mem space\n");
		return;
	}
	sc->sc.sc_size = PXA2X0_USBHC_SIZE;

	/* XXX copied from ohci_pci.c. needed? */
	bus_space_barrier(sc->sc.iot, sc->sc.ioh, 0, sc->sc.sc_size,
	    BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE);

	/* start the usb clock */
	pxa2x0_clkman_config(CKEN_USBHC, 1);
	pxaohci_enable(sc);

	/* Disable interrupts, so we don't get any spurious ones. */
	bus_space_write_4(sc->sc.iot, sc->sc.ioh, OHCI_INTERRUPT_DISABLE,
	    OHCI_MIE);

	sc->sc_ih = pxa2x0_intr_establish(PXA2X0_INT_USBH1, IPL_USB,
	    ohci_intr, &sc->sc, sc->sc.sc_bus.bdev.dv_xname);
	if (sc->sc_ih == NULL) {
		printf(": unable to establish interrupt\n");
		pxaohci_disable(sc);
		pxa2x0_clkman_config(CKEN_USBHC, 0);
		bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size);
		sc->sc.sc_size = 0;
		return;
	}

	strlcpy(sc->sc.sc_vendor, "PXA27x", sizeof(sc->sc.sc_vendor));

	if (ohci_checkrev(&sc->sc) != USBD_NORMAL_COMPLETION)
		goto unsupported;

	r = ohci_init(&sc->sc);
	if (r != USBD_NORMAL_COMPLETION) {
		printf("%s: init failed, error=%d\n",
		    sc->sc.sc_bus.bdev.dv_xname, r);
unsupported:
		pxa2x0_intr_disestablish(sc->sc_ih);
		sc->sc_ih = NULL;
		pxaohci_disable(sc);
		pxa2x0_clkman_config(CKEN_USBHC, 0);
		bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size);
		sc->sc.sc_size = 0;
		return;
	}

	config_found(self, &sc->sc.sc_bus, usbctlprint);
}

int
pxaohci_detach(struct device *self, int flags)
{
	struct pxaohci_softc		*sc = (struct pxaohci_softc *)self;
	int				rv;

	rv = ohci_detach(self, flags);
	if (rv)
		return (rv);

	if (sc->sc_ih != NULL) {
		pxa2x0_intr_disestablish(sc->sc_ih);
		sc->sc_ih = NULL;
	}

	pxaohci_disable(sc);

	/* stop clock */
	pxa2x0_clkman_config(CKEN_USBHC, 0);

	if (sc->sc.sc_size) {
		bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size);
		sc->sc.sc_size = 0;
	}

	return (0);
}

int
pxaohci_activate(struct device *self, int act)
{
	struct pxaohci_softc *sc = (struct pxaohci_softc *)self;

	switch (act) {
	case DVACT_SUSPEND:
		sc->sc.sc_bus.use_polling++;
		ohci_activate((struct device *)&sc->sc, act);
		pxa2x0_clkman_config(CKEN_USBHC, 0);
		sc->sc.sc_bus.use_polling--;
		break;
	case DVACT_RESUME:
		sc->sc.sc_bus.use_polling++;
		pxa2x0_clkman_config(CKEN_USBHC, 1);
		pxaohci_enable(sc);
		ohci_activate((struct device *)&sc->sc, act);
		sc->sc.sc_bus.use_polling--;
		break;
	}
	return 0;
}

void
pxaohci_enable(struct pxaohci_softc *sc)
{
	u_int32_t			hr;

	/* Full host reset */
	hr = bus_space_read_4(sc->sc.iot, sc->sc.ioh, USBHC_HR);
	bus_space_write_4(sc->sc.iot, sc->sc.ioh, USBHC_HR,
	    (hr & USBHC_HR_MASK) | USBHC_HR_FHR);

	DELAY(USBHC_RST_WAIT);

	hr = bus_space_read_4(sc->sc.iot, sc->sc.ioh, USBHC_HR);
	bus_space_write_4(sc->sc.iot, sc->sc.ioh, USBHC_HR,
	    (hr & USBHC_HR_MASK) & ~(USBHC_HR_FHR));

	/* Force system bus interface reset */
	hr = bus_space_read_4(sc->sc.iot, sc->sc.ioh, USBHC_HR);
	bus_space_write_4(sc->sc.iot, sc->sc.ioh, USBHC_HR,
	    (hr & USBHC_HR_MASK) | USBHC_HR_FSBIR);

	while (bus_space_read_4(sc->sc.iot, sc->sc.ioh, USBHC_HR) & \
	    USBHC_HR_FSBIR)
		DELAY(3);

	/* Enable the ports (physically only one, only enable that one?) */
	hr = bus_space_read_4(sc->sc.iot, sc->sc.ioh, USBHC_HR);
	bus_space_write_4(sc->sc.iot, sc->sc.ioh, USBHC_HR,
	    (hr & USBHC_HR_MASK) & ~(USBHC_HR_SSE));
	hr = bus_space_read_4(sc->sc.iot, sc->sc.ioh, USBHC_HR);
	bus_space_write_4(sc->sc.iot, sc->sc.ioh, USBHC_HR,
	    (hr & USBHC_HR_MASK) & ~(USBHC_HR_SSEP2));
}

void
pxaohci_disable(struct pxaohci_softc *sc)
{
	u_int32_t			hr;

	/* Full host reset */
	hr = bus_space_read_4(sc->sc.iot, sc->sc.ioh, USBHC_HR);
	bus_space_write_4(sc->sc.iot, sc->sc.ioh, USBHC_HR,
	    (hr & USBHC_HR_MASK) | USBHC_HR_FHR);

	DELAY(USBHC_RST_WAIT);

	hr = bus_space_read_4(sc->sc.iot, sc->sc.ioh, USBHC_HR);
	bus_space_write_4(sc->sc.iot, sc->sc.ioh, USBHC_HR,
	    (hr & USBHC_HR_MASK) & ~(USBHC_HR_FHR));
}


code:
/*	$OpenBSD: pxa2x0_pcic.c,v 1.20 2014/04/03 10:17:34 mpi Exp $	*/

/*
 * Copyright (c) 2005 Dale Rahn <drahn@openbsd.org>
 *
 * Permission to use, copy, modify, and distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <sys/kernel.h>
#include <sys/kthread.h>
#include <sys/malloc.h>

#include <uvm/uvm_extern.h>

#include <machine/bus.h>
#include <machine/intr.h>

#include <dev/pcmcia/pcmciareg.h>
#include <dev/pcmcia/pcmciavar.h>
#include <dev/pcmcia/pcmciachip.h>

#include <arm/xscale/pxa2x0reg.h>
#include <arm/xscale/pxa2x0var.h>
#include <arm/xscale/pxa2x0_gpio.h>
#include <arm/xscale/pxapcicvar.h>

int	pxapcic_print(void *, const char *);
int	pxapcic_submatch(struct device *, void *, void *);

void	pxapcic_create_event_thread(void *);
void    pxapcic_event_thread(void *);
void	pxapcic_event_process(struct pxapcic_socket *);
void	pxapcic_attach_card(struct pxapcic_socket *);
void	pxapcic_detach_card(struct pxapcic_socket *, int);
int	pxapcic_intr(void *);

int	pxapcic_mem_alloc(pcmcia_chipset_handle_t, bus_size_t,
    struct pcmcia_mem_handle *);
void	pxapcic_mem_free(pcmcia_chipset_handle_t,
    struct pcmcia_mem_handle *);
int	pxapcic_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t,
    bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *);
void	pxapcic_mem_unmap(pcmcia_chipset_handle_t, int);

int	pxapcic_io_alloc(pcmcia_chipset_handle_t, bus_addr_t,
    bus_size_t, bus_size_t, struct pcmcia_io_handle *);
void	pxapcic_io_free(pcmcia_chipset_handle_t,
    struct pcmcia_io_handle *);
int	pxapcic_io_map(pcmcia_chipset_handle_t, int,
    bus_addr_t, bus_size_t, struct pcmcia_io_handle *, int *);
void	pxapcic_io_unmap(pcmcia_chipset_handle_t, int);

void	*pxapcic_intr_establish(pcmcia_chipset_handle_t,
    struct pcmcia_function *, int, int (*)(void *), void *, char *);
void	pxapcic_intr_disestablish(pcmcia_chipset_handle_t, void *);
const char *pxapcic_intr_string(pcmcia_chipset_handle_t, void *);

void	pxapcic_socket_setup(struct pxapcic_socket *);
void	pxapcic_socket_enable(pcmcia_chipset_handle_t);
void	pxapcic_socket_disable(pcmcia_chipset_handle_t);

struct cfdriver pxapcic_cd = {
	NULL, "pxapcic", DV_DULL
};

/*
 * PCMCIA chipset methods
 */
struct pcmcia_chip_functions pxapcic_pcmcia_functions = {
	pxapcic_mem_alloc,
	pxapcic_mem_free,
	pxapcic_mem_map,
	pxapcic_mem_unmap,

	pxapcic_io_alloc,
	pxapcic_io_free,
	pxapcic_io_map,
	pxapcic_io_unmap,

	pxapcic_intr_establish,
	pxapcic_intr_disestablish,
	pxapcic_intr_string,

	pxapcic_socket_enable,
	pxapcic_socket_disable,
};

/*
 * PCMCIA Helpers
 */

int
pxapcic_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size,
    struct pcmcia_mem_handle *pmh)
{
	struct pxapcic_socket *so = pch;

	/* All we need is the bus space tag */
	memset(pmh, 0, sizeof(*pmh));
	pmh->memt = so->sc->sc_iot;
	return (0);
}

void
pxapcic_mem_free(pcmcia_chipset_handle_t pch, struct pcmcia_mem_handle *pmh)
{
}

int
pxapcic_mem_map(pcmcia_chipset_handle_t pch, int kind, bus_addr_t card_addr,
    bus_size_t size, struct pcmcia_mem_handle *pmh, bus_size_t *offsetp,
    int *windowp)
{
	struct pxapcic_socket *so = pch;
	int error;
	bus_addr_t pa;

	pa = trunc_page(card_addr);
	*offsetp = card_addr - pa;
	size = round_page(card_addr + size) - pa;
	pmh->realsize = size;

#define PXA2X0_SOCKET_OFFSET	(PXA2X0_PCMCIA_SLOT1-PXA2X0_PCMCIA_SLOT0)
#define PXAPCIC_ATTR_OFFSET	0x08000000
#define PXAPCIC_COMMON_OFFSET	0x0C000000

	pa += PXA2X0_PCMCIA_SLOT0;
	pa += PXA2X0_SOCKET_OFFSET * so->socket;

	switch (kind & ~PCMCIA_WIDTH_MEM_MASK) {
	case PCMCIA_MEM_ATTR:
		pa += PXAPCIC_ATTR_OFFSET;
		break;
	case PCMCIA_MEM_COMMON:
		pa += PXAPCIC_COMMON_OFFSET;
		break;
	default:
		panic("pxapcic_mem_map: bogus kind");
	}

	error = bus_space_map(so->sc->sc_iot, pa, size, 0, &pmh->memh);
	if (! error)
		*windowp = (int)pmh->memh;
	return (error);
}

void
pxapcic_mem_unmap(pcmcia_chipset_handle_t pch, int window)
{
        struct pxapcic_socket *so = pch;

        bus_space_unmap(so->sc->sc_iot, (bus_addr_t)window, 4096); /* XXX */
}

int
pxapcic_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start,
    bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pih)
{
        struct pxapcic_socket *so = pch;
        int error;
        bus_addr_t pa;

        memset(pih, 0, sizeof(*pih));
        pih->iot = so->sc->sc_iot;
        pih->addr = start;
        pih->size = size;

        pa = pih->addr;
        pa += PXA2X0_PCMCIA_SLOT0;
        pa += PXA2X0_SOCKET_OFFSET * so->socket;

#if 0
        printf("pxapcic_io_alloc: %x %x\n", (unsigned int)pa,
                 (unsigned int)size);
#endif
        /* XXX Are we ignoring alignment constraints? */
        error = bus_space_map(so->sc->sc_iot, pa, size, 0, &pih->ioh);

        return (error);
}

void
pxapcic_io_free(pcmcia_chipset_handle_t pch, struct pcmcia_io_handle *pih)
{
        struct pxapcic_socket *so = pch;

        bus_space_unmap(so->sc->sc_iot, pih->ioh, pih->size);
}

int
pxapcic_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset,
    bus_size_t size, struct pcmcia_io_handle *pih, int *windowp)
{
        return (0);
}

void pxapcic_io_unmap(pcmcia_chipset_handle_t pch, int window)
{
}

void *
pxapcic_intr_establish(pcmcia_chipset_handle_t pch,
    struct pcmcia_function *pf, int ipl, int (*fct)(void *), void *arg,
    char *name)
{
        struct pxapcic_socket *so = pch;
        /* XXX need to check if something should be done here */

	return (pxa2x0_gpio_intr_establish(so->irqpin, IST_EDGE_FALLING,
	    ipl, fct, arg, name));
}

void
pxapcic_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih)
{
	pxa2x0_gpio_intr_disestablish(ih);
}

const char *
pxapcic_intr_string(pcmcia_chipset_handle_t pch, void *ih)
{
	return (pxa2x0_gpio_intr_string(ih));
}

void
pxapcic_socket_enable(pcmcia_chipset_handle_t pch)
{
	struct pxapcic_socket *so = pch;
	int i;

	/* Power down the card and socket before setting the voltage. */
	so->pcictag->write(so, PXAPCIC_CARD_POWER, PXAPCIC_POWER_OFF);
	so->pcictag->set_power(so, PXAPCIC_POWER_OFF);

	/*
	 * Wait 300ms until power fails (Tpf).  Then, wait 100ms since
	 * we are changing Vcc (Toff).
	 */
	delay((300 + 100) * 1000);

	/* Power up the socket and card at appropriate voltage. */
	if (so->power_capability & PXAPCIC_POWER_5V) {
		so->pcictag->set_power(so, PXAPCIC_POWER_5V);
		so->pcictag->write(so, PXAPCIC_CARD_POWER,
		    PXAPCIC_POWER_5V);
	} else {
		so->pcictag->set_power(so, PXAPCIC_POWER_3V);
		so->pcictag->write(so, PXAPCIC_CARD_POWER,
		    PXAPCIC_POWER_3V);
	}

	/*
	 * Wait 100ms until power raise (Tpr) and 20ms to become
	 * stable (Tsu(Vcc)).
	 *
	 * Some machines require some more time to be settled
	 * (another 200ms is added here).
	 */
	delay((100 + 20 + 200) * 1000);

	/* Hold RESET at least 10us. */
	so->pcictag->write(so, PXAPCIC_CARD_RESET, 1);
	delay(10);
	/* XXX wrong, but lets TE-CF100 cards work for some reason. */
	delay(3000);
	so->pcictag->write(so, PXAPCIC_CARD_RESET, 0);

	/* Wait 20ms as per PC Card standard (r2.01) section 4.3.6. */
	delay(20000);

	/* Wait for the card to become ready. */
	for (i = 0; i < 10000; i++) {
		if (so->pcictag->read(so, PXAPCIC_CARD_READY))
			break;
		delay(500);
#ifdef PCICDEBUG
		if ((i>5000) && (i%100 == 99))
			printf(".");
#endif
	}
}

void
pxapcic_socket_disable(pcmcia_chipset_handle_t pch)
{
	struct pxapcic_socket *so = pch;

#ifdef PCICDEBUG
	printf("pxapcic_socket_disable: socket %d\n", so->socket);
#endif

	/* Power down the card and socket. */
	so->pcictag->write(so, PXAPCIC_CARD_POWER, PXAPCIC_POWER_OFF);
	so->pcictag->set_power(so, PXAPCIC_POWER_OFF);
}

/*
 * Attachment and initialization
 */

int
pxapcic_print(void *aux, const char *name)
{
	return (UNCONF);
}

int
pxapcic_submatch(struct device *parent, void *match, void *aux)
{
	struct cfdata *cf = match;

	return ((*cf->cf_attach->ca_match)(parent, cf, aux));
}

void
pxapcic_attach(struct pxapcic_softc *sc,
    void (*socket_setup_hook)(struct pxapcic_socket *))
{
	struct pcmciabus_attach_args paa;
	struct pxapcic_socket *so;
	int i;

	printf(": %d slot%s\n", sc->sc_nslots, sc->sc_nslots==1 ? "" : "s");

	if (bus_space_map(sc->sc_iot, PXA2X0_MEMCTL_BASE, PXA2X0_MEMCTL_SIZE,
	    0, &sc->sc_memctl_ioh)) {
		printf("%s: failed to map MEMCTL\n", sc->sc_dev.dv_xname);
		return;
	}

	/* Clear CIT (card present) and set NOS correctly. */
	bus_space_write_4(sc->sc_iot, sc->sc_memctl_ioh, MEMCTL_MECR,
	    sc->sc_nslots == 2 ? MECR_NOS : 0);

	/* zaurus: configure slot 1 first to make internal drive be wd0. */
	for (i = sc->sc_nslots-1; i >= 0; i--) {
		so = &sc->sc_socket[i];
		so->sc = sc;
		so->socket = i;
		so->flags = 0;

		socket_setup_hook(so);

		paa.paa_busname = "pcmcia";
		paa.pct = (pcmcia_chipset_tag_t)&pxapcic_pcmcia_functions;
		paa.pch = (pcmcia_chipset_handle_t)so;
		paa.iobase = 0;
		paa.iosize = 0x4000000;

		so->pcmcia = config_found_sm(&sc->sc_dev, &paa,
		    pxapcic_print, pxapcic_submatch);

		pxa2x0_gpio_set_function(sc->sc_irqpin[i], GPIO_IN);
		pxa2x0_gpio_set_function(sc->sc_irqcfpin[i], GPIO_IN);

		/* Card slot interrupt */
		so->irq = pxa2x0_gpio_intr_establish(sc->sc_irqcfpin[i],
		    IST_EDGE_BOTH, IPL_BIO /* XXX */, pxapcic_intr, so,
		    sc->sc_dev.dv_xname);

		/* GPIO pin for interrupt */
		so->irqpin = sc->sc_irqpin[i];

#ifdef DO_CONFIG_PENDING
		config_pending_incr();
#endif
		kthread_create_deferred(pxapcic_create_event_thread, so);
	}
}

/*
 * Card slot interrupt handling
 */

int
pxapcic_intr(void *arg)
{
        struct pxapcic_socket *so = arg;

	so->pcictag->clear_intr(so);
        wakeup(so);
        return (1);
}

/*
 * Event management
 */

void
pxapcic_create_event_thread(void *arg)
{
	struct pxapcic_socket *sock = arg;
	struct pxapcic_softc *sc = sock->sc;
	char name[MAXCOMLEN+1];
	u_int cs;

	/* If there's a card there, attach it. */
	cs = sock->pcictag->read(sock, PXAPCIC_CARD_STATUS);
	if (cs == PXAPCIC_CARD_VALID)
		pxapcic_attach_card(sock);

	snprintf(name, sizeof name, "%s-%d", sc->sc_dev.dv_xname, sock->socket);
	if (kthread_create(pxapcic_event_thread, sock, &sock->event_thread,
	     name))
		printf("%s: unable to create event thread for %s\n",
		     sc->sc_dev.dv_xname, sock->socket ? "1" : "0");
#ifdef DO_CONFIG_PENDING
	config_pending_decr();
#endif
}

void
pxapcic_event_thread(void *arg)
{
	struct pxapcic_socket *sock = arg;
	u_int cs;
	int present;

	while (sock->sc->sc_shutdown == 0) {

		(void) tsleep(sock, PWAIT, "pxapcicev", 0);

		/* sleep .25s to avoid chattering interrupts */
		(void) tsleep((caddr_t)sock, PWAIT,
		    "pxapcicss", hz/4);

		cs = sock->pcictag->read(sock, PXAPCIC_CARD_STATUS);

		present = sock->flags & PXAPCIC_FLAG_CARDP;

		if ((cs == PXAPCIC_CARD_VALID) == (present == 1))
			continue; /* state unchanged */

		/* XXX Do both? */
		pxapcic_event_process(sock);
	}

	sock->event_thread = NULL;

	/* In case parent is waiting for us to exit. */
	wakeup(sock->sc);

	kthread_exit(0);
}

void
pxapcic_event_process(struct pxapcic_socket *sock)
{
	u_int cs;

	cs = sock->pcictag->read(sock, PXAPCIC_CARD_STATUS);

	if (cs == PXAPCIC_CARD_VALID) {
		if (!(sock->flags & PXAPCIC_FLAG_CARDP))
			pxapcic_attach_card(sock);
	} else {
		if ((sock->flags & PXAPCIC_FLAG_CARDP))
			pxapcic_detach_card(sock, DETACH_FORCE);
	}
}

void
pxapcic_attach_card(struct pxapcic_socket *h)
{
	struct pxapcic_softc *sc = h->sc;
	u_int32_t rv;

	if (h->flags & PXAPCIC_FLAG_CARDP)
		panic("pcic_attach_card: already attached");
	h->flags |= PXAPCIC_FLAG_CARDP;

	/* Set CIT if any card is present. */
	rv = bus_space_read_4(sc->sc_iot, sc->sc_memctl_ioh, MEMCTL_MECR);
	bus_space_write_4(sc->sc_iot, sc->sc_memctl_ioh, MEMCTL_MECR,
	    rv | MECR_CIT);

	/* call the MI attach function */
	pcmcia_card_attach(h->pcmcia);
}

void
pxapcic_detach_card(struct pxapcic_socket *h, int flags)
{
	struct pxapcic_softc *sc = h->sc;
	u_int32_t rv;
	int i;

	if (h->flags & PXAPCIC_FLAG_CARDP) {
		h->flags &= ~PXAPCIC_FLAG_CARDP;

		/* call the MI detach function */
		pcmcia_card_detach(h->pcmcia, flags);
	}

	/* Clear CIT if no other card is present. */
	for (i = 0; i < sc->sc_nslots; i++)
		if (sc->sc_socket[i].flags & PXAPCIC_FLAG_CARDP)
			return;
	rv = bus_space_read_4(sc->sc_iot, sc->sc_memctl_ioh, MEMCTL_MECR);
	bus_space_write_4(sc->sc_iot, sc->sc_memctl_ioh, MEMCTL_MECR,
	    rv & ~MECR_CIT);
}


code:
/*	$OpenBSD: pxa2x0_space.c,v 1.5 2014/11/16 12:30:56 deraadt Exp $ */
/*	$NetBSD: pxa2x0_space.c,v 1.5 2004/06/07 19:45:22 nathanw Exp $ */

/*
 * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
 * All rights reserved.
 *
 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *	This product includes software developed for the NetBSD Project by
 *	Wasabi Systems, Inc.
 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
 *    or promote products derived from this software without specific prior
 *    written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */
/*
 * Copyright (c) 1997 Mark Brinicombe.
 * Copyright (c) 1997 Causality Limited.
 * All rights reserved.
 *
 * This code is derived from software contributed to The NetBSD Foundation
 * by Ichiro FUKUHARA.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *	This product includes software developed by Mark Brinicombe.
 * 4. The name of the company nor the name of the author may be used to
 *    endorse or promote products derived from this software without specific
 *    prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */

/*
 * bus_space functions for Intel PXA2[51]0 application processor.
 * Derived from i80321_space.c.
 */

#include <sys/param.h>
#include <sys/systm.h>

#include <uvm/uvm_extern.h>

#include <machine/bus.h>

/* Prototypes for all the bus_space structure functions */
bs_protos(pxa2x0);
bs_protos(generic);
bs_protos(generic_armv4);
bs_protos(bs_notimpl);

struct bus_space pxa2x0_bs_tag = {
	/* cookie */
	(void *) 0,

	/* mapping/unmapping */
	pxa2x0_bs_map,
	pxa2x0_bs_unmap,
	pxa2x0_bs_subregion,

	/* allocation/deallocation */
	pxa2x0_bs_alloc,	/* not implemented */
	pxa2x0_bs_free,		/* not implemented */

	/* get kernel virtual address */
	pxa2x0_bs_vaddr,

	/* mmap */
	bs_notimpl_bs_mmap,

	/* barrier */
	pxa2x0_bs_barrier,

	/* read (single) */
	generic_bs_r_1,
	generic_armv4_bs_r_2,
	generic_bs_r_4,
	bs_notimpl_bs_r_8,

	/* read multiple */
	generic_bs_rm_1,
	generic_armv4_bs_rm_2,
	generic_bs_rm_4,
	bs_notimpl_bs_rm_8,

	/* read region */
	generic_bs_rr_1,
	generic_armv4_bs_rr_2,
	generic_bs_rr_4,
	bs_notimpl_bs_rr_8,

	/* write (single) */
	generic_bs_w_1,
	generic_armv4_bs_w_2,
	generic_bs_w_4,
	bs_notimpl_bs_w_8,

	/* write multiple */
	generic_bs_wm_1,
	generic_armv4_bs_wm_2,
	generic_bs_wm_4,
	bs_notimpl_bs_wm_8,

	/* write region */
	generic_bs_wr_1,
	generic_armv4_bs_wr_2,
	generic_bs_wr_4,
	bs_notimpl_bs_wr_8,

	/* set multiple */
	bs_notimpl_bs_sm_1,
	bs_notimpl_bs_sm_2,
	bs_notimpl_bs_sm_4,
	bs_notimpl_bs_sm_8,

	/* set region */
	generic_bs_sr_1,
	generic_armv4_bs_sr_2,
	bs_notimpl_bs_sr_4,
	bs_notimpl_bs_sr_8,

	/* copy */
	bs_notimpl_bs_c_1,
	generic_armv4_bs_c_2,
	bs_notimpl_bs_c_4,
	bs_notimpl_bs_c_8,
};

int
pxa2x0_bs_map(void *t, bus_addr_t bpa, bus_size_t size,
	      int flag, bus_space_handle_t *bshp)
{
	u_long startpa, endpa, pa;
	vaddr_t va;
	pt_entry_t *pte;

	if ((u_long)bpa > (u_long)KERNEL_BASE) {
		/* Some IO registers (ex. UART ports for console)
		   are mapped to fixed address by board specific
		   routine. */
		*bshp = bpa;
		return(0);
	}

	startpa = trunc_page(bpa);
	endpa = round_page(bpa + size);

	/* XXX use extent manager to check duplicate mapping */

	va = uvm_km_valloc(kernel_map, endpa - startpa);
	if (! va)
		return(ENOMEM);

	*bshp = (bus_space_handle_t)(va + (bpa - startpa));

	for (pa = startpa; pa < endpa; pa += PAGE_SIZE, va += PAGE_SIZE) {
		pmap_kenter_pa(va, pa, PROT_READ | PROT_WRITE);
		if ((flag & BUS_SPACE_MAP_CACHEABLE) == 0) {
			pte = vtopte(va);
			*pte &= ~L2_S_CACHE_MASK;
			PTE_SYNC(pte);
			/* XXX: pmap_kenter_pa() also does PTE_SYNC(). a bit of
			 *      waste.
			 */
		}
	}
	pmap_update(pmap_kernel());

	return(0);
}

void
pxa2x0_bs_unmap(void *t, bus_space_handle_t bsh, bus_size_t size)
{

	if (bsh > (u_long)KERNEL_BASE)
		return;

	uvm_km_free(kernel_map, bsh, size);
}

int
pxa2x0_bs_subregion(void *t, bus_space_handle_t bsh, bus_size_t offset,
    bus_size_t size, bus_space_handle_t *nbshp)
{

	*nbshp = bsh + offset;
	return (0);
}

void
pxa2x0_bs_barrier(void *t, bus_space_handle_t bsh, bus_size_t offset,
    bus_size_t len, int flags)
{

	/* Nothing to do. */
}

void *
pxa2x0_bs_vaddr(void *t, bus_space_handle_t bsh)
{

	return ((void *)bsh);
}

int
pxa2x0_bs_alloc(void *t, bus_addr_t rstart, bus_addr_t rend,
    bus_size_t size, bus_size_t alignment, bus_size_t boundary, int flags,
    bus_addr_t *bpap, bus_space_handle_t *bshp)
{

	panic("pxa2x0_io_bs_alloc(): not implemented");
}

void
pxa2x0_bs_free(void *t, bus_space_handle_t bsh, bus_size_t size)
{

	panic("pxa2x0_io_bs_free(): not implemented");
}


code:
/*	$OpenBSD: pxa2x0reg.h,v 1.31 2009/09/09 12:14:39 marex Exp $ */
/* $NetBSD: pxa2x0reg.h,v 1.4 2003/06/11 20:43:01 scw Exp $ */

/*
 * Copyright (c) 2002  Genetec Corporation.  All rights reserved.
 * Written by Hiroyuki Bessho for Genetec Corporation.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *	This product includes software developed for the NetBSD Project by
 *	Genetec Corporation.
 * 4. The name of Genetec Corporation may not be used to endorse or
 *    promote products derived from this software without specific prior
 *    written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL GENETEC CORPORATION
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

/*
 * Intel PXA2[15]0 processor is XScale based integrated CPU
 *
 * Reference:
 *  Intel(r) PXA250 and PXA210 Application Processors
 *   Developer's Manual
 *  (278522-001.pdf)
 *
 *  Intel PXA 27x Processor Family Developers Manual (280000-002)
 */
#ifndef _ARM_XSCALE_PXA2X0REG_H_
#define _ARM_XSCALE_PXA2X0REG_H_

/* Borrow some register definitions from sa11x0 */
#include <arm/sa11x0/sa11x0_reg.h>

#ifndef _LOCORE
#include <sys/types.h>		/* for uint32_t */
#endif

/*
 * Chip select domains
 */
#define PXA2X0_CS0_START 0x00000000
#define PXA2X0_CS1_START 0x04000000
#define PXA2X0_CS2_START 0x08000000
#define PXA2X0_CS3_START 0x0c000000
#define PXA2X0_CS4_START 0x10000000
#define PXA2X0_CS5_START 0x14000000

#define PXA2X0_PCMCIA_SLOT0  0x20000000
#define PXA2X0_PCMCIA_SLOT1  0x30000000

#define PXA2X0_PERIPH_START 0x40000000
/* #define PXA2X0_MEMCTL_START 0x48000000 */
#define PXA2X0_PERIPH_END   0x480fffff

#define PXA2X0_SDRAM0_START 0xa0000000
#define PXA2X0_SDRAM1_START 0xa4000000
#define PXA2X0_SDRAM2_START 0xa8000000
#define PXA2X0_SDRAM3_START 0xac000000
#define	PXA2X0_SDRAM_BANKS      4
#define	PXA2X0_SDRAM_BANK_SIZE  0x04000000

/*
 * Physical address of integrated peripherals
 */

#define PXA2X0_DMAC_BASE	0x40000000
#define PXA2X0_DMAC_SIZE	0x300
#define PXA27X_DMAC_SIZE	0x0400
#define PXA2X0_FFUART_BASE	0x40100000 /* Full Function UART */
#define PXA2X0_BTUART_BASE	0x40200000 /* Bluetooth UART */
#define PXA2X0_I2C_BASE		0x40300000 /* I2C Bus Interface Unit */
#define PXA2X0_I2C_SIZE		0x16a4
#define PXA2X0_I2S_BASE		0x40400000 /* Inter-IC Sound Controller */
#define PXA2X0_I2S_SIZE		0x0084
#define PXA2X0_AC97_BASE	0x40500000 /* AC '97 Controller */
#define PXA2X0_AC97_SIZE	0x0600
#define PXA2X0_USBDC_BASE 	0x40600000 /* USB Client Controller */
#define PXA2X0_USBDC_SIZE 	0x0460
#define PXA2X0_STUART_BASE	0x40700000 /* Standard UART */
#define PXA2X0_ICP_BASE 	0x40800000
#define PXA2X0_RTC_BASE 	0x40900000
#define PXA2X0_RTC_SIZE 	0x10
#define PXA2X0_OST_BASE 	0x40a00000 /* OS Timer */
#define PXA2X0_OST_SIZE		0x24
#define PXA2X0_PWM0_BASE	0x40b00000
#define PXA2X0_PWM1_BASE	0x40c00000
#define PXA2X0_INTCTL_BASE	0x40d00000 /* Interrupt controller */
#define	PXA2X0_INTCTL_SIZE	0x20
#define PXA2X0_GPIO_BASE	0x40e00000
#define PXA2X0_GPIO_SIZE  	0x70
#define PXA2X0_POWMAN_BASE  	0x40f00000 /* Power management */
#define PXA2X0_POWMAN_SIZE	0x1a4	   /* incl. PI2C unit */
#define PXA2X0_SSP_BASE		0x41000000 /* SSP serial port */
#define PXA2X0_SSP1_BASE	0x41700000 /* PXA270 */
#define PXA2X0_SSP2_BASE	0x41900000 /* PXA270 */
#define PXA2X0_SSP_SIZE		0x40
#define PXA2X0_MMC_BASE 	0x41100000 /* MultiMediaCard/SD/SDIO */
#define PXA2X0_MMC_SIZE		0x50
#define PXA2X0_CLKMAN_BASE  	0x41300000 /* Clock Manager */
#define PXA2X0_CLKMAN_SIZE	12
#define PXA2X0_LCDC_BASE	0x44000000 /* LCD Controller */
#define PXA2X0_LCDC_SIZE	0x220
#define PXA2X0_MEMCTL_BASE	0x48000000 /* Memory Controller */
#define PXA2X0_MEMCTL_SIZE	0x84
#define PXA2X0_USBHC_BASE	0x4c000000 /* USB Host Controller */
#define PXA2X0_USBHC_SIZE	0x70
#define PXA2X0_KPC_BASE		0x41500000 /* Keypad Controller */
#define PXA2X0_KPC_SIZE		0x50

/* width of interrupt controller */
#define ICU_LEN			32	/* but some are not used */
#define ICU_INT_HWMASK		0xffffff0f
#define PXA2X0_IRQ_MIN		1

/*
 * [0..1,15..16] are used as soft intrs by SI_TO_IRQBIT,
 * and [4..6] are not likely to be used by us.
 */
#define PXA2X0_INT_USBH2	2	/* USB host (all other events) */
#define PXA2X0_INT_USBH1	3	/* USB host (OHCI) */
#define PXA2X0_INT_KPC		4
#define PXA2X0_INT_OST		7	/* OS timers */
#define PXA2X0_INT_GPIO0	8
#define PXA2X0_INT_GPIO1	9
#define PXA2X0_INT_GPION	10	/* IRQ from GPIO[2..80] */
#define PXA2X0_INT_USB  	11
#define PXA2X0_INT_PMU  	12
#define PXA2X0_INT_I2S  	13
#define PXA2X0_INT_AC97  	14
#define PXA2X0_INT_LCD  	17
#define PXA2X0_INT_I2C  	18
#define PXA2X0_INT_ICP  	19
#define PXA2X0_INT_STUART  	20
#define PXA2X0_INT_BTUART  	21
#define PXA2X0_INT_FFUART  	22
#define PXA2X0_INT_MMC  	23
#define PXA2X0_INT_SSP  	24
#define PXA2X0_INT_DMA  	25
#define PXA2X0_INT_OST0  	26
#define PXA2X0_INT_OST1  	27
#define PXA2X0_INT_OST2  	28
#define PXA2X0_INT_OST3  	29
#define PXA2X0_INT_RTCHZ  	30
#define PXA2X0_INT_ALARM  	31	/* RTC Alarm interrupt */

/* Interrupt Controller similar to SA11x0's, but not exactly the same. */
#define INTCTL_ICIP	0x00
#define INTCTL_ICMR	0x04
#define INTCTL_ICLR	0x08
#define INTCTL_ICFP	0x0c
#define INTCTL_ICPR	0x10
#define INTCTL_ICCR	0x14
#define  ICCR_DIM	(1<<0)

/* DMAC */
#define DMAC_N_CHANNELS 		16
#define DMAC_N_CHANNELS_PXA27X		32
#define DMAC_N_PRIORITIES		3
#define DMAC_N_PRIORITIES_PXA27X	4

#define DMAC_DCSR(n)	((n)*4)
#define  DCSR_BUSERRINTR    (1<<0)	/* bus error interrupt */
#define  DCSR_STARTINR      (1<<1)	/* start interrupt */
#define  DCSR_ENDINTR       (1<<2)	/* end interrupt */
#define  DCSR_STOPSTATE     (1<<3)	/* channel is not running */
#define  DCSR_REQPEND       (1<<8)	/* request pending */
#define  DCSR_STOPIRQEN     (1<<29)     /* stop interrupt enable */
#define  DCSR_NODESCFETCH   (1<<30)	/* no-descriptor fetch mode */
#define  DCSR_RUN  	    (1<<31)
#define DMAC_DINT 	0x00f0		/* DMA interrupt */
#define  DMAC_DINT_MASK	0xffffu
#define DMAC_DRCMR(n)	(0x100+(n)*4)	/* Channel map register */
#define  DRCMR_CHLNUM	0x0f		/* channel number */
#define  DRCMR_MAPVLD	(1<<7)		/* map valid */
#define DMAC_DDADR(n)	(0x0200+(n)*16)
#define  DDADR_STOP	(1<<0)
#define DMAC_DSADR(n)	(0x0204+(n)*16)
#define DMAC_DTADR(n)	(0x0208+(n)*16)
#define DMAC_DCMD(n)	(0x020c+(n)*16)
#define  DCMD_LENGTH_MASK	0x1fff
#define  DCMD_WIDTH_SHIFT  14
#define  DCMD_WIDTH_0	(0<<DCMD_WIDTH_SHIFT)	/* for mem-to-mem transfer*/
#define  DCMD_WIDTH_1	(1<<DCMD_WIDTH_SHIFT)
#define  DCMD_WIDTH_2	(2<<DCMD_WIDTH_SHIFT)
#define  DCMD_WIDTH_4	(3<<DCMD_WIDTH_SHIFT)
#define  DCMD_SIZE_SHIFT  16
#define  DCMD_SIZE_8	(1<<DCMD_SIZE_SHIFT)
#define  DCMD_SIZE_16	(2<<DCMD_SIZE_SHIFT)
#define  DCMD_SIZE_32	(3<<DCMD_SIZE_SHIFT)
#define  DCMD_LITTLE_ENDIAN	(0<<18)
#define	 DCMD_ENDIRQEN	  (1<<21)
#define  DCMD_STARTIRQEN  (1<<22)
#define  DCMD_FLOWTRG     (1<<28)	/* flow control by target */
#define  DCMD_FLOWSRC     (1<<29)	/* flow control by source */
#define  DCMD_INCTRGADDR  (1<<30)	/* increment target address */
#define  DCMD_INCSRCADDR  (1<<31)	/* increment source address */

#ifndef __ASSEMBLER__
/* DMA descriptor */
struct pxa2x0_dma_desc {
	volatile uint32_t	dd_ddadr;
#define	DMAC_DESC_LAST	0x1
	volatile uint32_t	dd_dsadr;
	volatile uint32_t	dd_dtadr;
	volatile uint32_t	dd_dcmd;		/* command and length */
};
#endif

/* UART */
#define PXA2X0_COM_FREQ   14745600L

/* I2C */
#define I2C_IBMR	0x1680		/* Bus monitor register */
#define I2C_IDBR	0x1688		/* Data buffer */
#define I2C_ICR  	0x1690		/* Control register */
#define  ICR_START	(1<<0)
#define  ICR_STOP	(1<<1)
#define  ICR_ACKNAK	(1<<2)
#define  ICR_TB  	(1<<3)
#define  ICR_MA  	(1<<4)
#define  ICR_SCLE	(1<<5)		/* PXA270? */
#define  ICR_IUE	(1<<6)		/* PXA270? */
#define  ICR_UR		(1<<14)		/* PXA270? */
#define  ICR_FM		(1<<15)		/* PXA270? */
#define I2C_ISR  	0x1698		/* Status register */
#define  ISR_ACKNAK	(1<<1)
#define  ISR_ITE	(1<<6)
#define  ISR_IRF	(1<<7)
#define I2C_ISAR	0x16a0		/* Slave address */

/* Power Manager */
#define POWMAN_PMCR	0x00
#define POWMAN_PSSR	0x04	/* Sleep Status register */
#define  PSSR_SSS	 (1<<0)		/* Software Sleep Status */
#define  PSSR_BFS	 (1<<1)		/* Battery Fault Status */
#define  PSSR_VFS	 (1<<2)		/* VCC Fault Status */
#define  PSSR_STS	 (1<<3)		/* Standby Mode Status */
#define  PSSR_PH	 (1<<4)		/* Peripheral Control Hold */
#define  PSSR_RDH	 (1<<5)		/* Read Disable Hold */
#define  PSSR_OTGPH	 (1<<6)		/* OTG Peripheral Control Hold */
#define POWMAN_PSPR	0x08
#define POWMAN_PWER	0x0c
#define POWMAN_PRER	0x10
#define POWMAN_PFER	0x14
#define POWMAN_PEDR	0x18
#define POWMAN_PCFR	0x1c	/* General Configuration register */
#define  PCFR_OPDE	 (1<<0)
#define  PCFR_GPR_EN	 (1<<4)		/* PXA270 */
#define  PCFR_PI2C_EN	 (1<<6)		/* PXA270 */
#define  PCFR_GP_ROD	 (1<<8)		/* PXA270 */
#define  PCFR_FVC	 (1<<10)	/* PXA270 */
#define POWMAN_PGSR0	0x20	/* GPIO Sleep State register */
#define POWMAN_PGSR1	0x24
#define POWMAN_PGSR2	0x28
#define POWMAN_PGSR3	0x2c		/* PXA270 */
#define POWMAN_RCSR	0x30	/* Reset Controller Status register */
#define  RCSR_HWR	 (1<<0)
#define  RCSR_WDR	 (1<<1)
#define  RCSR_SMR	 (1<<2)
#define  RCSR_GPR	 (1<<3)
#define POWMAN_PSLR	0x34		/* PXA270 */
#define POWMAN_PKWR	0x50		/* PXA270 */
#define POWMAN_PKSR	0x54		/* PXA270 */

/* Power Manager I2C unit */
#define POWMAN_PIDBR	0x188
#define POWMAN_PICR	0x190
#define  PICR_START	ICR_START
#define  PICR_STOP	ICR_STOP
#define  PICR_ACKNAK	ICR_ACKNAK
#define  PICR_TB	ICR_TB
#define  PICR_SCLE	(1<<5)		/* PXA270? */
#define  PICR_IUE	(1<<6)		/* PXA270? */
#define  PICR_UR	(1<<14)		/* PXA270? */
#define POWMAN_PISR	0x198
#define  PISR_ACKNAK	(1<<1)
#define  PISR_ITE	(1<<6)
#define  PISR_IRF	(1<<7)
#define POWMAN_PISAR	0x1a0

/* Clock Manager */
#define CLKMAN_CCCR	0x00	/* Core Clock Configuration */
#define  CCCR_CPDIS	 (1<<31)	/* PXA270 */
#define  CCCR_A		 (1<<25)	/* PXA270 */
#define  CCCR_TURBO_X1	 (2<<7)
#define  CCCR_TURBO_X15	 (3<<7)	/* x 1.5 */
#define  CCCR_TURBO_X2	 (4<<7)
#define  CCCR_TURBO_X25	 (5<<7)	/* x 2.5 */
#define  CCCR_TURBO_X3	 (6<<7)	/* x 3.0 */
/* PXA255 */
#define  CCCR_RUN_X1	 (1<<5)
#define  CCCR_RUN_X2	 (2<<5)
#define  CCCR_RUN_X4	 (3<<5)
#define  CCCR_MEM_X27	 (1<<0)	/* x27, 99.53MHz */
#define  CCCR_MEM_X32	 (2<<0)	/* x32, 117,96MHz */
#define  CCCR_MEM_X36	 (3<<0)	/* x26, 132.71MHz */
#define  CCCR_MEM_X40	 (4<<0)	/* x27, 99.53MHz */
#define  CCCR_MEM_X45	 (5<<0)	/* x27, 99.53MHz */
#define  CCCR_MEM_X9	 (0x1f<<0)	/* x9, 33.2MHz */
/* PXA27x: L is the core run frequency to 13MHz oscillator ratio. */
#define  CCCR_RUN_X7	 (7<<0)	 /* 91MHz, 91MHz mem, 91MHz LCD */
#define  CCCR_RUN_X8	 (8<<0)	 /* 104MHz, 104MHz mem, 52MHz LCD */
#define  CCCR_RUN_X16	 (16<<0) /* 208MHz, 104/208MHz mem, 104MHz LCD */

#define CLKMAN_CKEN	0x04	/* Clock Enable Register */
#define CLKMAN_OSCC	0x08	/* Oscillator Configuration Register */

#define CCCR_N_SHIFT	7
#define CCCR_N_MASK	(0x07<<CCCR_N_SHIFT)
#define CCCR_M_SHIFT	5
#define CCCR_M_MASK	(0x03<<CCCR_M_SHIFT)
#define CCCR_L_MASK	0x1f

#define CKEN_PWM0	(1<<0)
#define CKEN_PWM1	(1<<1)
#define CKEN_AC97	(1<<2)
#define CKEN_SSP	(1<<3)
#define CKEN_STUART	(1<<5)
#define CKEN_FFUART	(1<<6)
#define CKEN_BTUART	(1<<7)
#define CKEN_I2S	(1<<8)
#define CKEN_USBHC	(1<<10)
#define CKEN_USBDC	(1<<11)
#define CKEN_MMC	(1<<12)
#define CKEN_FICP	(1<<13)
#define CKEN_I2C	(1<<14)
#define CKEN_PI2C	(1<<15)	/* PXA270? */
#define CKEN_LCD	(1<<16)
#define CKEN_KEY	(1<<19)	/* PXA270? */
#define CKEN_MEM	(1<<22)	/* PXA270? */
#define CKEN_AC97CC	(1<<31) /* PXA27x */

#define OSCC_OOK	(1<<0)	/* 32.768KHz oscillator status */
#define OSCC_OON	(1<<1)	/* 32.768KHz oscillator */

/*
 * RTC
 */
#define RTC_RCNR	0x0000	/* count register */
#define RTC_RTAR	0x0004	/* alarm register */
#define RTC_RTSR	0x0008	/* status register */
#define  RTSR_AL	(1<<0)
#define  RTSR_HZ	(1<<1)
#define  RTSR_ALE	(1<<2)
#define RTC_RTTR	0x000c	/* trim register */
/*
 * GPIO
 */
#define GPIO_GPLR0  0x00	/* Level reg [31:0] */
#define GPIO_GPLR1  0x04	/* Level reg [63:32] */
#define GPIO_GPLR2  0x08	/* Level reg [80:64] PXA 270 [95:64] */

#define GPIO_GPDR0  0x0c	/* dir reg [31:0] */
#define GPIO_GPDR1  0x10	/* dir reg [63:32] */
#define GPIO_GPDR2  0x14	/* dir reg [80:64] PXA 270 [95:64] */

#define GPIO_GPSR0  0x18	/* set reg [31:0] */
#define GPIO_GPSR1  0x1c	/* set reg [63:32] */
#define GPIO_GPSR2  0x20	/* set reg [80:64] PXA 270 [95:64] */

#define GPIO_GPCR0  0x24	/* clear reg [31:0] */
#define GPIO_GPCR1  0x28	/* clear reg [63:32] */
#define GPIO_GPCR2  0x2c	/* clear reg [80:64] PXA 270 [95:64] */

#define GPIO_GPER0  0x30	/* rising edge [31:0] */
#define GPIO_GPER1  0x34	/* rising edge [63:32] */
#define GPIO_GPER2  0x38	/* rising edge [80:64] PXA 270 [95:64] */

#define GPIO_GRER0  0x30	/* rising edge [31:0] */
#define GPIO_GRER1  0x34	/* rising edge [63:32] */
#define GPIO_GRER2  0x38	/* rising edge [80:64] PXA 270 [95:64] */

#define GPIO_GFER0  0x3c	/* falling edge [31:0] */
#define GPIO_GFER1  0x40	/* falling edge [63:32] */
#define GPIO_GFER2  0x44	/* falling edge [80:64] PXA 270 [95:64] */

#define GPIO_GEDR0  0x48	/* edge detect [31:0] */
#define GPIO_GEDR1  0x4c	/* edge detect [63:32] */
#define GPIO_GEDR2  0x50	/* edge detect [80:64] PXA 270 [95:64] */

#define GPIO_GAFR0_L  0x54	/* alternate function [15:0] */
#define GPIO_GAFR0_U  0x58	/* alternate function [31:16] */
#define GPIO_GAFR1_L  0x5c	/* alternate function [47:32] */
#define GPIO_GAFR1_U  0x60	/* alternate function [63:48] */
#define GPIO_GAFR2_L  0x64	/* alternate function [79:64] */
#define GPIO_GAFR2_U  0x68	/* alternate function [80] PXA 270 [95:80] */

#define GPIO_GAFR3_L  0x6C	/* alternate function PXA 270 [111:96] */
#define GPIO_GAFR3_U  0x70	/* alternate function PXA 270 [120:112] */

#define GPIO_GPLR3  0x100	/* Level PXA 270 [120:96] */
#define GPIO_GPDR3  0x10C	/* dir reg PXA 270 [120:96] */
#define GPIO_GPSR3  0x118	/* set reg PXA 270 [120:96] */
#define GPIO_GPCR3  0x124	/* clear reg PXA 270 [120:96] */
#define GPIO_GRER3  0x130	/* rising edge PXA 270 [120:96] */
#define GPIO_GFER3  0x13c	/* falling edge PXA 270 [120:96] */
#define GPIO_GEDR3  0x148	/* edge detect PXA270 [120:96] */

#define	GPIO_REG(r, pin)	((r) + \
    ((pin > 95) ? GPIO_GPLR3 : (((pin) / 32) * 4)))
#define	GPIO_BANK(pin)		((pin) / 32)
#define	GPIO_BIT(pin)		(1u << ((pin) & 0x1f))
#define	GPIO_FN_REG(pin)	(GPIO_GAFR0_L + (((pin) / 16) * 4))
#define	GPIO_FN_SHIFT(pin)	((pin & 0xf) * 2)

#define	GPIO_IN		  	0x00	/* Regular GPIO input pin */
#define	GPIO_OUT	  	0x10	/* Regular GPIO output pin */
#define	GPIO_ALT_FN_1_IN	0x01	/* Alternate function 1 input */
#define	GPIO_ALT_FN_1_OUT	0x11	/* Alternate function 1 output */
#define	GPIO_ALT_FN_2_IN	0x02	/* Alternate function 2 input */
#define	GPIO_ALT_FN_2_OUT	0x12	/* Alternate function 2 output */
#define	GPIO_ALT_FN_3_IN	0x03	/* Alternate function 3 input */
#define	GPIO_ALT_FN_3_OUT	0x13	/* Alternate function 3 output */
#define	GPIO_SET		0x20	/* Initial state is Set */
#define	GPIO_CLR		0x00	/* Initial state is Clear */

#define	GPIO_FN_MASK		0x03
#define	GPIO_FN_IS_OUT(n)	((n) & GPIO_OUT)
#define	GPIO_FN_IS_SET(n)	((n) & GPIO_SET)
#define	GPIO_FN(n)		((n) & GPIO_FN_MASK)
#define	GPIO_IS_GPIO(n)		(GPIO_FN(n) == 0)
#define	GPIO_IS_GPIO_IN(n)	(((n) & (GPIO_FN_MASK|GPIO_OUT)) == GPIO_IN)
#define	GPIO_IS_GPIO_OUT(n)	(((n) & (GPIO_FN_MASK|GPIO_OUT)) == GPIO_OUT)

#define	GPIO_NPINS_25x	85
#define	GPIO_NPINS	121

/*
 * memory controller
 */

#define MEMCTL_MDCNFG	0x0000
#define  MDCNFG_DE0		(1<<0)
#define  MDCNFG_DE1		(1<<1)
#define  MDCNFD_DWID01_SHIFT	2
#define  MDCNFD_DCAC01_SHIFT	3
#define  MDCNFD_DRAC01_SHIFT	5
#define  MDCNFD_DNB01_SHIFT	7
#define  MDCNFG_DE2		(1<<16)
#define  MDCNFG_DE3		(1<<17)
#define  MDCNFD_DWID23_SHIFT	18
#define  MDCNFD_DCAC23_SHIFT	19
#define  MDCNFD_DRAC23_SHIFT	21
#define  MDCNFD_DNB23_SHIFT	23

#define  MDCNFD_DWID_MASK	0x1
#define  MDCNFD_DCAC_MASK	0x3
#define  MDCNFD_DRAC_MASK	0x3
#define  MDCNFD_DNB_MASK	0x1

#define MEMCTL_MDREFR   0x04	/* refresh control register */
#define  MDREFR_DRI	0xfff
#define  MDREFR_E0PIN	(1<<12)
#define  MDREFR_K0RUN   (1<<13)	/* SDCLK0 enable */
#define  MDREFR_K0DB2   (1<<14)	/* SDCLK0 1/2 freq */
#define  MDREFR_E1PIN	(1<<15)
#define  MDREFR_K1RUN   (1<<16)	/* SDCLK1 enable */
#define  MDREFR_K1DB2   (1<<17)	/* SDCLK1 1/2 freq */
#define  MDREFR_K2RUN   (1<<18)	/* SDCLK2 enable */
#define  MDREFR_K2DB2	(1<<19)	/* SDCLK2 1/2 freq */
#define	 MDREFR_APD	(1<<20)	/* Auto Power Down */
#define  MDREFR_SLFRSH	(1<<22)	/* Self Refresh */
#define  MDREFR_K0FREE	(1<<23)	/* SDCLK0 free run */
#define  MDREFR_K1FREE	(1<<24)	/* SDCLK1 free run */
#define  MDREFR_K2FREE	(1<<25)	/* SDCLK2 free run */

#define MEMCTL_MSC0	0x08	/* Asynchronous Static memory Control CS[01] */
#define MEMCTL_MSC1	0x0c	/* Asynchronous Static memory Control CS[23] */
#define MEMCTL_MSC2	0x10	/* Asynchronous Static memory Control CS[45] */
#define  MSC_RBUFF_SHIFT 15	/* return data buffer */
#define  MSC_RBUFF	(1<<MSC_RBUFF_SHIFT)
#define  MSC_RRR_SHIFT   12  	/* recovery time */
#define	 MSC_RRR	(7<<MSC_RRR_SHIFT)
#define  MSC_RDN_SHIFT    8	/* ROM delay next access */
#define  MSC_RDN	(0x0f<<MSC_RDN_SHIFT)
#define  MSC_RDF_SHIFT    4	/*  ROM delay first access*/
#define  MSC_RDF  	(0x0f<<MSC_RDF_SHIFT)
#define  MSC_RBW_SHIFT    3	/* 32/16 bit bus */
#define  MSC_RBW 	(1<<MSC_RBW_SHIFT)
#define  MSC_RT_SHIFT	   0	/* type */
#define  MSC_RT 	(7<<MSC_RT_SHIFT)
#define  MSC_RT_NONBURST	0
#define  MSC_RT_SRAM    	1
#define  MSC_RT_BURST4  	2
#define  MSC_RT_BURST8  	3
#define  MSC_RT_VLIO   	 	4

/* expansion memory timing configuration */
#define MEMCTL_MCMEM(n)	(0x28+4*(n))
#define MEMCTL_MCATT(n)	(0x30+4*(n))
#define MEMCTL_MCIO(n)	(0x38+4*(n))

#define  MC_HOLD_SHIFT	14
#define  MC_ASST_SHIFT	7
#define  MC_SET_SHIFT	0
#define  MC_TIMING_VAL(hold,asst,set)	(((hold)<<MC_HOLD_SHIFT)| \
		((asst)<<MC_ASST_SHIFT)|((set)<<MC_SET_SHIFT))

#define MEMCTL_MECR	0x14	/* Expansion memory configuration */
#define MECR_NOS	(1<<0)	/* Number of sockets */
#define MECR_CIT	(1<<1)	/* Card-is-there */

#define MEMCTL_MDMRS	0x0040

#define MEMCTL_ARB_CNTRL 0x0048	/* System Bus Arbiter */

/*
 * LCD Controller
 */
#define LCDC_LCCR0	0x000	/* Controller Control Register 0 */
#define  LCCR0_ENB	(1U<<0)	/* LCD Controller Enable */
#define  LCCR0_CMS	(1U<<1)	/* Color/Mono select */
#define  LCCR0_SDS	(1U<<2)	/* Single/Dual -panel */
#define  LCCR0_LDM	(1U<<3)	/* LCD Disable Done Mask */
#define  LCCR0_SFM	(1U<<4)	/* Start of Frame Mask */
#define  LCCR0_IUM	(1U<<5)	/* Input FIFO Underrun Mask */
#define  LCCR0_EFM	(1U<<6)	/* End of Frame Mask */
#define  LCCR0_PAS	(1U<<7)	/* Passive/Active Display select */
#define  LCCR0_DPD	(1U<<9)	/* Double-Pixel Data pin mode */
#define  LCCR0_DIS	(1U<<10) /* LCD Disable */
#define  LCCR0_QDM	(1U<<11) /* LCD Quick Disable Mask */
#define  LCCR0_BM	(1U<<20) /* Branch Mask */
#define  LCCR0_OUM	(1U<<21) /* Output FIFO Underrun Mask */
/* PXA270 */
#define  LCCR0_LCDT	(1U<<22) /* LCD Panel Type */
#define  LCCR0_RDSTM	(1U<<23) /* Read Status Interrupt Mask */
#define  LCCR0_CMDIM	(1U<<24) /* Command Interrupt Mask */
#define  LCCR0_OUC	(1U<<25) /* Overlay Underlay Control */
#define  LCCR0_LDDALT	(1U<<26) /* LDD Alternate Mapping Control Bit */

#define  LCCR0_IMASK	(LCCR0_LDM|LCCR0_SFM|LCCR0_IUM|LCCR0_EFM|LCCR0_QDM|LCCR0_BM|LCCR0_OUM)

#define LCDC_LCCR1	0x004	/* Controller Control Register 1 */
#define LCDC_LCCR2	0x008	/* Controller Control Register 2 */
#define LCDC_LCCR3	0x00c	/* Controller Control Register 2 */
#define  LCCR3_BPP_SHIFT 24		/* Bits per pixel */
#define  LCCR3_BPP	(0x07<<LCCR3_BPP_SHIFT)
#define LCDC_FBR0	0x020	/* DMA ch0 frame branch register */
#define LCDC_FBR1	0x024	/* DMA ch1 frame branch register */
#define LCDC_LCSR	0x038	/* controller status register */
#define  LCSR_LDD	(1U<<0) /* LCD disable done */
#define  LCSR_SOF	(1U<<1) /* Start of frame */
#define LCDC_LIIDR	0x03c	/* controller interrupt ID Register */
#define LCDC_TRGBR	0x040	/* TMED RGB Speed Register */
#define LCDC_TCR	0x044	/* TMED Control Register */
#define LCDC_FDADR0	0x200	/* DMA ch0 frame descriptor address */
#define LCDC_FSADR0	0x204	/* DMA ch0 frame source address */
#define LCDC_FIDR0	0x208	/* DMA ch0 frame ID register */
#define LCDC_LDCMD0	0x20c	/* DMA ch0 command register */
#define LCDC_FDADR1	0x210	/* DMA ch1 frame descriptor address */
#define LCDC_FSADR1	0x214	/* DMA ch1 frame source address */
#define LCDC_FIDR1	0x218	/* DMA ch1 frame ID register */
#define LCDC_LDCMD1	0x21c	/* DMA ch1 command register */

/*
 * MMC/SD controller
 */
#define MMC_STRPCL	0x00	/* start/stop MMC clock */
#define  STRPCL_NOOP	0
#define  STRPCL_STOP	1	/* stop MMC clock */
#define  STRPCL_START	2	/* start MMC clock */
#define MMC_STAT	0x04	/* status register */
#define  STAT_READ_TIME_OUT   		(1<<0)
#define  STAT_TIMEOUT_RESPONSE		(1<<1)
#define  STAT_CRC_WRITE_ERROR		(1<<2)
#define  STAT_CRC_READ_ERROR		(1<<3)
#define  STAT_SPI_READ_ERROR_TOKEN	(1<<4)
#define  STAT_RES_CRC_ERR		(1<<5)
#define  STAT_XMIT_FIFO_EMPTY		(1<<6) /* (PXA27x: reserved) */
#define  STAT_RECV_FIFO_FULL		(1<<7) /* (PXA27x: reserved) */
#define  STAT_CLK_EN			(1<<8)
#define  STAT_DATA_TRAN_DONE		(1<<11)
#define  STAT_PRG_DONE			(1<<12)
#define  STAT_END_CMD_RES		(1<<13)
#define MMC_CLKRT	0x08	/* MMC clock rate */
#define  CLKRT_20M	0
#define  CLKRT_10M	1
#define  CLKRT_5M	2
#define  CLKRT_2_5M	3
#define  CLKRT_1_25M	4
#define  CLKRT_625K	5
#define  CLKRT_312K	6
#define MMC_SPI  	0x0c	/* SPI mode control */
#define  SPI_EN  	(1<<0)	/* enable SPI mode */
#define  SPI_CRC_ON	(1<<1)	/* enable CRC generation */
#define  SPI_CS_EN	(1<<2)	/* Enable CS[01] */
#define  SPI_CS_ADDRESS	(1<<3)	/* CS0/CS1 */
#define MMC_CMDAT	0x10	/* command/response/data */
#define  CMDAT_RESPONSE_FORMAT	0x03
#define  CMDAT_RESPONSE_FORMAT_NO 0 /* no response */
#define  CMDAT_RESPONSE_FORMAT_R1 1 /* R1, R1b, R4, R5, R5b, R6 */
#define  CMDAT_RESPONSE_FORMAT_R2 2
#define  CMDAT_RESPONSE_FORMAT_R3 3
#define  CMDAT_DATA_EN		(1<<2)
#define  CMDAT_WRITE		(1<<3) /* 1=write 0=read operation */
#define  CMDAT_STREAM_BLOCK	(1<<4) /* stream mode */
#define  CMDAT_BUSY		(1<<5) /* busy signal is expected */
#define  CMDAT_INIT		(1<<6) /* precede command with 80 clocks */
#define  CMDAT_MMC_DMA_EN	(1<<7) /* DMA enable */
#define MMC_RESTO	0x14	/* expected response time out */
#define MMC_RDTO 	0x18	/* expected data read time out */
#define MMC_BLKLEN	0x1c	/* block length of data transaction */
#define MMC_NUMBLK  	0x20	/* number of blocks (block mode) */
#define MMC_PRTBUF	0x24	/* partial MMC_TXFIFO written */
#define  PRTBUF_BUF_PART_FULL (1<<0) /* buffer partially full */
#define MMC_I_MASK	0x28	/* interrupt mask */
#define MMC_I_REG	0x2c	/* interrupt register */
#define  MMC_I_DATA_TRAN_DONE	(1<<0)
#define  MMC_I_PRG_DONE		(1<<1)
#define  MMC_I_END_CMD_RES	(1<<2)
#define  MMC_I_STOP_CMD		(1<<3)
#define  MMC_I_CLK_IS_OFF	(1<<4)
#define  MMC_I_RXFIFO_RD_REQ	(1<<5)
#define  MMC_I_TXFIFO_WR_REQ	(1<<6)
#define  MMC_I_DAT_ERR		(1<<8)	/* PXA27x */
#define  MMC_I_RES_ERR		(1<<9)	/* PXA27x */
#define  MMC_I_SDIO_INT		(1<<11)	/* PXA27x */
#define MMC_CMD  	0x30	/* index of current command */
#define MMC_ARGH 	0x34	/* MSW part of the current command arg */
#define MMC_ARGL 	0x38	/* LSW part of the current command arg */
#define MMC_RES  	0x3c	/* response FIFO */
#define MMC_RXFIFO	0x40	/* receive FIFO */
#define MMC_TXFIFO	0x44 	/* transmit FIFO */

/*
 * Inter-IC Sound (I2S) Controller
 */
#define I2S_SACR0	0x0000	/* Serial Audio Global Control */
#define  SACR0_ENB		(1<<0)	/* Enable I2S Function */
#define  SACR0_BCKD		(1<<2)	/* I/O Direction of I2S_BITCLK */
#define  SACR0_RST		(1<<3)	/* FIFO Reset */
#define  SACR0_EFWR		(1<<4)	/* Special-Purpose FIFO W/R Func */
#define  SACR0_STRF		(1<<5)	/* Select TX or RX FIFO */
#define  SACR0_TFTH_MASK	(0xf<<8) /* Trans FIFO Intr/DMA Trig Thresh */
#define  SACR0_RFTH_MASK	(0xf<<12) /* Recv FIFO Intr/DMA Trig Thresh */
#define  SACR0_SET_TFTH(x)	(((x) & 0xf)<<8)
#define  SACR0_SET_RFTH(x)	(((x) & 0xf)<<12)
#define I2S_SACR1	0x0004	/* Serial Audio I2S/MSB-Justified Control */
#define  SACR1_AMSL		(1<<0)	/* Specify Alt Mode (I2S or MSB) */
#define  SACR1_DREC		(1<<3)	/* Disable Recording Func */
#define  SACR1_DRPL		(1<<4)	/* Disable Replay Func */
#define  SACR1_ENLBF		(1<<5)	/* Enable Interface Loopback Func */
#define I2S_SASR0	0x000c	/* Serial Audio I2S/MSB-Justified Status */
#define  SASR0_TNF		(1<<0)	/* Transmit FIFO Not Full */
#define  SASR0_RNE		(1<<1)	/* Recv FIFO Not Empty */
#define  SASR0_BSY		(1<<2)	/* I2S Busy */
#define  SASR0_TFS		(1<<3)	/* Trans FIFO Service Request */
#define  SASR0_RFS		(1<<4)	/* Recv FIFO Service Request */
#define  SASR0_TUR		(1<<5)	/* Trans FIFO Underrun */
#define  SASR0_ROR		(1<<6)	/* Recv FIFO Overrun */
#define  SASR0_I2SOFF		(1<<7)	/* I2S Controller Off */
#define  SASR0_TFL_MASK		(0xf<<8) /* Trans FIFO Level */
#define  SASR0_RFL_MASK		(0xf<<12) /* Recv FIFO Level */
#define  SASR0_GET_TFL(x)	(((x) & 0xf) >> 8)
#define  SASR0_GET_RFL(x)	(((x) & 0xf) >> 12)
#define I2S_SAIMR	0x0014	/* Serial Audio Interrupt Mask */
#define  SAIMR_TFS		(1<<3)	/* Enable TX FIFO Service Req Intr */
#define  SAIMR_RFS		(1<<4)	/* Enable RX FIFO Service Req Intr */
#define  SAIMR_TUR		(1<<5)	/* Enable TX FIFO Underrun Intr */
#define  SAIMR_ROR		(1<<6)	/* Enable RX FIFO Overrun Intr */
#define I2S_SAICR	0x0018	/* Serial Audio Interrupt Clear */
#define  SAICR_TUR		(1<<5)	/* Clear Intr and SASR0_TUR */
#define  SAICR_ROR		(1<<6)	/* Clear Intr and SASR0_ROR */
#define I2S_SADIV	0x0060	/* Audio Clock Divider */
#define  SADIV_MASK		0x7f
#define  SADIV_3_058MHz		0x0c	/* 3.058 MHz */
#define  SADIV_2_836MHz		0x0d	/* 2.836 MHz */
#define  SADIV_1_405MHz		0x1a	/* 1.405 MHz */
#define  SADIV_1_026MHz		0x24	/* 1.026 MHz */
#define  SADIV_702_75kHz	0x34	/* 702.75 kHz */
#define  SADIV_513_25kHz	0x48	/* 513.25 kHz */
#define I2S_SADR	0x0080	/* Serial Audio Data Register */
#define  SADR_DTL		(0xffff<<0) /* Left Data Sample */
#define  SADR_DTH		(0xffff<<16) /* Right Data Sample */

/*
 * AC '97 Controller
 */
#define AC97_POCR	0x0000	/* PCM Out Control Register */
#define  POCR_FSRIE		(1<<1)	/* FIFO Service Request Intr Enable */
#define  POCR_FEIE		(1<<3)	/* FIFO Error Intr Enable */
#define AC97_PCMICR	0x0004	/* PCM In Control Register */
#define  PCMICR_FSRIE		(1<<1)	/* FIFO Service Request Intr Enable */
#define  PCMICR_FEIE		(1<<3)	/* FIFO Error Intr Enable */
#define AC97_MCCR	0x0008	/* Microphone In Control Register */
#define  MCCR_FSRIE		(1<<1)	/* FIFO Service Request Intr Enable */
#define  MCCR_FEIE		(1<<3)	/* FIFO Error Intr Enable */
#define AC97_GCR	0x000c	/* Global Control Register */
#define  GCR_GPI_IE		(1<<0)	/* Codec GPI Interrupt Enable */
#define  GCR_nCRST		(1<<1)	/* AC '97 Cold Reset */
#define  GCR_WRST		(1<<2)	/* AC '97 Warm Reset */
#define  GCR_ACOFF		(1<<3)	/* AC-Link Shut Off */
#define  GCR_PRES_IE		(1<<4)	/* Primary Resume Intr Enable */
#define  GCR_SRES_IE		(1<<5)	/* Secondary Resume Intr Enable */
#define  GCR_PRDY_IE		(1<<8)	/* Primary Ready Intr Enable */
#define  GCR_SRDY_IE		(1<<9)	/* Secondary Ready Intr Enable */
#define  GCR_SDONE_IE		(1<<18)	/* Status Done Intr Enable */
#define  GCR_CDONE_IE		(1<<19)	/* Command Done Intr Enable */
#define  GCR_nDMAEN		(1<<24)	/* DMA Enable (PXA27x) */
#define AC97_POSR	0x0010	/* PCM Out Status Register */
#define  POSR_FSR		(1<<2)	/* FIFO Service Request */
#define  POSR_FIFOE		(1<<4)	/* FIFO Error */
#define AC97_PCMISR	0x0014	/* PCM In Status Register */
#define  PCMISR_FSR		(1<<2)	/* FIFO Service Request */
#define  PCMISR_ECC		(1<<3)	/* DMA End of Chain Intr */
#define  PCMISR_FIFOE		(1<<4)	/* FIFO Error */
#define AC97_MCSR	0x0018	/* Microphone In Status Register */
#define  MCSR_FSR		(1<<2)	/* FIFO Service Request */
#define  MCSR_ECC		(1<<3)	/* DMA End of Chain Intr */
#define  MCSR_FIFOE		(1<<4)	/* FIFO Error */
#define AC97_GSR	0x001c	/* Global Status Register */
#define  GSR_GSCI		(1<<0)	/* Codec GPI Status Change Intr */
#define  GSR_MIINT		(1<<1)	/* Modem-In Intr */
#define  GSR_MOINT		(1<<2)	/* Modem-Out Intr */
#define  GSR_ACOFFD		(1<<3)	/* AC-link Shut Off Done */
#define  GSR_PIINT		(1<<5)	/* PCM-In Intr */
#define  GSR_POINT		(1<<6)	/* PCM-Out Intr */
#define  GSR_MCINT		(1<<7)	/* Mic-In Intr */
#define  GSR_PCRDY		(1<<8)	/* Primay Codec Ready */
#define  GSR_SCRDY		(1<<9)	/* Secondary Codec Ready */
#define  GSR_PRESINT		(1<<10)	/* Primary Resume Intr */
#define  GSR_SRESINT		(1<<11)	/* Secondary Resume Intr */
#define  GSR_B1S12		(1<<12)	/* Bit 1 of Slot 12 */
#define  GSR_B2S12		(1<<13)	/* Bit 2 of Slot 12 */
#define  GSR_B3S12		(1<<14)	/* Bit 3 of Slot 12 */
#define  GSR_RCS		(1<<15)	/* Read Completion Status */
#define  GSR_SDONE		(1<<18)	/* Status Done */
#define  GSR_CDONE		(1<<19)	/* Command Done */
#define AC97_CAR	0x0020	/* Codec Access Register */
#define  CAR_CAIP		(1<<0)	/* Codec Access In Progress */
/* 0x0024 to 0x003c is reserved */
#define AC97_PCDR	0x0040	/* PCM Data Register */
#define  PCDR_PCML		(0xffff<<0)	/* PCM Left Channel Data */
#define  PCDR_PCMR		(0xffff<<16)	/* PCM Right Channel Data */
/* 0x0044 to 0x005c is reserved */
#define AC97_MCDR	0x0060	/* Microphone In Data Register */
#define  MCDR_MCDAT		(0xffff<<0)	/* Mic-In Data */
/* 0x0064 to 0x00fc is reserved */
#define AC97_MOCR	0x0100	/* Modem Out Control Register */
#define  MOCR_FSRIE		(1<<1)	/* FIFO Service Request Intr Enable */
#define  MOCR_FEIE		(1<<3)	/* FIFO Error Intr Enable */
/* 0x0104 is reserved */
#define AC97_MICR	0x0108	/* Modem In Control Register */
#define  MICR_FSRIE		(1<<1)	/* FIFO Service Request Intr Enable */
#define  MICR_FEIE		(1<<3)	/* FIFO Error Intr Enable */
/* 0x010c is reserved */
#define AC97_MOSR	0x0110	/* Modem Out Status Register */
#define  MOSR_FSR		(1<<2)	/* FIFO Service Request */
#define  MOSR_FIFOE		(1<<2)	/* FIFO Error */
/* 0x0114 is reserved */
#define AC97_MISR	0x0118	/* Modem In Status Register */
#define  MOSR_FSR		(1<<2)	/* FIFO Service Request */
#define  MOSR_EOC		(1<<2)	/* DMA End of Chain Intr */
#define  MOSR_FIFOE		(1<<2)	/* FIFO Error */
/* 0x011c  to 0x013c is reserved */
#define AC97_MODR	0x0140	/* Modem Data Register */
#define  MODR_MODAT		(0xffff<<0)	/* Modem Data */
/* 0x0144 to 0x01fc is reserved */

#define AC97_PRIAUDIO	0x0200	/* Primary Audio Codec Registers */
#define AC97_SECAUDIO	0x0300	/* Secondary Audio Codec Registers */
#define AC97_PRIMODEM	0x0400	/* Primary Modem Codec Registers */
#define AC97_SECMODEM	0x0500	/* Secondary modem Codec Registers */

/*
 * USB device controller differs between pxa255 and pxa27x, defined separately
 */

/*
 * USB Host Controller
 */
#define USBHC_STAT	0x0060	/* UHC Status Register */
#define  USBHC_STAT_RWUE	(1<<7)	/* HCI Remote Wake-Up Event */
#define  USBHC_STAT_HBA		(1<<8)	/* HCI Buffer Active */
#define  USBHC_STAT_HTA		(1<<10)	/* HCI Transfer Abort */
#define  USBHC_STAT_UPS1	(1<<11)	/* USB Power Sense Port 1 */
#define  USBHC_STAT_UPS2	(1<<12)	/* USB Power Sense Port 2 */
#define  USBHC_STAT_UPRI	(1<<13)	/* USB Port Resume Interrupt */
#define  USBHC_STAT_SBTAI	(1<<14)	/* System Bus Target Abort Interrupt */
#define  USBHC_STAT_SBMAI	(1<<15)	/* System Bus Master Abort Interrupt */
#define  USBHC_STAT_UPS3	(1<<16)	/* USB Power Sense Port 3 */
#define  USBHC_STAT_MASK	(USBHC_STAT_RWUE | USBHC_STAT_HBA | \
    USBHC_STAT_HTA | USBHC_STAT_UPS1 | USBHC_STAT_UPS2 | USBHC_STAT_UPRI | \
    USBHC_STAT_SBTAI | USBHC_STAT_SBMAI | USBHC_STAT_UPS3)
#define USBHC_HR	0x0064	/* UHC Reset Register */
#define  USBHC_HR_FSBIR		(1<<0)	/* Force System Bus Interface Reset */
#define  USBHC_HR_FHR		(1<<1)	/* Force Host Controller Reset */
#define  USBHC_HR_CGR		(1<<2)	/* Clock Generation Reset */
#define  USBHC_HR_SSDC		(1<<3)	/* Simulation Scale Down Clock */
#define  USBHC_HR_UIT		(1<<4)	/* USB Interrupt Test */
#define  USBHC_HR_SSE		(1<<5)	/* Sleep Standby Enable */
#define  USBHC_HR_PSPL		(1<<6)	/* Power Sense Polarity Low */
#define  USBHC_HR_PCPL		(1<<7)	/* Power Control Polarity Low */
#define  USBHC_HR_SSEP1		(1<<9)	/* Sleep Standby Enable for Port 1 */
#define  USBHC_HR_SSEP2		(1<<10)	/* Sleep Standby Enable for Port 2 */
#define  USBHC_HR_SSEP3		(1<<11)	/* Sleep Standby Enable for Port 3 */
#define  USBHC_HR_MASK		(USBHC_HR_FSBIR | USBHC_HR_FHR | \
    USBHC_HR_CGR | USBHC_HR_SSDC | USBHC_HR_UIT | USBHC_HR_SSE | \
    USBHC_HR_PSPL | USBHC_HR_PCPL | USBHC_HR_SSEP1 | USBHC_HR_SSEP2 | \
    USBHC_HR_SSEP3)
#define USBHC_HIE	0x0068	/* UHC Interrupt Enable Register */
#define  USBHC_HIE_RWIE		(1<<7)	/* HCI Remote Wake-Up */
#define  USBHC_HIE_HBAIE	(1<<8)	/* HCI Buffer Active */
#define  USBHC_HIE_TAIE		(1<<10)	/* HCI Interface Transfer Abort */
#define  USBHC_HIE_UPS1IE	(1<<11)	/* USB Power Sense Port 1 */
#define  USBHC_HIE_UPS2IE	(1<<12)	/* USB Power Sense Port 2 */
#define  USBHC_HIE_UPRIE	(1<<13)	/* USB Port Resume */
#define  USBHC_HIE_UPS3IE	(1<<14)	/* USB Power Sense Port 3 */
#define  USBHC_HIE_MASK		(USBHC_HIE_RWIE | USBHC_HIE_HBAIE | \
    USBHC_HIE_TAIE | USBHC_HIE_UPS1IE | USBHC_HIE_UPS2IE | USBHC_HIE_UPRIE | \
    USBHC_HIE_UPS3IE)
#define USBHC_HIT	0x006C	/* UHC Interrupt Test Register */
#define  USBHC_HIT_RWUT		(1<<7)	/* HCI Remote Wake-Up */
#define  USBHC_HIT_BAT		(1<<8)	/* HCI Buffer Active */
#define  USBHC_HIT_IRQT		(1<<9)	/* Normal OHC */
#define  USBHC_HIT_TAT		(1<<10)	/* HCI Interface Transfer Abort */
#define  USBHC_HIT_UPS1T	(1<<11)	/* USB Power Sense Port 1 */
#define  USBHC_HIT_UPS2T	(1<<12)	/* USB Power Sense Port 2 */
#define  USBHC_HIT_UPRT		(1<<13)	/* USB Port Resume */
#define  USBHC_HIT_STAT		(1<<14)	/* System Bus Target Abort */
#define  USBHC_HIT_SMAT		(1<<15)	/* System Bus Master Abort */
#define  USBHC_HIT_UPS3T	(1<<16)	/* USB Power Sense Port 3 */
#define  USBHC_HIT_MASK		(USBHC_HIT_RWUT | USBHC_HIT_BAT | \
    USBHC_HIT_IRQT | USBHC_HIT_TAT | USBHC_HIT_UPS1T | USBHC_HIT_UPS2T | \
    USBHC_HIT_UPRT | USBHC_HIT_STAT | USBHC_HIT_SMAT | USBHC_HIT_UPS3T)
#define USBHC_RST_WAIT	10000	/* usecs to wait for reset */

/* OS Timer */
#define OST_OSMR0	0x0000	/* Match 0 */
#define OST_OSMR1	0x0004	/* Match 1 */
#define OST_OSMR2	0x0008	/* Match 2 */
#define OST_OSMR3	0x000c	/* Match 3 */
#define OST_OSCR0	0x0010	/* Counter 0 */

#define OST_OSCR4	0x0040	/* Counter 4 */
#define OST_OMCR4	0x00c0	/* Counter 4 match control */
#define OST_OSMR4	0x0080	/* Counter 4 match */
#define OST_OSCR5	0x0044	/* Counter 5 */
#define OST_OMCR5	0x00c4	/* Counter 5 match control */
#define OST_OSMR5	0x0084	/* Counter 4 match */

#define OST_OSSR	0x0014	/* Status (all counters) */
#define OST_OWER	0x0018	/* Watchdog Enable */
#define  OWER_WME	 (1<<0)
#define OST_OIER	0x001c	/* Interrupt Enable */
#define  OIER_E3	 (1<<3)

/* Synchronous Serial Protocol (SSP) serial ports */
#define SSP_SSCR0	0x00
#define SSP_SSCR1	0x04
#define SSP_SSSR	0x08
#define  SSSR_TNF	(1<<2)
#define  SSSR_RNE	(1<<3)
#define SSP_SSDR	0x10

/* KPC */
#define KPC_KPC		0x00
#define  KPC_MIE	(1<<11)
#define  KPC_ME		(1<<12)
#define  KPC_MS(n)	((n & 0xff) << 13)
#define  KPC_IMKP	(1<<21)
#define  KPC_MI		(1<<22)
#define  KPC_MKCN(n)	((n & 0x7) << 23)
#define  KPC_MKRN(n)	((n & 0x7) << 26)
#define  KPC_ASACT	(1<<29)
#define KPC_KPAS	0x20
#define  KPAS_CP	(0xf<<0)
#define  KPAS_RP	(0xf<<4)
#define  KPAS_MUKP	(0x1f<<26)
#define  KPAS_SO	(1<<31)
#define KPC_KPKDI	0x48

#endif /* _ARM_XSCALE_PXA2X0REG_H_ */


code:
/*	$OpenBSD: pxa2x0var.h,v 1.5 2005/05/27 21:10:05 uwe Exp $ */
/* $NetBSD: pxa2x0var.h,v 1.2 2003/06/05 13:48:28 scw Exp $ */

/*
 * Copyright (c) 2002  Genetec Corporation.  All rights reserved.
 * Written by Hiroyuki Bessho for Genetec Corporation.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *	This product includes software developed for the NetBSD Project by
 *	Genetec Corporation.
 * 4. The name of Genetec Corporation may not be used to endorse or
 *    promote products derived from this software without specific prior
 *    written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL GENETEC CORPORATION
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef _ARM_XSCALE_PXA2X0VAR_H_
#define _ARM_XSCALE_PXA2X0VAR_H_

#include <arm/sa11x0/sa11x0_var.h>

/* PXA2X0's integrated peripheral bus. */

typedef int (* pxa2x0_irq_handler_t)(void *);

struct pxaip_attach_args {
	struct sa11x0_attach_args  pxa_sa;
	bus_dma_tag_t pxa_dmat;
	int pxa_index;			/* to specify device by index number */

#define pxa_iot 	pxa_sa.sa_iot
#define pxa_addr	pxa_sa.sa_addr
#define pxa_size	pxa_sa.sa_size
#define pxa_intr	pxa_sa.sa_intr
};

#define	cf_addr		cf_loc[0]
#define	cf_size		cf_loc[1]
#define	cf_intr		cf_loc[2]
#define	cf_index	cf_loc[3]

extern struct bus_space pxa2x0_bs_tag;
extern struct arm32_bus_dma_tag pxa2x0_bus_dma_tag;
extern struct bus_space pxa2x0_a4x_bs_tag;

/* misc. */
extern void pxa2x0_fcs_init(void);
extern void pxa2x0_freq_change(int);
extern void pxa2x0_turbo_mode(int);
extern int pxa2x0_i2c_master_tx( int, uint8_t *, int );

/*
 * Probe the memory controller to determine which SDRAM banks
 * are populated, and what size SDRAM is present in each bank.
 *
 * This routine should be called from a port's initarm()
 * function, with the first parameter set to the address
 * of the memory controller's registers.
 */
extern void pxa2x0_probe_sdram(vaddr_t, paddr_t *, psize_t *);

/*
 * Configure one or more clock enables in the Clock Manager's
 * CKEN register.
 */
extern void pxa2x0_clkman_config(u_int, int);

/*
 * Get/set the Real Time Clock's counter and alarm registers.
 */
extern void pxa2x0_rtc_setalarm(u_int32_t);
extern u_int32_t pxa2x0_rtc_getalarm(void);
extern u_int32_t pxa2x0_rtc_getsecs(void);

#endif /* _ARM_XSCALE_PXA2X0VAR_H_ */


code:
/*	$OpenBSD: pxammcvar.h,v 1.2 2009/09/03 21:40:29 marex Exp $	*/

/*
 * Copyright (c) 2007 Uwe Stuehler <uwe@openbsd.org>
 *
 * Permission to use, copy, modify, and distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include <machine/bus.h>

struct pxammc_tag {
	void *cookie;
	u_int32_t (*get_ocr)(void *);
	int (*set_power)(void *, u_int32_t);
};

struct pxammc_softc {
	struct device sc_dev;		/* base device */
	struct pxammc_tag tag;		/* attachment driver functions */
	bus_space_tag_t sc_iot;		/* register space tag */
	bus_space_handle_t sc_ioh;	/* register space handle */
	struct device *sc_sdmmc;	/* generic sdmmc bus device */
	void *sc_card_ih;		/* card interrupt handle */
	void *sc_ih;			/* MMC interrupt handle */
	int sc_flags;			/* driver state flags */
#define PMF_CARD_INITED	0x0001		/* card init sequence sent */
	int sc_clkdiv;			/* current clock divider */
	struct sdmmc_command * volatile sc_cmd;	/* command in progress */
	int sc_gpio_detect;		/* card detect GPIO */
};

int	pxammc_match(void);
void	pxammc_attach(struct pxammc_softc *, void *);


code:
/*	$OpenBSD: pxapcicvar.h,v 1.7 2005/12/14 15:08:51 uwe Exp $ */

/*
 * Copyright (c) 2005 Dale Rahn <drahn@openbsd.org>
 *
 * Permission to use, copy, modify, and distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

struct pxapcic_socket {
        struct pxapcic_softc *sc;
        int socket;		/* socket number */
        struct device *pcmcia;
	struct proc *event_thread;

        int flags;
        int power_capability;	/* PXAPCIC_POWER_3V | PXAPCIC_POWER_5V */

	int irqpin;
	void *irq;

        void *pcictag_cookie;	/* opaque data for pcictag functions */
	struct pxapcic_tag *pcictag;
};

/* event */
#define PXAPCIC_EVENT_INSERTION	0
#define PXAPCIC_EVENT_REMOVAL	1

/* flags */
#define PXAPCIC_FLAG_CARDD	0
#define PXAPCIC_FLAG_CARDP	1

struct pxapcic_tag {
	u_int (*read)(struct pxapcic_socket *, int);
	void (*write)(struct pxapcic_socket *, int, u_int);
	void (*set_power)(struct pxapcic_socket *, int);
	void (*clear_intr)(struct pxapcic_socket *);
	void *(*intr_establish)(struct pxapcic_socket *, int,
	    int (*)(void *), void *);
	void (*intr_disestablish)(struct pxapcic_socket *, void *);
	const char *(*intr_string)(struct pxapcic_socket *);
};

/* pcictag registers and their values */
#define PXAPCIC_CARD_STATUS	0
#define  PXAPCIC_CARD_INVALID	0
#define  PXAPCIC_CARD_VALID	1
#define PXAPCIC_CARD_READY	1
#define PXAPCIC_CARD_POWER	2
#define  PXAPCIC_POWER_OFF	0
#define  PXAPCIC_POWER_3V	1
#define  PXAPCIC_POWER_5V	2
#define PXAPCIC_CARD_RESET	3

struct pxapcic_softc {
	struct device sc_dev;
	struct pxapcic_socket sc_socket[2];

        bus_space_tag_t sc_iot;
        bus_space_handle_t sc_memctl_ioh;

	void *sc_irq;
        int sc_shutdown;
	int sc_nslots;
	int sc_irqpin[2];
	int sc_irqcfpin[2];
};

void	pxapcic_attach(struct pxapcic_softc *,
    void (*socket_setup_hook)(struct pxapcic_socket *));
int	pxapcic_intr(void *);


code:
/*	$OpenBSD: xscalereg.h,v 1.2 2006/05/29 17:27:31 drahn Exp $	*/
/*	$NetBSD: xscalereg.h,v 1.2 2002/08/07 05:15:02 briggs Exp $	*/

/*
 * Copyright (c) 2001 Wasabi Systems, Inc.
 * All rights reserved.
 *
 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *	This product includes software developed for the NetBSD Project by
 *	Wasabi Systems, Inc.
 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
 *    or promote products derived from this software without specific prior
 *    written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef _ARM_XSCALE_XSCALEREG_H_
#define _ARM_XSCALE_XSCALEREG_H_

/*
 * Register definitions for the Intel XScale processor core.
 */

/*
 * Performance Monitoring Unit		(CP14)
 *
 *	CP14.0		Performance Monitor Control Register
 *	CP14.1		Clock Counter
 *	CP14.2		Performance Counter Register 0
 *	CP14.3		Performance Counter Register 1
 */

#define	PMNC_E		0x00000001	/* enable counters */
#define	PMNC_P		0x00000002	/* reset both PMNs to 0 */
#define	PMNC_C		0x00000004	/* clock counter reset */
#define	PMNC_D		0x00000008	/* clock counter / 64 */
#define	PMNC_PMN0_IE	0x00000010	/* enable PMN0 interrupt */
#define	PMNC_PMN1_IE	0x00000020	/* enable PMN1 interrupt */
#define	PMNC_CC_IE	0x00000040	/* enable clock counter interrupt */
#define	PMNC_PMN0_IF	0x00000100	/* PMN0 overflow/interrupt */
#define	PMNC_PMN1_IF	0x00000200	/* PMN1 overflow/interrupt */
#define	PMNC_CC_IF	0x00000400	/* clock counter overflow/interrupt */
#define	PMNC_EVCNT0_MASK 0x000ff000	/* event to count for PMN0 */
#define	PMNC_EVCNT0_SHIFT 12
#define	PMNC_EVCNT1_MASK 0x0ff00000	/* event to count for PMN1 */
#define	PMNC_EVCNT1_SHIFT 20

void	xscale_pmu_init(void);

#endif /* _ARM_XSCALE_XSCALEREG_H_ */


code:
/Makefile/1.6/Sun Dec  8 14:46:39 2013//TOPENBSD_5_8_BASE
D/armish////
D/compile////
D/conf////
D/dev////
D/include////
D/stand////

path: sys/arch/armish/CVS/Entries


code: src/sys/arch/armish

path: sys/arch/armish/CVS/Repository


code:
#	$OpenBSD: Makefile,v 1.6 2013/12/08 14:46:39 espie Exp $

S=	${.CURDIR}/../..
KFILE=	GENERIC
.if exists(conf/GENERIC.MP)
KFILE=	GENERIC.MP
.endif
TDIRS=	${_arch} include
TAGS=	${.CURDIR}/tags

NOPROG=
NOMAN=
NOOBJ=
SUBDIR=	stand

# config the fattest kernel we can find into a temporary dir
# to create a Makefile.  Then use make to pull some variables
# out and push them into the sub-shell to expand the paths,
# and finally run ctags.
tags::
	TDIR=`mktemp -d /tmp/_tagXXXXXXXXXX` || exit 1; \
	eval "S=${S}" && \
	config -s ${S} -b $${TDIR} ${.CURDIR}/conf/${KFILE} && \
	eval "_arch=\"`make -V _arch -f $${TDIR}/Makefile`\"" && \
	eval "_mach=\"`make -V _mach -f $${TDIR}/Makefile`\"" && \
	eval "_machdir=\$S/arch/$${_mach}" && \
	eval "_archdir=\$S/arch/$${_arch}" && \
	eval "HFILES=\"`find $S \( -path $S/'arch' -o -path $S/stand -o -path $S/lib/libsa -o -path $S'/lib/libkern/arch' \) -prune -o -name '*.h'; find $${_machdir} $${_archdir} $S/lib/libkern/arch/$${_mach} \( -name boot -o -name stand \) -prune -o -name '*.h'`\"" && \
	eval "SFILES=\"`make -V SFILES -f $${TDIR}/Makefile`\"" && \
	eval "CFILES=\"`make -V CFILES -f $${TDIR}/Makefile`\"" && \
	eval "AFILES=\"`make -V AFILES -f $${TDIR}/Makefile`\"" && \
	ctags -wd -f ${TAGS} $${CFILES} $${HFILES} && \
	egrep "^[_A-Z]*ENTRY[_A-Z]*\(.*\)" $${SFILES} $${AFILES} | \
	    sed "s;\\([^:]*\\):\\([^(]*\\)(\\([^, )]*\\)\\(.*\\);\\3	\\1	/^\\2(\\3\\4$$/;" \
	    >> ${TAGS} && \
	sort -o ${TAGS} ${TAGS} && \
	rm -rf $${TDIR}

links:
	-for i in conf ${TDIRS}; do \
	    (cd $$i && rm -f tags; ln -s tags tags); done

obj:	_SUBDIRUSE

.include <bsd.prog.mk>

path: sys/arch/armish/Makefile


code:
/armish_machdep.c/1.39/Sun May 10 15:56:28 2015//TOPENBSD_5_8_BASE
/armish_start.S/1.2/Mon May 29 17:30:26 2006//TOPENBSD_5_8_BASE
/autoconf.c/1.12/Tue Sep 20 22:02:13 2011//TOPENBSD_5_8_BASE
/genassym.cf/1.1/Mon Apr 26 22:11:38 2010//TOPENBSD_5_8_BASE
D

path: sys/arch/armish/armish/CVS/Entries


code: src/sys/arch/armish/armish

path: sys/arch/armish/armish/CVS/Repository