Instruct: Identify the main and secondary category of Arxiv papers based on the titles and abstracts
Query: RVCoreP-32IC: A high-performance RISC-V soft processor with an efficient
  fetch unit supporting the compressed instructions   In this paper, we propose a high-performance RISC-V soft processor with an
efficient fetch unit supporting the compressed instructions targeting on FPGA.
The compressed instruction extension in RISC-V can reduce the program size by
about 25%. But it needs a complicated logic for the instruction fetch unit and
has a significant impact on performance. We propose an instruction fetch unit
that supports the compressed instructions while exhibiting high performance.
Furthermore, we propose a RISC-V soft processor using this unit. We implement
this proposed processor in Verilog HDL and verify the behavior using Verilog
simulation and an actual Xilinx Atrix-7 FPGA board. We compare the results of
some benchmarks and the amount of hardware with related works. DMIPS, CoreMark
value, and Embench value of the proposed processor achieved 42.5%, 41.1% and
21.3% higher performance than the related work, respectively.

2
The categories of this paper are: math
16
The categories of this paper are: stat
28
The categories of this paper are: alg-geom
17
The categories of this paper are: q-fin
19
The categories of this paper are: eess
13
The categories of this paper are: quant-ph
23
The categories of this paper are: solv-int
37
The categories of this paper are: supr-con
15
The categories of this paper are: nucl-ex
3
The categories of this paper are: physics
27
The categories of this paper are: comp-gas
11
The categories of this paper are: hep-lat
24
The categories of this paper are: dg-ga
0
The categories of this paper are: hep-ph
7
The categories of this paper are: hep-th
5
The categories of this paper are: gr-qc