Instruct: Identify the main and secondary category of Arxiv papers based on the titles and abstracts
Query: Fast Prefix Adders for Non-Uniform Input Arrival Times   We consider the problem of constructing fast and small parallel prefix adders
for non-uniform input arrival times. This problem arises whenever the adder is
embedded into a more complex circuit, e. g. a multiplier.
  Most previous results are based on representing binary carry-propagate adders
as so-called parallel prefix graphs, in which pairs of generate and propagate
signals are combined using complex gates known as prefix gates. Adders
constructed in this model usually minimize the delay in terms of these prefix
gates. However, the delay in terms of logic gates can be worse by a factor of
two.
  In contrast, we aim to minimize the delay of the underlying logic circuit
directly. We prove a lower bound on the delay of a carry bit computation
achievable by any prefix carry bit circuit and develop an algorithm that
computes a prefix carry bit circuit with optimum delay up to a small additive
constant. Furthermore, we use this algorithm to construct a small parallel
prefix adder.
  Compared to existing algorithms we simultaneously improve the delay and size
guarantee, as well as the running time for constructing prefix carry bit and
adder circuits.

26
The categories of this paper are: bayes-an
22
The categories of this paper are: chao-dyn
37
The categories of this paper are: supr-con
12
The categories of this paper are: nucl-th
36
The categories of this paper are: cmp-lg
19
The categories of this paper are: eess
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The categories of this paper are: alg-geom
18
The categories of this paper are: econ
23
The categories of this paper are: solv-int
13
The categories of this paper are: quant-ph
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The categories of this paper are: atom-ph
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The categories of this paper are: comp-gas
10
The categories of this paper are: q-bio
34
The categories of this paper are: chem-ph
6
The categories of this paper are: astro-ph
11
The categories of this paper are: hep-lat