next hlt =>
cases Nat.eq_or_lt_of_le hidx2 with
| inl heq =>
  rw [← hgo]
  rw [go_getRef (hidx := by omega)]
  rw [AIG.RefStream.getRef_push_ref_eq' (hidx := by rw [heq])]
  simp only [← heq]
  rw [go_denote_mem_prefix]
  . unfold mkFullAdder
    simp [hcin]
  . simp only [Ref_cast']
    apply Ref.hgate
| inr hlt =>
  rw [← hgo]
  rw [go_eq_eval_getLsb (lhsExpr := lhsExpr) (rhsExpr := rhsExpr) (curr := curr + 1)]
  . rw [mkFullAdder_denote_mem_prefix]
    rw [mkFullAdder_denote_mem_prefix]
    . simp
    . simp [Ref.hgate]
    . simp [Ref.hgate]
  . intro idx hidx
    rw [mkFullAdder_denote_mem_prefix]
    rw [← hleft idx hidx]
    . simp
    . simp [Ref.hgate]
  . intro idx hidx
    rw [mkFullAdder_denote_mem_prefix]
    rw [← hright idx hidx]
    . simp
    . simp [Ref.hgate]
  . unfold mkFullAdder
    simp only [Ref_cast', id_eq, Int.reduceNeg, denote_projected_entry, denote_mkFullAdderCarry,
      FullAdderInput.lhs_cast, FullAdderInput.rhs_cast, FullAdderInput.cin_cast,
      BitVec.carry_succ]
    rw [AIG.LawfulOperator.denote_mem_prefix (f := mkFullAdderOut)]
    rw [AIG.LawfulOperator.denote_mem_prefix (f := mkFullAdderOut)]
    rw [AIG.LawfulOperator.denote_mem_prefix (f := mkFullAdderOut)]
    rw [hleft, hright, hcin]
    simp [_root_.Bool.atLeastTwo_eq_halfAdder]
  . omega
case isTrue
α : Type
inst✝² : BEq α
inst✝¹ : Hashable α
inst✝ : DecidableEq α
w : Nat
aig : AIG α
curr : Nat
hcurr : curr ≤ w
cin : aig.Ref
s : aig.RefStream curr
lhs rhs : aig.RefStream w
assign : α → Bool
lhsExpr rhsExpr : BitVec w
hleft : ∀ (idx : Nat) (hidx : idx < w), ⟦{ aig := aig, ref := lhs.getRef idx hidx }, assign⟧ = lhsExpr.getLsb idx
hright : ∀ (idx : Nat) (hidx : idx < w), ⟦{ aig := aig, ref := rhs.getRef idx hidx }, assign⟧ = rhsExpr.getLsb idx
hcin : ⟦{ aig := aig, ref := cin }, assign⟧ = BitVec.carry curr lhsExpr rhsExpr false
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry α w
h✝ : curr < w
hgo :
  go (mkFullAdder aig { lhs := lhs.getRef curr h✝, rhs := rhs.getRef curr h✝, cin := cin }).aig (curr + 1) ⋯
      (mkFullAdder aig { lhs := lhs.getRef curr h✝, rhs := rhs.getRef curr h✝, cin := cin }).cout
      ((s.cast ⋯).pushRef (mkFullAdder aig { lhs := lhs.getRef curr h✝, rhs := rhs.getRef curr h✝, cin := cin }).out)
      (lhs.cast ⋯) (rhs.cast ⋯) =
    res
⊢ ⟦{ aig := res.aig, ref := res.stream.getRef idx hidx1 }, assign⟧ =
    ⟦{ aig := aig, ref := lhs.getRef idx hidx1 }, assign⟧.xor
      (⟦{ aig := aig, ref := rhs.getRef idx hidx1 }, assign⟧.xor (BitVec.carry idx lhsExpr rhsExpr false))
no goals