simp [hcin]
case inl
α : Type
inst✝² : BEq α
inst✝¹ : Hashable α
inst✝ : DecidableEq α
w : Nat
aig : AIG α
curr : Nat
hcurr : curr ≤ w
cin : aig.Ref
s : aig.RefStream curr
lhs rhs : aig.RefStream w
assign : α → Bool
lhsExpr rhsExpr : BitVec w
hleft : ∀ (idx : Nat) (hidx : idx < w), ⟦{ aig := aig, ref := lhs.getRef idx hidx }, assign⟧ = lhsExpr.getLsb idx
hright : ∀ (idx : Nat) (hidx : idx < w), ⟦{ aig := aig, ref := rhs.getRef idx hidx }, assign⟧ = rhsExpr.getLsb idx
hcin : ⟦{ aig := aig, ref := cin }, assign⟧ = BitVec.carry curr lhsExpr rhsExpr false
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry α w
hlt : curr < w
hgo :
  go (mkFullAdder aig { lhs := lhs.getRef curr hlt, rhs := rhs.getRef curr hlt, cin := cin }).aig (curr + 1) ⋯
      (mkFullAdder aig { lhs := lhs.getRef curr hlt, rhs := rhs.getRef curr hlt, cin := cin }).cout
      ((s.cast ⋯).pushRef (mkFullAdder aig { lhs := lhs.getRef curr hlt, rhs := rhs.getRef curr hlt, cin := cin }).out)
      (lhs.cast ⋯) (rhs.cast ⋯) =
    res
heq : curr = idx
⊢ ⟦{
        aig :=
          (let res := mkFullAdderOut aig { lhs := lhs.getRef curr hlt, rhs := rhs.getRef curr hlt, cin := cin };
            let aig_1 := res.aig;
            let outRef := res.ref;
            let_fun haig1 := ⋯;
            let input := { lhs := lhs.getRef curr hlt, rhs := rhs.getRef curr hlt, cin := cin }.cast haig1;
            let res_1 := mkFullAdderCarry aig_1 input;
            let aig_2 := res_1.aig;
            let carryRef := res_1.ref;
            let_fun haig2 := ⋯;
            let outRef := outRef.cast haig2;
            let_fun hle := ⋯;
            { aig := aig_2, out := outRef, cout := carryRef, hle := hle }).aig,
        ref :=
          {
            gate :=
              ((let res := mkFullAdderOut aig { lhs := lhs.getRef curr hlt, rhs := rhs.getRef curr hlt, cin := cin };
                      let aig_1 := res.aig;
                      let outRef := res.ref;
                      let_fun haig1 := ⋯;
                      let input := { lhs := lhs.getRef curr hlt, rhs := rhs.getRef curr hlt, cin := cin }.cast haig1;
                      let res_1 := mkFullAdderCarry aig_1 input;
                      let aig_2 := res_1.aig;
                      let carryRef := res_1.ref;
                      let_fun haig2 := ⋯;
                      let outRef := outRef.cast haig2;
                      let_fun hle := ⋯;
                      { aig := aig_2, out := outRef, cout := carryRef, hle := hle }).out.cast
                  ⋯).gate,
            hgate := ?inl.hstart } },
      assign⟧ =
    ⟦{ aig := aig, ref := lhs.getRef curr ⋯ }, assign⟧.xor
      (⟦{ aig := aig, ref := rhs.getRef curr ⋯ }, assign⟧.xor (BitVec.carry curr lhsExpr rhsExpr false))
no goals