rw [← hgo]
case isTrue.inr
α : Type
inst✝² : BEq α
inst✝¹ : Hashable α
inst✝ : DecidableEq α
assign : α → Bool
w : Nat
aig : AIG α
curr : Nat
hcurr : curr ≤ w
discr : aig.Ref
lhs rhs : aig.RefStream w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry α w
h✝ : curr < w
hgo :
  go (aig.mkIfCached { discr := discr, lhs := lhs.getRef curr h✝, rhs := rhs.getRef curr h✝ }).aig (curr + 1) ⋯
      { gate := discr.gate, hgate := ⋯ } (lhs.cast ⋯) (rhs.cast ⋯)
      ((s.cast ⋯).pushRef
        (aig.mkIfCached { discr := discr, lhs := lhs.getRef curr h✝, rhs := rhs.getRef curr h✝ }).ref) =
    res
heq : curr < idx
⊢ ⟦{ aig := res.aig, ref := res.stream.getRef idx hidx1 }, assign⟧ =
    if ⟦{ aig := aig, ref := discr }, assign⟧ = true then ⟦{ aig := aig, ref := lhs.getRef idx hidx1 }, assign⟧
    else ⟦{ aig := aig, ref := rhs.getRef idx hidx1 }, assign⟧
case isTrue.inr
α : Type
inst✝² : BEq α
inst✝¹ : Hashable α
inst✝ : DecidableEq α
assign : α → Bool
w : Nat
aig : AIG α
curr : Nat
hcurr : curr ≤ w
discr : aig.Ref
lhs rhs : aig.RefStream w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry α w
h✝ : curr < w
hgo :
  go (aig.mkIfCached { discr := discr, lhs := lhs.getRef curr h✝, rhs := rhs.getRef curr h✝ }).aig (curr + 1) ⋯
      { gate := discr.gate, hgate := ⋯ } (lhs.cast ⋯) (rhs.cast ⋯)
      ((s.cast ⋯).pushRef
        (aig.mkIfCached { discr := discr, lhs := lhs.getRef curr h✝, rhs := rhs.getRef curr h✝ }).ref) =
    res
heq : curr < idx
⊢ ⟦{
        aig :=
          (go (aig.mkIfCached { discr := discr, lhs := lhs.getRef curr h✝, rhs := rhs.getRef curr h✝ }).aig (curr + 1) ⋯
              { gate := discr.gate, hgate := ⋯ } (lhs.cast ⋯) (rhs.cast ⋯)
              ((s.cast ⋯).pushRef
                (aig.mkIfCached { discr := discr, lhs := lhs.getRef curr h✝, rhs := rhs.getRef curr h✝ }).ref)).aig,
        ref :=
          (go (aig.mkIfCached { discr := discr, lhs := lhs.getRef curr h✝, rhs := rhs.getRef curr h✝ }).aig (curr + 1) ⋯
                  { gate := discr.gate, hgate := ⋯ } (lhs.cast ⋯) (rhs.cast ⋯)
                  ((s.cast ⋯).pushRef
                    (aig.mkIfCached
                        { discr := discr, lhs := lhs.getRef curr h✝, rhs := rhs.getRef curr h✝ }).ref)).stream.getRef
            idx hidx1 },
      assign⟧ =
    if ⟦{ aig := aig, ref := discr }, assign⟧ = true then ⟦{ aig := aig, ref := lhs.getRef idx hidx1 }, assign⟧
    else ⟦{ aig := aig, ref := rhs.getRef idx hidx1 }, assign⟧