. intros
  rw [AIG.LawfulOperator.denote_mem_prefix (f := mkFullAdderCarry)]
  . simp [hright]
  . simp [Ref.hgate]
case isTrue.hright
α : Type
inst✝² : BEq α
inst✝¹ : Hashable α
inst✝ : DecidableEq α
w : Nat
aig : AIG α
curr : Nat
hcurr : curr ≤ w
cin origCin : aig.Ref
lhs rhs : aig.RefStream w
lhsExpr rhsExpr : BitVec w
assign : α → Bool
hleft : ∀ (idx : Nat) (hidx : idx < w), ⟦{ aig := aig, ref := lhs.getRef idx hidx }, assign⟧ = lhsExpr.getLsb idx
hright : ∀ (idx : Nat) (hidx : idx < w), ⟦{ aig := aig, ref := rhs.getRef idx hidx }, assign⟧ = rhsExpr.getLsb idx
hcin : ⟦{ aig := aig, ref := cin }, assign⟧ = BitVec.carry curr lhsExpr rhsExpr ⟦{ aig := aig, ref := origCin }, assign⟧
h✝ : curr < w
⊢ ∀ (idx : Nat) (hidx : idx < w),
    ⟦{ aig := (mkFullAdderCarry aig { lhs := lhs.getRef curr h✝, rhs := rhs.getRef curr h✝, cin := cin }).aig,
          ref := (rhs.cast ⋯).getRef idx hidx },
        assign⟧ =
      rhsExpr.getLsb idx

case isTrue.hcin
α : Type
inst✝² : BEq α
inst✝¹ : Hashable α
inst✝ : DecidableEq α
w : Nat
aig : AIG α
curr : Nat
hcurr : curr ≤ w
cin origCin : aig.Ref
lhs rhs : aig.RefStream w
lhsExpr rhsExpr : BitVec w
assign : α → Bool
hleft : ∀ (idx : Nat) (hidx : idx < w), ⟦{ aig := aig, ref := lhs.getRef idx hidx }, assign⟧ = lhsExpr.getLsb idx
hright : ∀ (idx : Nat) (hidx : idx < w), ⟦{ aig := aig, ref := rhs.getRef idx hidx }, assign⟧ = rhsExpr.getLsb idx
hcin : ⟦{ aig := aig, ref := cin }, assign⟧ = BitVec.carry curr lhsExpr rhsExpr ⟦{ aig := aig, ref := origCin }, assign⟧
h✝ : curr < w
⊢ ⟦{ aig := (mkFullAdderCarry aig { lhs := lhs.getRef curr h✝, rhs := rhs.getRef curr h✝, cin := cin }).aig,
        ref := (mkFullAdderCarry aig { lhs := lhs.getRef curr h✝, rhs := rhs.getRef curr h✝, cin := cin }).ref },
      assign⟧ =
    BitVec.carry (curr + 1) lhsExpr rhsExpr
      ⟦{ aig := (mkFullAdderCarry aig { lhs := lhs.getRef curr h✝, rhs := rhs.getRef curr h✝, cin := cin }).aig,
          ref := { gate := origCin.gate, hgate := ⋯ } },
        assign⟧
case isTrue.hcin
α : Type
inst✝² : BEq α
inst✝¹ : Hashable α
inst✝ : DecidableEq α
w : Nat
aig : AIG α
curr : Nat
hcurr : curr ≤ w
cin origCin : aig.Ref
lhs rhs : aig.RefStream w
lhsExpr rhsExpr : BitVec w
assign : α → Bool
hleft : ∀ (idx : Nat) (hidx : idx < w), ⟦{ aig := aig, ref := lhs.getRef idx hidx }, assign⟧ = lhsExpr.getLsb idx
hright : ∀ (idx : Nat) (hidx : idx < w), ⟦{ aig := aig, ref := rhs.getRef idx hidx }, assign⟧ = rhsExpr.getLsb idx
hcin : ⟦{ aig := aig, ref := cin }, assign⟧ = BitVec.carry curr lhsExpr rhsExpr ⟦{ aig := aig, ref := origCin }, assign⟧
h✝ : curr < w
⊢ ⟦{ aig := (mkFullAdderCarry aig { lhs := lhs.getRef curr h✝, rhs := rhs.getRef curr h✝, cin := cin }).aig,
        ref := (mkFullAdderCarry aig { lhs := lhs.getRef curr h✝, rhs := rhs.getRef curr h✝, cin := cin }).ref },
      assign⟧ =
    BitVec.carry (curr + 1) lhsExpr rhsExpr
      ⟦{ aig := (mkFullAdderCarry aig { lhs := lhs.getRef curr h✝, rhs := rhs.getRef curr h✝, cin := cin }).aig,
          ref := { gate := origCin.gate, hgate := ⋯ } },
        assign⟧