\hypertarget{structFSMC__Bank1__TypeDef}{}\doxysection{F\+S\+M\+C\+\_\+\+Bank1\+\_\+\+Type\+Def Struct Reference}
\label{structFSMC__Bank1__TypeDef}\index{FSMC\_Bank1\_TypeDef@{FSMC\_Bank1\_TypeDef}}


Flexible Static Memory Controller.  




{\ttfamily \#include $<$stm32f407xx.\+h$>$}

\doxysubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{core__sc300_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{structFSMC__Bank1__TypeDef_a6d3aefd66a99e71ae4a22444a507a720}{B\+T\+CR}} \mbox{[}8\mbox{]}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
Flexible Static Memory Controller. 

\doxysubsection{Member Data Documentation}
\mbox{\Hypertarget{structFSMC__Bank1__TypeDef_a6d3aefd66a99e71ae4a22444a507a720}\label{structFSMC__Bank1__TypeDef_a6d3aefd66a99e71ae4a22444a507a720}} 
\index{FSMC\_Bank1\_TypeDef@{FSMC\_Bank1\_TypeDef}!BTCR@{BTCR}}
\index{BTCR@{BTCR}!FSMC\_Bank1\_TypeDef@{FSMC\_Bank1\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BTCR}{BTCR}}
{\footnotesize\ttfamily \mbox{\hyperlink{core__sc300_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t F\+S\+M\+C\+\_\+\+Bank1\+\_\+\+Type\+Def\+::\+B\+T\+CR\mbox{[}8\mbox{]}}

N\+O\+R/\+P\+S\+R\+AM chip-\/select control register(\+B\+C\+R) and chip-\/select timing register(\+B\+T\+R), Address offset\+: 0x00-\/1C 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
hal/stm32f407/cmsis/\mbox{\hyperlink{stm32f407xx_8h}{stm32f407xx.\+h}}\end{DoxyCompactItemize}
