\hypertarget{struct_r_c_c___p_l_l_s_a_i_init_type_def}{}\section{R\+C\+C\+\_\+\+P\+L\+L\+S\+A\+I\+Init\+Type\+Def Struct Reference}
\label{struct_r_c_c___p_l_l_s_a_i_init_type_def}\index{R\+C\+C\+\_\+\+P\+L\+L\+S\+A\+I\+Init\+Type\+Def@{R\+C\+C\+\_\+\+P\+L\+L\+S\+A\+I\+Init\+Type\+Def}}


P\+L\+L\+S\+AI Clock structure definition.  




{\ttfamily \#include $<$stm32f4xx\+\_\+hal\+\_\+rcc\+\_\+ex.\+h$>$}

\subsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
uint32\+\_\+t \hyperlink{struct_r_c_c___p_l_l_s_a_i_init_type_def_a8cf099e8f1fcd2aae663b7dec31af622}{P\+L\+L\+S\+A\+IM}
\item 
uint32\+\_\+t \hyperlink{struct_r_c_c___p_l_l_s_a_i_init_type_def_a7ec92e831b8ca06243fce02f46b76807}{P\+L\+L\+S\+A\+IN}
\item 
uint32\+\_\+t \hyperlink{struct_r_c_c___p_l_l_s_a_i_init_type_def_a8cfa7d387fc9b118e9066a63d2b845bf}{P\+L\+L\+S\+A\+IP}
\item 
uint32\+\_\+t \hyperlink{struct_r_c_c___p_l_l_s_a_i_init_type_def_addd252bc81b5eb646803cf3e0941499c}{P\+L\+L\+S\+A\+IQ}
\end{DoxyCompactItemize}


\subsection{Detailed Description}
P\+L\+L\+S\+AI Clock structure definition. 

\subsection{Member Data Documentation}
\index{R\+C\+C\+\_\+\+P\+L\+L\+S\+A\+I\+Init\+Type\+Def@{R\+C\+C\+\_\+\+P\+L\+L\+S\+A\+I\+Init\+Type\+Def}!P\+L\+L\+S\+A\+IM@{P\+L\+L\+S\+A\+IM}}
\index{P\+L\+L\+S\+A\+IM@{P\+L\+L\+S\+A\+IM}!R\+C\+C\+\_\+\+P\+L\+L\+S\+A\+I\+Init\+Type\+Def@{R\+C\+C\+\_\+\+P\+L\+L\+S\+A\+I\+Init\+Type\+Def}}
\subsubsection[{\texorpdfstring{P\+L\+L\+S\+A\+IM}{PLLSAIM}}]{\setlength{\rightskip}{0pt plus 5cm}uint32\+\_\+t R\+C\+C\+\_\+\+P\+L\+L\+S\+A\+I\+Init\+Type\+Def\+::\+P\+L\+L\+S\+A\+IM}\hypertarget{struct_r_c_c___p_l_l_s_a_i_init_type_def_a8cf099e8f1fcd2aae663b7dec31af622}{}\label{struct_r_c_c___p_l_l_s_a_i_init_type_def_a8cf099e8f1fcd2aae663b7dec31af622}
Spcifies division factor for P\+LL V\+CO input clock. This parameter must be a number between Min\+\_\+\+Data = 2 and Max\+\_\+\+Data = 63 \index{R\+C\+C\+\_\+\+P\+L\+L\+S\+A\+I\+Init\+Type\+Def@{R\+C\+C\+\_\+\+P\+L\+L\+S\+A\+I\+Init\+Type\+Def}!P\+L\+L\+S\+A\+IN@{P\+L\+L\+S\+A\+IN}}
\index{P\+L\+L\+S\+A\+IN@{P\+L\+L\+S\+A\+IN}!R\+C\+C\+\_\+\+P\+L\+L\+S\+A\+I\+Init\+Type\+Def@{R\+C\+C\+\_\+\+P\+L\+L\+S\+A\+I\+Init\+Type\+Def}}
\subsubsection[{\texorpdfstring{P\+L\+L\+S\+A\+IN}{PLLSAIN}}]{\setlength{\rightskip}{0pt plus 5cm}uint32\+\_\+t R\+C\+C\+\_\+\+P\+L\+L\+S\+A\+I\+Init\+Type\+Def\+::\+P\+L\+L\+S\+A\+IN}\hypertarget{struct_r_c_c___p_l_l_s_a_i_init_type_def_a7ec92e831b8ca06243fce02f46b76807}{}\label{struct_r_c_c___p_l_l_s_a_i_init_type_def_a7ec92e831b8ca06243fce02f46b76807}
Specifies the multiplication factor for P\+L\+L\+I2S V\+CO output clock. This parameter must be a number between Min\+\_\+\+Data = 192 and Max\+\_\+\+Data = 432 \index{R\+C\+C\+\_\+\+P\+L\+L\+S\+A\+I\+Init\+Type\+Def@{R\+C\+C\+\_\+\+P\+L\+L\+S\+A\+I\+Init\+Type\+Def}!P\+L\+L\+S\+A\+IP@{P\+L\+L\+S\+A\+IP}}
\index{P\+L\+L\+S\+A\+IP@{P\+L\+L\+S\+A\+IP}!R\+C\+C\+\_\+\+P\+L\+L\+S\+A\+I\+Init\+Type\+Def@{R\+C\+C\+\_\+\+P\+L\+L\+S\+A\+I\+Init\+Type\+Def}}
\subsubsection[{\texorpdfstring{P\+L\+L\+S\+A\+IP}{PLLSAIP}}]{\setlength{\rightskip}{0pt plus 5cm}uint32\+\_\+t R\+C\+C\+\_\+\+P\+L\+L\+S\+A\+I\+Init\+Type\+Def\+::\+P\+L\+L\+S\+A\+IP}\hypertarget{struct_r_c_c___p_l_l_s_a_i_init_type_def_a8cfa7d387fc9b118e9066a63d2b845bf}{}\label{struct_r_c_c___p_l_l_s_a_i_init_type_def_a8cfa7d387fc9b118e9066a63d2b845bf}
Specifies division factor for O\+TG FS, S\+D\+IO and R\+NG clocks. This parameter must be a value of \hyperlink{group___r_c_c_ex___p_l_l_s_a_i_p___clock___divider}{R\+CC P\+L\+L\+S\+A\+IP Clock Divider} \index{R\+C\+C\+\_\+\+P\+L\+L\+S\+A\+I\+Init\+Type\+Def@{R\+C\+C\+\_\+\+P\+L\+L\+S\+A\+I\+Init\+Type\+Def}!P\+L\+L\+S\+A\+IQ@{P\+L\+L\+S\+A\+IQ}}
\index{P\+L\+L\+S\+A\+IQ@{P\+L\+L\+S\+A\+IQ}!R\+C\+C\+\_\+\+P\+L\+L\+S\+A\+I\+Init\+Type\+Def@{R\+C\+C\+\_\+\+P\+L\+L\+S\+A\+I\+Init\+Type\+Def}}
\subsubsection[{\texorpdfstring{P\+L\+L\+S\+A\+IQ}{PLLSAIQ}}]{\setlength{\rightskip}{0pt plus 5cm}uint32\+\_\+t R\+C\+C\+\_\+\+P\+L\+L\+S\+A\+I\+Init\+Type\+Def\+::\+P\+L\+L\+S\+A\+IQ}\hypertarget{struct_r_c_c___p_l_l_s_a_i_init_type_def_addd252bc81b5eb646803cf3e0941499c}{}\label{struct_r_c_c___p_l_l_s_a_i_init_type_def_addd252bc81b5eb646803cf3e0941499c}
Specifies the division factor for S\+AI clock. This parameter must be a number between Min\+\_\+\+Data = 2 and Max\+\_\+\+Data = 15. This parameter will be used only when P\+L\+L\+S\+AI is selected as Clock Source S\+AI 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
Dynamixel-\/\+M\+X106/mbed/\+T\+A\+R\+G\+E\+T\+\_\+\+N\+U\+C\+L\+E\+O\+\_\+\+F446\+R\+E/\hyperlink{stm32f4xx__hal__rcc__ex_8h}{stm32f4xx\+\_\+hal\+\_\+rcc\+\_\+ex.\+h}\end{DoxyCompactItemize}
