<filename>doc/SoC-RISCV.tex<gh_stars>1-10
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\title{System on Chip with RISCV}
\author{QueenField}
\date{}

\begin{document}
\maketitle

\section{1. INTRODUCTION}\label{introduction}

\subsection{1.1. OPEN SOURCE PHILOSOPHY}\label{open-source-philosophy}

\textbf{For Windows Users!}

\begin{enumerate}
\def\labelenumi{\arabic{enumi}.}
\item
  Settings → Apps → Apps \& features → Related settings, Programs and
  Features → Turn Windows features on or off → Windows Subsystem for
  Linux
\item
  Microsoft Store → INSTALL UBUNTU
\end{enumerate}

type:

\begin{verbatim}
sudo apt update
sudo apt upgrade
\end{verbatim}

\subsubsection{1.2.1. Open Source Hardware}\label{open-source-hardware}

\paragraph{1.2.1.1. MSP430 Processing
Unit}\label{msp430-processing-unit}

\paragraph{1.2.1.2. OpenRISC Processing
Unit}\label{openrisc-processing-unit}

\paragraph{1.2.1.3. RISC-V Processing
Unit}\label{risc-v-processing-unit}

\subsubsection{1.2.2. Open Source Software}\label{open-source-software}

\paragraph{1.2.2.1. MSP430 GNU Compiler
Collection}\label{msp430-gnu-compiler-collection}

\paragraph{1.2.2.2. OpenRISC GNU Compiler
Collection}\label{openrisc-gnu-compiler-collection}

\paragraph{1.2.2.3. RISC-V GNU Compiler
Collection}\label{risc-v-gnu-compiler-collection}

\subsection{1.2. RISC-V ISA}\label{risc-v-isa}

\subsubsection{1.2.1. ISA Bases}\label{isa-bases}

\paragraph{1.2.2.1. RISC-V 32}\label{risc-v-32}

\paragraph{1.2.2.2. RISC-V 64}\label{risc-v-64}

\paragraph{1.2.2.3. RISC-V 128}\label{risc-v-128}

\subsubsection{1.2.2. ISA Extensions}\label{isa-extensions}

\paragraph{1.2.2.1. Base Integer Instruction
Set}\label{base-integer-instruction-set}

\textbf{RV32I : Base Integer Instruction Set (32 bit)}

\begin{longtable}[]{@{}lcccccc@{}}
\toprule
RV32I & 31:25 & 24:20 & 19:15 & 14:12 & 11:7 & 6:0\tabularnewline
\midrule
\endhead
LUI RD, IMM & IIIIIII & IIIII & IIIII & III & RD4:0 &
0110111\tabularnewline
AUPIC RD, IMM & IIIIIII & IIIII & IIIII & III & RD4:0 &
0010111\tabularnewline
JAL RD, IMM & IIIIIII & IIIII & IIIII & III & RD4:0 &
1101111\tabularnewline
JALR RD,RS1,IMM & IIIIIII & IIIII & RS14:0 & 000 & RD4:0 &
1101111\tabularnewline
BEQ RS1,RS2,IMM & IIIIIII & RS24:0 & RS14:0 & 000 & IIIII &
1100011\tabularnewline
BNE RS1,RS2,IMM & IIIIIII & RS24:0 & RS14:0 & 001 & IIIII &
1100011\tabularnewline
BLT RS1,RS2,IMM & IIIIIII & RS24:0 & RS14:0 & 100 & IIIII &
1100011\tabularnewline
BGE RS1,RS2,IMM & IIIIIII & RS24:0 & RS14:0 & 101 & IIIII &
1100011\tabularnewline
BLTU RS1,RS2,IMM & IIIIIII & RS24:0 & RS14:0 & 110 & IIIII &
1100011\tabularnewline
BGEU RS1,RS2,IMM & IIIIIII & RS24:0 & RS14:0 & 111 & IIIII &
1100011\tabularnewline
LB RD, RS1 & IIIIIII & IIIII & RS14:0 & 000 & RD4:0 &
0000011\tabularnewline
LH RD, RS1 & IIIIIII & IIIII & RS14:0 & 001 & RD4:0 &
0000011\tabularnewline
LW RD, RS1 & IIIIIII & IIIII & RS14:0 & 010 & RD4:0 &
0000011\tabularnewline
LBU RD, RS1 & IIIIIII & IIIII & RS14:0 & 100 & RD4:0 &
0000011\tabularnewline
LHU RD, RS1 & IIIIIII & IIIII & RS14:0 & 101 & RD4:0 &
0000011\tabularnewline
SB RS2,RS1 & IIIIIII & RS24:0 & RS14:0 & 000 & IIIII &
0100011\tabularnewline
SH RS2,RS1 & IIIIIII & RS24:0 & RS14:0 & 001 & IIIII &
0100011\tabularnewline
SW RS2,RS1 & IIIIIII & RS24:0 & RS14:0 & 010 & IIIII &
0100011\tabularnewline
ADDI RD,RS1,IMM & IIIIIII & IIIII & RS14:0 & 000 & RD4:0 &
0010011\tabularnewline
SLTI RD,RS1,IMM & IIIIIII & IIIII & RS14:0 & 010 & RD4:0 &
0010011\tabularnewline
SLTIU RD,RS1,IMM & IIIIIII & IIIII & RS14:0 & 011 & RD4:0 &
0010011\tabularnewline
XORI RD,RS1,IMM & IIIIIII & IIIII & RS14:0 & 100 & RD4:0 &
0010011\tabularnewline
ORI RD,RS1,IMM & IIIIIII & IIIII & RS14:0 & 110 & RD4:0 &
0010011\tabularnewline
ANDI RD,RS1,IMM & IIIIIII & IIIII & RS14:0 & 111 & RD4:0 &
0010011\tabularnewline
SLLI RD,RS1,IMM & 0000000 & IIII & RS14:0 & 001 & RD4:0 &
0010011\tabularnewline
SRLI RD,RS1,IMM & 0000000 & IIII & RS14:0 & 101 & RD4:0 &
0010011\tabularnewline
SRAI RD,RS1,IMM & 0100000 & IIII & RS14:0 & 101 & RD4:0 &
0010011\tabularnewline
ADD RD,RS1,RS2 & 0000000 & RS24:0 & RS14:0 & 000 & RD4:0 &
0110011\tabularnewline
SUB RD,RS1,RS2 & 0100000 & RS24:0 & RS14:0 & 000 & RD4:0 &
0110011\tabularnewline
SLL RD,RS1,RS2 & 0000000 & RS24:0 & RS14:0 & 001 & RD4:0 &
0110011\tabularnewline
SLT RD,RS1,RS2 & 0000000 & RS24:0 & RS14:0 & 010 & RD4:0 &
0110011\tabularnewline
SLTU RD,RS1,RS2 & 0000000 & RS24:0 & RS14:0 & 011 & RD4:0 &
0110011\tabularnewline
XOR RD,RS1,RS2 & 0000000 & RS24:0 & RS14:0 & 100 & RD4:0 &
0110011\tabularnewline
SRL RD,RS1,RS2 & 0000000 & RS24:0 & RS14:0 & 101 & RD4:0 &
0110011\tabularnewline
SRA RD,RS1,RS2 & 0100000 & RS24:0 & RS14:0 & 101 & RD4:0 &
0110011\tabularnewline
OR RD,RS1,RS2 & 0000000 & RS24:0 & RS14:0 & 110 & RD4:0 &
0110011\tabularnewline
AND RD,RS1,RS2 & 0000000 & RS24:0 & RS14:0 & 111 & RD4:0 &
0110011\tabularnewline
FENCE PRED,SUCC & 0000PPP & PSSSS & 00000 & 000 & 00000 &
0001111\tabularnewline
FENCE.I & 0000P00 & 00000 & 00000 & 001 & 00000 & 0001111\tabularnewline
\bottomrule
\end{longtable}

\textbf{RV64I : Base Integer Instruction Set (64 bit)}

\begin{longtable}[]{@{}lcccccc@{}}
\toprule
RV64I & 31:25 & 24:20 & 19:15 & 14:12 & 11:7 & 6:0\tabularnewline
\midrule
\endhead
LWU RD, RS1 & IIIIIII & IIIII & RS14:0 & 110 & RD4:0 &
0000011\tabularnewline
LD RD, RS1 & IIIIIII & IIIII & RS14:0 & 011 & RD4:0 &
0000011\tabularnewline
SD RD, RS1,RS2 & IIIIIII & RS24:0 & RS14:0 & 011 & IIIII &
0000011\tabularnewline
SLLI RD, RS1,IMM & 0000000 & IIIII & RS14:0 & 001 & RD4:0 &
0010011\tabularnewline
SRLI RD, RS1,IMM & 0000000 & IIIII & RS14:0 & 001 & RD4:0 &
0010011\tabularnewline
SRAI RD, RS1,IMM & 0100000 & IIIII & RS14:0 & 001 & RD4:0 &
0010011\tabularnewline
ADDIW RD, RS1 & IIIIIII & IIIII & RS14:0 & 000 & RD4:0 &
0011011\tabularnewline
SLLIW RD, RS1 & 0000000 & IIIII & RS14:0 & 001 & RD4:0 &
0011011\tabularnewline
SRLIW RD, RS1 & 0000000 & IIIII & RS14:0 & 101 & RD4:0 &
0011011\tabularnewline
SRAIW RD, RS1 & 0100000 & IIIII & RS14:0 & 101 & RD4:0 &
0011011\tabularnewline
ADDW RD, RS1,RS2 & 0000000 & RS24:0 & RS14:0 & 000 & RD4:0 &
0111011\tabularnewline
SUBW RD, RS1,RS2 & 0100000 & RS24:0 & RS14:0 & 000 & RD4:0 &
0111011\tabularnewline
SLIW RD, RS1,RS2 & 0000000 & RS24:0 & RS14:0 & 001 & RD4:0 &
0111011\tabularnewline
SRLW RD, RS1,RS2 & 0000000 & RS24:0 & RS14:0 & 101 & RD4:0 &
0111011\tabularnewline
SRAW RD, RS1,RS2 & 0100000 & RS24:0 & RS14:0 & 101 & RD4:0 &
0111011\tabularnewline
\bottomrule
\end{longtable}

\paragraph{1.2.2.2. Standard Extension for Integer Multiply and
Divide}\label{standard-extension-for-integer-multiply-and-divide}

\textbf{RV32M : Standard Extension for Integer Multiply and Divide (32
bit)}

\begin{longtable}[]{@{}lcccccc@{}}
\toprule
RV32M & 31:25 & 24:20 & 19:15 & 14:12 & 11:7 & 6:0\tabularnewline
\midrule
\endhead
MUL RD,RS1,RS2 & 0000001 & RS24:0 & RS14:0 & 000 & RD4:0 &
0110011\tabularnewline
MULH RD,RS1,RS2 & 0000001 & RS24:0 & RS14:0 & 001 & RD4:0 &
0110011\tabularnewline
MULHSU RD,RS1,RS2 & 0000001 & RS24:0 & RS14:0 & 010 & RD4:0 &
0110011\tabularnewline
MULHU RD,RS1,RS2 & 0000001 & RS24:0 & RS14:0 & 011 & RD4:0 &
0110011\tabularnewline
DIV RD,RS1,RS2 & 0000001 & RS24:0 & RS14:0 & 100 & RD4:0 &
0110011\tabularnewline
DIVU RD,RS1,RS2 & 0000001 & RS24:0 & RS14:0 & 101 & RD4:0 &
0110011\tabularnewline
REM RD,RS1,RS2 & 0000001 & RS24:0 & RS14:0 & 110 & RD4:0 &
0110011\tabularnewline
REMU RD,RS1,RS2 & 0000001 & RS24:0 & RS14:0 & 111 & RD4:0 &
0110011\tabularnewline
\bottomrule
\end{longtable}

\textbf{Standard Extension for Integer Multiply and Divide (64 bit)}

\begin{longtable}[]{@{}lcccccc@{}}
\toprule
RV64M & 31:25 & 24:20 & 19:15 & 14:12 & 11:7 & 6:0\tabularnewline
\midrule
\endhead
MULW RD,RS1,RS2 & 0000001 & RS24:0 & RS14:0 & 000 & RD4:0 &
0111011\tabularnewline
DIVW RD,RS1,RS2 & 0000001 & RS24:0 & RS14:0 & 100 & RD4:0 &
0111011\tabularnewline
DIVUW RD,RS1,RS2 & 0000001 & RS24:0 & RS14:0 & 101 & RD4:0 &
0111011\tabularnewline
REMW RD,RS1,RS2 & 0000001 & RS24:0 & RS14:0 & 110 & RD4:0 &
0111011\tabularnewline
REMUW RD,RS1,RS2 & 0000001 & RS24:0 & RS14:0 & 111 & RD4:0 &
0111011\tabularnewline
\bottomrule
\end{longtable}

\paragraph{1.2.2.3. Standard Extension for Atomic
Instructions}\label{standard-extension-for-atomic-instructions}

\textbf{RV32A : Standard Extension for Atomic Instructions (32 bit)}

\begin{longtable}[]{@{}lcccccc@{}}
\toprule
RV32A & 31:25 & 24:20 & 19:15 & 14:12 & 11:7 & 6:0\tabularnewline
\midrule
\endhead
LR.W AQRL,RD,RS1 & 00010AQRL & 00000 & RS14:0 & 010 & RD4:0 &
0101111\tabularnewline
SC.W AQRL,RD,RS2,RS1 & 00011AQRL & RS24:0 & RS14:0 & 010 & RD4:0 &
0101111\tabularnewline
AMOSWAP.W AQRL,RD,RS2,RS1 & 00001AQRL & RS24:0 & RS14:0 & 010 & RD4:0 &
0101111\tabularnewline
AMOSADD.W AQRL,RD,RS2,RS1 & 00000AQRL & RS24:0 & RS14:0 & 010 & RD4:0 &
0101111\tabularnewline
AMOSXOR.W AQRL,RD,RS2,RS1 & 00100AQRL & RS24:0 & RS14:0 & 010 & RD4:0 &
0101111\tabularnewline
AMOOR.W AQRL,RD,RS2,RS1 & 01000AQRL & RS24:0 & RS14:0 & 010 & RD4:0 &
0101111\tabularnewline
AMOAMD.W AQRL,RD,RS2,RS1 & 01100AQRL & RS24:0 & RS14:0 & 010 & RD4:0 &
0101111\tabularnewline
AMOMIN.W AQRL,RD,RS2,RS1 & 10000AQRL & RS24:0 & RS14:0 & 010 & RD4:0 &
0101111\tabularnewline
AMOMAX.W AQRL,RD,RS2,RS1 & 10100AQRL & RS24:0 & RS14:0 & 010 & RD4:0 &
0101111\tabularnewline
AMOMINU.W AQRL,RD,RS2,RS1 & 11000AQRL & RS24:0 & RS14:0 & 010 & RD4:0 &
0101111\tabularnewline
AMOMAXU.W AQRL,RD,RS2,RS1 & 11100AQRL & RS24:0 & RS14:0 & 010 & RD4:0 &
0101111\tabularnewline
\bottomrule
\end{longtable}

\textbf{RV64A : Standard Extension for Atomic Instructions (64 bit)}

\begin{longtable}[]{@{}lcccccc@{}}
\toprule
RV64A & 31:25 & 24:20 & 19:15 & 14:12 & 11:7 & 6:0\tabularnewline
\midrule
\endhead
LR.D AQRL,RD,RS1 & 00010AQRL & 00000 & RS14:0 & 011 & RD4:0 &
0101111\tabularnewline
SC.D AQRL,RD,RS2,RS1 & 00011AQRL & RS24:0 & RS14:0 & 011 & RD4:0 &
0101111\tabularnewline
AMOSWAP.D AQRL,RD,RS2,RS1 & 00001AQRL & RS24:0 & RS14:0 & 011 & RD4:0 &
0101111\tabularnewline
AMOSADD.D AQRL,RD,RS2,RS1 & 00000AQRL & RS24:0 & RS14:0 & 011 & RD4:0 &
0101111\tabularnewline
AMOSXOR.D AQRL,RD,RS2,RS1 & 00100AQRL & RS24:0 & RS14:0 & 011 & RD4:0 &
0101111\tabularnewline
AMOOR.D AQRL,RD,RS2,RS1 & 01000AQRL & RS24:0 & RS14:0 & 011 & RD4:0 &
0101111\tabularnewline
AMOAMD.D AQRL,RD,RS2,RS1 & 01100AQRL & RS24:0 & RS14:0 & 011 & RD4:0 &
0101111\tabularnewline
AMOMIN.D AQRL,RD,RS2,RS1 & 10000AQRL & RS24:0 & RS14:0 & 011 & RD4:0 &
0101111\tabularnewline
AMOMAX.D AQRL,RD,RS2,RS1 & 10100AQRL & RS24:0 & RS14:0 & 011 & RD4:0 &
0101111\tabularnewline
AMOMINU.D AQRL,RD,RS2,RS1 & 11000AQRL & RS24:0 & RS14:0 & 011 & RD4:0 &
0101111\tabularnewline
AMOMAXU.D AQRL,RD,RS2,RS1 & 11100AQRL & RS24:0 & RS14:0 & 011 & RD4:0 &
0101111\tabularnewline
\bottomrule
\end{longtable}

\paragraph{1.2.2.4. Standard Extension for Single-Precision
Floating-Point}\label{standard-extension-for-single-precision-floating-point}

\textbf{RV32F : Standard Extension for Single-Precision Floating-Point
(32 bit)}

\begin{longtable}[]{@{}lcccccc@{}}
\toprule
RV32F & 31:25 & 24:20 & 19:15 & 14:12 & 11:7 & 6:0\tabularnewline
\midrule
\endhead
FLW FRD,RS1 & IIIIIII & IIIII & FRS1 & 010 & FRD &
0000111\tabularnewline
FSW FRS2,RS1 & IIIIIII & FRS2 & FRS1 & 010 & IIIII &
0100111\tabularnewline
FMADD.S RM,FRD,FRS1,FRS2,FRS3 & FRS3\_00 & FRS2 & FRS1 & RM & FRD &
1000011\tabularnewline
FMSUB.S RM,FRD,FRS1,FRS2,FRS3 & FRS3\_00 & FRS2 & FRS1 & RM & FRD &
1000111\tabularnewline
FNMSUB.S RM,FRD,FRS1,FRS2,FRS3 & FRS3\_00 & FRS2 & FRS1 & RM & FRD &
1001011\tabularnewline
FNMADD.S RM,FRD,FRS1,FRS2,FRS3 & FRS3\_00 & FRS2 & FRS1 & RM & FRD &
1001111\tabularnewline
FADD.S RM,FRD,FRS1,FRS2,FRS3 & 0000000 & FRS2 & FRS1 & RM & FRD &
1010011\tabularnewline
FSUB.S RM,FRD,FRS1,FRS2,FRS3 & 0000100 & FRS2 & FRS1 & RM & FRD &
1010011\tabularnewline
FMUL.S RM,FRD,FRS1,FRS2,FRS3 & 0001000 & FRS2 & FRS1 & RM & FRD &
1010011\tabularnewline
FDIV.S RM,FRD,FRS1,FRS2,FRS3 & 0001100 & FRS2 & FRS1 & RM & FRD &
1010011\tabularnewline
FSGNJ.S FRD,FRS1,FRS2 & 0010000 & FRS2 & FRS1 & 000 & FRD &
1010011\tabularnewline
FSGNJN.S FRD,FRS1,FRS2 & 0010000 & FRS2 & FRS1 & 001 & FRD &
1010011\tabularnewline
FSGNJX.S FRD,FRS1,FRS2 & 0010000 & FRS2 & FRS1 & 010 & FRD &
1010011\tabularnewline
FMIN.S FRD,FRS1,FRS2 & 0010100 & FRS2 & FRS1 & 000 & FRD &
1010011\tabularnewline
FMAX.S FRD,FRS1,FRS2 & 0010100 & FRS2 & FRS1 & 001 & FRD &
1010011\tabularnewline
FSQRT.S FRD,FRS1,FRS2 & 0101100 & 00000 & FRS1 & RM & FRD &
1010011\tabularnewline
FLE.S FRD,FRS1,FRS2 & 1010000 & FRS2 & FRS1 & 000 & FRD &
1010011\tabularnewline
FLT.S FRD,FRS1,FRS2 & 1010000 & FRS2 & FRS1 & 001 & FRD &
1010011\tabularnewline
FEQ.S FRD,FRS1,FRS2 & 1010000 & FRS2 & FRS1 & 010 & FRD &
1010011\tabularnewline
FCVT.W.S RM,RD,FRS1 & 1100000 & 00000 & FRS1 & RM & FRD &
1010011\tabularnewline
FCVT.WU.S RM,RD,FRS1 & 1100000 & 00010 & FRS1 & RM & FRD &
1010011\tabularnewline
FCVT.S.W RM,RD,FRS1 & 1101000 & 00000 & FRS1 & RM & FRD &
1010011\tabularnewline
FCVT.S.WU RM,RD,FRS1 & 1101000 & 00010 & FRS1 & RM & FRD &
1010011\tabularnewline
FMV.X.S RD,FRS1 & 1110000 & 00000 & FRS1 & 000 & RD &
1010011\tabularnewline
FCLASS.S RD,FRS1 & 1110000 & 00000 & FRS1 & 001 & RD &
1010011\tabularnewline
FMV.S.X RD,FRS1 & 1111000 & 00000 & RS1 & 000 & FRD &
1010011\tabularnewline
\bottomrule
\end{longtable}

\textbf{RV64F : Standard Extension for Single-Precision Floating-Point
(64 bit)}

\begin{longtable}[]{@{}lcccccc@{}}
\toprule
RV64F & 31:25 & 24:20 & 19:15 & 14:12 & 11:7 & 6:0\tabularnewline
\midrule
\endhead
FCVT.L.S RM,RD,FRS1 & 1100000 & 00010 & FRS1 & RM & FRD &
1010011\tabularnewline
FCVT.LU.S RM,RD,FRS1 & 1100000 & 00011 & FRS1 & RM & FRD &
1010011\tabularnewline
FCVT.S.L RM,RD,FRS1 & 1101000 & 00010 & FRS1 & RM & FRD &
1010011\tabularnewline
FCVT.S.LU RM,RD,FRS1 & 1101000 & 00011 & FRS1 & RM & FRD &
1010011\tabularnewline
\bottomrule
\end{longtable}

\paragraph{1.2.2.5. Standard Extension for Double-Precision
Floating-Point}\label{standard-extension-for-double-precision-floating-point}

\textbf{RV32D : Standard Extension for Double-Precision Floating-Point
(32 bit)}

\begin{longtable}[]{@{}lcccccc@{}}
\toprule
RV32F & 31:25 & 24:20 & 19:15 & 14:12 & 11:7 & 6:0\tabularnewline
\midrule
\endhead
FLW FRD,RS1 & IIIIIII & IIIII & FRS1 & 011 & FRD &
0000111\tabularnewline
FSW FRS2,RS1 & IIIIIII & FRS2 & FRS1 & 011 & IIIII &
0100111\tabularnewline
FMADD.D RM,FRD,FRS1,FRS2,FRS3 & FRS3\_01 & FRS2 & FRS1 & RM & FRD &
1000011\tabularnewline
FMSUB.D RM,FRD,FRS1,FRS2,FRS3 & FRS3\_01 & FRS2 & FRS1 & RM & FRD &
1000111\tabularnewline
FNMSUB.D RM,FRD,FRS1,FRS2,FRS3 & FRS3\_01 & FRS2 & FRS1 & RM & FRD &
1001011\tabularnewline
FNMADD.D RM,FRD,FRS1,FRS2,FRS3 & FRS3\_01 & FRS2 & FRS1 & RM & FRD &
1001111\tabularnewline
FADD.D RM,FRD,FRS1,FRS2,FRS3 & 0000001 & FRS2 & FRS1 & RM & FRD &
1010011\tabularnewline
FSUB.D RM,FRD,FRS1,FRS2,FRS3 & 0000101 & FRS2 & FRS1 & RM & FRD &
1010011\tabularnewline
FMUL.D RM,FRD,FRS1,FRS2,FRS3 & 0001001 & FRS2 & FRS1 & RM & FRD &
1010011\tabularnewline
FDIV.D RM,FRD,FRS1,FRS2,FRS3 & 0001101 & FRS2 & FRS1 & RM & FRD &
1010011\tabularnewline
FSGNJ.D FRD,FRS1,FRS2 & 0010001 & FRS2 & FRS1 & 000 & FRD &
1010011\tabularnewline
FSGNJN.D FRD,FRS1,FRS2 & 0010001 & FRS2 & FRS1 & 001 & FRD &
1010011\tabularnewline
FSGNJX.D FRD,FRS1,FRS2 & 0010001 & FRS2 & FRS1 & 010 & FRD &
1010011\tabularnewline
FMIN.D FRD,FRS1,FRS2 & 0010101 & FRS2 & FRS1 & 000 & FRD &
1010011\tabularnewline
FMAX.D FRD,FRS1,FRS2 & 0010101 & FRS2 & FRS1 & 001 & FRD &
1010011\tabularnewline
FSQRT.D FRD,FRS1,FRS2 & 0101101 & 00000 & FRS1 & RM & FRD &
1010011\tabularnewline
FLE.D FRD,FRS1,FRS2 & 1010001 & FRS2 & FRS1 & 000 & FRD &
1010011\tabularnewline
FLT.D FRD,FRS1,FRS2 & 1010001 & FRS2 & FRS1 & 001 & FRD &
1010011\tabularnewline
FEQ.D FRD,FRS1,FRS2 & 1010001 & FRS2 & FRS1 & 010 & FRD &
1010011\tabularnewline
FCVT.W.D RM,RD,FRS1 & 1100001 & 00000 & FRS1 & RM & FRD &
1010011\tabularnewline
FCVT.WU.D RM,RD,FRS1 & 1100001 & 00010 & FRS1 & RM & FRD &
1010011\tabularnewline
FCVT.D.W RM,RD,FRS1 & 1101001 & 00000 & FRS1 & RM & FRD &
1010011\tabularnewline
FCVT.D.WU RM,RD,FRS1 & 1101001 & 00010 & FRS1 & RM & FRD &
1010011\tabularnewline
FCLASS.D RD,FRS1 & 1110001 & 00000 & FRS1 & 001 & RD &
1010011\tabularnewline
\bottomrule
\end{longtable}

\textbf{RV64D : Standard Extension for Double-Precision Floating-Point
(64 bit)}

\begin{longtable}[]{@{}lcccccc@{}}
\toprule
RV64D & 31:25 & 24:20 & 19:15 & 14:12 & 11:7 & 6:0\tabularnewline
\midrule
\endhead
FCVT.L.D RM,RD,FRS1 & 1100001 & 00010 & FRS1 & RM & FRD &
1010011\tabularnewline
FCVT.LU.D RM,RD,FRS1 & 1100001 & 00011 & FRS1 & RM & FRD &
1010011\tabularnewline
FCVT.D.L RM,RD,FRS1 & 1101001 & 00010 & FRS1 & RM & FRD &
1010011\tabularnewline
FCVT.D.LU RM,RD,FRS1 & 1101001 & 00011 & FRS1 & RM & FRD &
1010011\tabularnewline
FMV.X.D RD,FRS1 & 1110001 & 00000 & FRS1 & 000 & RD &
1010011\tabularnewline
FMV.D.X RD,FRS1 & 1111001 & 00000 & RS1 & 000 & FRD &
1010011\tabularnewline
\bottomrule
\end{longtable}

\subsubsection{1.2.3. ISA Modes}\label{isa-modes}

\paragraph{1.2.3.1. RISC-V User}\label{risc-v-user}

\paragraph{1.2.3.2. RISC-V Supervisor}\label{risc-v-supervisor}

\paragraph{1.2.3.3. RISC-V Hypervisor}\label{risc-v-hypervisor}

\paragraph{1.2.3.4. RISC-V Machine}\label{risc-v-machine}

\section{2. PROJECTS}\label{projects}

\subsection{2.1. CORE-RISCV}\label{core-riscv}

\subsubsection{2.1.1. Functionality}\label{functionality}

\paragraph{2.1.1.1. Organization}\label{organization}

The CORE-RISCV is based on the Harvard architecture, which is a computer
architecture with separate storage and signal pathways for instructions
and data. The implementation is heavily modular, with each particular
functional block of the design being contained within its own HDL module
or modules. The RISCV implementation was developed in order to provide a
better platform for processor component development than previous
implementations.

\begin{longtable}[]{@{}ll@{}}
\toprule
Core & Module description\tabularnewline
\midrule
\endhead
\texttt{riscv\_core} & Core\tabularnewline
\texttt{...riscv\_if} & Instruction Fetch\tabularnewline
\texttt{...riscv\_id} & Instruction Decoder\tabularnewline
\texttt{...riscv\_execution} & Execution Unit\tabularnewline
\texttt{.....riscv\_alu} & Arithmetic \& Logical Unit\tabularnewline
\texttt{.....riscv\_lsu} & Load Store Unit\tabularnewline
\texttt{.....riscv\_bu} & Branch Unit\tabularnewline
\texttt{.....riscv\_mul} & Multiplier Unit\tabularnewline
\texttt{.....riscv\_div} & Division Unit\tabularnewline
\texttt{...riscv\_memory} & Memory Unit\tabularnewline
\texttt{...riscv\_wb} & Data Memory Access (Write Back)\tabularnewline
\texttt{...riscv\_state} & State Unit\tabularnewline
\texttt{...riscv\_rf} & Register File\tabularnewline
\texttt{...riscv\_bp} & Correlating Branch Prediction
Unit\tabularnewline
\texttt{.....riscv\_ram\_1r1w} & RAM 1RW1\tabularnewline
\texttt{.......riscv\_ram\_1r1w\_generic} & RAM 1RW1
Generic\tabularnewline
\texttt{...riscv\_du} & Debug Unit\tabularnewline
\bottomrule
\end{longtable}

In a Harvard architecture, there is no need to make the two memories
share characteristics. In particular, the word width, timing,
implementation technology, and memory address structure can differ. In
some systems, instructions for pre-programmed tasks can be stored in
read-only memory while data memory generally requires read-write memory.
In some systems, there is much more instruction memory than data memory
so instruction addresses are wider than data addresses.

\paragraph{2.1.1.2. Pipeline}\label{pipeline}

In computer science, instruction pipelining is a technique for
implementing instruction-level parallelism within a PU. Pipelining
attempts to keep every part of the processor busy with some instruction
by dividing incoming instructions into a series of sequential steps
performed by different PUs with different parts of instructions
processed in parallel. It allows faster PU throughput than would
otherwise be possible at a given clock rate.

\begin{longtable}[]{@{}lll@{}}
\toprule
Typical & Modified & Module\tabularnewline
\midrule
\endhead
FETCH & FETCH & \texttt{riscv\_if}\tabularnewline
\ldots{} & PRE-DECODE & \texttt{riscv\_id}\tabularnewline
DECODE & DECODE & \texttt{riscv\_id}\tabularnewline
EXECUTE & EXECUTE & \texttt{riscv\_execution}\tabularnewline
MEMORY & MEMORY & \texttt{riscv\_memory}\tabularnewline
WRITE-BACK & WRITE-BACK & \texttt{riscv\_wb}\tabularnewline
\bottomrule
\end{longtable}

\begin{itemize}
\item
  IF -- Instruction Fetch Unit : Send out the PC and fetch the
  instruction from memory into the Instruction Register (IR); increment
  the PC to address the next sequential instruction. The IR is used to
  hold the next instruction that will be needed on subsequent clock
  cycles; likewise the register NPC is used to hold the next sequential
  PC.
\item
  ID -- Instruction Decode Unit : Decode the instruction and access the
  register file to read the registers. This unit gets instruction from
  IF, and extracts opcode and operand from that instruction. It also
  retrieves register values if requested by the operation.
\item
  EX -- Execution Unit : The ALU operates on the operands prepared in
  prior cycle, performing one functions depending on instruction type.
\item
  MEM -- Memory Access Unit : Instructions active in this unit are
  loads, stores and branches.
\item
  WB -- WriteBack Unit : Write the result into the register file,
  whether it comes from the memory system or from the ALU.
\end{itemize}

\subsubsection{2.1.2. Interface}\label{interface}

\paragraph{2.1.2.1. Constants}\label{constants}

\begin{longtable}[]{@{}lccl@{}}
\toprule
Parameter & Type & Default & Description\tabularnewline
\midrule
\endhead
\texttt{JEDEC\_BANK} & \texttt{Integer} & 0x0A & JEDEC
Bank\tabularnewline
\texttt{JEDEC\_MANUFACTURER\_ID} & \texttt{Integer} & 0x6E & JEDEC
Manufacturer ID\tabularnewline
\texttt{XLEN} & \texttt{Integer} & 64 & Data Path Width\tabularnewline
\texttt{PLEN} & \texttt{Integer} & 64 & Physical Memory Address
Size\tabularnewline
\texttt{PMP\_CNT} & \texttt{Integer} & 16 & Physical Memory Protection
Entries\tabularnewline
\texttt{PMA\_CNT} & \texttt{Integer} & 16 & Physical Menory Attribute
Entries\tabularnewline
\texttt{HAS\_USER} & \texttt{Integer} & 1 & User Mode
Enable\tabularnewline
\texttt{HAS\_SUPER} & \texttt{Integer} & 1 & Supervisor Mode
Enable\tabularnewline
\texttt{HAS\_HYPER} & \texttt{Integer} & 1 & Hypervisor Mode
Enable\tabularnewline
\texttt{HAS\_RVM} & \texttt{Integer} & 1 & ``M'' Extension
Enable\tabularnewline
\texttt{HAS\_RVA} & \texttt{Integer} & 1 & ``A'' Extension
Enable\tabularnewline
\texttt{HAS\_RVC} & \texttt{Integer} & 1 & ``C'' Extension
Enable\tabularnewline
\texttt{HAS\_BPU} & \texttt{Integer} & 1 & Branch Prediction Unit
Control Enable\tabularnewline
\texttt{IS\_RV32E} & \texttt{Integer} & 0 & Base Integer Instruction Set
Enable\tabularnewline
\texttt{MULT\_LATENCY} & \texttt{Integer} & 1 & Hardware Multiplier
Latency\tabularnewline
\texttt{ICACHE\_SIZE} & \texttt{Integer} & 16 & Instruction Cache
size\tabularnewline
\texttt{ICACHE\_BLOCK\_SIZE} & \texttt{Integer} & 64 & Instruction Cache
block length\tabularnewline
\texttt{ICACHE\_WAYS} & \texttt{Integer} & 2 & Instruction Cache
associativity\tabularnewline
\texttt{ICACHE\_REPLACE\_ALG} & \texttt{Integer} & 0 & Instruction Cache
replacement\tabularnewline
\texttt{DCACHE\_SIZE} & \texttt{Integer} & 16 & Data Cache
size\tabularnewline
\texttt{DCACHE\_BLOCK\_SIZE} & \texttt{Integer} & 64 & Data Cache block
length\tabularnewline
\texttt{DCACHE\_WAYS} & \texttt{Integer} & 2 & Data Cache
associativity\tabularnewline
\texttt{DCACHE\_REPLACE\_ALG} & \texttt{Integer} & 0 & Data Cache
replacement algorithm\tabularnewline
\texttt{HARTID} & \texttt{Integer} & 0 & Hart Identifier\tabularnewline
\texttt{PC\_INIT} & \texttt{Address} & \texttt{\textquotesingle{}h200} &
Program Counter Initialisation Vector\tabularnewline
\texttt{MNMIVEC\_DEFAULT} & \texttt{Address} &
\texttt{PC\_INIT-\textquotesingle{}h004} & Machine Mode
Non-Maskable\tabularnewline
\texttt{MTVEC\_DEFAULT} & \texttt{Address} &
\texttt{PC\_INIT-\textquotesingle{}h040} & Machine Mode Interrupt
Address\tabularnewline
\texttt{HTVEC\_DEFAULT} & \texttt{Address} &
\texttt{PC\_INIT-\textquotesingle{}h080} & Hypervisor Mode Interrupt
Address\tabularnewline
\texttt{STVEC\_DEFAULT} & \texttt{Address} &
\texttt{PC\_INIT-\textquotesingle{}h0C0} & Supervisor Mode Interrupt
Address\tabularnewline
\texttt{UTVEC\_DEFAULT} & \texttt{Address} &
\texttt{PC\_INIT-\textquotesingle{}h100} & User Mode Interrupt
Address\tabularnewline
\texttt{BP\_LOCAL\_BITS} & \texttt{Integer} & 10 & Number of local
predictor bits\tabularnewline
\texttt{BP\_GLOBAL\_BITS} & \texttt{Integer} & 2 & Number of global
predictor bits\tabularnewline
\texttt{BREAKPOINTS} & \texttt{Integer} & 3 & Number of hardware
breakpoints\tabularnewline
\texttt{TECHNOLOGY} & \texttt{String} & \texttt{GENERIC} & Target
Silicon Technology\tabularnewline
\bottomrule
\end{longtable}

\paragraph{2.1.2.2. Signals}\label{signals}

\subparagraph{2.1.2.2.1. Instruction Inputs/Outputs
Bus}\label{instruction-inputsoutputs-bus}

\begin{longtable}[]{@{}lccl@{}}
\toprule
Port & Size & Direction & Description\tabularnewline
\midrule
\endhead
\texttt{ins\_stb} & 1 & Input & Strobe\tabularnewline
\texttt{ins\_stb\_ack} & 1 & Output & Strobe acknowledge\tabularnewline
\texttt{ins\_d\_ack} & 1 & Output & Data acknowledge\tabularnewline
\texttt{ins\_adri} & \texttt{PLEN} & Input & Start
address\tabularnewline
\texttt{ins\_adro} & \texttt{PLEN} & Output & Response
address\tabularnewline
\texttt{ins\_size} & 3 & Input & Syze\tabularnewline
\texttt{ins\_type} & 3 & Input & Type\tabularnewline
\texttt{ins\_prot} & 3 & Input & Protection\tabularnewline
\texttt{ins\_lock} & 1 & Input & Locked access\tabularnewline
\texttt{ins\_d} & \texttt{XLEN} & Input & Write data\tabularnewline
\texttt{ins\_q} & \texttt{XLEN} & Output & Read data\tabularnewline
\texttt{ins\_ack} & 1 & Output & Acknowledge\tabularnewline
\texttt{ins\_err} & 1 & Output & Error\tabularnewline
\bottomrule
\end{longtable}

\subparagraph{2.1.2.2.2. Data Inputs/Outputs
Bus}\label{data-inputsoutputs-bus}

\begin{longtable}[]{@{}lccl@{}}
\toprule
Port & Size & Direction & Description\tabularnewline
\midrule
\endhead
\texttt{dat\_stb} & 1 & Input & Strobe\tabularnewline
\texttt{dat\_stb\_ack} & 1 & Output & Strobe acknowledge\tabularnewline
\texttt{dat\_d\_ack} & 1 & Output & Data acknowledge\tabularnewline
\texttt{dat\_adri} & \texttt{PLEN} & Input & Start
address\tabularnewline
\texttt{dat\_adro} & \texttt{PLEN} & Output & Response
address\tabularnewline
\texttt{dat\_size} & 3 & Input & Syze\tabularnewline
\texttt{dat\_type} & 3 & Input & Type\tabularnewline
\texttt{dat\_prot} & 3 & Input & Protection\tabularnewline
\texttt{dat\_lock} & 1 & Input & Locked access\tabularnewline
\texttt{dat\_d} & \texttt{XLEN} & Input & Write data\tabularnewline
\texttt{dat\_q} & \texttt{XLEN} & Output & Read data\tabularnewline
\texttt{dat\_ack} & 1 & Output & Acknowledge\tabularnewline
\texttt{dat\_err} & 1 & Output & Error\tabularnewline
\bottomrule
\end{longtable}

\subsubsection{2.1.3. Registers}\label{registers}

\subsubsection{2.1.4. Interruptions}\label{interruptions}

\subsection{2.2. PU-RISCV}\label{pu-riscv}

\subsubsection{2.2.1. Processing Unit}\label{processing-unit}

The RISC-V implementation has a 32/64/128 bit Microarchitecture, 6
stages data pipeline and an Instruction Set Architecture based on
Reduced Instruction Set Computer. Compatible with AMBA and Wishbone
Buses. For Researching and Developing.

\begin{longtable}[]{@{}ll@{}}
\toprule
Processing Unit & Module description\tabularnewline
\midrule
\endhead
\texttt{riscv\_pu} & Processing Unit\tabularnewline
\texttt{...riscv\_core} & Core\tabularnewline
\texttt{...riscv\_imem\_ctrl} & Instruction Memory Access
Block\tabularnewline
\texttt{...riscv\_biu\ -\ imem} & Bus Interface Unit
(Instruction)\tabularnewline
\texttt{...riscv\_dmem\_ctrl} & Data Memory Access Block\tabularnewline
\texttt{...riscv\_biu\ -\ dmem} & Bus Interface Unit
(Data)\tabularnewline
\bottomrule
\end{longtable}

A PU cache is a hardware cache used by the PU to reduce the average cost
(time or energy) to access instruction/data from the main memory. A
cache is a smaller, faster memory, closer to a core, which stores copies
of the data from frequently used main memory locations. Most CPUs have
different independent caches, including instruction and data caches.

\subsubsection{2.2.2. Instruction Cache}\label{instruction-cache}

\paragraph{2.2.2.1. Functionality}\label{functionality-1}

\begin{longtable}[]{@{}ll@{}}
\toprule
Instruction Memory & Module description\tabularnewline
\midrule
\endhead
\texttt{riscv\_imem\_ctrl} & Instruction Memory Access
Block\tabularnewline
\texttt{...riscv\_membuf} & Memory Access Buffer\tabularnewline
\texttt{.....riscv\_ram\_queue} & Fall-through Queue\tabularnewline
\texttt{...riscv\_memmisaligned} & Misalignment Check\tabularnewline
\texttt{...riscv\_mmu} & Memory Management Unit\tabularnewline
\texttt{...riscv\_pmachk} & Physical Memory Attributes
Checker\tabularnewline
\texttt{...riscv\_pmpchk} & Physical Memory Protection
Checker\tabularnewline
\texttt{...riscv\_icache\_core} & Instruction Cache (Write
Back)\tabularnewline
\texttt{.....riscv\_ram\_1rw} & RAM 1RW\tabularnewline
\texttt{.......riscv\_ram\_1rw\_generic} & RAM 1RW
Generic\tabularnewline
\texttt{...riscv\_dext} & Data External Access Logic\tabularnewline
\texttt{...riscv\_ram\_queue} & Fall-through Queue\tabularnewline
\texttt{...riscv\_mux} & Bus-Interface-Unit Mux\tabularnewline
\texttt{riscv\_biu} & Bus Interface Unit\tabularnewline
\bottomrule
\end{longtable}

\paragraph{2.2.2.2. Interface}\label{interface-1}

\subparagraph{2.2.2.2.1. Instruction INPUTS/OUTPUTS AMBA4 AXI-Lite
Bus}\label{instruction-inputsoutputs-amba4-axi-lite-bus}

2.2.2.2.1.1. Signals of the Read and Write Address channels

\begin{longtable}[]{@{}llccl@{}}
\toprule
Write Port & Read Port & Size & Direction & Description\tabularnewline
\midrule
\endhead
\texttt{AWID} & \texttt{ARID} & \texttt{AXI\_ID\_WIDTH} & Output &
Address ID, to identify multiple streams\tabularnewline
\texttt{AWADDR} & \texttt{ARADDR} & \texttt{AXI\_ADDR\_WIDTH} & Output &
Address of the first beat of the burst\tabularnewline
\texttt{AWLEN} & \texttt{ARLEN} & 8 & Output & Number of beats inside
the burst\tabularnewline
\texttt{AWSIZE} & \texttt{ARSIZE} & 3 & Output & Size of each
beat\tabularnewline
\texttt{AWBURST} & \texttt{ARBURST} & 2 & Output & Type of the
burst\tabularnewline
\texttt{AWLOCK} & \texttt{ARLOCK} & 1 & Output & Lock type, to provide
atomic operations\tabularnewline
\texttt{AWCACHE} & \texttt{ARCACHE} & 4 & Output & Memory type, progress
through the system\tabularnewline
\texttt{AWPROT} & \texttt{ARPROT} & 3 & Output & Protection
type\tabularnewline
\texttt{AWQOS} & \texttt{ARQOS} & 4 & Output & Quality of Service of the
transaction\tabularnewline
\texttt{AWREGION} & \texttt{ARREGION} & 4 & Output & Region identifier,
physical to logical\tabularnewline
\texttt{AWUSER} & \texttt{ARUSER} & \texttt{AXI\_USER\_WIDTH} & Output &
User-defined data\tabularnewline
\texttt{AWVALID} & \texttt{ARVALID} & 1 & Output & xVALID handshake
signal\tabularnewline
\texttt{AWREADY} & \texttt{ARREADY} & 1 & Input & xREADY handshake
signal\tabularnewline
\bottomrule
\end{longtable}

2.2.2.2.1.2. Signals of the Read and Write Data channels

\begin{longtable}[]{@{}llccl@{}}
\toprule
Write Port & Read Port & Size & Direction & Description\tabularnewline
\midrule
\endhead
\texttt{WID} & \texttt{RID} & \texttt{AXI\_ID\_WIDTH} & Output & Data
ID, to identify multiple streams\tabularnewline
\texttt{WDATA} & \texttt{RDATA} & \texttt{AXI\_DATA\_WIDTH} & Output &
Read/Write data\tabularnewline
\texttt{-\/-} & \texttt{RRESP} & 2 & Output & Read response, current
RDATA status\tabularnewline
\texttt{WSTRB} & \texttt{-\/-} & \texttt{AXI\_STRB\_WIDTH} & Output &
Byte strobe, WDATA signal\tabularnewline
\texttt{WLAST} & \texttt{RLAST} & 1 & Output & Last beat
identifier\tabularnewline
\texttt{WUSER} & \texttt{RUSER} & \texttt{AXI\_USER\_WIDTH} & Output &
User-defined data\tabularnewline
\texttt{WVALID} & \texttt{RVALID} & 1 & Output & xVALID handshake
signal\tabularnewline
\texttt{WREADY} & \texttt{RREADY} & 1 & Input & xREADY handshake
signal\tabularnewline
\bottomrule
\end{longtable}

2.2.2.2.1.3. Signals of the Write Response channel

\begin{longtable}[]{@{}lccl@{}}
\toprule
Write Port & Size & Direction & Description\tabularnewline
\midrule
\endhead
\texttt{BID} & \texttt{AXI\_ID\_WIDTH} & Input & Write response ID, to
identify multiple streams\tabularnewline
\texttt{BRESP} & 2 & Input & Write response, to specify the burst
status\tabularnewline
\texttt{BUSER} & \texttt{AXI\_USER\_WIDTH} & Input & User-defined
data\tabularnewline
\texttt{BVALID} & 1 & Input & xVALID handshake signal\tabularnewline
\texttt{BREADY} & 1 & Output & xREADY handshake signal\tabularnewline
\bottomrule
\end{longtable}

\subparagraph{2.2.2.2.2. Instruction INPUTS/OUTPUTS AMBA3 AHB-Lite
Bus}\label{instruction-inputsoutputs-amba3-ahb-lite-bus}

\begin{longtable}[]{@{}lccl@{}}
\toprule
Port & Size & Direction & Description\tabularnewline
\midrule
\endhead
\texttt{HRESETn} & 1 & Input & Asynchronous Active Low
Reset\tabularnewline
\texttt{HCLK} & 1 & Input & System Clock Input\tabularnewline
& & &\tabularnewline
\texttt{IHSEL} & 1 & Output & Instruction Bus Select\tabularnewline
\texttt{IHADDR} & \texttt{PLEN} & Output & Instruction Address
Bus\tabularnewline
\texttt{IHRDATA} & \texttt{XLEN} & Input & Instruction Read Data
Bus\tabularnewline
\texttt{IHWDATA} & \texttt{XLEN} & Output & Instruction Write Data
Bus\tabularnewline
\texttt{IHWRITE} & 1 & Output & Instruction Write Select\tabularnewline
\texttt{IHSIZE} & 3 & Output & Instruction Transfer Size\tabularnewline
\texttt{IHBURST} & 3 & Output & Instruction Transfer Burst
Size\tabularnewline
\texttt{IHPROT} & 4 & Output & Instruction Transfer Protection
Level\tabularnewline
\texttt{IHTRANS} & 2 & Output & Instruction Transfer Type\tabularnewline
\texttt{IHMASTLOCK} & 1 & Output & Instruction Transfer Master
Lock\tabularnewline
\texttt{IHREADY} & 1 & Input & Instruction Slave Ready
Indicator\tabularnewline
\texttt{IHRESP} & 1 & Input & Instruction Transfer
Response\tabularnewline
\bottomrule
\end{longtable}

\subparagraph{2.2.2.2.3. Instruction INPUTS/OUTPUTS Wishbone
Bus}\label{instruction-inputsoutputs-wishbone-bus}

\begin{longtable}[]{@{}lccl@{}}
\toprule
Port & Size & Direction & Description\tabularnewline
\midrule
\endhead
\texttt{rst} & 1 & Input & Synchronous Active High Reset\tabularnewline
\texttt{clk} & 1 & Input & System Clock Input\tabularnewline
& & &\tabularnewline
\texttt{iadr} & \texttt{AW} & Input & Instruction Address
Bus\tabularnewline
\texttt{idati} & \texttt{DW} & Input & Instruction Input
Bus\tabularnewline
\texttt{idato} & \texttt{DW} & Output & Instruction Output
Bus\tabularnewline
\texttt{isel} & \texttt{DW/8} & Input & Byte Select
Signals\tabularnewline
\texttt{iwe} & 1 & Input & Write Enable Input\tabularnewline
\texttt{istb} & 1 & Input & Strobe Signal/Core Select
Input\tabularnewline
\texttt{icyc} & 1 & Input & Valid Bus Cycle Input\tabularnewline
\texttt{iack} & 1 & Output & Bus Cycle Acknowledge Output\tabularnewline
\texttt{ierr} & 1 & Output & Bus Cycle Error Output\tabularnewline
\texttt{iint} & 1 & Output & Interrupt Signal Output\tabularnewline
\bottomrule
\end{longtable}

\subsubsection{2.2.3. Data Cache}\label{data-cache}

\paragraph{2.2.3.1. Functionality}\label{functionality-2}

\begin{longtable}[]{@{}ll@{}}
\toprule
Data Memory & Module description\tabularnewline
\midrule
\endhead
\texttt{riscv\_dmem\_ctrl} & Data Memory Access Block\tabularnewline
\texttt{...riscv\_membuf} & Memory Access Buffer\tabularnewline
\texttt{.....riscv\_ram\_queue} & Fall-through Queue\tabularnewline
\texttt{...riscv\_memmisaligned} & Misalignment Check\tabularnewline
\texttt{...riscv\_mmu} & Memory Management Unit\tabularnewline
\texttt{...riscv\_pmachk} & Physical Memory Attributes
Checker\tabularnewline
\texttt{...riscv\_pmpchk} & Physical Memory Protection
Checker\tabularnewline
\texttt{...riscv\_dcache\_core} & Data Cache (Write Back)\tabularnewline
\texttt{.....riscv\_ram\_1rw} & RAM 1RW\tabularnewline
\texttt{.......riscv\_ram\_1rw\_generic} & RAM 1RW
Generic\tabularnewline
\texttt{...riscv\_dext} & Data External Access Logic\tabularnewline
\texttt{...riscv\_mux} & Bus-Interface-Unit Mux\tabularnewline
\texttt{riscv\_biu} & Bus Interface Unit\tabularnewline
\bottomrule
\end{longtable}

\paragraph{2.2.3.2. Interface}\label{interface-2}

\subparagraph{2.2.3.2.1. Data INPUTS/OUTPUTS AMBA4 AXI-Lite
Bus}\label{data-inputsoutputs-amba4-axi-lite-bus}

2.2.3.2.1.1. Signals of the Read and Write Address channels

\begin{longtable}[]{@{}llccl@{}}
\toprule
Write Port & Read Port & Size & Direction & Description\tabularnewline
\midrule
\endhead
\texttt{AWID} & \texttt{ARID} & \texttt{AXI\_ID\_WIDTH} & Output &
Address ID, to identify multiple streams\tabularnewline
\texttt{AWADDR} & \texttt{ARADDR} & \texttt{AXI\_ADDR\_WIDTH} & Output &
Address of the first beat of the burst\tabularnewline
\texttt{AWLEN} & \texttt{ARLEN} & 8 & Output & Number of beats inside
the burst\tabularnewline
\texttt{AWSIZE} & \texttt{ARSIZE} & 3 & Output & Size of each
beat\tabularnewline
\texttt{AWBURST} & \texttt{ARBURST} & 2 & Output & Type of the
burst\tabularnewline
\texttt{AWLOCK} & \texttt{ARLOCK} & 1 & Output & Lock type, to provide
atomic operations\tabularnewline
\texttt{AWCACHE} & \texttt{ARCACHE} & 4 & Output & Memory type, progress
through the system\tabularnewline
\texttt{AWPROT} & \texttt{ARPROT} & 3 & Output & Protection
type\tabularnewline
\texttt{AWQOS} & \texttt{ARQOS} & 4 & Output & Quality of Service of the
transaction\tabularnewline
\texttt{AWREGION} & \texttt{ARREGION} & 4 & Output & Region identifier,
physical to logical\tabularnewline
\texttt{AWUSER} & \texttt{ARUSER} & \texttt{AXI\_USER\_WIDTH} & Output &
User-defined data\tabularnewline
\texttt{AWVALID} & \texttt{ARVALID} & 1 & Output & xVALID handshake
signal\tabularnewline
\texttt{AWREADY} & \texttt{ARREADY} & 1 & Input & xREADY handshake
signal\tabularnewline
\bottomrule
\end{longtable}

2.2.3.2.1.2. Signals of the Read and Write Data channels

\begin{longtable}[]{@{}llccl@{}}
\toprule
Write Port & Read Port & Size & Direction & Description\tabularnewline
\midrule
\endhead
\texttt{WID} & \texttt{RID} & \texttt{AXI\_ID\_WIDTH} & Output & Data
ID, to identify multiple streams\tabularnewline
\texttt{WDATA} & \texttt{RDATA} & \texttt{AXI\_DATA\_WIDTH} & Output &
Read/Write data\tabularnewline
\texttt{-\/-} & \texttt{RRESP} & 2 & Output & Read response, current
RDATA status\tabularnewline
\texttt{WSTRB} & \texttt{-\/-} & \texttt{AXI\_STRB\_WIDTH} & Output &
Byte strobe, WDATA signal\tabularnewline
\texttt{WLAST} & \texttt{RLAST} & 1 & Output & Last beat
identifier\tabularnewline
\texttt{WUSER} & \texttt{RUSER} & \texttt{AXI\_USER\_WIDTH} & Output &
User-defined data\tabularnewline
\texttt{WVALID} & \texttt{RVALID} & 1 & Output & xVALID handshake
signal\tabularnewline
\texttt{WREADY} & \texttt{RREADY} & 1 & Input & xREADY handshake
signal\tabularnewline
\bottomrule
\end{longtable}

2.2.3.2.1.3. Signals of the Write Response channel

\begin{longtable}[]{@{}lccl@{}}
\toprule
Write Port & Size & Direction & Description\tabularnewline
\midrule
\endhead
\texttt{BID} & \texttt{AXI\_ID\_WIDTH} & Input & Write response ID, to
identify multiple streams\tabularnewline
\texttt{BRESP} & 2 & Input & Write response, to specify the burst
status\tabularnewline
\texttt{BUSER} & \texttt{AXI\_USER\_WIDTH} & Input & User-defined
data\tabularnewline
\texttt{BVALID} & 1 & Input & xVALID handshake signal\tabularnewline
\texttt{BREADY} & 1 & Output & xREADY handshake signal\tabularnewline
\bottomrule
\end{longtable}

\paragraph{2.2.3.2.2. Data INPUTS/OUTPUTS AMBA3 AHB-Lite
Bus}\label{data-inputsoutputs-amba3-ahb-lite-bus}

\begin{longtable}[]{@{}lccl@{}}
\toprule
Port & Size & Direction & Description\tabularnewline
\midrule
\endhead
\texttt{HRESETn} & 1 & Input & Asynchronous Active Low
Reset\tabularnewline
\texttt{HCLK} & 1 & Input & System Clock Input\tabularnewline
& & &\tabularnewline
\texttt{DHSEL} & 1 & Output & Data Bus Select\tabularnewline
\texttt{DHADDR} & \texttt{PLEN} & Output & Data Address
Bus\tabularnewline
\texttt{DHRDATA} & \texttt{XLEN} & Input & Data Read Data
Bus\tabularnewline
\texttt{DHWDATA} & \texttt{XLEN} & Output & Data Write Data
Bus\tabularnewline
\texttt{DHWRITE} & 1 & Output & Data Write Select\tabularnewline
\texttt{DHSIZE} & 3 & Output & Data Transfer Size\tabularnewline
\texttt{DHBURST} & 3 & Output & Data Transfer Burst Size\tabularnewline
\texttt{DHPROT} & 4 & Output & Data Transfer Protection
Level\tabularnewline
\texttt{DHTRANS} & 2 & Output & Data Transfer Type\tabularnewline
\texttt{DHMASTLOCK} & 1 & Output & Data Transfer Master
Lock\tabularnewline
\texttt{DHREADY} & 1 & Input & Data Slave Ready Indicator\tabularnewline
\texttt{DHRESP} & 1 & Input & Data Transfer Response\tabularnewline
\bottomrule
\end{longtable}

\paragraph{2.2.3.2.3. Data INPUTS/OUTPUTS Wishbone
Bus}\label{data-inputsoutputs-wishbone-bus}

\begin{longtable}[]{@{}lccl@{}}
\toprule
Port & Size & Direction & Description\tabularnewline
\midrule
\endhead
\texttt{rst} & 1 & Input & Synchronous Active High Reset\tabularnewline
\texttt{clk} & 1 & Input & System Clock Input\tabularnewline
& & &\tabularnewline
\texttt{dadr} & \texttt{AW} & Input & Data Address Bus\tabularnewline
\texttt{ddati} & \texttt{DW} & Input & Data Input Bus\tabularnewline
\texttt{ddato} & \texttt{DW} & Output & Data Output Bus\tabularnewline
\texttt{dsel} & \texttt{DW/8} & Input & Byte Select
Signals\tabularnewline
\texttt{dwe} & 1 & Input & Write Enable Input\tabularnewline
\texttt{dstb} & 1 & Input & Strobe Signal/Core Select
Input\tabularnewline
\texttt{dcyc} & 1 & Input & Valid Bus Cycle Input\tabularnewline
\texttt{dack} & 1 & Output & Bus Cycle Acknowledge Output\tabularnewline
\texttt{derr} & 1 & Output & Bus Cycle Error Output\tabularnewline
\texttt{dint} & 1 & Output & Interrupt Signal Output\tabularnewline
\bottomrule
\end{longtable}

\subsection{2.3. SoC-RISCV}\label{soc-riscv}

\subsubsection{2.3.1. MPSoC-DBG}\label{mpsoc-dbg}

\subsubsection{2.3.2. MPSoC-DMA}\label{mpsoc-dma}

\subsubsection{2.3.3. MPSoC-GPIO}\label{mpsoc-gpio}

\subsubsection{2.3.4. MPSoC-MPI}\label{mpsoc-mpi}

\subsubsection{2.3.5. MPSoC-MPRAM}\label{mpsoc-mpram}

\subsubsection{2.3.6. MPSoC-MSI}\label{mpsoc-msi}

\subsubsection{2.3.7. MPSoC-NoC}\label{mpsoc-noc}

\subsubsection{2.3.8. MPSoC-SPRAM}\label{mpsoc-spram}

\subsubsection{2.3.9. MPSoC-UART}\label{mpsoc-uart}

\section{3. WORKFLOW}\label{workflow}

\subsection{3.1. HARDWARE}\label{hardware}

\textbf{1. System Level (SystemC/SystemVerilog)}

The System Level abstraction of a system only looks at its biggest
building blocks like processing units or peripheral devices. At this
level the circuit is usually described using traditional programming
languages like SystemC or SystemVerilog. Sometimes special software
libraries are used that are aimed at simulation circuits on the system
level. The IEEE 1685-2009 standard defines the IP-XACT file format that
can be used to represent designs on the system level and building blocks
that can be used in such system level designs.

\textbf{2. Behavioral \& Register Transfer Level (VHDL/Verilog)}

At the Behavioural Level abstraction a language aimed at hardware
description such as Verilog or VHDL is used to describe the circuit, but
so-called behavioural modeling is used in at least part of the circuit
description. In behavioural modeling there must be a language feature
that allows for imperative programming to be used to describe data paths
and registers. This is the always -block in Verilog and the process
-block in VHDL.

A design in Register Transfer Level representation is usually stored
using HDLs like Verilog and VHDL. But only a very limited subset of
features is used, namely minimalistic always blocks (Verilog) or process
blocks (VHDL) that model the register type used and unconditional
assignments for the datapath logic. The use of HDLs on this level
simplifies simulation as no additional tools are required to simulate a
design in Register Transfer Level representation.

\textbf{3. Logical Gate}

At the Logical Gate Level the design is represented by a netlist that
uses only cells from a small number of single-bit cells, such as basic
logic gates (AND, OR, NOT, XOR, etc.) and registers (usually D-Type
Flip-flops). A number of netlist formats exists that can be used on this
level such as the Electronic Design Interchange Format (EDIF), but for
ease of simulation often a HDL netlist is used. The latter is a HDL file
(Verilog or VHDL) that only uses the most basic language constructs for
instantiation and connecting of cells.

\textbf{4. Physical Gate}

On the Physical Gate Level only gates are used that are physically
available on the target architecture. In some cases this may only be
NAND, NOR and NOT gates as well as D-Type registers. In the case of an
FPGA-based design the Physical Gate Level representation is a netlist of
LUTs with optional output registers, as these are the basic building
blocks of FPGA logic cells.

\textbf{5. Switch Level}

A Switch Level representation of a circuit is a netlist utilizing single
transistors as cells. Switch Level modeling is possible in Verilog and
VHDL, but is seldom used in modern designs, as in modern digital ASIC or
FPGA flows the physical gates are considered the atomic build blocks of
the logic circuit.

\subsubsection{3.1.1. Front-End Open Source
Tools}\label{front-end-open-source-tools}

\paragraph{3.1.1.1. Modeling System Level of
Hardware}\label{modeling-system-level-of-hardware}

\emph{A System Description Language Editor is a computer tool allows to
generate software code. A System Description Language is a formal
language, which comprises a Programming Language (input), producing a
Hardware Description (output). Programming languages are used in
computer programming to implement algorithms. The description of a
programming language is split into the two components of syntax (form)
and semantics (meaning).}

\textbf{SystemVerilog System Description Language Editor}

type:

\begin{verbatim}
git clone --recursive https://github.com/emacs-mirror/emacs

cd emacs
./configure
make
sudo make install
\end{verbatim}

\paragraph{3.1.1.2. Simulating System Level of
Hardware}\label{simulating-system-level-of-hardware}

\emph{A System Description Language Simulator (translator) is a computer
program that translates computer code written in a Programming Language
(the source language) into a Hardware Description Language (the target
language). The compiler is primarily used for programs that translate
source code from a high-level programming language to a low-level
language to create an executable program.}

\textbf{SystemVerilog System Description Language Simulator}

type:

\begin{verbatim}
git clone --recursive http://git.veripool.org/git/verilator

cd verilator
autoconf
./configure
make
sudo make install
\end{verbatim}

\begin{verbatim}
cd sim/verilog/regression/wb/verilator
source SIMULATE-IT
\end{verbatim}

\begin{verbatim}
cd sim/verilog/regression/ahb3/verilator
source SIMULATE-IT
\end{verbatim}

\begin{verbatim}
cd sim/verilog/regression/axi4/verilator
source SIMULATE-IT
\end{verbatim}

\paragraph{3.1.1.3. Verifying System Level of
Hardware}\label{verifying-system-level-of-hardware}

\emph{A UVM standard improves interoperability and reduces the cost of
repurchasing and rewriting IP for each new project or Electronic Design
Automation tool. It also makes it easier to reuse verification
components. The UVM Class Library provides generic utilities, such as
component hierarchy, Transaction Library Model or configuration
database, which enable the user to create virtually any structure wanted
for the testbench.}

\textbf{SystemVerilog System Description Language Verifier}

type:

\begin{verbatim}
git clone --recursive https://github.com/QueenField/UVM
\end{verbatim}

\begin{verbatim}
cd sim/verilog/pu/riscv/wb/msim
source SIMULATE-IT
\end{verbatim}

\begin{verbatim}
cd sim/verilog/pu/riscv/ahb3/msim
source SIMULATE-IT
\end{verbatim}

\begin{verbatim}
cd sim/verilog/pu/riscv/axi4/msim
source SIMULATE-IT
\end{verbatim}

\paragraph{3.1.1.4. Describing Register Transfer Level of
Hardware}\label{describing-register-transfer-level-of-hardware}

\emph{A Hardware Description Language Editor is any editor that allows
to generate hardware code. Hardware Description Language is a
specialized computer language used to describe the structure and
behavior of digital logic circuits. It allows for the synthesis of a HDL
into a netlist, which can then be synthesized, placed and routed to
produce the set of masks used to create an integrated circuit.}

\textbf{VHDL/Verilog Hardware Description Language Editor}

type:

\begin{verbatim}
git clone --recursive https://github.com/emacs-mirror/emacs

cd emacs
./configure
make
sudo make install
\end{verbatim}

\paragraph{3.1.1.5. Simulating Register Transfer Level of
Hardware}\label{simulating-register-transfer-level-of-hardware}

\emph{A Hardware Description Language Simulator uses mathematical models
to replicate the behavior of an actual hardware device. Simulation
software allows for modeling of circuit operation and is an invaluable
analysis tool. Simulating a circuit's behavior before actually building
it can greatly improve design efficiency by making faulty designs known
as such, and providing insight into the behavior of electronics circuit
designs.}

\textbf{Verilog Hardware Description Language Simulator}

type:

\begin{verbatim}
git clone --recursive https://github.com/steveicarus/iverilog

cd iverilog
sh autoconf.sh
./configure
make
sudo make install
\end{verbatim}

\begin{verbatim}
cd sim/verilog/regression/wb/iverilog
source SIMULATE-IT
\end{verbatim}

\begin{verbatim}
cd sim/verilog/regression/ahb3/iverilog
source SIMULATE-IT
\end{verbatim}

\begin{verbatim}
cd sim/verilog/regression/axi4/iverilog
source SIMULATE-IT
\end{verbatim}

\textbf{VHDL Hardware Description Language Simulator}

type:

\begin{verbatim}
git clone --recursive https://github.com/ghdl/ghdl

cd ghdl
./configure --prefix=/usr/local
make
sudo make install
\end{verbatim}

\begin{verbatim}
cd sim/vhdl/regression/wb/ghdl
source SIMULATE-IT
\end{verbatim}

\begin{verbatim}
cd sim/vhdl/regression/ahb3/ghdl
source SIMULATE-IT
\end{verbatim}

\begin{verbatim}
cd sim/vhdl/regression/axi4/ghdl
source SIMULATE-IT
\end{verbatim}

\paragraph{3.1.1.6. Synthesizing Register Transfer Level of
Hardware}\label{synthesizing-register-transfer-level-of-hardware}

\emph{A Hardware Description Language Synthesizer turns a RTL
implementation into a Logical Gate Level implementation. Logical design
is a step in the standard design cycle in which the functional design of
an electronic circuit is converted into the representation which
captures logic operations, arithmetic operations, control flow, etc. In
EDA parts of the logical design is automated using synthesis tools based
on the behavioral description of the circuit.}

\textbf{Verilog Hardware Description Language Synthesizer}

type:

\begin{verbatim}
git clone --recursive https://github.com/YosysHQ/yosys

cd yosys
make
sudo make install
\end{verbatim}

\textbf{VHDL Hardware Description Language Synthesizer}

type:

\begin{verbatim}
git clone --recursive https://github.com/ghdl/ghdl-yosys-plugin
cd ghdl-yosys-plugin
make GHDL=/usr/local
sudo yosys-config --exec mkdir -p --datdir/plugins
sudo yosys-config --exec cp "ghdl.so" --datdir/plugins/ghdl.so
\end{verbatim}

\paragraph{3.1.1.7. Optimizing Register Transfer Level of
Hardware}\label{optimizing-register-transfer-level-of-hardware}

\emph{A Hardware Description Language Optimizer finds an equivalent
representation of the specified logic circuit under specified
constraints (minimum area, pre-specified delay). This tool combines
scalable logic optimization based on And-Inverter Graphs (AIGs),
optimal-delay DAG-based technology mapping for look-up tables and
standard cells, and innovative algorithms for sequential synthesis and
verification.}

\textbf{Verilog Hardware Description Language Optimizer}

type:

\begin{verbatim}
git clone --recursive https://github.com/YosysHQ/yosys

cd yosys
make
sudo make install
\end{verbatim}

\paragraph{3.1.1.8. Verifying Register Transfer Level of
Hardware}\label{verifying-register-transfer-level-of-hardware}

\emph{A Hardware Description Language Verifier proves or disproves the
correctness of intended algorithms underlying a hardware system with
respect to a certain formal specification or property, using formal
methods of mathematics. Formal verification uses modern techniques
(SAT/SMT solvers, BDDs, etc.) to prove correctness by essentially doing
an exhaustive search through the entire possible input space (formal
proof).}

\textbf{Verilog Hardware Description Language Verifier}

type:

\begin{verbatim}
git clone --recursive https://github.com/YosysHQ/SymbiYosys
\end{verbatim}

\subsubsection{3.1.2. Back-End Open Source
Tools}\label{back-end-open-source-tools}

\textbf{I. Back-End Workflow Qflow for ASICs}

type:

\begin{verbatim}
sudo apt install bison cmake flex freeglut3-dev libcairo2-dev libgsl-dev \
libncurses-dev libx11-dev m4 python-tk python3-tk swig tcl tcl-dev tk-dev tcsh
\end{verbatim}

type:

\begin{verbatim}
git clone --recursive https://github.com/RTimothyEdwards/qflow

cd qflow
./configure
make
sudo make install
\end{verbatim}

\paragraph{3.1.2.1. Planning Switch Level of
Hardware}\label{planning-switch-level-of-hardware}

\emph{A Floor-Planner of an Integrated Circuit (IC) is a schematic
representation of tentative placement of its major functional blocks. In
modern electronic design process floor-plans are created during the
floor-planning design stage, an early stage in the hierarchical approach
to Integrated Circuit design. Depending on the design methodology being
followed, the actual definition of a floor-plan may differ.}

\textbf{Floor-Planner}

type:

\begin{verbatim}
git clone --recursive https://github.com/RTimothyEdwards/magic

cd magic
./configure
make
sudo make install
\end{verbatim}

\paragraph{3.1.2.2. Placing Switch Level of
Hardware}\label{placing-switch-level-of-hardware}

\emph{A Standard Cell Placer takes a given synthesized circuit netlist
together with a technology library and produces a valid placement
layout. The layout is optimized according to the aforementioned
objectives and ready for cell resizing and buffering, a step essential
for timing and signal integrity satisfaction. Physical design flow are
iterated a number of times until design closure is achieved.}

\textbf{Standard Cell Placer}

type:

\begin{verbatim}
git clone --recursive https://github.com/rubund/graywolf

cd graywolf
mkdir build
cd build
cmake ..
make
sudo make install
\end{verbatim}

\paragraph{3.1.2.3. Timing Switch Level of
Hardware}\label{timing-switch-level-of-hardware}

\emph{A Standard Cell Timing-Analizer is a simulation method of
computing the expected timing of a digital circuit without requiring a
simulation of the full circuit. High-performance integrated circuits
have traditionally been characterized by the clock frequency at which
they operate. Measuring the ability of a circuit to operate at the
specified speed requires an ability to measure, during the design
process, its delay at numerous steps.}

\textbf{Standard Cell Timing-Analizer}

type:

\begin{verbatim}
git clone --recursive https://github.com/The-OpenROAD-Project/OpenSTA

cd OpenSTA
mkdir build
cd build
cmake ..
make
sudo make install
\end{verbatim}

\paragraph{3.1.2.4. Routing Switch Level of
Hardware}\label{routing-switch-level-of-hardware}

\emph{A Standard Cell Router takes pre-existing polygons consisting of
pins on cells, and pre-existing wiring called pre-routes. Each of these
polygons are associated with a net. The primary task of the router is to
create geometries such that all terminals assigned to the same net are
connected, no terminals assigned to different nets are connected, and
all design rules are obeyed.}

\textbf{Standard Cell Router}

type:

\begin{verbatim}
git clone --recursive https://github.com/RTimothyEdwards/qrouter

cd qrouter
./configure
make
sudo make install
\end{verbatim}

\paragraph{3.1.2.5. Simulating Switch Level of
Hardware}\label{simulating-switch-level-of-hardware}

\emph{A Standard Cell Simulator treats transistors as ideal switches.
Extracted capacitance and lumped resistance values are used to make the
switch a little bit more realistic than the ideal, using the RC time
constants to predict the relative timing of events. This simulator
represents a circuit in terms of its exact transistor structure but
describes the electrical behavior in a highly idealized way.}

\textbf{Standard Cell Simulator}

type:

\begin{verbatim}
git clone --recursive https://github.com/RTimothyEdwards/irsim

cd irsim
./configure
make
sudo make install
\end{verbatim}

\paragraph{3.1.2.6. Verifying Switch Level of Hardware
LVS}\label{verifying-switch-level-of-hardware-lvs}

\emph{A Standard Cell Verifier compares netlists, a process known as LVS
(Layout vs.~Schematic). This step ensures that the geometry that has
been laid out matches the expected circuit. The greatest need for LVS is
in large analog or mixed-signal circuits that cannot be simulated in
reasonable time. LVS can be done faster than simulation, and provides
feedback that makes it easier to find errors.}

\textbf{Standard Cell Verifier}

type:

\begin{verbatim}
git clone --recursive https://github.com/RTimothyEdwards/netgen

cd netgen
./configure
make
sudo make install
\end{verbatim}

\paragraph{3.1.2.7. Checking Switch Level of Hardware
DRC}\label{checking-switch-level-of-hardware-drc}

\emph{A Standard Cell Checker is a geometric constraint imposed on
Printed Circuit Board (PCB) and Integrated Circuit (IC) designers to
ensure their designs function properly, reliably, and can be produced
with acceptable yield. Design Rules for production are developed by
hardware engineers based on the capability of their processes to realize
design intent. Design Rule Checking (DRC) is used to ensure that
designers do not violate design rules.}

\textbf{Standard Cell Checker}

type:

\begin{verbatim}
git clone --recursive https://github.com/RTimothyEdwards/magic

cd magic
./configure
make
sudo make install
\end{verbatim}

\paragraph{3.1.2.8. Printing Switch Level of Hardware
GDS}\label{printing-switch-level-of-hardware-gds}

\emph{A Standard Cell Editor allows to print a set of standard cells.
The standard cell methodology is an abstraction, whereby a low-level
VLSI layout is encapsulated into a logical representation. A standard
cell is a group of transistor and interconnect structures that provides
a boolean logic function (AND, OR, XOR, XNOR, inverters) or a storage
function (flipflop or latch).}

\textbf{Standard Cell Editor}

type:

\begin{verbatim}
git clone --recursive https://github.com/RTimothyEdwards/magic

cd magic
./configure
make
sudo make install
\end{verbatim}

\textbf{II. Back-End Workflow Symbiflow for FPGAs}

\subsection{3.2. SOFTWARE}\label{software}

\subsubsection{3.2.1. Compilers}\label{compilers}

type:

\begin{verbatim}
sudo apt install autoconf automake autotools-dev curl python3 libmpc-dev \
libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf \
libtool patchutils bc zlib1g-dev libexpat-dev
\end{verbatim}

\paragraph{3.2.1.1. RISC-V GNU C/C++}\label{risc-v-gnu-cc}

type:

\begin{verbatim}
git clone --recursive https://github.com/riscv/riscv-gnu-toolchain

cd riscv-gnu-toolchain

./configure --prefix=/opt/riscv-elf-gcc
sudo make clean
sudo make

./configure --prefix=/opt/riscv-elf-gcc
sudo make clean
sudo make linux

./configure --prefix=/opt/riscv-elf-gcc --enable-multilib
sudo make clean
sudo make linux
\end{verbatim}

\paragraph{3.2.1.2. RISC-V GNU Go}\label{risc-v-gnu-go}

type:

\begin{verbatim}
git clone --recursive https://go.googlesource.com/go riscv-go
cd riscv-go/src
./all.bash
cd ../..
sudo mv riscv-go /opt
\end{verbatim}

\subsubsection{3.2.2. Simulators}\label{simulators}

type:

\begin{verbatim}
sudo apt install device-tree-compiler libglib2.0-dev libpixman-1-dev pkg-config
\end{verbatim}

\paragraph{3.2.2.1. Spike (For Hardware
Engineers)}\label{spike-for-hardware-engineers}

\textbf{Building Proxy Kernel}

type:

\begin{verbatim}
export PATH=/opt/riscv-elf-gcc/bin:${PATH}

git clone --recursive https://github.com/riscv/riscv-pk

cd riscv-pk
mkdir build
cd build
../configure --prefix=/opt/riscv-elf-gcc --host=riscv64-unknown-elf
make
sudo make install
\end{verbatim}

\textbf{Building Spike}

type:

\begin{verbatim}
export PATH=/opt/riscv-elf-gcc/bin:${PATH}

git clone --recursive https://github.com/riscv/riscv-isa-sim

cd riscv-isa-sim
mkdir build
cd build
../configure --prefix=/opt/riscv-elf-gcc
make
sudo make install
\end{verbatim}

\paragraph{3.2.2.2. QEMU (For Software
Engineers)}\label{qemu-for-software-engineers}

type:

\begin{verbatim}
export PATH=/opt/riscv-elf-gcc/bin:${PATH}

git clone --recursive https://github.com/qemu/qemu

cd qemu
./configure --prefix=/opt/riscv-elf-gcc \
--target-list=riscv64-softmmu,riscv32-softmmu,riscv64-linux-user,riscv32-linux-user
make
sudo make install
\end{verbatim}

\section{4. CONCLUSION}\label{conclusion}

\subsection{4.1. HARDWARE}\label{hardware-1}

\begin{verbatim}
cd synthesis/yosys
source SYNTHESIZE-IT
\end{verbatim}

\subsubsection{4.1.1. GSCL 45 nm ASIC}\label{gscl-45-nm-asic}

type:

\begin{verbatim}
cd synthesis/qflow
source FLOW-IT
\end{verbatim}

\subsubsection{4.1.2. Lattice iCE40 FPGA}\label{lattice-ice40-fpga}

type:

\begin{verbatim}
cd synthesis/symbiflow
source FLOW-IT
\end{verbatim}

\subsection{4.2. SOFTWARE}\label{software-1}

\subsubsection{4.2.1. RISC-V Tests}\label{risc-v-tests}

type:

\begin{verbatim}
export PATH=/opt/riscv-elf-gcc/bin:${PATH}

rm -rf tests
rm -rf riscv-tests

mkdir tests
mkdir tests/dump
mkdir tests/hex

git clone --recursive https://github.com/riscv/riscv-tests
cd riscv-tests

autoconf
./configure --prefix=/opt/riscv-elf-gcc/bin
make

cd isa

source ../../elf2hex.sh

mv *.dump ../../tests/dump
mv *.hex ../../tests/hex

cd ..

make clean
\end{verbatim}

elf2hex.sh:

\begin{verbatim}
riscv64-unknown-elf-objcopy -O ihex rv32mi-p-breakpoint rv32mi-p-breakpoint.hex
riscv64-unknown-elf-objcopy -O ihex rv32mi-p-csr rv32mi-p-csr.hex
...
riscv64-unknown-elf-objcopy -O ihex rv64um-v-remw rv64um-v-remw.hex
\end{verbatim}

type:

\begin{verbatim}
export PATH=/opt/riscv-elf-gcc/bin:${PATH}

spike rv32mi-p-breakpoint
spike rv32mi-p-csr
...
spike rv64um-v-remw
\end{verbatim}

\subsubsection{4.2.2. RISC-V Bare Metal}\label{risc-v-bare-metal}

type:

\begin{verbatim}
rm -rf hello_c.elf
rm -rf hello_c.hex

export PATH=/opt/riscv-elf-gcc/bin:${PATH}

riscv64-unknown-elf-gcc -o hello_c.elf hello_c.c
riscv64-unknown-elf-objcopy -O ihex hello_c.elf hello_c.hex
\end{verbatim}

C Language:

\begin{Shaded}
\begin{Highlighting}[]
\PreprocessorTok{#include }\ImportTok{<stdio.h>}

\DataTypeTok{int}\NormalTok{ main() \{}
\NormalTok{  printf(}\StringTok{"Hello QueenField!}\SpecialCharTok{\textbackslash{}n}\StringTok{"}\NormalTok{);}
  \ControlFlowTok{return} \DecValTok{0}\NormalTok{;}
\NormalTok{\}}
\end{Highlighting}
\end{Shaded}

type:

\begin{verbatim}
export PATH=/opt/riscv-elf-gcc/bin:${PATH}

spike pk hello_c.elf
\end{verbatim}

type:

\begin{verbatim}
rm -rf hello_cpp.elf
rm -rf hello_cpp.hex

export PATH=/opt/riscv-elf-gcc/bin:${PATH}

riscv64-unknown-elf-g++ -o hello_cpp.elf hello_cpp.cpp
riscv64-unknown-elf-objcopy -O ihex hello_cpp.elf hello_cpp.hex
\end{verbatim}

C++ Language:

\begin{Shaded}
\begin{Highlighting}[]
\PreprocessorTok{#include }\ImportTok{<iostream>}

\DataTypeTok{int}\NormalTok{ main() \{}
  \BuiltInTok{std::}\NormalTok{cout << }\StringTok{"Hello QueenField!}\SpecialCharTok{\textbackslash{}n}\StringTok{"}\NormalTok{;}
  \ControlFlowTok{return} \DecValTok{0}\NormalTok{;}
\NormalTok{\}}
\end{Highlighting}
\end{Shaded}

type:

\begin{verbatim}
export PATH=/opt/riscv-elf-gcc/bin:${PATH}

spike pk hello_cpp.elf
\end{verbatim}

type:

\begin{verbatim}
rm -rf hello_go.elf
rm -rf hello_go.hex

export PATH=/opt/riscv-elf-gcc/bin:${PATH}
export PATH=/opt/riscv-go/bin:${PATH}

GOOS=linux GOARCH=riscv64 go build -o hello_go.elf hello_go.go
riscv64-unknown-elf-objcopy -O ihex hello_go.elf hello_go.hex
\end{verbatim}

Go Language:

\begin{Shaded}
\begin{Highlighting}[]
\KeywordTok{package}\NormalTok{ main}

\KeywordTok{import} \StringTok{"fmt"}
\KeywordTok{func}\NormalTok{ main() \{}
\NormalTok{  fmt.Println(}\StringTok{"Hello QueenField!"}\NormalTok{)}
\NormalTok{\}}
\end{Highlighting}
\end{Shaded}

\subsubsection{4.2.3. RISC-V Operating
System}\label{risc-v-operating-system}

\paragraph{4.2.3.1. GNU Linux}\label{gnu-linux}

\textbf{Building BusyBox}

type:

\begin{verbatim}
export PATH=/opt/riscv-elf-gcc/bin:${PATH}

git clone --recursive https://git.busybox.net/busybox

cd busybox
make CROSS_COMPILE=riscv64-unknown-linux-gnu- defconfig
make CROSS_COMPILE=riscv64-unknown-linux-gnu-
\end{verbatim}

\textbf{Building Linux}

type:

\begin{verbatim}
export PATH=/opt/riscv-elf-gcc/bin:${PATH}

git clone --recursive https://github.com/torvalds/linux

cd linux
make ARCH=riscv CROSS_COMPILE=riscv64-unknown-linux-gnu- defconfig
make ARCH=riscv CROSS_COMPILE=riscv64-unknown-linux-gnu-
\end{verbatim}

\textbf{Running Linux}

type:

\begin{verbatim}
export PATH=/opt/riscv-elf-gcc/bin:${PATH}

qemu-system-riscv64 -nographic -machine virt \
-kernel Image -append "root=/dev/vda ro console=ttyS0" \
-drive file=busybox,format=raw,id=hd0 \
-device virtio-blk-device,drive=hd0
\end{verbatim}

\paragraph{4.2.3.2. GNU Hurd}\label{gnu-hurd}

\subsubsection{4.2.4. RISC-V Distribution}\label{risc-v-distribution}

\paragraph{4.2.4.1. GNU Debian}\label{gnu-debian}

\paragraph{4.2.4.2. GNU Fedora}\label{gnu-fedora}

\end{document}
