def _addClockBuffer(io_rtl):
  """
  explicitly add a clock buffer so that clock net could be fully routed
  """
  io_rtl_clk_buffer = [io.replace('ap_clk', 'ap_clk_port') for io in io_rtl]
  io_rtl_clk_buffer.append(f'wire ap_clk; ')
  io_rtl_clk_buffer.append(f'(* DONT_TOUCH = "yes", LOC = "BUFGCE_X0Y194" *) BUFGCE test_bufg ( ')
  io_rtl_clk_buffer.append(f'  .I(ap_clk_port), ')
  io_rtl_clk_buffer.append(f'  .CE(1\'b1),')
  io_rtl_clk_buffer.append(f'  .O(ap_clk) );')

  return io_rtl_clk_buffer