def generate_registers_sifive_clic0_cliccfg(addr):
    """Generate xml string for riscv_clic0 cfg register"""
    return """\
                <register>
                  <name>cliccfg</name>
                  <description>CLICCFG Register</description>
                  <addressOffset>""" + addr + """</addressOffset>
                  <size>8</size>
                  <fields>
                    <field>
                      <name>nvbits</name>
                      <description>When set, selective hardware vectoring is enabled.</description>
                      <bitRange>[0:0]</bitRange>
                      <access>read-write</access>
                    </field>
                    <field>
                      <name>nlbits</name>
                      <description>Determines the number of Level bits available in clicintctl.</description>
                      <bitRange>[4:1]</bitRange>
                      <access>read-write</access>
                    </field>
                    <field>
                      <name>nmbits</name>
                      <description>Determines the number of Mode bits available in clicintctl.</description>
                      <bitRange>[6:5]</bitRange>
                      <access>read-only</access>
                    </field>
                  </fields>
                </register>
"""