def calculate_clock_settings(requested_frequency,
                             clock_divisors,
                             phase_correct_mode,
                             max_frequency=40000,
                             min_frequency=40,
                             base_clock_frequency=40000000,
                             max_counter=65535,
                             min_counter=100,
                             coerce_range=True):
    """
    Determine the counter settings that will produce the requested frequency
    or as close a frequency as possible. This function is used internally and
    should only used for SPI and PWM API. Do not use this function in other
    examples.

    Args:
        requested_frequency (int):
            The range is from 40Hz to 400000Hz.
        clock_divisors (int array):
            The available clock divisors for SPI mode are 1, 2, 4, and 8. The
            available clock divisors for PWM mode are 1, 2, 4, 8, 16, 32, and
            64.
        phase_correct_mode (bool):
            The phase_correct_mode should be False for SPI mode; it should be
            True for PWM mode. 
        max_frequency (int):
            The the default value is 4000000Hz.
        min_frequency (int):
            The default value is 40Hz.
        base_clock_frequency (int):
            The minmum posslbie clock frequency is 611Hz and the maximum
            possible clock frequency is 40MHz due to the impelementation in
            the FPGA. The default value is 4000000Hz.
        max_counter (int):
            NI ELVIS III is using a 16-bit counter, so the valid max counter
            value is 2^16 -1 which is equal to 65535. The default value is
            65535 which is also the suggestted value.
        min_counter (int):
            We want to guarantee 1% duty cycle resolution, the value used for
            Resolution is % x 100 is 100. The default value is 100  which is
            also the suggestted value.
        coerce_range (bool):
            The default value is True.

    Returns:
        actual_frequency (float)
        actual_top (float)
        actual_clock_divisor (int)
    """
    if coerce_range:
        if not (min_frequency < requested_frequency < max_frequency):
            raise ValueError('frequency is out of range: 40 - 4000000 (Hz)')
        requested_frequency = max(min_frequency, min(requested_frequency, max_frequency))
    if requested_frequency < 0:
        requested_frequency = 0
    actual_frequency = 0
    actual_top = 0
    actual_clock_divisor = 0
    for divisor in clock_divisors:
        if phase_correct_mode:
            top = round(base_clock_frequency / (2 * divisor * requested_frequency))
            frequency = base_clock_frequency / (2 * top * divisor)
        else:
            top = round(base_clock_frequency / (divisor * requested_frequency)) - 1
            frequency = base_clock_frequency / (divisor * (1 + top))
            min_counter -= 1
        coerced = frequency != requested_frequency
        if coerced:
            frequency_comparison = abs(requested_frequency - actual_frequency) <= abs(requested_frequency - frequency)
            if not (frequency_comparison and (actual_frequency != 0)):
                actual_frequency = frequency
                actual_top = top
                actual_clock_divisor = divisor
        else:
            actual_frequency = frequency
            actual_top = top
            actual_clock_divisor = divisor
        if (top < min_counter) or not coerced:
            break
    return actual_frequency, actual_top, actual_clock_divisor