def reg_dims(reg):
  """ 
  Accepts a dict containing the fields 'start' and 'nbits'.
  Returns a string containing the dims in verilog syntax.
  If nbits is 0, returns empty string.
  """
  if (int(reg['nbits']) == 0):
    return ''
  else:
    return "["+str(int(reg['nbits'])+int(reg['start'])-1)+":"+reg['start']+"]"