#=========================================================================
# test_utils
#=========================================================================
# Simple helper test functions.

from   pymtl       import *
import collections
import re

#-------------------------------------------------------------------------
# mk_test_case_table
#-------------------------------------------------------------------------

def mk_test_case_table( raw_test_case_table ):

  # First row in test vectors contains port names

  if isinstance(raw_test_case_table[0],str):
    test_param_names = raw_test_case_table[0].split()
  else:
    test_param_names = raw_test_case_table[0]

  TestCase = collections.namedtuple("TestCase",test_param_names)

  ids = []
  test_cases = []
  for row in raw_test_case_table[1:]:
    ids.append( row[0] )
    test_cases.append( TestCase(*row[1:]) )

  return {
    'ids'      : ids,
    'argnames' : ('test_params'),
    'argvalues' : test_cases,
  }

#-------------------------------------------------------------------------
# run sim
#-------------------------------------------------------------------------

def run_sim( model, dump_vcd=None, test_verilog=False ):

  # Setup the model

  model.vcd_file = dump_vcd
  if test_verilog:
    model = TranslationTool( model )
  model.elaborate()

  # Create a simulator

  sim = SimulationTool( model )

  # Reset model

  sim.reset()
  print()

  # Run simulation

  while not model.done():
    sim.print_line_trace()
    sim.cycle()

  # Extra ticks to make VCD easier to read

  sim.cycle()
  sim.cycle()
  sim.cycle()

#-------------------------------------------------------------------------
# run_test_vector_sim
#-------------------------------------------------------------------------

def run_test_vector_sim( model, test_vectors, dump_vcd=None, test_verilog=False ):

  # First row in test vectors contains port names

  if isinstance(test_vectors[0],str):
    port_names = test_vectors[0].split()
  else:
    port_names = test_vectors[0]

  # Remaining rows contain the actual test vectors

  test_vectors = test_vectors[1:]

  # Setup the model

  model.vcd_file = dump_vcd
  if test_verilog:
    model = get_verilated( model )
  model.elaborate()

  # Create a simulator

  sim = SimulationTool( model )

  # Reset model

  sim.reset()
  print ""

  # Run the simulation

  for row in test_vectors:

    # Apply test inputs

    for port_name, in_value in zip( port_names, row ):
      if port_name[-1] != "*":

        # Special case for lists of ports
        if '[' in port_name:
          m = re.match( r'(\w+)\[(\d+)\]', port_name )
          if not m:
            raise Exception("Could not parse port name: {}".format(port_name))
          getattr( model, m.group(1) )[int(m.group(2))].value = in_value
        else:
          getattr( model, port_name ).value = in_value

    # Evaluate combinational concurrent blocks

    sim.eval_combinational()

    # Display line trace output

    sim.print_line_trace()

    # Check test outputs

    for port_name, ref_value in zip( port_names, row ):
      if port_name[-1] == "*":

        # Special case for lists of ports
        if '[' in port_name:
          m = re.match( r'(\w+)\[(\d+)\]', port_name[0:-1] )
          if not m:
            raise Exception("Could not parse port name: {}".format(port_name))
          out_value = getattr( model, m.group(1) )[int(m.group(2))]
        else:
          out_value = getattr( model, port_name[0:-1] )

        if ( ref_value != '?' ):
          assert out_value == ref_value

    # Tick the simulation

    sim.cycle()

  # Extra ticks to make VCD easier to read

  sim.cycle()
  sim.cycle()
  sim.cycle()


@@ -2198,21 +2198,23 @@
 l = 
-get_verilated
+TranslationTool
 ( mo

move to using new TranslationTool