from __future__ import absolute_import
from myhdl import *
from myhdl import ConversionError
from myhdl.conversion._misc import _error
from myhdl.conversion import verify


def sigAugmAssignUnsupported(z, a):
    @always(a)
    def logic():
        z.next += a
    return logic

def test_SigAugmAssignUnsupported():
    z = Signal(intbv(0)[8:])
    a = Signal(intbv(0)[8:])
    try:
        verify(sigAugmAssignUnsupported, z, a)
    except ConversionError as e:
        assert e.kind == _error.NotSupported
    else:
        assert False
        
def modbvRange(z, a, b):
    @always(a, b)
    def logic():
        s = modbv(0, min=0, max=35)
        s[:] = a + b
        z.next = s
    return logic

def test_modbvRange():
    z = Signal(intbv(0)[8:])
    a = Signal(intbv(0)[4:])
    b = Signal(intbv(0)[4:])
    try:
        verify(modbvRange, z, a, b)
    except ConversionError as e:
        assert e.kind == _error.ModbvRange
    else:
        assert False
        
def modbvSigRange(z, a, b):
    @always(a, b)
    def logic():
        z.next = a + b
    return logic

def test_modbvSigRange():
    z = Signal(modbv(0, min=0, max=42))
    a = Signal(intbv(0)[4:])
    b = Signal(intbv(0)[4:])
    try:
        verify(modbvSigRange, z, a, b)
    except ConversionError as e:
        assert e.kind == _error.ModbvRange
    else:
        assert False
        





@@ -166,16 +166,24 @@
 erify%0A%0A%0A
+@module%0A
 def sigA
@@ -427,15 +427,15 @@
 rted
-, 
+(
 z, a)
+)
 %0A   
@@ -541,32 +541,40 @@
  False%0A        %0A
+@module%0A
 def modbvRange(z
@@ -851,34 +851,33 @@
 y(modbvRange
-, 
+(
 z, a, b)
 %0A    except 
@@ -856,32 +856,33 @@
 bvRange(z, a, b)
+)
 %0A    except Conv
@@ -982,16 +982,24 @@
        %0A
+@module%0A
 def modb
@@ -1259,18 +1259,17 @@
 ange
-, 
+(
 z, a, b)
 %0A   
@@ -1260,24 +1260,25 @@
 nge(z, a, b)
+)
 %0A    except 

Migrate a test