# Copyright (c) 2006 The Regents of The University of Michigan
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#
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# this software without specific prior written permission.
#
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#
# Authors: Lisa Hsu

import m5
from m5.objects import *
m5.util.addToPath('../configs/')
from common import Benchmarks, FSConfig, SysPaths

test_sys = makeLinuxAlphaSystem('atomic',
                                SysConfig('netperf-stream-client.rcS'))
test_sys.kernel = SysPaths.binary('vmlinux')

# Dummy voltage domain for all test_sys clock domains
test_sys.voltage_domain = VoltageDomain()

# Create the system clock domain
test_sys.clk_domain = SrcClockDomain(clock = '1GHz',
                                     voltage_domain = test_sys.voltage_domain)

test_sys.cpu = AtomicSimpleCPU(cpu_id=0)
# create the interrupt controller
test_sys.cpu.createInterruptController()
test_sys.cpu.connectAllPorts(test_sys.membus)

# Create a seperate clock domain for components that should run at
# CPUs frequency
test_sys.cpu.clk_domain = SrcClockDomain(clock = '2GHz',
                                         voltage_domain =
                                         test_sys.voltage_domain)

# Create a separate clock domain for Ethernet
test_sys.tsunami.ethernet.clk_domain = SrcClockDomain(clock = '500MHz',
                                                      voltage_domain =
                                                      test_sys.voltage_domain)

# In contrast to the other (one-system) Tsunami configurations we do
# not have an IO cache but instead rely on an IO bridge for accesses
# from masters on the IO bus to the memory bus
test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
test_sys.iobridge.slave = test_sys.iobus.master
test_sys.iobridge.master = test_sys.membus.slave

test_sys.physmem = SimpleMemory(range = test_sys.mem_ranges[0])
test_sys.physmem.port = test_sys.membus.master

drive_sys = makeLinuxAlphaSystem('atomic',
                                 SysConfig('netperf-server.rcS'))
drive_sys.kernel = SysPaths.binary('vmlinux')
# Dummy voltage domain for all drive_sys clock domains
drive_sys.voltage_domain = VoltageDomain()
# Create the system clock domain
drive_sys.clk_domain = SrcClockDomain(clock = '1GHz',
                                      voltage_domain =
                                      drive_sys.voltage_domain)
drive_sys.cpu = AtomicSimpleCPU(cpu_id=0)
# create the interrupt controller
drive_sys.cpu.createInterruptController()
drive_sys.cpu.connectAllPorts(drive_sys.membus)

# Create a seperate clock domain for components that should run at
# CPUs frequency
drive_sys.cpu.clk_domain = SrcClockDomain(clock = '4GHz',
                                          voltage_domain =
                                          drive_sys.voltage_domain)

# Create a separate clock domain for Ethernet
drive_sys.tsunami.ethernet.clk_domain = SrcClockDomain(clock = '500MHz',
                                                       voltage_domain =
                                                       drive_sys.voltage_domain)

drive_sys.iobridge = Bridge(delay='50ns', ranges = drive_sys.mem_ranges)
drive_sys.iobridge.slave = drive_sys.iobus.master
drive_sys.iobridge.master = drive_sys.membus.slave

drive_sys.physmem = SimpleMemory(range = drive_sys.mem_ranges[0])
drive_sys.physmem.port = drive_sys.membus.master

root = makeDualRoot(True, test_sys, drive_sys, "ethertrace")

maxtick = 199999999

@@ -1689,24 +1689,33 @@
 %0Atest_sys = 
+FSConfig.
 makeLinuxAlp
@@ -1741,36 +1741,19 @@
     
-                            
+Benchmarks.
 SysC
@@ -3273,16 +3273,25 @@
 e_sys = 
+FSConfig.
 makeLinu
@@ -3321,37 +3321,19 @@
     
-                             
+Benchmarks.
 SysC
@@ -4719,16 +4719,25 @@
 %0Aroot = 
+FSConfig.
 makeDual

Fix import scope of test