@@ -0,0 +1,2933 @@
+#!/usr/bin/env python3%0A%0A#%0A# This file is part of LiteX-Boards.%0A#%0A# Copyright (c) 2020 Florent Kermarrec %3Cflorent@enjoy-digital.fr%3E%0A# SPDX-License-Identifier: BSD-2-Clause%0A%0Aimport os%0Aimport sys%0Aimport argparse%0A%0Afrom migen import *%0A%0Afrom litex.build.io import CRG%0A%0Afrom litex_boards.platforms import tinyfpga_bx%0A%0Afrom litex.soc.cores.spi_flash import SpiFlash%0Afrom litex.soc.integration.soc_core import *%0Afrom litex.soc.integration.soc import SoCRegion%0Afrom litex.soc.integration.builder import *%0Afrom litex.soc.cores.led import LedChaser%0A%0AkB = 1024%0AmB = 1024*kB%0A%0A# BaseSoC ------------------------------------------------------------------------------------------%0A%0Aclass BaseSoC(SoCCore):%0A    mem_map = %7B**SoCCore.mem_map, **%7B%22spiflash%22: 0x80000000%7D%7D%0A    def __init__(self, bios_flash_offset, **kwargs):%0A        sys_clk_freq = int(16e6)%0A        platform = tinyfpga_bx.Platform()%0A%0A        # Disable Integrated ROM since too large for iCE40.%0A        kwargs%5B%22integrated_rom_size%22%5D  = 0%0A%0A        # Set CPU variant / reset address%0A        kwargs%5B%22cpu_reset_address%22%5D = self.mem_map%5B%22spiflash%22%5D + bios_flash_offset%0A%0A        # SoCCore ----------------------------------------------------------------------------------%0A        SoCCore.__init__(self, platform, sys_clk_freq,%0A            ident          = %22LiteX SoC on TinyFPGA BX%22,%0A            ident_version  = True,%0A            **kwargs)%0A%0A        # CRG --------------------------------------------------------------------------------------%0A        self.submodules.crg = CRG(platform.request(%22clk16%22))%0A%0A        # SPI Flash --------------------------------------------------------------------------------%0A        self.add_spi_flash(mode=%221x%22, dummy_cycles=8)%0A%0A        # Add ROM linker region --------------------------------------------------------------------%0A        self.bus.add_region(%22rom%22, SoCRegion(%0A            origin = self.mem_map%5B%22spiflash%22%5D + bios_flash_offset,%0A            size   = 32*kB,%0A            linker = True)%0A        )%0A%0A        # Leds -------------------------------------------------------------------------------------%0A        self.submodules.leds = LedChaser(%0A            pads         = platform.request_all(%22user_led%22),%0A            sys_clk_freq = sys_clk_freq)%0A        self.add_csr(%22leds%22)%0A%0A# Build --------------------------------------------------------------------------------------------%0A%0Adef main():%0A    parser = argparse.ArgumentParser(description=%22LiteX SoC on TinyFPGA BX%22)%0A    parser.add_argument(%22--build%22,             action=%22store_true%22, help=%22Build bitstream%22)%0A    parser.add_argument(%22--bios-flash-offset%22, default=0x60000,     help=%22BIOS offset in SPI Flash (default: 0x60000)%22)%0A    builder_args(parser)%0A    soc_core_args(parser)%0A    args = parser.parse_args()%0A%0A    soc = BaseSoC(args.bios_flash_offset, **soc_core_argdict(args))%0A    builder = Builder(soc, **builder_argdict(args))%0A    builder.build(run=args.build)%0A%0Aif __name__ == %22__main__%22:%0A    main()%0A

add tinyfpga_bx target (based on icebreaker/fomu targets).