#!/usr/bin/env python3
# -*- coding: utf-8 -*-

from hwt.hdl.constants import READ, WRITE, Time
from hwt.simulator.simTestCase import SimTestCase
from hwtLib.abstract.busInterconnect import AUTO_ADDR, ALL
from hwtLib.ipif.interconnectMatrix import IpifInterconnectMatrix
from pyMathBitPrecise.bit_utils import mask


class IpifInterconnectMatrixTC(SimTestCase):
    CLK = 10 * Time.ns

    def mySetUp(self, read_latency=0, write_latency=0):
        SimTestCase.setUp(self)

        AUTO = AUTO_ADDR

        u = IpifInterconnectMatrix()
        u.MASTERS = (ALL, )
        u.SLAVES = (
            (0x0000, 0x0100),
            (0x0100, 0x0100),
            (AUTO,   0x0100),
            (AUTO,   0x1000),
        )
        self.DW = 32
        self.wordSize = self.DW // 8
        u.DATA_WIDTH = self.DW
        u.ADDR_WIDTH = u.getOptimalAddrSize()
        self.m = mask(self.wordSize)
        self.u = u
        self.compileSimAndStart(u)
        for s in u.m:
            s._ag.READ_LATENCY = read_latency
            s._ag.WRITE_LATENCY = write_latency

    def test_readAndWrite(self, read_latency=0, write_latency=0, N=2):
        self.mySetUp(read_latency=read_latency,
                     write_latency=write_latency)
        u = self.u
        offsets = [0x0, 0x100, 0x200, 0x1000]
        for s, o in zip(u._slaves, offsets):
            self.assertEqual(s[0], o)

        m = self.u.s[0]._ag
        s = [_s._ag for _s in self.u.m]
        MAGIC_R = 10
        MAGIC_W = 100

        expected = []
        for si, (_s, offset) in enumerate(zip(s, offsets)):
            d = {}
            for i in range(N):
                d[i] = _s.mem[i] = MAGIC_R + i + si * N
                m.requests.append((READ, i * 4 + offset))
                w_a = (i + N) * 4 + offset
                w_d = MAGIC_W + i + si * N
                m.requests.append((WRITE, w_a, w_d, self.m))
                d[(w_a - offset) // self.wordSize] = w_d
            expected.append(d)

        self.runSim((10 + 4 * len(offsets) * N) *
                    (max(read_latency, write_latency) + 1) * self.CLK)

        for i, (e, s) in enumerate(zip(expected, s)):
            d = {k: int(v) for k, v in s.mem.items()}
            self.assertDictEqual(d, e, i)


if __name__ == "__main__":
    import unittest
    suite = unittest.TestSuite()

    # suite.addTest(IpifInterconnectMatrixTC('test_read_lat1'))
    suite.addTest(unittest.makeSuite(IpifInterconnectMatrixTC))

    runner = unittest.TextTestRunner(verbosity=3)
    runner.run(suite)

@@ -1505,16 +1505,40 @@
 ed = %5B%5D%0A
+        expected_r = %5B%5D%0A
         
@@ -1687,32 +1687,72 @@
 _R + i + si * N%0A
+                expected_r.append(d%5Bi%5D)%0A
                 
@@ -1793,16 +1793,17 @@
 ffset))%0A
+%0A
         
@@ -2302,16 +2302,74 @@
 , e, i)%0A
+        self.assertValSequenceEqual(m.readed, expected_r)%0A
 %0A%0Aif __n

add missing check in sim