#
# ------------------------------------------------------------
# Copyright (c) SILAB , Physics Institute of Bonn University
# ------------------------------------------------------------
#
# SVN revision information:
#  $Rev::                       $:
#  $Author::                    $:
#  $Date::                      $:
#

from HL.HardwareLayer import HardwareLayer
from struct import pack, unpack


class fadc_rx(HardwareLayer):
    '''
    Fast ADC channel receiver
    '''

    def __init__(self, intf, conf):
        HardwareLayer.__init__(self, intf, conf)

    def init(self):
        self.reset()

    def reset(self):
        self._intf.write(self._conf['base_addr'], [0])

    def start(self):
        self._intf.write(self._conf['base_addr'] + 1, [0])

    def set_align_to_sync(self, value=False):
        '''
        Align data taking to a synchronisation signal, reset signal is the synchronisation signal (hardcoded connection in verilog code)
        '''
        current = self._intf.read(self._conf['base_addr'] + 2, 1)[0]
        self._intf.write(self._conf['base_addr'] + 2, [(current & 0xfe) | value])
    
    def get_align_to_sync(self):
        return True if (self._intf.read(self._conf['base_addr'] + 2, 1)[0] & 0x01) else False

    def set_data_count(self, count):
        self._intf.write(self._conf['base_addr'] + 3, unpack('BBBB', pack('>L', count))[1:4])

    def get_data_count(self):
        ret = self._intf.read(self._conf['base_addr'] + 3, 3)
        return ret[0] * (2 ** 16) + ret[1] * (2 ** 8) + ret[2]

    def is_done(self):
        return True if (self._intf.read(self._conf['base_addr'] + 1, 1)[0] & 0x01) else False

@@ -434,21 +434,16 @@
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@@ -460,24 +460,24 @@
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@@ -468,17 +468,16 @@
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@@ -512,29 +512,36 @@
         
-HardwareLayer
+super(fadc_rx, self)
 .__init_
@@ -534,38 +534,32 @@
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-self, 
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@@ -845,33 +845,33 @@
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@@ -897,17 +897,17 @@
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@@ -916,16 +916,17 @@
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+ 
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@@ -941,16 +941,23 @@
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@@ -1121,20 +1121,16 @@
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use super