from litex.gen.fhdl import *
from litex.soc.interconnect.csr import *


def binify(s, size):
    assert size % 8 == 0
    blen = int(size / 8)
    assert len(s) <= blen
    s = s+'\0'*(blen-len(s))
    return sum(ord(c) << i * 8 for i, c in enumerate(reversed(s)))


class PlatformInfo(Module, AutoCSR):
    def __init__(self, platform, target):
        self.platform = CSRStatus(64)
        self.target = CSRStatus(64)

        self.comb += [
            self.platform.status.eq(binify(platform, 64)),
            self.target.status.eq(binify(target, 64)),
        ]

@@ -161,16 +161,49 @@
  %3C= blen
+, %22%7B%7D %3C= %7B%7D%22.format(len(s), blen)
 %0A    s =
@@ -521,16 +521,20 @@
 platform
+%5B:8%5D
 , 64)),%0A
@@ -580,16 +580,20 @@
 y(target
+%5B:8%5D
 , 64)),%0A

Fix value length.