npcx: i2c: Don't set ACK when using FIFO mode
npcx: i2c: Don't set ACK when using FIFO mode

In the single-byte mode, the I2C driver sets ACK bit in the SMBnCTL1
register to NACK the last byte when receiving data.
In the FIFO mode, it sets the LAST bit in the SMBnTXF_CTL register in
most of the protocol except "receive byte" and "read byte" protocols.
(In these two protocols, both LAST and ACK bit are set.) In the normal
case, there is no problem to set them together. However, it was observed
in b:163076059 that the ACK bit is not cleared after a transaction when
the I2C bus encounters an error. This CL changes the I2C driver to set
the ACK bit only when it runs on the single-byte mode.

BRANCH=none
BUG=b:163076059
TEST=pass "make buildall"
TEST=test test "read byte" and "receive byte" protocol on EVB about 500
thousands of transactions.
test=build and flash image on yorp, check yorp can boot up to OS and
there is no I2C error msg in the EC console.

Signed-off-by: CHLin <4865d89268068846db8afe2dcacc793288c792a0@nuvoton.com>
Change-Id: Ife31d6e35caa9ccbb108571a887c4fab4d802406
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2393404
Reviewed-by: Edward Hill <db1406b34e091703092b6b136bdfeb2c8125fc0e@chromium.org>
Commit-Queue: Edward Hill <db1406b34e091703092b6b136bdfeb2c8125fc0e@chromium.org>
Tested-by: Edward Hill <db1406b34e091703092b6b136bdfeb2c8125fc0e@chromium.org>

coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec