Delayed output of vvp dff to end of current time slot.
Delayed output of vvp dff to end of current time slot.

Flip-flops are generally modelled in behavioural code using non-blocking
assignments. This change makes the synthesised code behave the same as
the behavioural code. It's a more realistic model of a real flip-flop
too, which will always have some clock-to-output delay.

themperek/iverilog,themperek/iverilog,themperek/iverilog