O3: Allow a store entry to store up to 16 bytes (instead of TheISA::IntReg).
O3: Allow a store entry to store up to 16 bytes (instead of TheISA::IntReg).

The store queue doesn't need to be ISA specific and architectures can
frequently store more than an int registers worth of data. A 128 bits seems
more common, but even 256 bits may be appropriate. Pretty much anything less
than a cache line size is buildable.

gedare/gem5,samueldotj/TeeRISC-Simulator,KuroeKurose/gem5,rallylee/gem5,aclifton/cpeg853-gem5,briancoutinho0905/2dsampling,KuroeKurose/gem5,rjschof/gem5,austinharris/gem5-riscv,rallylee/gem5,rallylee/gem5,rjschof/gem5,samueldotj/TeeRISC-Simulator,austinharris/gem5-riscv,kaiyuanl/gem5,Weil0ng/gem5,markoshorro/gem5,gem5/gem5,cancro7/gem5,sobercoder/gem5,cancro7/gem5,cancro7/gem5,kaiyuanl/gem5,sobercoder/gem5,markoshorro/gem5,gedare/gem5,KuroeKurose/gem5,TUD-OS/gem5-dtu,rjschof/gem5,yb-kim/gemV,samueldotj/TeeRISC-Simulator,TUD-OS/gem5-dtu,gem5/gem5,qizenguf/MLC-STT,yb-kim/gemV,austinharris/gem5-riscv,SanchayanMaity/gem5,aclifton/cpeg853-gem5,briancoutinho0905/2dsampling,cancro7/gem5,kaiyuanl/gem5,sobercoder/gem5,briancoutinho0905/2dsampling,yb-kim/gemV,qizenguf/MLC-STT,zlfben/gem5,powerjg/gem5-ci-test,TUD-OS/gem5-dtu,powerjg/gem5-ci-test,zlfben/gem5,HwisooSo/gemV-update,samueldotj/TeeRISC-Simulator,yb-kim/gemV,rallylee/gem5,gem5/gem5,qizenguf/MLC-STT,Weil0ng/gem5,qizenguf/MLC-STT,zlfben/gem5,yb-kim/gemV,rjschof/gem5,powerjg/gem5-ci-test,joerocklin/gem5,Weil0ng/gem5,aclifton/cpeg853-gem5,markoshorro/gem5,cancro7/gem5,samueldotj/TeeRISC-Simulator,briancoutinho0905/2dsampling,yb-kim/gemV,qizenguf/MLC-STT,qizenguf/MLC-STT,sobercoder/gem5,HwisooSo/gemV-update,joerocklin/gem5,markoshorro/gem5,markoshorro/gem5,gedare/gem5,sobercoder/gem5,powerjg/gem5-ci-test,austinharris/gem5-riscv,HwisooSo/gemV-update,SanchayanMaity/gem5,kaiyuanl/gem5,TUD-OS/gem5-dtu,KuroeKurose/gem5,KuroeKurose/gem5,yb-kim/gemV,TUD-OS/gem5-dtu,sobercoder/gem5,samueldotj/TeeRISC-Simulator,aclifton/cpeg853-gem5,SanchayanMaity/gem5,HwisooSo/gemV-update,joerocklin/gem5,austinharris/gem5-riscv,zlfben/gem5,kaiyuanl/gem5,markoshorro/gem5,gem5/gem5,aclifton/cpeg853-gem5,rjschof/gem5,gedare/gem5,samueldotj/TeeRISC-Simulator,rjschof/gem5,zlfben/gem5,SanchayanMaity/gem5,zlfben/gem5,rallylee/gem5,rjschof/gem5,markoshorro/gem5,joerocklin/gem5,Weil0ng/gem5,HwisooSo/gemV-update,joerocklin/gem5,kaiyuanl/gem5,gedare/gem5,KuroeKurose/gem5,joerocklin/gem5,rallylee/gem5,TUD-OS/gem5-dtu,austinharris/gem5-riscv,SanchayanMaity/gem5,powerjg/gem5-ci-test,gedare/gem5,austinharris/gem5-riscv,yb-kim/gemV,KuroeKurose/gem5,Weil0ng/gem5,qizenguf/MLC-STT,cancro7/gem5,Weil0ng/gem5,HwisooSo/gemV-update,HwisooSo/gemV-update,aclifton/cpeg853-gem5,briancoutinho0905/2dsampling,rallylee/gem5,briancoutinho0905/2dsampling,zlfben/gem5,briancoutinho0905/2dsampling,gem5/gem5,sobercoder/gem5,cancro7/gem5,SanchayanMaity/gem5,aclifton/cpeg853-gem5,kaiyuanl/gem5,joerocklin/gem5,TUD-OS/gem5-dtu,gem5/gem5,Weil0ng/gem5,SanchayanMaity/gem5,gedare/gem5,gem5/gem5,powerjg/gem5-ci-test,powerjg/gem5-ci-test,joerocklin/gem5