[dv/hmac] Fix alert_test register scb error
[dv/hmac] Fix alert_test register scb error

Design recently added an `alert_test` register. In stress_all_with_rand_reset
test, we are reading all CSRs. This PR adds `alert_test` to the list of
valid registers.

Signed-off-by: Cindy Chen <399ad771a111eac8923348b1e2af093034e5d4f1@opentitan.org>

lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan