i965/fs: Migrate register spills and fills to the IR builder.
i965/fs: Migrate register spills and fills to the IR builder.

Yes, it's incorrect to use the 0-th channel enable group
unconditionally without considering the execution and regioning
controls of the instruction that uses the spilled value, but it
matches the previous behaviour exactly, the builder just makes the
preexisting problem more obvious because emitting an instruction of
non-native SIMD width without having called .group() or .exec_all()
explicitly would have led to an assertion failure.

I'll fix the problem in a follow-up series, as the solution is going
to be non-trivial.

Reviewed-by: Matt Turner <789b315743a28dd066a4ba1459c35951c291d8a6@gmail.com>

metora/MesaGLSLCompiler,metora/MesaGLSLCompiler,metora/MesaGLSLCompiler