Fix brw instruction field "flag"
Fix brw instruction field "flag"

bits2.da1.flag_subreg_nr is missing in brw_instruction.
The location of bits2.da1.flag_reg_nr is wrong. See IVB spec.

This patch fixes bugs above, also
make disassembler output correct flag_subreg_nr for conditional modifier
and prediction.

Before we change it:
(+f0.1) cmp.l(8)      null g12<8,8,1>D g2.2<0,1,0>D {align1 WE_normal 1Q};

After we change it:
(+f1.1) cmp.l.f1.1(8) null g12<8,8,1>D g2.2<0,1,0>D {align1 WE_normal 1Q};

Although flag_reg_nr has moved position, other code is still right,
because if we use f0.1 before, now we use f1.0

Signed-off-by: Homer Hsing <f17cb7083eb6a94c3fb9d8f09ceefa518f721ab2@intel.com>
Reviewed-by: Lu, Guanqun <2dad72ae5fe48bf7bd43ddccece96ab3f4a6c25d@intel.com>

ignatenkobrain/beignet,zhenyw/beignet,wdv4758h/beignet,freedesktop-unofficial-mirror/beignet,freedesktop-unofficial-mirror/beignet,zhenyw/beignet,ignatenkobrain/beignet,freedesktop-unofficial-mirror/beignet,freedesktop-unofficial-mirror/beignet,zhenyw/beignet,ignatenkobrain/beignet,wdv4758h/beignet,ignatenkobrain/beignet,zhenyw/beignet,wdv4758h/beignet,wdv4758h/beignet,ignatenkobrain/beignet,wdv4758h/beignet,zhenyw/beignet