[rtl] Bug Fix related to SRLI/SLLI Decoding
[rtl] Bug Fix related to SRLI/SLLI Decoding

This commit fixes a bug where the SRLI or SLLI instruction passes as valid when they
have 25/26 bitfields as 1. In ISA they would not have 1 at their 25/26th bitfields.

Signed-off-by: Canberk Topal <e6b05429a51cc3258c31cb1f7836595b60921a29@lowrisc.org>

lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan