arch-riscv: fixed read of {M,S,U}TVEC.
arch-riscv: fixed read of {M,S,U}TVEC.

As stated in 4.1.4 of the privileged ISA manual, the BASE field in the
STVEC register contains the bits [SXLEN-1:2] of the base address, not
the base address shifted left by 2.

Change-Id: I799ec0dc1cbd7b271b91b53adb033a5d1ca3306f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25648
Tested-by: kokoro <2ac7b1f3fa578934c95181d4272be0d3bca00121@google.com>
Reviewed-by: Jason Lowe-Power <92de577f37050ad05b60626d2f17913f40dcb1a2@gmail.com>
Maintainer: Jason Lowe-Power <92de577f37050ad05b60626d2f17913f40dcb1a2@gmail.com>

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