fpga: zynq-fpga: Fix unbalanced clock handling
fpga: zynq-fpga: Fix unbalanced clock handling

This commit fixes the unbalanced clock handling, where
a failed probe would leave the clock with an enable count of -1.

Reported-by: Josh Cartwright <8ab3595d4bac68c19ea44f183d51b50908f1de91@ni.com>
Signed-off-by: Moritz Fischer <16c4312f096cb05ec900643fe7a5f22f7761ab4a@ettus.com>
Signed-off-by: Greg Kroah-Hartman <4645f7897fd33786a2ee1264d590b3c400559d85@linuxfoundation.org>

KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs