mem: Add precharge all (PREA) to the DRAM controller
mem: Add precharge all (PREA) to the DRAM controller

This patch adds the basic ingredients for a precharge all operation,
to be used in conjunction with DRAM power modelling.

Currently we do not try and apply any cleverness when precharging all
banks, thus even if only a single bank is open we use PREA as opposed
to PRE. At the moment we only have a single tRP (tRPpb), and do not
model the slightly longer all-bank precharge constraint (tRPab).

HwisooSo/gemV-update,KuroeKurose/gem5,rallylee/gem5,gem5/gem5,zlfben/gem5,HwisooSo/gemV-update,powerjg/gem5-ci-test,kaiyuanl/gem5,HwisooSo/gemV-update,briancoutinho0905/2dsampling,SanchayanMaity/gem5,HwisooSo/gemV-update,kaiyuanl/gem5,cancro7/gem5,TUD-OS/gem5-dtu,gem5/gem5,qizenguf/MLC-STT,gedare/gem5,sobercoder/gem5,markoshorro/gem5,gedare/gem5,austinharris/gem5-riscv,rjschof/gem5,sobercoder/gem5,Weil0ng/gem5,rallylee/gem5,rallylee/gem5,sobercoder/gem5,powerjg/gem5-ci-test,KuroeKurose/gem5,markoshorro/gem5,rjschof/gem5,cancro7/gem5,Weil0ng/gem5,kaiyuanl/gem5,briancoutinho0905/2dsampling,cancro7/gem5,rjschof/gem5,KuroeKurose/gem5,briancoutinho0905/2dsampling,SanchayanMaity/gem5,cancro7/gem5,briancoutinho0905/2dsampling,qizenguf/MLC-STT,aclifton/cpeg853-gem5,gem5/gem5,sobercoder/gem5,SanchayanMaity/gem5,HwisooSo/gemV-update,Weil0ng/gem5,rjschof/gem5,Weil0ng/gem5,zlfben/gem5,rallylee/gem5,briancoutinho0905/2dsampling,TUD-OS/gem5-dtu,Weil0ng/gem5,TUD-OS/gem5-dtu,powerjg/gem5-ci-test,zlfben/gem5,sobercoder/gem5,Weil0ng/gem5,kaiyuanl/gem5,SanchayanMaity/gem5,gedare/gem5,kaiyuanl/gem5,SanchayanMaity/gem5,rjschof/gem5,markoshorro/gem5,powerjg/gem5-ci-test,qizenguf/MLC-STT,cancro7/gem5,rjschof/gem5,gedare/gem5,cancro7/gem5,kaiyuanl/gem5,gedare/gem5,gedare/gem5,austinharris/gem5-riscv,TUD-OS/gem5-dtu,markoshorro/gem5,qizenguf/MLC-STT,briancoutinho0905/2dsampling,qizenguf/MLC-STT,HwisooSo/gemV-update,powerjg/gem5-ci-test,TUD-OS/gem5-dtu,rallylee/gem5,markoshorro/gem5,KuroeKurose/gem5,zlfben/gem5,aclifton/cpeg853-gem5,zlfben/gem5,KuroeKurose/gem5,gem5/gem5,cancro7/gem5,aclifton/cpeg853-gem5,markoshorro/gem5,kaiyuanl/gem5,powerjg/gem5-ci-test,austinharris/gem5-riscv,powerjg/gem5-ci-test,qizenguf/MLC-STT,aclifton/cpeg853-gem5,zlfben/gem5,KuroeKurose/gem5,KuroeKurose/gem5,qizenguf/MLC-STT,aclifton/cpeg853-gem5,Weil0ng/gem5,briancoutinho0905/2dsampling,aclifton/cpeg853-gem5,gem5/gem5,HwisooSo/gemV-update,rjschof/gem5,austinharris/gem5-riscv,austinharris/gem5-riscv,gedare/gem5,rallylee/gem5,SanchayanMaity/gem5,sobercoder/gem5,austinharris/gem5-riscv,zlfben/gem5,austinharris/gem5-riscv,gem5/gem5,SanchayanMaity/gem5,TUD-OS/gem5-dtu,rallylee/gem5,TUD-OS/gem5-dtu,markoshorro/gem5,gem5/gem5,sobercoder/gem5,aclifton/cpeg853-gem5