Optimise add,sub,and,or,xor where rd and (rs1 or rs2) are spilt
Optimise add,sub,and,or,xor where rd and (rs1 or rs2) are spilt

- Elide a load from the 3 instruction sequence by loading the
  source operand into a temporary and performing the ALU op on
  the temporary. Improve the worst case for 3 spilt registers
  to emitting 3 instructions instead of 4.

rv8-io/rv8,rv8-io/rv8,rv8-io/rv8