config, x86: Ensure that PCI devs get bridged to the memory bus
config, x86: Ensure that PCI devs get bridged to the memory bus

This patch force IO device to be mapped to 0xC0000000-0xFFFF0000 by
reserve anything between the end of memory and 3GB if memory is less
than 3GB. It also statically bridge these address range to the IO bus,
which guaranty access to pci address space will pass though bridge to
iobus.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

rallylee/gem5,rallylee/gem5,aclifton/cpeg853-gem5,powerjg/gem5-ci-test,gem5/gem5,markoshorro/gem5,TUD-OS/gem5-dtu,sobercoder/gem5,kaiyuanl/gem5,briancoutinho0905/2dsampling,SanchayanMaity/gem5,KuroeKurose/gem5,gem5/gem5,rjschof/gem5,gedare/gem5,briancoutinho0905/2dsampling,kaiyuanl/gem5,aclifton/cpeg853-gem5,cancro7/gem5,TUD-OS/gem5-dtu,kaiyuanl/gem5,gem5/gem5,qizenguf/MLC-STT,markoshorro/gem5,cancro7/gem5,kaiyuanl/gem5,gedare/gem5,briancoutinho0905/2dsampling,cancro7/gem5,HwisooSo/gemV-update,markoshorro/gem5,zlfben/gem5,Weil0ng/gem5,gem5/gem5,powerjg/gem5-ci-test,TUD-OS/gem5-dtu,zlfben/gem5,briancoutinho0905/2dsampling,aclifton/cpeg853-gem5,sobercoder/gem5,qizenguf/MLC-STT,powerjg/gem5-ci-test,gem5/gem5,HwisooSo/gemV-update,markoshorro/gem5,sobercoder/gem5,rjschof/gem5,SanchayanMaity/gem5,rjschof/gem5,qizenguf/MLC-STT,zlfben/gem5,rjschof/gem5,HwisooSo/gemV-update,rallylee/gem5,TUD-OS/gem5-dtu,zlfben/gem5,cancro7/gem5,gedare/gem5,sobercoder/gem5,aclifton/cpeg853-gem5,powerjg/gem5-ci-test,zlfben/gem5,austinharris/gem5-riscv,aclifton/cpeg853-gem5,cancro7/gem5,rallylee/gem5,Weil0ng/gem5,TUD-OS/gem5-dtu,Weil0ng/gem5,powerjg/gem5-ci-test,briancoutinho0905/2dsampling,SanchayanMaity/gem5,gedare/gem5,briancoutinho0905/2dsampling,markoshorro/gem5,KuroeKurose/gem5,sobercoder/gem5,powerjg/gem5-ci-test,rallylee/gem5,Weil0ng/gem5,cancro7/gem5,austinharris/gem5-riscv,rjschof/gem5,zlfben/gem5,Weil0ng/gem5,gedare/gem5,SanchayanMaity/gem5,KuroeKurose/gem5,TUD-OS/gem5-dtu,rallylee/gem5,austinharris/gem5-riscv,qizenguf/MLC-STT,rjschof/gem5,austinharris/gem5-riscv,gedare/gem5,aclifton/cpeg853-gem5,austinharris/gem5-riscv,HwisooSo/gemV-update,qizenguf/MLC-STT,Weil0ng/gem5,briancoutinho0905/2dsampling,powerjg/gem5-ci-test,gem5/gem5,markoshorro/gem5,rjschof/gem5,kaiyuanl/gem5,cancro7/gem5,KuroeKurose/gem5,qizenguf/MLC-STT,KuroeKurose/gem5,HwisooSo/gemV-update,gedare/gem5,kaiyuanl/gem5,SanchayanMaity/gem5,HwisooSo/gemV-update,SanchayanMaity/gem5,zlfben/gem5,austinharris/gem5-riscv,qizenguf/MLC-STT,sobercoder/gem5,austinharris/gem5-riscv,sobercoder/gem5,KuroeKurose/gem5,Weil0ng/gem5,aclifton/cpeg853-gem5,markoshorro/gem5,SanchayanMaity/gem5,KuroeKurose/gem5,kaiyuanl/gem5,HwisooSo/gemV-update,gem5/gem5,rallylee/gem5,TUD-OS/gem5-dtu