cpu/stm32: fix l4l5wb clock configuration
cpu/stm32: fix l4l5wb clock configuration

Default values were wrong for WB when using HSE 32MHz as PLL input source
Default PLL input source was wrong when not using HSE and the board
provides an HSE

authmillenon/RIOT,OlegHahm/RIOT,kaspar030/RIOT,OlegHahm/RIOT,RIOT-OS/RIOT,kaspar030/RIOT,kaspar030/RIOT,kYc0o/RIOT,kYc0o/RIOT,OTAkeys/RIOT,RIOT-OS/RIOT,RIOT-OS/RIOT,jasonatran/RIOT,miri64/RIOT,authmillenon/RIOT,kaspar030/RIOT,OTAkeys/RIOT,ant9000/RIOT,miri64/RIOT,kYc0o/RIOT,kaspar030/RIOT,RIOT-OS/RIOT,jasonatran/RIOT,jasonatran/RIOT,jasonatran/RIOT,ant9000/RIOT,RIOT-OS/RIOT,kYc0o/RIOT,miri64/RIOT,OlegHahm/RIOT,jasonatran/RIOT,OTAkeys/RIOT,ant9000/RIOT,authmillenon/RIOT,OTAkeys/RIOT,ant9000/RIOT,miri64/RIOT,OlegHahm/RIOT,authmillenon/RIOT,ant9000/RIOT,OTAkeys/RIOT,authmillenon/RIOT,kYc0o/RIOT,OlegHahm/RIOT,miri64/RIOT,authmillenon/RIOT