Encoder and Peripheral Register tested. Fixed SpiSlave, MISO was generated one SCK cycle to late and one more cycle was needed for the internal bus before reading bus_i.data after read.
Encoder and Peripheral Register tested.
Fixed SpiSlave, MISO was generated one SCK cycle to late and one more cycle was needed for the internal bus before reading bus_i.data after read.

loa-org/loa-hdl