Change 'name_slice_part' to accept multi-level slicing
Change 'name_slice_part' to accept multi-level slicing

VHDL supports multiple levels of one-dimensional slicing in assignments. Example:
    MEM(2)(3) <= a;

antlr/grammars-v4,antlr/grammars-v4,antlr/grammars-v4,antlr/grammars-v4,antlr/grammars-v4,antlr/grammars-v4,antlr/grammars-v4,antlr/grammars-v4,antlr/grammars-v4,antlr/grammars-v4,antlr/grammars-v4,antlr/grammars-v4