MIPS: Netlogic: L1D cacheflush before thread enable on XLPII
MIPS: Netlogic: L1D cacheflush before thread enable on XLPII

On XLPII CPUs, the L1D cache has to be flushed with regular cache
operations before enabling threads in a core.

Signed-off-by: Jayachandran C <1bc8cf2274d8680f3a9b88ac7b7d2a9e0d1d4ca2@broadcom.com>
Signed-off-by: John Crispin <be6487f9df4dce44a640672d6c07330104d43593@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6276/

KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs