dts: arm: stm32h7 devices have spi clock source on pll1_q
dts: arm: stm32h7 devices have spi clock source on pll1_q

All the SPI1,2,3 clock of the stm32h7x mcus
are sourced by the PLL1_Q by default. This must be set
in the DTS to have a valid clock rate calculation.
The pll1_q is divided by the <div-q> property of the pll node.

Signed-off-by: Francois Ramu <b83adc7f8a23ee911a37fcb61c4033581aae0b7a@st.com>

galak/zephyr,zephyrproject-rtos/zephyr,zephyrproject-rtos/zephyr,zephyrproject-rtos/zephyr,finikorg/zephyr,finikorg/zephyr,galak/zephyr,zephyrproject-rtos/zephyr,finikorg/zephyr,zephyrproject-rtos/zephyr,galak/zephyr,finikorg/zephyr,galak/zephyr,galak/zephyr,finikorg/zephyr