ARM: Reset simulation statistics when pref counters are reset.
ARM: Reset simulation statistics when pref counters are reset.

The ARM performance counters are not currently supported by the model.
This patch interprets a 'reset performance counters' command to mean 'reset
the simulator statistics' instead.

rallylee/gem5,rjschof/gem5,kaiyuanl/gem5,rallylee/gem5,qizenguf/MLC-STT,yb-kim/gemV,powerjg/gem5-ci-test,zlfben/gem5,Weil0ng/gem5,rallylee/gem5,KuroeKurose/gem5,SanchayanMaity/gem5,rallylee/gem5,briancoutinho0905/2dsampling,zlfben/gem5,sobercoder/gem5,SanchayanMaity/gem5,joerocklin/gem5,qizenguf/MLC-STT,qizenguf/MLC-STT,zlfben/gem5,rjschof/gem5,KuroeKurose/gem5,SanchayanMaity/gem5,rallylee/gem5,Weil0ng/gem5,aclifton/cpeg853-gem5,zlfben/gem5,austinharris/gem5-riscv,cancro7/gem5,cancro7/gem5,joerocklin/gem5,cancro7/gem5,kaiyuanl/gem5,gem5/gem5,markoshorro/gem5,KuroeKurose/gem5,yb-kim/gemV,gem5/gem5,samueldotj/TeeRISC-Simulator,yb-kim/gemV,kaiyuanl/gem5,aclifton/cpeg853-gem5,yb-kim/gemV,TUD-OS/gem5-dtu,KuroeKurose/gem5,yb-kim/gemV,cancro7/gem5,aclifton/cpeg853-gem5,Weil0ng/gem5,qizenguf/MLC-STT,yb-kim/gemV,austinharris/gem5-riscv,samueldotj/TeeRISC-Simulator,zlfben/gem5,joerocklin/gem5,TUD-OS/gem5-dtu,gem5/gem5,powerjg/gem5-ci-test,joerocklin/gem5,HwisooSo/gemV-update,Weil0ng/gem5,zlfben/gem5,KuroeKurose/gem5,sobercoder/gem5,powerjg/gem5-ci-test,yb-kim/gemV,markoshorro/gem5,austinharris/gem5-riscv,HwisooSo/gemV-update,rjschof/gem5,gedare/gem5,aclifton/cpeg853-gem5,gedare/gem5,markoshorro/gem5,TUD-OS/gem5-dtu,sobercoder/gem5,rjschof/gem5,joerocklin/gem5,austinharris/gem5-riscv,rjschof/gem5,SanchayanMaity/gem5,Weil0ng/gem5,gedare/gem5,rjschof/gem5,gedare/gem5,sobercoder/gem5,powerjg/gem5-ci-test,qizenguf/MLC-STT,kaiyuanl/gem5,SanchayanMaity/gem5,HwisooSo/gemV-update,austinharris/gem5-riscv,samueldotj/TeeRISC-Simulator,briancoutinho0905/2dsampling,SanchayanMaity/gem5,powerjg/gem5-ci-test,HwisooSo/gemV-update,TUD-OS/gem5-dtu,samueldotj/TeeRISC-Simulator,kaiyuanl/gem5,briancoutinho0905/2dsampling,briancoutinho0905/2dsampling,kaiyuanl/gem5,samueldotj/TeeRISC-Simulator,aclifton/cpeg853-gem5,HwisooSo/gemV-update,TUD-OS/gem5-dtu,joerocklin/gem5,gem5/gem5,gedare/gem5,markoshorro/gem5,KuroeKurose/gem5,zlfben/gem5,cancro7/gem5,gem5/gem5,austinharris/gem5-riscv,HwisooSo/gemV-update,rallylee/gem5,joerocklin/gem5,Weil0ng/gem5,aclifton/cpeg853-gem5,sobercoder/gem5,powerjg/gem5-ci-test,aclifton/cpeg853-gem5,gedare/gem5,cancro7/gem5,cancro7/gem5,yb-kim/gemV,TUD-OS/gem5-dtu,joerocklin/gem5,markoshorro/gem5,powerjg/gem5-ci-test,rallylee/gem5,SanchayanMaity/gem5,TUD-OS/gem5-dtu,rjschof/gem5,markoshorro/gem5,gem5/gem5,qizenguf/MLC-STT,gedare/gem5,sobercoder/gem5,kaiyuanl/gem5,HwisooSo/gemV-update,qizenguf/MLC-STT,briancoutinho0905/2dsampling,samueldotj/TeeRISC-Simulator,briancoutinho0905/2dsampling,sobercoder/gem5,austinharris/gem5-riscv,gem5/gem5,briancoutinho0905/2dsampling,KuroeKurose/gem5,samueldotj/TeeRISC-Simulator,markoshorro/gem5,Weil0ng/gem5