Correct/complete a partially-disabled TX interrupt mitigation configuration.
Correct/complete a partially-disabled TX interrupt mitigation configuration.

Although a previous commit disabled TX interrupt mitigation handling and
configuration, the mask register bits weren't setup correctly.

jrobhoward/SCADAbase,jrobhoward/SCADAbase,jrobhoward/SCADAbase,jrobhoward/SCADAbase,jrobhoward/SCADAbase,jrobhoward/SCADAbase,jrobhoward/SCADAbase,jrobhoward/SCADAbase,jrobhoward/SCADAbase,jrobhoward/SCADAbase,jrobhoward/SCADAbase