mtl: soc: store power gating state in D3 state
mtl: soc: store power gating state in D3 state

Power gating register must be stored when CPU is in
power off state

Signed-off-by: Marcin Szkudlinski <2c84ee38d6d890101459fb64812a3a38803e9b60@intel.com>

zephyrproject-rtos/zephyr,zephyrproject-rtos/zephyr,zephyrproject-rtos/zephyr,zephyrproject-rtos/zephyr,zephyrproject-rtos/zephyr