clk: pistachio: Lock the PLL when enabled upon rate change
clk: pistachio: Lock the PLL when enabled upon rate change

Currently, when the rate is changed, the driver makes sure the
PLL is enabled before doing so. This is done because the PLL
cannot be locked while disabled. Once locked, the drivers
returns the PLL to its previous enable/disable state.

This is a bit cumbersome, and can be simplified.

This commit reworks the .set_rate() functions for the integer
and fractional PLLs. Upon rate change, the PLL is now locked
only if it's already enabled.

Also, the driver locks the PLL on .enable(). This makes sure
the PLL is locked when enabled, and not locked when disabled.

Signed-off-by: Andrew Bresticker <6f9d97df82107736b1c4f0e11d74242c25499ec8@chromium.org>
Signed-off-by: Ezequiel Garcia <7248f52d8926fd82a5eb079a13afe9dd79e34c7a@imgtec.com>
Signed-off-by: Stephen Boyd <010521127f513270fe503d86ab8316ac5147f4b7@codeaurora.org>

KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs