doc: Compress the text vertically.
doc: Compress the text vertically.

Specifically:
  * use smaller page margins;
  * use smaller margin under figures;
  * expand all tables to full page-width to make them less tall,
    which also improves how they look;
  * use compact item lists within tables;
  * remove newlines in function descriptions after parameter value
    (but keep it for condition descriptions);
  * remove now-unneeded page breaks before figures.

After these changes all but two Verilog usage examples end up
on the same page as the rest of description.

rqou/openfpga,azonenberg/openfpga,azonenberg/openfpga,rqou/openfpga,azonenberg/openfpga,rqou/openfpga,rqou/openfpga,azonenberg/openfpga,rqou/openfpga,azonenberg/openfpga