[spi_device] Adjust timing of p2s_sent
[spi_device] Adjust timing of p2s_sent

In previous design TPM sees `sck_p2s_sent` signal that is latched in SCK
posedge of `isck_p2s_sent`.

Problem:

    `sck_p2s_sent` is half clock delayed signal of `isck_p2s_sent`. The
    signal is not visible at the last beat of Address phase. After
    moving to StartByte (if FIFO is ready), the state machine sees the
    `p2s_sent` right away. Then moves to the next state without sending
    StartByte.

To avoid this behavior, two options are possible:

1. Use `isck_p2s_sent` signal directly. Then, the logic sees the valid
   `p2s_sent` the last half of the SCK. It requires the timing to be
   less than half of SCK period. It is already one of the SPI_DEVICE
   constraint.

2. Compute p2s_sent in SCK domain. Running another `bitcnt` in SCK, the
   SCK also can compute when p2s_sent is asserted.

This commit chooses Option 1.

Signed-off-by: Eunchan Kim <cb7bc7ceb22698f298c67faa994fd9ddf3cab298@opentitan.org>

lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan