[rtl/sram_ctrl] update error signaling logic
[rtl/sram_ctrl] update error signaling logic

Currently SRAM controller performs a bitwise OR of the 2-bit error
signal to check whether there are any correctable/uncorrectable memory
errors.

However correctable memory errors are not supported by the SRAM.

This patch adds an assertion to ensure that the error bit
indicating a correctable error never goes high and updates the error
signaling logic to only rely on the bit indicating uncorrectable errors.

Signed-off-by: Udi Jonnalagadda <790cd677b6a22a419ffcfe0eb4293d8866eb70c9@google.com>

lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan