Fixed incorrect acc_fir_i port width.
Fixed incorrect acc_fir_i port width.

Signed-off-by: Maciej Kurc <572803cc6e8d7bb35033942e4b03254951a2e0d6@antmicro.com>

chipsalliance/yosys-f4pga-plugins,chipsalliance/yosys-f4pga-plugins