Modified rules for primitive gate port expression widths.
Modified rules for primitive gate port expression widths.

The IEEE standard states that the port expressions used for arrays
of primitive gates must be the exact width required, but is silent
about the requirements for single instances. The consensus among
other simulators is that for input ports of single instances, the
expression is silently truncated to a single bit.

This patch also fixes a compiler crash if an error is found when
elaborating a primitive gate port expression.

themperek/iverilog,CastMi/iverilog,themperek/iverilog,CastMi/iverilog,CastMi/iverilog,themperek/iverilog