read_aiger to create sane $lut names, and rename when renaming driving wire
read_aiger to create sane $lut names, and rename when renaming driving wire

antmicro/yosys,YosysHQ/yosys,SymbiFlow/yosys,cliffordwolf/yosys,cliffordwolf/yosys,SymbiFlow/yosys,antmicro/yosys,antmicro/yosys,cliffordwolf/yosys,YosysHQ/yosys,YosysHQ/yosys,antmicro/yosys,YosysHQ/yosys,YosysHQ/yosys,cliffordwolf/yosys,YosysHQ/yosys,SymbiFlow/yosys,SymbiFlow/yosys,antmicro/yosys,SymbiFlow/yosys,antmicro/yosys,YosysHQ/yosys,cliffordwolf/yosys,SymbiFlow/yosys,cliffordwolf/yosys,SymbiFlow/yosys,cliffordwolf/yosys,antmicro/yosys,SymbiFlow/yosys,cliffordwolf/yosys,YosysHQ/yosys,antmicro/yosys,cliffordwolf/yosys