x86inc: Support memory operands in src1 in 3-operand instructions
x86inc: Support memory operands in src1 in 3-operand instructions

Particularly in code that makes heavy use of macros it's possible
to end up with 3-operand instructions with a memory operand in src1.
In the case of SSE this works fine due to automatic move insertions,
but in AVX that fails since memory operands are only allowed in src2.

The main purpose of this feature is to minimize the amount of code
changes required to facilitate conversion of existing SSE code to AVX.

xiph/rav1e,xiph/rav1e