OvmfPkg: IndustryStandard/Q35MchIch9.h: add PCIEXBAR macros
OvmfPkg: IndustryStandard/Q35MchIch9.h: add PCIEXBAR macros

Section 5.1.16 ("PCIEXBAR -- PCI Express Register Range Base Address") in
Intel document #316966-002 (already referenced near the top of this header
file) describes the Q35 DRAM Controller register that configures the
memory-mapped PCI config space (also known as MMCONFIG, and ECAM /
Enhanced Configuration Access Method).

In this patch we add the macros we'll need later. We'll only support the
256 MB memory-mapped config space -- enough for buses [0, 255].

Cc: Gabriel Somlo <0bda901f34b59fdc0593dc5ef2b1790278d1dfd8@cmu.edu>
Cc: Gerd Hoffmann <cad73e70082427fddc9be3baaf34e698dffd21c0@redhat.com>
Cc: Jordan Justen <a79006884ba9cf5f4f7fcbb92a15b208780d8c97@intel.com>
Cc: Marcel Apfelbaum <44592b4eea36663c86b994bb0ea99d15309c1c7d@redhat.com>
Cc: Michał Zegan <60ced9b9d4fecee1bf8c56beb3fc951573933e4e@poczta.onet.pl>
Ref: https://github.com/tianocore/edk2/issues/32
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <7437296077edea1cb64451c122c4dac071f0cfbc@redhat.com>
Reviewed-by: Marcel Apfelbaum <44592b4eea36663c86b994bb0ea99d15309c1c7d@redhat.com>
Reviewed-by: Jordan Justen <a79006884ba9cf5f4f7fcbb92a15b208780d8c97@intel.com>
Tested-by: Gabriel Somlo <0bda901f34b59fdc0593dc5ef2b1790278d1dfd8@cmu.edu>
Tested-by: Michał Zegan <60ced9b9d4fecee1bf8c56beb3fc951573933e4e@poczta.onet.pl>

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