less register pressure with bsf loops, possibly better branching
less register pressure with bsf loops, possibly better branching

- unconditional jump down to the bsf and jne instructions instead of bsf
  je. This should give the jne better branching predictability
- let gcc decide what registers to use (where possible). This needs
  special mov instructions that I had to learn about first. :-) imul can
  also read directly from a memory location, thus requiring one less
  instruction in the loop. Reorder the btr to be called somewhere in the
  middle - where the probabilty is highest that the following instruction
  is still waiting for the data to arrive from cache/memory
- remove unused constraints, which should reduce register pressure

VcDevel/Vc,chr-engwer/Vc,VcDevel/Vc,VcDevel/Vc,chr-engwer/Vc,chr-engwer/Vc,VcDevel/Vc