i2c: at91: fix write transfers by clearing pending interrupt first
i2c: at91: fix write transfers by clearing pending interrupt first

In some cases a NACK interrupt may be pending in the Status Register (SR)
as a result of a previous transfer. However at91_do_twi_transfer() did not
read the SR to clear pending interruptions before starting a new transfer.
Hence a NACK interrupt rose as soon as it was enabled again at the I2C
controller level, resulting in a wrong sequence of operations and strange
patterns of behaviour on the I2C bus, such as a clock stretch followed by
a restart of the transfer.

This first issue occurred with both DMA and PIO write transfers.

Also when a NACK error was detected during a PIO write transfer, the
interrupt handler used to wrongly start a new transfer by writing into the
Transmit Holding Register (THR). Then the I2C slave was likely to reply
with a second NACK.

This second issue is fixed in atmel_twi_interrupt() by handling the TXRDY
status bit only if both the TXCOMP and NACK status bits are cleared.

Tested with a at24 eeprom on sama5d36ek board running a linux-4.1-at91
kernel image. Adapted to linux-next.

Reported-by: Peter Rosin <3a0ad89228e0bf11d9bd43fb0f453cf9d7ca9376@lysator.liu.se>
Signed-off-by: Cyrille Pitchen <e50fad4ce891c9ba2f33288a3659adde668ff62d@atmel.com>
Signed-off-by: Ludovic Desroches <627575320a9526cb6c91021c9940202b0e84c416@atmel.com>
Tested-by: Peter Rosin <3a0ad89228e0bf11d9bd43fb0f453cf9d7ca9376@lysator.liu.se>
Signed-off-by: Wolfram Sang <fd4ce474653598159cad06f3c83387a05cd53a44@the-dreams.de>
Fixes: 93563a6a71bb ("i2c: at91: fix a race condition when using the DMA controller")
Cc: 4fbacc2fa0ffdbb11bf1ad6925b886ebd08dd15f@vger.kernel.org #4.1

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