[media] v4l: of: Correct pclk-sample for BT656 bus
[media] v4l: of: Correct pclk-sample for BT656 bus

Current v4l2_of_parse_parallel_bus function attempts to parse the
DT properties for the parallel bus as well as BT656 bus.
If the pclk-sample property is defined for the BT656 bus, it is still
marked as a parallel bus.
Fix this by parsing the pclk after the bus_type is selected.
Only when hsync or vsync properties are specified, the bus_type should
be set to V4L2_MBUS_PARALLEL.

Signed-off-by: Nikhil Devshatwar <466b99620f37fbf4c399ce1ec977d154363a5836@ti.com>
Acked-by: Sylwester Nawrocki <1ca386fdc5066df13f7236f0837f22126191d06b@samsung.com>
Signed-off-by: Hans Verkuil <3a513708f73c27e7d36ebc496aa41dad6a3153ea@cisco.com>
Signed-off-by: Mauro Carvalho Chehab <ad86ba2154032c9f55743a190faa2459a9d61d42@osg.samsung.com>

KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs