The first fully coded version of decoder.isa!!!!! ================================================= -every MIPS32 ISA is represented with some type of code block. -any instruction that doesnt have a code block would be of format WarnUnimpl. Examples of the ones I am waiting on further info to implement are the TLB register insts, memory consistency instructions (ll,sc,etc.) and software debug insts.
The first fully coded version of decoder.isa!!!!!
=================================================
-every MIPS32 ISA is represented with some type
of code block.
-any instruction that doesnt have a code block
would be of format WarnUnimpl. Examples of the
ones I am waiting on further info to implement
are the TLB register insts, memory consistency
instructions (ll,sc,etc.) and software debug
insts.

--HG--
extra : convert_revision : 4a26c72e4fa1f63b8689fe2631a7508daf660969

rjschof/gem5,gem5/gem5,sobercoder/gem5,samueldotj/TeeRISC-Simulator,powerjg/gem5-ci-test,KuroeKurose/gem5,samueldotj/TeeRISC-Simulator,TUD-OS/gem5-dtu,SanchayanMaity/gem5,HwisooSo/gemV-update,HwisooSo/gemV-update,powerjg/gem5-ci-test,cancro7/gem5,TUD-OS/gem5-dtu,powerjg/gem5-ci-test,aclifton/cpeg853-gem5,yb-kim/gemV,austinharris/gem5-riscv,gem5/gem5,rjschof/gem5,HwisooSo/gemV-update,Weil0ng/gem5,sobercoder/gem5,gedare/gem5,austinharris/gem5-riscv,zlfben/gem5,joerocklin/gem5,kaiyuanl/gem5,rallylee/gem5,zlfben/gem5,Weil0ng/gem5,briancoutinho0905/2dsampling,joerocklin/gem5,qizenguf/MLC-STT,HwisooSo/gemV-update,austinharris/gem5-riscv,SanchayanMaity/gem5,briancoutinho0905/2dsampling,TUD-OS/gem5-dtu,yb-kim/gemV,qizenguf/MLC-STT,HwisooSo/gemV-update,joerocklin/gem5,briancoutinho0905/2dsampling,cancro7/gem5,powerjg/gem5-ci-test,qizenguf/MLC-STT,sobercoder/gem5,yb-kim/gemV,sobercoder/gem5,aclifton/cpeg853-gem5,qizenguf/MLC-STT,joerocklin/gem5,samueldotj/TeeRISC-Simulator,samueldotj/TeeRISC-Simulator,gem5/gem5,rallylee/gem5,markoshorro/gem5,Weil0ng/gem5,markoshorro/gem5,gem5/gem5,KuroeKurose/gem5,gem5/gem5,briancoutinho0905/2dsampling,rallylee/gem5,yb-kim/gemV,KuroeKurose/gem5,aclifton/cpeg853-gem5,gem5/gem5,kaiyuanl/gem5,kaiyuanl/gem5,gedare/gem5,Weil0ng/gem5,sobercoder/gem5,aclifton/cpeg853-gem5,briancoutinho0905/2dsampling,kaiyuanl/gem5,rjschof/gem5,TUD-OS/gem5-dtu,aclifton/cpeg853-gem5,briancoutinho0905/2dsampling,rjschof/gem5,samueldotj/TeeRISC-Simulator,qizenguf/MLC-STT,Weil0ng/gem5,joerocklin/gem5,aclifton/cpeg853-gem5,samueldotj/TeeRISC-Simulator,powerjg/gem5-ci-test,cancro7/gem5,qizenguf/MLC-STT,kaiyuanl/gem5,yb-kim/gemV,HwisooSo/gemV-update,cancro7/gem5,rallylee/gem5,kaiyuanl/gem5,gedare/gem5,KuroeKurose/gem5,samueldotj/TeeRISC-Simulator,rjschof/gem5,joerocklin/gem5,markoshorro/gem5,yb-kim/gemV,rallylee/gem5,rallylee/gem5,austinharris/gem5-riscv,SanchayanMaity/gem5,yb-kim/gemV,Weil0ng/gem5,gedare/gem5,sobercoder/gem5,kaiyuanl/gem5,joerocklin/gem5,TUD-OS/gem5-dtu,zlfben/gem5,aclifton/cpeg853-gem5,zlfben/gem5,austinharris/gem5-riscv,gedare/gem5,gem5/gem5,gedare/gem5,powerjg/gem5-ci-test,rjschof/gem5,sobercoder/gem5,zlfben/gem5,markoshorro/gem5,SanchayanMaity/gem5,cancro7/gem5,rallylee/gem5,markoshorro/gem5,Weil0ng/gem5,TUD-OS/gem5-dtu,KuroeKurose/gem5,austinharris/gem5-riscv,TUD-OS/gem5-dtu,zlfben/gem5,markoshorro/gem5,yb-kim/gemV,joerocklin/gem5,SanchayanMaity/gem5,powerjg/gem5-ci-test,cancro7/gem5,gedare/gem5,briancoutinho0905/2dsampling,rjschof/gem5,SanchayanMaity/gem5,KuroeKurose/gem5,markoshorro/gem5,SanchayanMaity/gem5,zlfben/gem5,cancro7/gem5,qizenguf/MLC-STT,austinharris/gem5-riscv,HwisooSo/gemV-update,KuroeKurose/gem5