Ensure only SINK nodes are placed in the logical outputs
Ensure only SINK nodes are placed in the logical outputs

Should fix issues on designs with combinational loops which cause
non-sink nodes to end up in the last timing graph level.

verilog-to-routing/tatum,kmurray/tatum,kmurray/tatum,kmurray/tatum,verilog-to-routing/tatum,verilog-to-routing/tatum