Ignore empty parameters in Verilog module instantiations
Ignore empty parameters in Verilog module instantiations

Fixes #2394

Signed-off-by: Claire Xenia Wolf <da7dd17269675e6648b2de3690262d0e18b89cca@symbioticeda.com>

cliffordwolf/yosys,cliffordwolf/yosys,YosysHQ/yosys,SymbiFlow/yosys,SymbiFlow/yosys,YosysHQ/yosys,cliffordwolf/yosys,antmicro/yosys,SymbiFlow/yosys,cliffordwolf/yosys,antmicro/yosys,antmicro/yosys,antmicro/yosys,YosysHQ/yosys,cliffordwolf/yosys,SymbiFlow/yosys,cliffordwolf/yosys,cliffordwolf/yosys,YosysHQ/yosys,YosysHQ/yosys,YosysHQ/yosys,cliffordwolf/yosys,YosysHQ/yosys,SymbiFlow/yosys,SymbiFlow/yosys,antmicro/yosys,SymbiFlow/yosys,antmicro/yosys,SymbiFlow/yosys,antmicro/yosys,antmicro/yosys,YosysHQ/yosys,cliffordwolf/yosys