Decoder: fix signaling and detection of illegal instructions
Decoder: fix signaling and detection of illegal instructions

This commit fixes two bugs in the decoder:

1. For illegal branch condition selections, the illegal instruction
condition must be signaled as long as the instruction is being executed
and not just during the first cycle, as the controller cannot interrupt
multicycle instructions.

2. Illegal instructions should also be signaled when `instr[28]` is set
for register-register ALU operations. Previously, these were not
signaled as the original design used `instr[28]` to encode custom bit-
manipulation instructions.

These bugs were discovered by @taoliug. This resolves issue #163.

lowRISC/ibex,lowRISC/ibex,AmbiML/ibex,AmbiML/ibex,AmbiML/ibex,lowRISC/ibex,lowRISC/ibex,AmbiML/ibex