plugin: CsrPlugin: Init cycle and instret registers
plugin: CsrPlugin: Init cycle and instret registers

Both counters are initialized with "randBoot()". This is fine for FPGA
designs because the registers can be loaded with default values but
ASIC designs require to load the value during a reset.

Since both counters require to start at 0 (read-only CSR registers),
change both registers from "randBoot()" to "init(0)".

Error:

    reg        [63:0]   CsrPlugin_mcycle = 64'b0000000...00000000000;

           |
  Warning : Ignoring unsynthesizable construct. [VLOGPT-37]

Signed-off-by: Daniel Schultz <adff8adca0fa13ca885c17ff484bfc0eae7d2508@phytec.de>

SpinalHDL/VexRiscv,SpinalHDL/VexRiscv,SpinalHDL/VexRiscv,SpinalHDL/VexRiscv,SpinalHDL/VexRiscv