[otbn,dv] Properly represent DMEM store latency in ISS
[otbn,dv] Properly represent DMEM store latency in ISS

This wouldn't matter except that we want to support a test where we
invalidate the whole of DMEM (to trigger integrity errors) at some
arbitrary point in the run.

If we're unlucky and happen to do this just after executing a store
then the RTL will apply the store on the following cycle (leaving
valid integrity bits) but the ISS, which had applied the store
already, would mark the location as having bad integrity.

The correct fix is easy enough: keep an extra "pending" queue that
only gets applied on the following cycle.

Signed-off-by: Rupert Swarbrick <290093e2ad2515ed2f14d749293c8cf8e02ca274@lowrisc.org>

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