flash: stm32l4: disable dcache before writting
flash: stm32l4: disable dcache before writting

Disable the data cache before writing to Flash, in order to workaround
silicon errata 2.2.3: "Data cache might be corrupted during Flash memory
read-while-write operation". The data cache is conditionally re-enabled
once the write is completed.

This silicon bug has been encountered while stress testing the
implementation. Here are the events leading to the fault:
- Code is executing from Flash bank 1
- A write to Flash bank 2 is initiated
- The Cortex SysTick interrupt fires while waiting for Flash write
  completion

In that case, the Flash controller will perform a read-while-write
operation in order to execute the ISR code. As the data cache is enabled
by default after reset, a corruption occurs due to the silicon bug,
leading to bizarre data bus faults or unaligned access faults inside
_timer_int_handler() or one of the functions called by the ISR.

Applying the workaround devised by ST fixes the problem.

Signed-off-by: Florian Vaussard <ef1e2bd37ca89620283a38ee0519838a257cab3b@gmail.com>

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