Avoid assertion failure in VHDL translate_select
Avoid assertion failure in VHDL translate_select

This avoids triggering an assertion failure by trying to
select bits from a std_logic (which isn't a vector type).

CastMi/iverilog,themperek/iverilog,CastMi/iverilog,themperek/iverilog,CastMi/iverilog,themperek/iverilog