mem-ruby: Enhance MOESI_AMD DmaWrite
mem-ruby: Enhance MOESI_AMD DmaWrite

This enhances MOESI_AMD_Base-dir DmaWrite to enable partial writes. This
is currently done by assuming a full cache line, invalidating caches,
and transitioning back to unblocked state. The enhanced write supports
partial writes (i.e., smaller than cache line size) by first reading
memory, merging the modified data, and then writing back to memory.
Implementation of this mirrors that of DmaRead in terms of state. This
means for each DmaRead state (BDR_PM, BDR_Pm, and BDR_M) there is a
write analogue (BDW_PM, BDW_Pm, and BDR_M) and the BDR_P state is
removed. Furthermore, this enhanced DmaWrite ... actually writes data to
memory instead of relying on DirectoryEntry / backing store for correct
data.

There are two possible state transitions for DmaWrite now. (1) Memory
data arrives before probe response and (2) probe response arrives before
memory data. In case (1), probe data overwrites memory data and merges
the partial write using the TBE write mask then updates write mask to
'filled' state. In case (2), probe data is merged with the partial data
using the TBE write mask then updates write mask to 'filled' state. The
memory data will then be clobbered by copying the TBE data over the
response since the write mask is now full.

Change-Id: I1eebb882b464c4c5ee5fd60932fd38d271ada4d7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57410
Reviewed-by: Matthew Poremba <f1eb50f3368ce197c52b19f7fdb5aa7a278f15fd@amd.com>
Maintainer: Matthew Poremba <f1eb50f3368ce197c52b19f7fdb5aa7a278f15fd@amd.com>
Reviewed-by: Matt Sinclair <d2406197fb1bedd1e23c70c50c510ff0e9ab0f5b@gmail.com>
Maintainer: Matt Sinclair <d2406197fb1bedd1e23c70c50c510ff0e9ab0f5b@gmail.com>
Tested-by: kokoro <2ac7b1f3fa578934c95181d4272be0d3bca00121@google.com>

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