Fix for br1027: incorrect inference of task/function port direction.
Fix for br1027: incorrect inference of task/function port direction.

In traditional Verilog, each task_port_item must have an explicit port
direction.

In SystemVerilog, if the port direction is not specified, it should be
inherited from the preceding task_port_item for that task/function, and
only the first task_port_item should infer the direction to be 'input'.

themperek/iverilog,themperek/iverilog,themperek/iverilog