mmc: sdhci-pxav3: Respect MMC_DDR52 timing on uhs signaling
mmc: sdhci-pxav3: Respect MMC_DDR52 timing on uhs signaling

commit bb8175a8aa42d731a840cd474e348ac3367eb5a0
  ("mmc: sdhci: clarify DDR timing mode between SD-UHS and eMMC")
added MMC_DDR52 as eMMC's DDR mode to be distinguished from SD-UHS.

While the differentation may be useful, pxav3 SDHCI controller lacks
a corresponding check in its custom .set_uhs_signaling callback for
MMC_DDR52. This patch adds a new switch case for MMC_TIMING_MMC_DDR52
to MMC_TIMING_UHS_DDR50 case.

Signed-off-by: Sebastian Hesselbarth <1d402fe89ace836b52164ed4c0f247cb6f80efc1@gmail.com>
Signed-off-by: Ulf Hansson <fe47b31f388f85ce6ddf64bf3a0cf6b46077d0e6@linaro.org>

KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs