Per the UEFI spec, if a PCI controller is a P2P bridge, then the I/O, Memory and Bus Master bits in the Command register of the PCI configuration header should be placed in the enabled state by the PCI Bus driver.
Per the UEFI spec, if a PCI controller is a P2P bridge, then the I/O, Memory and Bus Master bits in the Command register of the PCI configuration header should be placed in the enabled state by the PCI Bus driver.

But current PCI bus driver has a bug that if a P2P bridge has no child devices detected during enumeration, the bits won’t be set. This may impact PCI hot plug capable bridges because the OS may re-assign resources for them causing the reserved resource by the firmware will be overwritten.


git-svn-id: 5648d1bec6962b0a6d1d1b40eba8cf5cdb62da3d@11013 6f19259b-4bc3-4df7-8a09-765794883524

MattDevo/edk2,MattDevo/edk2,MattDevo/edk2,MattDevo/edk2,MattDevo/edk2,MattDevo/edk2,MattDevo/edk2,MattDevo/edk2