[otbn,dv] Exit on mismatch in otbn_top_sim
[otbn,dv] Exit on mismatch in otbn_top_sim

Now we'll print out the error message from one of the mismatches first
and then will stop a couple of cycles later (to allow things like
multiple errors in a cycle or wave dumping to proceed properly).

Example output:

    Simulation running, end by pressing CTRL-c.
    ERROR: At time 164, otbn_done_q != otbn_model_done (0 != 1).
    ERROR: At time 164, insn_cnt != otbn_model_insn_cnt (0x27 != 0x26).
    [171] %Error: otbn_top_sim.sv:347: Assertion failed in TOP.otbn_top_sim: Mismatch or model error (see message above)
    %Error: ../src/lowrisc_ip_otbn_top_sim_0.1/otbn_top_sim.sv:347: Verilog $stop

Signed-off-by: Rupert Swarbrick <290093e2ad2515ed2f14d749293c8cf8e02ca274@lowrisc.org>

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