npcx: monitor: set DEVALT0.bit7 for the internal flash
npcx: monitor: set DEVALT0.bit7 for the internal flash

The npcx monitor LFW (little firmware) can be used in two scenarios:
1. For npcx5 which supports the external flash and doesn't support UUT,
it is used by the openocd via servo JTAG to flash the EC image.
2. For npcx7 (and newer chips) which support the internal flash and UUT,
it is used by the UUT via UART to flash the EC image.
For case 1, the DEVALT0.bit7 (NO_F_SPI) should be cleared in order to
program the external flash. In case 2, this bit should be set because
the internal flash is used. Otherwise, the GPIOA0 (F_CS0) will also
toggles while programming the internal flash.
Before this CL, the monitor unconditionally clears this bit when
programming the flash.
In this CL, the monitor decides to set/clear this bit according to
the value of the tag filed in the monitor header.
(Assuming that when UUT is used, the target is always the internal
flash.)

BUG=none
BRANCH=none
TEST=No error for "make buildall"
TEST=Programming the internal flash via UUT, make sure the GPIOA0 doesn't
toggle with scope.

Change-Id: I9f1695351b201767cc5ed32877fb395c1e459bc8
Signed-off-by: CHLin <84d2fca36f9d804bb7b1903655f14e4c722a99c4@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2272419
Reviewed-by: Aseda Aboagye <12c9b286316a940fd31c24070da5ab64cdd4d0e7@chromium.org>
Commit-Queue: CH Lin <49997681dc186e71092740314bf6c6feeca6e227@nuvoton.com>
Commit-Queue: Aseda Aboagye <12c9b286316a940fd31c24070da5ab64cdd4d0e7@chromium.org>
Tested-by: CH Lin <49997681dc186e71092740314bf6c6feeca6e227@nuvoton.com>

coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec