i965: Use correct VertStride on align16 instructions.
i965: Use correct VertStride on align16 instructions.

In commit c35fa7a, we changed the "width" of DF source registers to 2,
which is conceptually fine. Unfortunately a VertStride of 2 is not
allowed by align16 instructions on IVB/BYT, and the regular VertStride
of 4 works fine in any case.

See generated_tests/spec/arb_gpu_shader_fp64/execution/built-in-functions/vs-round-double.shader_test
for example:

cmp.ge.f0(8)    g18<1>DF        g1<0>.xyxyDF    -g8<2>DF        { align16 1Q };
        ERROR: In Align16 mode, only VertStride of 0 or 4 is allowed
cmp.ge.f0(8)    g19<1>DF        g1<0>.xyxyDF    -g9<2>DF        { align16 2N };
        ERROR: In Align16 mode, only VertStride of 0 or 4 is allowed

v2:
- Add spec quote (Curro).
- Change the condition to only BRW_VERTICAL_STRIDE_2 (Curro)

Reviewed-by: Samuel Iglesias Gonsálvez <b753b212f30aed827c3eea2e437609dc37310153@igalia.com>
Reviewed-by: Francisco Jerez <5906ff32bdd9fd8db196f6ba5ad3afd6f9257ea5@riseup.net>

metora/MesaGLSLCompiler,metora/MesaGLSLCompiler,metora/MesaGLSLCompiler