intel: DATA_TRANSFER may imply rendering/sampling
intel: DATA_TRANSFER may imply rendering/sampling

Memories/images are assumed to be in DATA_TRANSFER state for blit operations.
The graphics pipeline implements blit operations with rendering and sampling
so we have to flush the render cache or invalidate the sampler cache.

The spec talks about copy operations and hazards in several places.  They are
all about write-after-write hazard, which is not an issue to us.  This commit
deals with read-after-write.

sashinde/VulkanTools,sashinde/VulkanTools,Radamanthe/VulkanSamples,Radamanthe/VulkanSamples,elongbug/Vulkan-LoaderAndValidationLayers,elongbug/Vulkan-LoaderAndValidationLayers,critsec/Vulkan-LoaderAndValidationLayers,KhronosGroup/Vulkan-LoaderAndValidationLayers,KhronosGroup/Vulkan-LoaderAndValidationLayers,Radamanthe/VulkanSamples,Radamanthe/VulkanSamples,critsec/Vulkan-LoaderAndValidationLayers,critsec/Vulkan-LoaderAndValidationLayers,Radamanthe/VulkanSamples,elongbug/Vulkan-LoaderAndValidationLayers,KhronosGroup/Vulkan-LoaderAndValidationLayers,Radamanthe/VulkanSamples,sashinde/VulkanTools,sashinde/VulkanTools,elongbug/Vulkan-LoaderAndValidationLayers,critsec/Vulkan-LoaderAndValidationLayers,KhronosGroup/Vulkan-LoaderAndValidationLayers