cometlake: EC should not delay RSMRST_L by 10 msec
cometlake: EC should not delay RSMRST_L by 10 msec

The PCH wants 10 msec delay between PP1050_A being valid prior to
RSMRST_L transitioning from low to high. In other big core chips this
has been enforced by the EC adding a 10 msec sleep before passing
RSMRST_L to the AP. However on Cometlake this delay is handled by the
Silego part, so the EC does not need to add any additional delay.

BRANCH=none
BUG=b:123751590
TEST=Verified that the delay from PP1050 rising to RSMRST_L rising is
now 10 msec and not 20 msec as it was prior to this change.

Change-Id: Iab463169a81579f64aa5957662d268adbde6a57c
Signed-off-by: Scott Collyer <7d40b3eb9e17bf55d972074a5e77a7ea4159f9dd@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1448817
Commit-Ready: Scott Collyer <7d40b3eb9e17bf55d972074a5e77a7ea4159f9dd@chromium.org>
Tested-by: Scott Collyer <7d40b3eb9e17bf55d972074a5e77a7ea4159f9dd@chromium.org>
Reviewed-by: Furquan Shaikh <6be5c96c464778f89679b1062a2e0a6af93d2aa5@chromium.org>

coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec