clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to domain being gated
clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to domain being gated

Audio subsystem clocks are located in separate block. On Exynos 5420 if
clock for this block (from main clock domain) 'mau_epll' is gated then
any read or write to audss registers will block.

This kind of boot hang was observed on Arndale Octa and Peach Pi/Pit
after introducing runtime PM to pl330 DMA driver. After that commit the
'mau_epll' was gated, because the "amba" clock was disabled and there
were no more users of mau_epll.

The system hang on one of steps:
1. Disabling unused clocks from audss block.
2. During audss GPIO setup (just before probing i2s0 because
   samsung_pinmux_setup() tried to access memory from audss block which was
   gated.

Add a workaround for this by enabling the 'mau_epll' clock in probe.

Signed-off-by: Krzysztof Kozlowski <1a8531307367602b8284517edb33d53d54e5ce8e@samsung.com>
Acked-by: Sylwester Nawrocki <1ca386fdc5066df13f7236f0837f22126191d06b@samsung.com>
Tested-by: Javier Martinez Canillas <039000e09e601bba70626bd0fbe59654c9cf8cac@collabora.co.uk>
Tested-by: Kevin Hilman <f9849b02abe18c1ece6bd40346458ed53f49d31b@linaro.org>
Signed-off-by: Michael Turquette <6dab61939fc5e23761050a66932f032dceda5ebf@linaro.org>

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