soc/intel_adsp/cavs_v25: Correct power gating state handling
soc/intel_adsp/cavs_v25: Correct power gating state handling

There is a hardware startup state where power gating can be "enabled"
even though the core is actually launchable via an IDC interrupt (in
fact that's the hardware default).  In that state, the CPU will launch
correctly but then unexpectedly shut itself off then it enters the
idle thread.

Don't rely on initialization state, always set the power and clock
gating bits (to disable gating) immediately before CPU launch.

Signed-off-by: Andy Ross <c70f9a6bf6ee0cd69c8af4ce5e6b131945769315@intel.com>

galak/zephyr,zephyrproject-rtos/zephyr,galak/zephyr,finikorg/zephyr,zephyrproject-rtos/zephyr,finikorg/zephyr,galak/zephyr,zephyrproject-rtos/zephyr,zephyrproject-rtos/zephyr,galak/zephyr,finikorg/zephyr,galak/zephyr,zephyrproject-rtos/zephyr,finikorg/zephyr,finikorg/zephyr