[AMDGPU] Fix-up cases where writelane has 2 SGPR operands - bug fixes
[AMDGPU] Fix-up cases where writelane has 2 SGPR operands - bug fixes

Update to previous commit to fix an issue where immediates are tested for copy
propagation but aren't suitable as inline constants. The old method caused
issues that resulted in seg faults in later cse phases.

Even though writelane doesn't have the same constraints as other valu
instructions it still can't violate the >1 SGPR operand constraint

Due to later register propagation (e.g. fixing up vgpr operands via
readfirstlane) changing writelane to only have a single SGPR is tricky.

This implementation puts a new check after SIFixSGPRCopies that prevents
multiple SGPRs being used in any writelane instructions.

The algorithm used is to check for trivial copy prop of constants into one of
the SGPR operands and perform that if possible. If this isn't possible put an
explicit copy of Src1 SGPR into M0 and use that instead (this is allowable for
writelane as the constraint is for SGPR read-port and not constant-bus access).

Change-Id: If25434941dcd34a0fdbf38034b9266846d58522f

GPUOpen-Drivers/llvm,GPUOpen-Drivers/llvm,GPUOpen-Drivers/llvm,GPUOpen-Drivers/llvm,GPUOpen-Drivers/llvm,GPUOpen-Drivers/llvm,GPUOpen-Drivers/llvm,GPUOpen-Drivers/llvm