The UART device infrasturcture wants these defined.  Define them just like we do in Malta.  We may want to look at consolidating things because *ALL* mips will *ALWAYS* be memory mapped.  The only wrinkle is that the tag may need to be a custom one (see endian issues with the Atheros port for one example).
The UART device infrasturcture wants these defined.  Define them just
like we do in Malta.  We may want to look at consolidating things
because *ALL* mips will *ALWAYS* be memory mapped.  The only wrinkle
is that the tag may need to be a custom one (see endian issues with
the Atheros port for one example).

jrobhoward/SCADAbase,jrobhoward/SCADAbase,jrobhoward/SCADAbase,jrobhoward/SCADAbase,jrobhoward/SCADAbase,jrobhoward/SCADAbase,jrobhoward/SCADAbase,jrobhoward/SCADAbase,jrobhoward/SCADAbase,jrobhoward/SCADAbase,jrobhoward/SCADAbase