stage2: Default AVR generic cpu to avr2
stage2: Default AVR generic cpu to avr2

The avr1 target is a very minimal subset of the AVR ISA, quoting the GCC
manual:

> This ISA is implemented by the minimal AVR core and supported for
> assembler only.

Default to avr2 as GCC and Clang do.

zig-lang/zig,andrewrk/zig,andrewrk/zig,zig-lang/zig,zig-lang/zig