ARM: cti: fix manipulation of debug lock registers
ARM: cti: fix manipulation of debug lock registers

The LOCKSTATUS register for memory-mapped coresight devices indicates
whether or not the device in question implements hardware locking. If
not, locking is not present (i.e. LSR.SLI == 0) and LAR is write-ignore,
so software doesn't actually need to check the status register at all.

This patch removes the broken LSR checks.

Cc: Ming Lei <8d0fc11caeb4659419f0ba3104eb4a9d30848d42@canonical.com>
Reported-by: Mike Williams <9dea341ff7d894f057dd5f915bb5ab463269d0c2@arm.com>
Signed-off-by: Will Deacon <b913f13ef92ac157955c954ccaaff7be065faba4@arm.com>

KristFoundation/Programs,KristFoundation/Programs,TeamVee-Kanas/android_kernel_samsung_kanas,KristFoundation/Programs,TeamVee-Kanas/android_kernel_samsung_kanas,TeamVee-Kanas/android_kernel_samsung_kanas,TeamVee-Kanas/android_kernel_samsung_kanas,KristFoundation/Programs,TeamVee-Kanas/android_kernel_samsung_kanas,KristFoundation/Programs,KristFoundation/Programs