arm64: ensure completion of TLB invalidatation
arm64: ensure completion of TLB invalidatation

Currently there is no dsb between the tlbi in __cpu_setup and the write
to SCTLR_EL1 which enables the MMU in __turn_mmu_on. This means that the
TLB invalidation is not guaranteed to have completed at the point
address translation is enabled, leading to a number of possible issues
including incorrect translations and TLB conflict faults.

This patch moves the tlbi in __cpu_setup above an existing dsb used to
synchronise I-cache invalidation, ensuring that the TLBs have been
invalidated at the point the MMU is enabled.

Signed-off-by: Mark Rutland <1db9dd262beaa64f35756dd39531d9747b7778bb@arm.com>
Cc: Catalin Marinas <15ce75b290ebaf27c3f9fd73ab848685ed3d8261@arm.com>
Cc: Will Deacon <b913f13ef92ac157955c954ccaaff7be065faba4@arm.com>
Signed-off-by: Catalin Marinas <15ce75b290ebaf27c3f9fd73ab848685ed3d8261@arm.com>

KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs