Sigh, ignoring instruction fetch bus errors for the kernel code should not depend upon the address being at the beginning of a cache line, for we may arrive in the middle of a line thanks to a branch. Noticed the hard way...
Sigh, ignoring instruction fetch bus errors for the kernel code should not
depend upon the address being at the beginning of a cache line, for we may
arrive in the middle of a line thanks to a branch. Noticed the hard way...

orumin/openbsd-efivars,orumin/openbsd-efivars,orumin/openbsd-efivars,orumin/openbsd-efivars