[otbn,dv] Fix "start" tracking around resets
[otbn,dv] Fix "start" tracking around resets

The bug here happens if a reset is asserted just after the write to
the CMD register that starts OTBN. Specifically, there was a problem
if the reset arrived after the negedge of the clock after start_i
signal is asserted but before the following posedge.

In this case, we would have converted "saw_start_tl_trans" into
"waiting_for_model" and then would see the DV_CHECK fail on the
following cycle (by which time, we were in reset) because the reset
would have arrived before the model started.

To fix things, we make the check conditional on not being in reset and
also clear the waiting_for_model flag when in reset (otherwise, we'd
see a failure next time rst_n went high).

Signed-off-by: Rupert Swarbrick <290093e2ad2515ed2f14d749293c8cf8e02ca274@lowrisc.org>

lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan