Updating submodules.
Updating submodules.

 * litex changed from v0.1-451-g537b0e90 to v0.1-494-g6e327cda
    * 6e327cda - bios/sdram: rewrite write_leveling (simplify and improve robustness) <Florent Kermarrec>
    * 975be668 - platforms/genesys2: add eth clock timing constraint <Florent Kermarrec>
    * 934a5da5 - soc/cores/clock: add expose_drp on S7PLL/S7MMCM <Florent Kermarrec>
    *   9097573e - Merge pull request #109 from cr1901/xip-improve <enjoy-digital>
    |\
    | * 0ff6d586 - Distinguish crt0 variants more clearly, update BIOS to use CTR variant (as it has no .data section). <William D. Jones>
    | * 81060081 - integration/builder: Create EXECUTE_IN_PLACE Makefile variable to complement COPY_TO_MAIN_RAM. <William D. Jones>
    | * db906190 - integration/builder: Add LiteX define to generated variables (to distinguish MiSoC and LiteX). <William D. Jones>
    * | 082b0301 - targets: use new clock abstraction on all 7-series targets <Florent Kermarrec>
    * | 74e74dc0 - soc/cores/clock: different clkin_freq_range for pll and mmcm <Florent Kermarrec>
    * | 91d8cc2d - soc/cores/clock: different vco_freq_range for pll and mmcm <Florent Kermarrec>
    * | 6cd95494 - soc/core/clock: allow selecting buffer type (None, BUFG, BUFR). (default = BUFG) <Florent Kermarrec>
    * | 912ca323 - soc/cores/clock: create specific S7IDELAYCTRL module <Florent Kermarrec>
    * | baec87f5 - soc/cores/clock: add S7MMCM support <Florent Kermarrec>
    * | ef405249 - soc/cores/clocks/S7PLL: add speedgrade support, default to -1 (slowest) <Florent Kermarrec>
    * | 5415b521 - targets/arty: use new clock abstraction module (compile, untested on board) <Florent Kermarrec>
    * | 63fc3950 - soc/cores: init clock abstraction module <Florent Kermarrec>
    |/
    * 70a32ed8 - sim/verilator: add multithread support (default=1) <Florent Kermarrec>
    * 7f0d116d - soc_core: use cpu instead of cpu_or_bridge internally (keep retro-compat for now) <Florent Kermarrec>
    * 22febe95 - boards/targets: uniformize things between targets <Florent Kermarrec>
    * 01b025aa - soc_core/get_mem_data: add endianness support and use it in builder/initialize_rom to avoid duplication <Florent Kermarrec>
    * b528a005 - cores/cpu: add software informations to cpu and simplify cpu_interface <Florent Kermarrec>
    * 2d785cb0 - boards/plarforms: fix issues found while testing simple design on all platforms <Florent Kermarrec>
    * 0b0e3ac1 - test/test_targets: test simple design with all platforms <Florent Kermarrec>
    * c88029d3 - soc_core: add uart-stub argument <Florent Kermarrec>
    * 0d2d3959 - setup.py: add litex_simple exec (to ease building simple design) <Florent Kermarrec>
    * e04530e0 - test/test_targets: update and reorganize targets <Florent Kermarrec>
    * e9ed7370 - ease RemoteClient import <Florent Kermarrec>
    *   346dcf94 - Merge pull request #108 from xobs/use-csr-accessors <enjoy-digital>
    |\
    | * 6f25a0d8 - csr: use external csr_readl()/csr_writel() if present <Sean Cross>
    | * 9a252e36 - csr: use readl()/writel() accessors for accessing mmio <Sean Cross>
    * |   1c1d87f8 - Merge pull request #106 from cr1901/data-crt0 <Tim Ansell>
    |\ \
    | |/
    | * 9d4da737 - libbase/crt0-lm32.S: Add provisions for loading .data from flash. <William D. Jones>
    |/
    * 01ae7d42 - README: add migen/litex clarification <Florent Kermarrec>
    * 15e584d8 - targets/sim: generate analyzer.csv <Florent Kermarrec>
    * cde72603 - targets/sim: generate csr.csv <Florent Kermarrec>
    * f62df502 - targets/sim: add rom-init <Florent Kermarrec>
    * 1dbf591e - targets/sim: add ram-init param to allow initializing ram from file (faster than tftp) <Florent Kermarrec>
    * 9893c246 - integration/soc_core: add get_mem_data function to read memory content from file <Florent Kermarrec>
    * a3eb2e40 - soc/intergration/builder: fix when no sdram <Florent Kermarrec>
    * 934b08ed - targets/sim: merge in a single class and ease configuration <Florent Kermarrec>
    * bd42b188 - Merge branch 'master' of http://github.com/enjoy-digital/litex <Florent Kermarrec>
    * 3e77ae78 - targets: replace MiniSoC with EthernetSoC <Florent Kermarrec>
    * badd9924 - targets/sim: add EtherboneSoC target (allow accessing wishbone over in simulation with litex_server) <Florent Kermarrec>

Full submodule status
--
 5eeb151a748788666534d6ea3da07f90400d24c2 edid-decode (remotes/origin/HEAD)
 a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD)
 ea1ac4d6d72ecb9a65fb884857db8ba6851f3230 litedram (heads/master-170-gea1ac4d)
 3d868449e9c38a00524cff8ed2bf5dec2fc0d858 liteeth (heads/master-27-g3d86844)
 3e8de2d1ef347a1fdfbd01601b1bbdc4558dd90a litepcie (heads/master-45-g3e8de2d)
 fb72044dabd121b4643a936b21ca3bf3aed75499 litesata (heads/master-20-gfb72044)
 686db4f3cd71bade8dd777d112e66797662f5bad litescope (heads/master-32-g686db4f)
 0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (remotes/origin/HEAD)
 13d85a1fe360678bebd57c55f1b35988c655ae95 litevideo (remotes/origin/HEAD)
 6e327cda2697d37b23f607a5a7712363dc60857a litex (v0.1-494-g6e327cda)
 ca0df1c148950213ff0551a8ec7c188a5910906e migen (0.6.dev-168-gca0df1c)

mithro/HDMI2USB-litex-firmware,mithro/HDMI2USB-litex-firmware,mithro/HDMI2USB-litex-firmware,mithro/HDMI2USB-litex-firmware