iommu/arm-smmu: Fix ATS1* register writes
iommu/arm-smmu: Fix ATS1* register writes

The ATS1* address translation registers only support being written
atomically - in SMMUv2 where they are 64 bits wide, 32-bit writes to
the lower half are automatically zero-extended, whilst 32-bit writes
to the upper half are ignored. Thus, the current logic of performing
64-bit writes as two 32-bit accesses is wrong.

Since we already limit IOVAs to 32 bits on 32-bit ARM, the lack of a
suitable writeq() implementation there is not an issue, and we only
need a little preprocessor ugliness to safely hide the 64-bit case.

Signed-off-by: Robin Murphy <4f9c5a5cfa819e47d69719a414c02aa6016a9f54@arm.com>
Signed-off-by: Will Deacon <b913f13ef92ac157955c954ccaaff7be065faba4@arm.com>
Signed-off-by: Joerg Roedel <61aff96566804ea1da8a65de5bcc892ce07caceb@suse.de>

KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs