Report that a vectored full connection only supports a single src/dst
Report that a vectored full connection only supports a single src/dst

In a specify block a full connection is defined to only support a single
source and destination path. This patch adds an error message when this
is found, except we skip the error if all the paths are a single bit
wide. This exemption was added to match the functionality found in
NC-Verilog and presumably Verilog-XL.

A message was also added in place of an assert if the source signals was
not found in the current scope.

themperek/iverilog,themperek/iverilog,CastMi/iverilog,CastMi/iverilog,themperek/iverilog,CastMi/iverilog