x86: timing: fix potential divide by zero
x86: timing: fix potential divide by zero

There is a possibility that the TSC frequency calculation
is divided by zero. So this fixes the issue by repeatedly
trying to get the delta clock cycles and delta TSC cycles
until they both are not zero.

Signed-off-by: Daniel Leung <d94e04d205b5962d7873a139ef298b03c1717f72@intel.com>

galak/zephyr,finikorg/zephyr,galak/zephyr,zephyrproject-rtos/zephyr,finikorg/zephyr,finikorg/zephyr,zephyrproject-rtos/zephyr,galak/zephyr,zephyrproject-rtos/zephyr,finikorg/zephyr,zephyrproject-rtos/zephyr,finikorg/zephyr,zephyrproject-rtos/zephyr,galak/zephyr,galak/zephyr