arm64: fix midr range for Cortex-A57 erratum 832075
arm64: fix midr range for Cortex-A57 erratum 832075

Register MIDR_EL1 is masked to get variant and revision fields, then
compared against midr_range_min and midr_range_max when checking
whether CPU is affected by any particular erratum. However, variant
and revision fields in MIDR_EL1 are separated by 16 bits, so the min
and max of midr range should be constructed accordingly, otherwise
the patch will not be applied when variant field is non-0.

Cc: 4fbacc2fa0ffdbb11bf1ad6925b886ebd08dd15f@vger.kernel.org # 3.19+
Acked-by: Andre Przywara <94eb15b8f54b8e37c3f8d338296201be47dc5c3e@arm.com>
Reviewed-by: Paul Walmsley <a027184a55211cd23e3f3094f1fdc728df5e0500@pwsan.com>
Signed-off-by: Bo Yan <fd5c498f123b1646feb1c4b58a7b9ef4b4e8b602@nvidia.com>
[will: use MIDR_VARIANT_SHIFT to construct upper bound]
Signed-off-by: Will Deacon <b913f13ef92ac157955c954ccaaff7be065faba4@arm.com>

KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs