ACPICA: For PM1B registers, do not shift value read or written
ACPICA: For PM1B registers, do not shift value read or written

The PM1B registers are mirrors of the PM1A registers with
different bits actually implemented. From the ACPI specification:
"Although the bits can be split between the two register blocks
(each register block has a unique pointer within the FADT), the bit
positions are maintained. The register block with unimplemented
bits (that is, those implemented in the other register block)
always returns zeros, and writes have no side effects"

Signed-off-by: Bob Moore <861d61e839a6c9cacf88c3a26b10371d2c9b211f@intel.com>
Signed-off-by: Lin Ming <d6f051473f553588884d51874952f6fb19ae8261@intel.com>
Signed-off-by: Len Brown <b060cfa1096cc6e8be83699ddb4ed8a77dd63af5@intel.com>

TeamVee-Kanas/android_kernel_samsung_kanas,KristFoundation/Programs,TeamVee-Kanas/android_kernel_samsung_kanas,TeamVee-Kanas/android_kernel_samsung_kanas,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,TeamVee-Kanas/android_kernel_samsung_kanas,TeamVee-Kanas/android_kernel_samsung_kanas,KristFoundation/Programs