cr50: use plt_rst_l low level as a sleep wake trigger
cr50: use plt_rst_l low level as a sleep wake trigger

When an x86 based system is reset, a pulse on the plt_rst_l line is
generated. This pulse is supposed to reset the system and the pulse'
rising edge is an interrupt trigger for H1 to reset the TPM. If H1 is
in sleep state at the time of the rising edge, the interrupt request
could be lost.

Luckily, the minimum plt_rst_l pulse duration is 1 ms, and the worst
case max time to wake up from sleep for H1 150 us. Let's wake up on
low level of plt_rst_l, this way by the time the rising edge comes
along the H1 would be awake and ready to process the interrupt.

BRANCH=cr50
BUG=b:35995492

TEST=verified that platform_KernelErrorPaths.CORRUPT_STACK passes
     hundreds of times on a system were it was failing after a few
     runs before this fix.

    - verified that suspend_stress_test still succeeds at least 300
      iterations

Change-Id: Ib9984efa08bdd185a95716dc9e48077cf4bb3c2a
Signed-off-by: Vadim Bendebury <5515d6d2d0829cbe0dd0dcf2094aaded06d58514@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/455579
Reviewed-by: Aaron Durbin <af0622ab041e8b0f8e5819838dcc93898196e71f@chromium.org>

coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec