mem-cache: Fix write hit latency calculation order
mem-cache: Fix write hit latency calculation order

Patch 6d8694a5fb5cfb905186249581cc6a3fde6cc38a changes the order
at which the access latency is calculated for hits. This order
is incorrect, since the calculations must use the blk's whenReady
value before the access is satisfied.

Change-Id: I30dae5435f54200cc8fdf71fd0dbd2cf9c6f8b17
Signed-off-by: Daniel <91779fc734d358d9575ec4910de29bfcbcaf1b22@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17190
Reviewed-by: Giacomo Travaglini <8eef13a4f970e2e9372c8d26ad0737b760f99c02@arm.com>
Reviewed-by: Nikos Nikoleris <b6a1b3cd9d36c44e9eeb16bc870df3cb2a0cf469@arm.com>
Maintainer: Nikos Nikoleris <b6a1b3cd9d36c44e9eeb16bc870df3cb2a0cf469@arm.com>

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