Reduce burst length to 4 DWORDs for now, since there seem to be 486 chip sets that can't tolerate bursts > cache line size. This should really made dependent on the particular buggy chip sets, but for now we'll play safe ...
Reduce burst length to 4 DWORDs for now, since there seem to
be 486 chip sets that can't tolerate bursts > cache line size.
This should really made dependent on the particular buggy
chip sets, but for now we'll play safe ...

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