Two fixes to try and get TLB miss cost more in line with real platform: 1) Add fault_handler_delay param to FullCPU to wait N cycles after committing faulting instruction before fetching fault handler. 2) Make hw_rei a serializing instruction (flushes pipe, basically).
Two fixes to try and get TLB miss cost more in line with real platform:
1) Add fault_handler_delay param to FullCPU to wait N cycles after
committing faulting instruction before fetching fault handler.
2) Make hw_rei a serializing instruction (flushes pipe, basically).

arch/alpha/isa_desc:
    Make hw_rei a serializing instruction (guarantees previous insts
    complete before hw_rei will issue).

--HG--
extra : convert_revision : 704cef65b3869be9eee724055cedb22114a78359

KuroeKurose/gem5,briancoutinho0905/2dsampling,HwisooSo/gemV-update,samueldotj/TeeRISC-Simulator,TUD-OS/gem5-dtu,aclifton/cpeg853-gem5,SanchayanMaity/gem5,gem5/gem5,rallylee/gem5,qizenguf/MLC-STT,powerjg/gem5-ci-test,zlfben/gem5,rallylee/gem5,sobercoder/gem5,gedare/gem5,austinharris/gem5-riscv,rjschof/gem5,sobercoder/gem5,samueldotj/TeeRISC-Simulator,qizenguf/MLC-STT,briancoutinho0905/2dsampling,sobercoder/gem5,samueldotj/TeeRISC-Simulator,cancro7/gem5,Weil0ng/gem5,gedare/gem5,qizenguf/MLC-STT,yb-kim/gemV,rjschof/gem5,samueldotj/TeeRISC-Simulator,zlfben/gem5,briancoutinho0905/2dsampling,rallylee/gem5,rjschof/gem5,gem5/gem5,kaiyuanl/gem5,KuroeKurose/gem5,Weil0ng/gem5,zlfben/gem5,Weil0ng/gem5,KuroeKurose/gem5,gem5/gem5,zlfben/gem5,TUD-OS/gem5-dtu,samueldotj/TeeRISC-Simulator,SanchayanMaity/gem5,austinharris/gem5-riscv,cancro7/gem5,cancro7/gem5,gem5/gem5,KuroeKurose/gem5,zlfben/gem5,rjschof/gem5,SanchayanMaity/gem5,rallylee/gem5,briancoutinho0905/2dsampling,joerocklin/gem5,TUD-OS/gem5-dtu,SanchayanMaity/gem5,powerjg/gem5-ci-test,KuroeKurose/gem5,yb-kim/gemV,yb-kim/gemV,rjschof/gem5,Weil0ng/gem5,TUD-OS/gem5-dtu,joerocklin/gem5,HwisooSo/gemV-update,gedare/gem5,HwisooSo/gemV-update,cancro7/gem5,HwisooSo/gemV-update,gedare/gem5,qizenguf/MLC-STT,powerjg/gem5-ci-test,markoshorro/gem5,austinharris/gem5-riscv,gem5/gem5,kaiyuanl/gem5,sobercoder/gem5,yb-kim/gemV,powerjg/gem5-ci-test,markoshorro/gem5,markoshorro/gem5,cancro7/gem5,gem5/gem5,qizenguf/MLC-STT,markoshorro/gem5,kaiyuanl/gem5,kaiyuanl/gem5,powerjg/gem5-ci-test,rjschof/gem5,markoshorro/gem5,cancro7/gem5,TUD-OS/gem5-dtu,joerocklin/gem5,joerocklin/gem5,samueldotj/TeeRISC-Simulator,sobercoder/gem5,cancro7/gem5,HwisooSo/gemV-update,gedare/gem5,aclifton/cpeg853-gem5,aclifton/cpeg853-gem5,joerocklin/gem5,sobercoder/gem5,briancoutinho0905/2dsampling,KuroeKurose/gem5,Weil0ng/gem5,austinharris/gem5-riscv,joerocklin/gem5,aclifton/cpeg853-gem5,markoshorro/gem5,austinharris/gem5-riscv,SanchayanMaity/gem5,yb-kim/gemV,markoshorro/gem5,rallylee/gem5,KuroeKurose/gem5,samueldotj/TeeRISC-Simulator,aclifton/cpeg853-gem5,Weil0ng/gem5,aclifton/cpeg853-gem5,briancoutinho0905/2dsampling,TUD-OS/gem5-dtu,powerjg/gem5-ci-test,zlfben/gem5,HwisooSo/gemV-update,rallylee/gem5,rallylee/gem5,qizenguf/MLC-STT,briancoutinho0905/2dsampling,Weil0ng/gem5,yb-kim/gemV,SanchayanMaity/gem5,austinharris/gem5-riscv,gedare/gem5,gedare/gem5,TUD-OS/gem5-dtu,kaiyuanl/gem5,powerjg/gem5-ci-test,SanchayanMaity/gem5,HwisooSo/gemV-update,kaiyuanl/gem5,joerocklin/gem5,yb-kim/gemV,rjschof/gem5,qizenguf/MLC-STT,gem5/gem5,aclifton/cpeg853-gem5,joerocklin/gem5,sobercoder/gem5,kaiyuanl/gem5,zlfben/gem5,yb-kim/gemV,austinharris/gem5-riscv