Improves the toplevel testbench output and readability (#15)
Improves the toplevel testbench output and readability (#15)

Signed-off-by: Flavien Solt <9ab791be8c4c6df08ae68c31cbabd9041b8c7d24@ethz.ch>
lowRISC/gsoc-sim-mem,lowRISC/gsoc-sim-mem