MFC r199645, r199646: Fix Intel PATA UDMA timings setting, affecting write performance. Binary divider value 10 specified in datasheet is not a hex 0x10. UDMA2 should be 33/2 instead of 66/4, which is documented as reverved, UDMA4 should be 66/2 instead of 66/4, which is definitely wrong. Release over-agressive WDMA0 mode timings as close to spec as chip can.
MFC r199645, r199646:
Fix Intel PATA UDMA timings setting, affecting write performance.
Binary divider value 10 specified in datasheet is not a hex 0x10.
UDMA2 should be 33/2 instead of 66/4, which is documented as reverved,
UDMA4 should be 66/2 instead of 66/4, which is definitely wrong.
Release over-agressive WDMA0 mode timings as close to spec as chip can.

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