Added better L2_TCM metric. Removed INVALID cache specifier from L2 events. According to AMD a refill to L1 from L2 or SYS cannot be in Invalid state. Which makes sense of course....
Added better L2_TCM metric. Removed INVALID cache specifier from L2 events.
According to AMD a refill to L1 from L2 or SYS cannot be in Invalid state.
Which makes sense of course....

pyrovski/papi,pyrovski/papi,pyrovski/papi,arm-hpc/papi,pyrovski/papi,arm-hpc/papi,pyrovski/papi,arm-hpc/papi,arm-hpc/papi,pyrovski/papi,arm-hpc/papi,arm-hpc/papi,arm-hpc/papi,pyrovski/papi,pyrovski/papi