mem: Fix prefetchSquash + memInhibitAsserted bug
mem: Fix prefetchSquash + memInhibitAsserted bug

This patch resolves a bug with hardware prefetches. Before a hardware prefetch
is sent towards the memory, the system generates a snoop request to check all
caches above the prefetch generating cache for the presence of the prefetth
target. If the prefetch target is found in the tags or the MSHRs of the upper
caches, the cache sets the prefetchSquashed flag in the snoop packet. When the
snoop packet returns with the prefetchSquashed flag set, the prefetch
generating cache deallocates the MSHR reserved for the prefetch. If the
prefetch target is found in the writeback buffer of the upper cache, the cache
sets the memInhibit flag, which signals the prefetch generating cache to
expect the data from the writeback. When the snoop packet returns with the
memInhibitAsserted flag set, it marks the allocated MSHR as inService and
waits for the data from the writeback.

If the prefetch target is found in multiple upper level caches, specifically
in the tags or MSHRs of one upper level cache and the writeback buffer of
another, the snoop packet will return with both prefetchSquashed and
memInhibitAsserted set, while the current code is not written to handle such
an outcome. Current code checks for the prefetchSquashed flag first, if it
finds the flag, it deallocates the reserved MSHR. This leads to assert failure
when the data from the writeback appears at cache. In this fix, we simply
switch the order of checks. We first check for memInhibitAsserted and then for
prefetch squashed.

KuroeKurose/gem5,briancoutinho0905/2dsampling,briancoutinho0905/2dsampling,gem5/gem5,TUD-OS/gem5-dtu,HwisooSo/gemV-update,TUD-OS/gem5-dtu,zlfben/gem5,rjschof/gem5,rjschof/gem5,HwisooSo/gemV-update,powerjg/gem5-ci-test,aclifton/cpeg853-gem5,austinharris/gem5-riscv,Weil0ng/gem5,rallylee/gem5,cancro7/gem5,aclifton/cpeg853-gem5,qizenguf/MLC-STT,TUD-OS/gem5-dtu,Weil0ng/gem5,rallylee/gem5,cancro7/gem5,cancro7/gem5,markoshorro/gem5,briancoutinho0905/2dsampling,briancoutinho0905/2dsampling,gedare/gem5,gedare/gem5,zlfben/gem5,qizenguf/MLC-STT,TUD-OS/gem5-dtu,KuroeKurose/gem5,qizenguf/MLC-STT,rallylee/gem5,KuroeKurose/gem5,kaiyuanl/gem5,KuroeKurose/gem5,HwisooSo/gemV-update,aclifton/cpeg853-gem5,SanchayanMaity/gem5,sobercoder/gem5,kaiyuanl/gem5,sobercoder/gem5,sobercoder/gem5,sobercoder/gem5,briancoutinho0905/2dsampling,qizenguf/MLC-STT,HwisooSo/gemV-update,markoshorro/gem5,austinharris/gem5-riscv,SanchayanMaity/gem5,austinharris/gem5-riscv,austinharris/gem5-riscv,gedare/gem5,briancoutinho0905/2dsampling,TUD-OS/gem5-dtu,rjschof/gem5,aclifton/cpeg853-gem5,KuroeKurose/gem5,powerjg/gem5-ci-test,powerjg/gem5-ci-test,zlfben/gem5,cancro7/gem5,gem5/gem5,aclifton/cpeg853-gem5,kaiyuanl/gem5,sobercoder/gem5,briancoutinho0905/2dsampling,rjschof/gem5,rallylee/gem5,KuroeKurose/gem5,rallylee/gem5,zlfben/gem5,gem5/gem5,Weil0ng/gem5,SanchayanMaity/gem5,gem5/gem5,TUD-OS/gem5-dtu,markoshorro/gem5,cancro7/gem5,aclifton/cpeg853-gem5,markoshorro/gem5,sobercoder/gem5,SanchayanMaity/gem5,zlfben/gem5,TUD-OS/gem5-dtu,powerjg/gem5-ci-test,zlfben/gem5,kaiyuanl/gem5,Weil0ng/gem5,KuroeKurose/gem5,HwisooSo/gemV-update,kaiyuanl/gem5,gedare/gem5,austinharris/gem5-riscv,gedare/gem5,qizenguf/MLC-STT,markoshorro/gem5,sobercoder/gem5,rjschof/gem5,gedare/gem5,gem5/gem5,SanchayanMaity/gem5,Weil0ng/gem5,rallylee/gem5,rallylee/gem5,cancro7/gem5,zlfben/gem5,austinharris/gem5-riscv,HwisooSo/gemV-update,Weil0ng/gem5,gem5/gem5,SanchayanMaity/gem5,rjschof/gem5,powerjg/gem5-ci-test,gedare/gem5,austinharris/gem5-riscv,kaiyuanl/gem5,aclifton/cpeg853-gem5,SanchayanMaity/gem5,qizenguf/MLC-STT,powerjg/gem5-ci-test,markoshorro/gem5,powerjg/gem5-ci-test,cancro7/gem5,gem5/gem5,Weil0ng/gem5,HwisooSo/gemV-update,kaiyuanl/gem5,qizenguf/MLC-STT,markoshorro/gem5,rjschof/gem5