[translation] update pymtl wrapper for verilator (details)
[translation] update pymtl wrapper for verilator (details)

The following steps for a simple Register are working:

- PyMTL HDL is translated to Verilog using our translation tools
  (Reg_nbits_16.v)

- Generated Verilog is converted to C++ using verilator
  (VReg_nbits_16.so)

- Verilator C++ is exposed to Python using Cython
  (Reg_nbits_16.cpp)

- The Cython interface is embedded in a PyMTL Wrapper module
  (WReg_nbits_16.py)

- The PyMTL Wrapper can be imported and tested like a normal PyMTL model

The above all works but requires a slight modification to the verilator
libraries to deal with the following error:

  include/verilated_vcd_c.h:162:48: error: call to 'isspace' is ambiguous

The line can be modified to use 'std::isspace', and it will work.

Glyfina-Fernando/pymtl,cfelton/pymtl,jjffryan/pymtl,cornell-brg/pymtl,12yujim/pymtl,cfelton/pymtl,Glyfina-Fernando/pymtl,jck/pymtl,tj93/pymtl,jjffryan/pymtl,tj93/pymtl,Glyfina-Fernando/pymtl,12yujim/pymtl,cornell-brg/pymtl,jjffryan/pymtl,jck/pymtl,cfelton/pymtl,jck/pymtl,12yujim/pymtl,cornell-brg/pymtl,tj93/pymtl