ARM: Add a .w to the disassembly of 32 bit thumb instructions. This isn't technically correct since the .w should only be added if there are 32 and 16 bit encodings, but always having it always is better than never having it.
ARM: Add a .w to the disassembly of 32 bit thumb instructions.
This isn't technically correct since the .w should only be added if there are
32 and 16 bit encodings, but always having it always is better than never
having it.

Weil0ng/gem5,HwisooSo/gemV-update,sobercoder/gem5,samueldotj/TeeRISC-Simulator,joerocklin/gem5,sobercoder/gem5,austinharris/gem5-riscv,gedare/gem5,joerocklin/gem5,gedare/gem5,powerjg/gem5-ci-test,rjschof/gem5,qizenguf/MLC-STT,KuroeKurose/gem5,sobercoder/gem5,aclifton/cpeg853-gem5,SanchayanMaity/gem5,briancoutinho0905/2dsampling,zlfben/gem5,gem5/gem5,zlfben/gem5,aclifton/cpeg853-gem5,TUD-OS/gem5-dtu,TUD-OS/gem5-dtu,kaiyuanl/gem5,HwisooSo/gemV-update,zlfben/gem5,cancro7/gem5,yb-kim/gemV,KuroeKurose/gem5,markoshorro/gem5,SanchayanMaity/gem5,KuroeKurose/gem5,Weil0ng/gem5,rallylee/gem5,TUD-OS/gem5-dtu,joerocklin/gem5,gedare/gem5,Weil0ng/gem5,yb-kim/gemV,rjschof/gem5,gedare/gem5,powerjg/gem5-ci-test,rallylee/gem5,austinharris/gem5-riscv,joerocklin/gem5,HwisooSo/gemV-update,samueldotj/TeeRISC-Simulator,aclifton/cpeg853-gem5,SanchayanMaity/gem5,gem5/gem5,powerjg/gem5-ci-test,kaiyuanl/gem5,rallylee/gem5,cancro7/gem5,TUD-OS/gem5-dtu,SanchayanMaity/gem5,HwisooSo/gemV-update,briancoutinho0905/2dsampling,yb-kim/gemV,sobercoder/gem5,yb-kim/gemV,SanchayanMaity/gem5,zlfben/gem5,rallylee/gem5,briancoutinho0905/2dsampling,austinharris/gem5-riscv,briancoutinho0905/2dsampling,KuroeKurose/gem5,HwisooSo/gemV-update,Weil0ng/gem5,markoshorro/gem5,markoshorro/gem5,aclifton/cpeg853-gem5,SanchayanMaity/gem5,HwisooSo/gemV-update,zlfben/gem5,briancoutinho0905/2dsampling,TUD-OS/gem5-dtu,powerjg/gem5-ci-test,joerocklin/gem5,qizenguf/MLC-STT,yb-kim/gemV,joerocklin/gem5,markoshorro/gem5,gem5/gem5,rallylee/gem5,HwisooSo/gemV-update,powerjg/gem5-ci-test,rjschof/gem5,cancro7/gem5,joerocklin/gem5,samueldotj/TeeRISC-Simulator,gem5/gem5,rjschof/gem5,aclifton/cpeg853-gem5,cancro7/gem5,markoshorro/gem5,sobercoder/gem5,cancro7/gem5,samueldotj/TeeRISC-Simulator,zlfben/gem5,gem5/gem5,briancoutinho0905/2dsampling,gem5/gem5,powerjg/gem5-ci-test,powerjg/gem5-ci-test,gedare/gem5,qizenguf/MLC-STT,kaiyuanl/gem5,yb-kim/gemV,SanchayanMaity/gem5,TUD-OS/gem5-dtu,cancro7/gem5,kaiyuanl/gem5,gem5/gem5,rjschof/gem5,rallylee/gem5,rjschof/gem5,Weil0ng/gem5,kaiyuanl/gem5,rallylee/gem5,yb-kim/gemV,Weil0ng/gem5,TUD-OS/gem5-dtu,qizenguf/MLC-STT,KuroeKurose/gem5,austinharris/gem5-riscv,sobercoder/gem5,zlfben/gem5,austinharris/gem5-riscv,cancro7/gem5,samueldotj/TeeRISC-Simulator,briancoutinho0905/2dsampling,markoshorro/gem5,austinharris/gem5-riscv,qizenguf/MLC-STT,markoshorro/gem5,KuroeKurose/gem5,joerocklin/gem5,gedare/gem5,KuroeKurose/gem5,rjschof/gem5,kaiyuanl/gem5,gedare/gem5,qizenguf/MLC-STT,sobercoder/gem5,kaiyuanl/gem5,aclifton/cpeg853-gem5,austinharris/gem5-riscv,samueldotj/TeeRISC-Simulator,qizenguf/MLC-STT,aclifton/cpeg853-gem5,samueldotj/TeeRISC-Simulator,yb-kim/gemV,Weil0ng/gem5