stm32: clock: avoid division by zero worries.
stm32: clock: avoid division by zero worries.

In chip_config.h, PLLM / PLLN / PLLR was predefined as 0. It raise
concern that frequency calculation would have division by zero issue.
Redefine PLLM / PLLN / PLLR as 1 to remove such worry.

BRANCH=main
BUG=b:188117811
TEST=make buildall

Signed-off-by: Bossen WU <bdf0d5f9d1715eb5414024c4670c571841ae5f36@stmicro.corp-partner.google.com>
Change-Id: If57aa40af29e0176762a981bd5b2dac9528b1144
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2999412
Reviewed-by: Eric Yilun Lin <2f2733c7206ea2b76bd2db1905cc5e8a75841c48@google.com>

coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec