Silence spurious warning in Verilog lexer when compiling with GCC
Silence spurious warning in Verilog lexer when compiling with GCC

The chosen value shouldn't have any effect. I considered something
clearly wrong like -1, but there's no checking inside the generated
lexer, and I suspect this will cause even weirder bugs if triggered
than just setting it to INITIAL.

SymbiFlow/yosys,antmicro/yosys,cliffordwolf/yosys,YosysHQ/yosys,SymbiFlow/yosys,YosysHQ/yosys,antmicro/yosys,cliffordwolf/yosys,cliffordwolf/yosys,YosysHQ/yosys,cliffordwolf/yosys,YosysHQ/yosys,SymbiFlow/yosys,SymbiFlow/yosys,antmicro/yosys,YosysHQ/yosys,YosysHQ/yosys,SymbiFlow/yosys,cliffordwolf/yosys,antmicro/yosys,antmicro/yosys,cliffordwolf/yosys,YosysHQ/yosys,YosysHQ/yosys,cliffordwolf/yosys,antmicro/yosys,SymbiFlow/yosys,antmicro/yosys,SymbiFlow/yosys,SymbiFlow/yosys,cliffordwolf/yosys,antmicro/yosys,cliffordwolf/yosys