fpga/system_build.tcl: Support oh_verilog_define flag
fpga/system_build.tcl: Support oh_verilog_define flag

Workaround for that recent Vivado versions (2016.4) doesn't seem to
support this any longer:
set_property -name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} -value $foo -objects [get_runs synth_1]

Signed-off-by: Ola Jeppsson <793f970c52ded1276b9264c742f19d1888cbaf73@adapteva.com>

olajep/oh,parallella/oh,olajep/oh,parallella/oh,olajep/oh,parallella/oh,olajep/oh,parallella/oh