arm: set uopSet_uop as conditional or unconditional control uopSet_uop is microop instruction that has the IsControl flags set, but the IsCondControl or IsUncondControl flags seems not to be set, neither in the construction nor where the microop is used. This patch adds the the flags in the constructor of the instruction (MicroUopSetPCCPSR).
arm: set uopSet_uop as conditional or unconditional control
uopSet_uop is microop instruction that has the IsControl flags set, but the
IsCondControl or IsUncondControl flags seems not to be set, neither in
the construction nor where the microop is used. This patch adds the the
flags in the constructor of the instruction (MicroUopSetPCCPSR).

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

joerocklin/gem5,briancoutinho0905/2dsampling,cancro7/gem5,gedare/gem5,gem5/gem5,rallylee/gem5,TUD-OS/gem5-dtu,markoshorro/gem5,rallylee/gem5,markoshorro/gem5,austinharris/gem5-riscv,kaiyuanl/gem5,joerocklin/gem5,KuroeKurose/gem5,gem5/gem5,aclifton/cpeg853-gem5,TUD-OS/gem5-dtu,powerjg/gem5-ci-test,yb-kim/gemV,rallylee/gem5,aclifton/cpeg853-gem5,briancoutinho0905/2dsampling,rallylee/gem5,rjschof/gem5,SanchayanMaity/gem5,yb-kim/gemV,TUD-OS/gem5-dtu,samueldotj/TeeRISC-Simulator,SanchayanMaity/gem5,briancoutinho0905/2dsampling,cancro7/gem5,yb-kim/gemV,rjschof/gem5,gedare/gem5,austinharris/gem5-riscv,gem5/gem5,samueldotj/TeeRISC-Simulator,rjschof/gem5,sobercoder/gem5,gedare/gem5,aclifton/cpeg853-gem5,zlfben/gem5,markoshorro/gem5,Weil0ng/gem5,joerocklin/gem5,powerjg/gem5-ci-test,austinharris/gem5-riscv,KuroeKurose/gem5,sobercoder/gem5,austinharris/gem5-riscv,qizenguf/MLC-STT,sobercoder/gem5,zlfben/gem5,austinharris/gem5-riscv,briancoutinho0905/2dsampling,KuroeKurose/gem5,qizenguf/MLC-STT,Weil0ng/gem5,samueldotj/TeeRISC-Simulator,powerjg/gem5-ci-test,sobercoder/gem5,HwisooSo/gemV-update,yb-kim/gemV,TUD-OS/gem5-dtu,cancro7/gem5,rjschof/gem5,cancro7/gem5,gem5/gem5,kaiyuanl/gem5,briancoutinho0905/2dsampling,joerocklin/gem5,qizenguf/MLC-STT,aclifton/cpeg853-gem5,SanchayanMaity/gem5,aclifton/cpeg853-gem5,zlfben/gem5,gedare/gem5,kaiyuanl/gem5,qizenguf/MLC-STT,HwisooSo/gemV-update,Weil0ng/gem5,aclifton/cpeg853-gem5,SanchayanMaity/gem5,kaiyuanl/gem5,gedare/gem5,kaiyuanl/gem5,TUD-OS/gem5-dtu,austinharris/gem5-riscv,powerjg/gem5-ci-test,joerocklin/gem5,yb-kim/gemV,joerocklin/gem5,SanchayanMaity/gem5,zlfben/gem5,sobercoder/gem5,Weil0ng/gem5,rallylee/gem5,Weil0ng/gem5,gem5/gem5,KuroeKurose/gem5,sobercoder/gem5,gedare/gem5,HwisooSo/gemV-update,rallylee/gem5,HwisooSo/gemV-update,KuroeKurose/gem5,cancro7/gem5,joerocklin/gem5,SanchayanMaity/gem5,samueldotj/TeeRISC-Simulator,zlfben/gem5,powerjg/gem5-ci-test,yb-kim/gemV,briancoutinho0905/2dsampling,powerjg/gem5-ci-test,markoshorro/gem5,gedare/gem5,zlfben/gem5,HwisooSo/gemV-update,rjschof/gem5,cancro7/gem5,samueldotj/TeeRISC-Simulator,rjschof/gem5,qizenguf/MLC-STT,yb-kim/gemV,markoshorro/gem5,HwisooSo/gemV-update,qizenguf/MLC-STT,briancoutinho0905/2dsampling,powerjg/gem5-ci-test,aclifton/cpeg853-gem5,SanchayanMaity/gem5,Weil0ng/gem5,qizenguf/MLC-STT,kaiyuanl/gem5,TUD-OS/gem5-dtu,KuroeKurose/gem5,rallylee/gem5,HwisooSo/gemV-update,samueldotj/TeeRISC-Simulator,markoshorro/gem5,TUD-OS/gem5-dtu,yb-kim/gemV,cancro7/gem5,KuroeKurose/gem5,zlfben/gem5,samueldotj/TeeRISC-Simulator,Weil0ng/gem5,gem5/gem5,rjschof/gem5,austinharris/gem5-riscv,markoshorro/gem5,joerocklin/gem5,kaiyuanl/gem5,gem5/gem5,sobercoder/gem5