AXI4_Deburster.bsv: Make implementation reasonably synthesisable
AXI4_Deburster.bsv: Make implementation reasonably synthesisable

Using the modulus operator does not synthesise efficiently as
wrap_boundary is not statically known to be a power of 2 without
external knowledge of the AXI specification, putting it on a critical
path with over -30ns WNS in the Connectal-based SSITH AWS SoC, and
likely also AWSteria once FPGA builds are attempted.

Instead, exploit the fact that the burst length is required to be a
power of two, and use a bitmask to wrap the address within the aligned
range.

bluespec/Flute,bluespec/Flute,bluespec/Flute