setup identity mapped paging tables
setup identity mapped paging tables

This commit moves the kernel into long mode with paging enabled. The P4,
P3, and P2 tables are set up, with P2 identity mapped to the lowest 1gib
using 2mib frames. We omit the P1 table entirely.

Paging isn't a difficult concept, but the x86 implementation needlessly
complicates the idea by making strange choices about how the address
bits are laid out. This is how I understand things:

Virtual addresses:

   .---------------------- nominal address ----------------------.
   |                                                             |
   +--------16|-------9|-------9|-------9|-------9|------------12|
   | sign ext | p4 idx | p3 idx | p2 idx | p1 idx | frame offset |
   63-------48|47----39|38----30|29----21|20----12|11------------0
              |                                   |              |
              '-------- effective address --------'              |
              |                                                  |
              '---------------- logical address -----------------'

   Virtual addresses are nominally (canonically) 64 bits, consisting of
   the sign extension bits, an index into each paging table, and an
   offset into the physical frame. Ignoring the sign extension (which
   can be derived from the p4 index), the address is logically 48 bits.
   The indexes and offset are sufficient to fully qualify the location.
   The offset bits are really a component of the physical address
   though, so effectively the virtual address is just the 36 bits used
   to navigate the paging tables.

Physical addresses (as page table entries):

   .---------------------- nominal address ----------------------.
   |                                                             |
   +---------1|----11|--------------------------40|-----3|------9|
   | exec bit | open | page-aligned frame address | open | flags |
   63-------63|62--52|51------------------------12|11---9|8------0
                     |                            |              |
                     '----- effective address ----'              |
                     |                                           |
                     '----- logical address (+frame offset) -----'

   Physical addresses are nominally 64 bits as well, consisting of a few
   bits for flags and then the page-aligned physical frame address. We
   can immediately omit the leading flags such that the physical address
   is logically 52 bits wide. What's more, the lower 12 bits of the
   address part are overloaded as flags to take advantage of the fact
   that these bits will always be zero due to page alignment. Thus
   physical addresses are effectively just 40 bits. To be exact, though,
   this address only describes the location of a page-aligned frame, not
   an arbitrary memory address. Hence a fully-qualified physical address
   must include the frame offset specified in the virtual address.[1]

   [1]: This is why paging tables must be aligned: their internal
        entries aren't treated as virtual addresses so the frame offset
        is unavailable.

caipre/mezzo,caipre/mezzo