[chip/dv] Fix ext_clk selection that causes uart failures
[chip/dv] Fix ext_clk selection that causes uart failures

in dv_base_test, we invoke initialize and then cfg.randomize
Need to disable cfg.clk_freq_mhz rand_mode in initialize, since it's set according
to plus-arg

Signed-off-by: Weicai Yang <4fa8c7762ee4da95e3dee7dae2c3263ea16637f9@google.com>

lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan