[aes] Fix clearing of data input registers without inferring combo loop
[aes] Fix clearing of data input registers without inferring combo loop

Previously, the write enable for the data input registers was set for
two clock cycles when clearing the registers. This caused the
data_in_qe_i signals used for status tracking to be high during the
first clock cycle when back in IDLE. As a result, the AES unit would
immediately start when running in automatic operation.

This is a second version of the fix that doesn't infer a combo loop by
splitting the clearing operation into two distinct states: First CLEAR_I
clears input registers such as Initial Key, IV and input data registers.
Then CLEAR_CO waits for the cipher core, clears the trigger bits and
if selected also clear the output data registers.

This is related to lowRISC/OpenTitan#11431 and lowRISC/OpenTitan#11758.

Signed-off-by: Pirmin Vogel <386a7fc8e7338ed7899b4d9883c0ebec5de81366@lowrisc.org>

lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan