npcx: workaround the bug that SHM data read via eSPI may be corrupted
npcx: workaround the bug that SHM data read via eSPI may be corrupted

In eSPI systems, when the Host performs a data read from the Shared
Memory space, the returned data may be corrupted. This is a result of
the Core-to-Host access enable bit being toggled (by toggling CSAE bit
in SIBCTRL register) during an eSPI transaction.

The workaround in this CL is to set CSAE bit to 1 during initialization
and remove the toggling of CSAE bit from other EC firmware code.
(i.e., let the CSAE bit be always 1.)

BRANCH=none
BUG=none
TEST=No build errors for make buildall. Flash poppy ec image, make sure
it can boot to OS. Run "ectool version" over 100000 times, no error
occurs.

Change-Id: I7aac6805ece64e8f77964d4acb026d9871cd2ebe
Signed-off-by: CHLin <84d2fca36f9d804bb7b1903655f14e4c722a99c4@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/590396
Commit-Ready: Shawn N <5259333ce42e3ace6a73988cec7115ed9d3a661a@chromium.org>
Tested-by: CH Lin <49997681dc186e71092740314bf6c6feeca6e227@nuvoton.com>
Reviewed-by: Shawn N <5259333ce42e3ace6a73988cec7115ed9d3a661a@chromium.org>

coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec