GBE: implement pre-register-allocation instruction scheduling.
GBE: implement pre-register-allocation instruction scheduling.

To find out an instruction scheduling policy to achieve the theoretical minimum
registers required in a basic block is a NP problem. We have to use some heuristic
factor to simplify the algorithm. There are many researchs which indicate a
bottom-up list scheduling is much better than the top-down method in turns of
register pressure.  I choose one of such research paper as our target. The paper
is as below:

"Register-Sensitive Selection, Duplication, and Sequencing of Instructions"
It use the bottom-up list scheduling with a Sethi-Ullman label as an
heuristic number. As we will do cycle awareness scheduling after the register
allocation, we don't need to bother with cycle related heuristic number here.
I just skipped the EST computing and usage part in the algorithm.

It turns out this algorithm works well. It could reduce the register spilling
in clBlas's sgemmBlock kernel from 83+ to only 20.

Although this scheduling method seems to be lowering the ILP(instruction level parallism).
It's not a big issue, because we will allocate as much as possible different registers
in the following register allocation stage, and we will do a after allocation
instruction scheduling which will try to get as much ILP as possible.

Signed-off-by: Zhigang Gong <e04a7b9b70b1e4c6318cf117dcd1a9056e14b97a@intel.com>
Reviewed-by: Ruiling Song <286a174c1339c6eff91abc41c3a1012c95030c95@intel.com>

wdv4758h/beignet,wdv4758h/beignet,wdv4758h/beignet,wdv4758h/beignet,wdv4758h/beignet