mtd: nand: pxa3xx: Fix PIO FIFO draining
mtd: nand: pxa3xx: Fix PIO FIFO draining

The NDDB register holds the data that are needed by the read and write
commands.

However, during a read PIO access, the datasheet specifies that after each 32
bytes read in that register, when BCH is enabled, we have to make sure that the
RDDREQ bit is set in the NDSR register.

This fixes an issue that was seen on the Armada 385, and presumably other mvebu
SoCs, when a read on a newly erased page would end up in the driver reporting a
timeout from the NAND.

Cc: <4fbacc2fa0ffdbb11bf1ad6925b886ebd08dd15f@vger.kernel.org> # v3.14
Signed-off-by: Maxime Ripard <2d324f4ca95610bde432fa2af2f28cd21110687d@free-electrons.com>
Reviewed-by: Boris Brezillon <4e91513d4f418754031d3d36b3fc73980c40a38c@free-electrons.com>
Acked-by: Ezequiel Garcia <7248f52d8926fd82a5eb079a13afe9dd79e34c7a@free-electrons.com>
Signed-off-by: Brian Norris <ac73eed4b8a8c9127255a2696c52b2e7503720b8@gmail.com>

KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs