Reset for the core was not properly synchronized into core clock domain. This may explain some of the intermittent failures on boot.
Reset for the core was not properly synchronized into core clock domain.
This may explain some of the intermittent failures on boot.

jbush001/NyuziProcessor,FulcronZ/NyuziProcessor,hoangt/NyuziProcessor,hoangt/NyuziProcessor,jbush001/NyuziProcessor,FulcronZ/NyuziProcessor,FulcronZ/NyuziProcessor,jbush001/NyuziProcessor,hoangt/NyuziProcessor,FulcronZ/NyuziProcessor,jbush001/NyuziProcessor,hoangt/NyuziProcessor,jbush001/NyuziProcessor,jbush001/NyuziProcessor