Add `mstack` CSRs for recoverable NMIs
Add `mstack` CSRs for recoverable NMIs

To enable recoverable non-maskeable interrupts (NMIs), an additional
set of registers is needed to backup `mstatus.MPP/MPIE` as well as
`mepc` and `mcause`. This is currently not part of the RISC-V Priv
Spec (v1.11). This commit adds these registers called `mstack` CSRs
according to the following proposal:
https://github.com/riscv/riscv-isa-manual/issues/261

These CSRs are only accessed by the hardware and not accessible to
software running on the core.

lowRISC/ibex,lowRISC/ibex,lowRISC/ibex,lowRISC/ibex,AmbiML/ibex,AmbiML/ibex,AmbiML/ibex,AmbiML/ibex