drm/i915: Modify DP set clock to accomodate more eDP timings v2
drm/i915: Modify DP set clock to accomodate more eDP timings v2

eDP 1.4 supports 4-5 extra link rates in additional to current 2 link
rate.  Create a structure to store the DPLL divisor data to improve
readability.

v2: Fix the gen4_dpll/pch_dpll initialization to C99
designated initializers, and use a single loop for all platforms. (Jani and Daniel)

Signed-off-by: Chon Ming Lee <cadf66cff30b6a19447acdb0353c5f8d301877c6@intel.com>
[danvet: Fix up checkpatch warnings.]
Signed-off-by: Daniel Vetter <c1b6782c4af8f0673da8923a0702a1832e5940f4@ffwll.ch>

KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs