Update ARM code generation of strided loads to generic vector code. LLVM >=3.7 lowers this to the correct intrinsics in the interleave access pass.
Update ARM code generation of strided loads to generic vector code. LLVM >=3.7 lowers this to the correct intrinsics in the interleave access pass.


Former-commit-id: 62bc28d94156cdffc6da161d7c320cea6c0dc7e4
darkbuck/Halide,Trass3r/Halide,Trass3r/Halide,Trass3r/Halide,darkbuck/Halide,Trass3r/Halide,darkbuck/Halide,darkbuck/Halide,Trass3r/Halide,Trass3r/Halide,Trass3r/Halide,darkbuck/Halide,darkbuck/Halide,darkbuck/Halide