Verilog output missing clk declaration. No further errors in simple combinational example.
Verilog output missing clk declaration. No further errors in simple combinational example.

UCSBarchlab/PyRTL,UCSBarchlab/PyRTL,nvandervoort/PyRTL,deekshadangwal/PyRTL,nvandervoort/PyRTL,deekshadangwal/PyRTL