GBE: implement further phi mov optimization based on intra-BB interefering analysis.
GBE: implement further phi mov optimization based on intra-BB interefering analysis.

The previous phi mov optimization try to reduce the phi copy source register
and the phi copy register if the phi copy source register is a normal SSA value.

But for some cases, many phi copy source registers are also phi copy value which
has multiple definitions. And they could all be reduced to one phi copy register
if there is no interfering in all BBs. This patch with the previous patches could
reduce the whole spilled register from 200+ to only 70 for a SGEMM kernel and the
performance could boost about 10 times.

v2:
Add one FIXME tag to indicate one more optimization opportunity we missed in current
implementation. Could be solved in the future.

v3:
Disable postPhi mov optimization for now as there is a liveness bug
need to be fixed.

Signed-off-by: Zhigang Gong <e04a7b9b70b1e4c6318cf117dcd1a9056e14b97a@intel.com>
Reviewed-by: Ruiling Song <286a174c1339c6eff91abc41c3a1012c95030c95@intel.com>

wdv4758h/beignet,wdv4758h/beignet,wdv4758h/beignet,wdv4758h/beignet,wdv4758h/beignet