write_verilog: emit intermediate wire for constant values in sensitivity list
write_verilog: emit intermediate wire for constant values in sensitivity list

antmicro/yosys,YosysHQ/yosys,SymbiFlow/yosys,cliffordwolf/yosys,antmicro/yosys,SymbiFlow/yosys,YosysHQ/yosys,antmicro/yosys,SymbiFlow/yosys,YosysHQ/yosys,cliffordwolf/yosys,antmicro/yosys,cliffordwolf/yosys,antmicro/yosys,antmicro/yosys,cliffordwolf/yosys,SymbiFlow/yosys,SymbiFlow/yosys,cliffordwolf/yosys,cliffordwolf/yosys,YosysHQ/yosys,cliffordwolf/yosys,YosysHQ/yosys,YosysHQ/yosys,cliffordwolf/yosys,antmicro/yosys,YosysHQ/yosys,SymbiFlow/yosys,cliffordwolf/yosys,antmicro/yosys,SymbiFlow/yosys,SymbiFlow/yosys,YosysHQ/yosys