Made changes recommended by Clifford Wolf ...
Made changes recommended by Clifford Wolf ...

Removed bit_check_equal(), used RTLIL::SigBit for individual bits, used
dict<> instead of std::map, and used RTLIL::SigSpec instead of
std::vector.

antmicro/yosys,cliffordwolf/yosys,antmicro/yosys,antmicro/yosys,cliffordwolf/yosys,cliffordwolf/yosys,azonenberg/yosys,azonenberg/yosys,SymbiFlow/yosys,swallat/yosys,SymbiFlow/yosys,YosysHQ/yosys,antmicro/yosys,YosysHQ/yosys,antmicro/yosys,antmicro/yosys,swallat/yosys,SymbiFlow/yosys,SymbiFlow/yosys,swallat/yosys,cliffordwolf/yosys,azonenberg/yosys,cliffordwolf/yosys,azonenberg/yosys,SymbiFlow/yosys,azonenberg/yosys,cliffordwolf/yosys,SymbiFlow/yosys,YosysHQ/yosys,swallat/yosys,swallat/yosys,SymbiFlow/yosys,SymbiFlow/yosys,cliffordwolf/yosys,azonenberg/yosys,antmicro/yosys,YosysHQ/yosys,swallat/yosys,YosysHQ/yosys,swallat/yosys,swallat/yosys,cliffordwolf/yosys,azonenberg/yosys,YosysHQ/yosys,antmicro/yosys,YosysHQ/yosys,YosysHQ/yosys,azonenberg/yosys,swallat/yosys,cliffordwolf/yosys,azonenberg/yosys