ARM: ux500: add CoreSight blocks to DTS file
ARM: ux500: add CoreSight blocks to DTS file

This registers all the CoreSight blocks on the DB8500 SoC:
each core has a PTM (v1.0, r1p0-00rel0) connected, both connected
to a funnel (DK-TM908-r0p1-00rel0) which in turn connects to a
replicator (DM-TM909-r0p1-00rel0). The replicator has two outputs,
port 0 to a TPIU interface and port 1 to an ETB
(DK-TM907-r0p3-00rel0). The CoreSight blocks are all clocked by
the APEATCLK from the PRCMU and their AHB interconnect is clocked
from a separate clock called APETRACECLK.

The SoC also has a CTI/CTM block which can be added later as we
have upstream support in the CoreSight subsystem.

Acked-by: Mathieu Poirier <b674a88f52ddcf15fbad298f5a49af203db9e3b7@linaro.org>
Signed-off-by: Linus Walleij <9cd9d802d23c0ed5e224beabf4ae4a5c478746ef@linaro.org>

KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs