clk: qcom: Fix sdc 144kHz frequency entry
clk: qcom: Fix sdc 144kHz frequency entry

The pre-divider for the sdc clocks only has 2 bits in it, so we
can't possibly divide by anything larger than 4 here.
Furthermore, we program the value of ~(n - m) and the n value is
larger than 8 bits (max of 256). Replace this entry with 200kHz
which is close enough to 144kHz to be usable.

Cc: Kumar Gala <383ef5577c6e1178b93f59ec8d0936f76d2a98c4@codeaurora.org>
Cc: Andy Gross <3e259a9c7ec8261c71cce57b93152e64c5e60da4@codeaurora.org>
Fixes: 24d8fba44af3 "clk: qcom: Add support for IPQ8064's global clock controller (GCC)"
Signed-off-by: Stephen Boyd <010521127f513270fe503d86ab8316ac5147f4b7@codeaurora.org>
Signed-off-by: Mike Turquette <6dab61939fc5e23761050a66932f032dceda5ebf@linaro.org>

KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs