trivial: fix reading the microcode version on AMD systems
trivial: fix reading the microcode version on AMD systems

The kernel will issue a CPUID of 0x1 before reading microcode.
Align this behavior with the MSR plugin.

AMD and Intel align their microcode diffrently in MSR 0x8b.
* Intel it's 4 bytes in.
* AMD it's at the start of the MSR.

fwupd/fwupd,fwupd/fwupd,fwupd/fwupd,fwupd/fwupd