Two fixes to try and get TLB miss cost more in line with real platform: 1) Add fault_handler_delay param to FullCPU to wait N cycles after committing faulting instruction before fetching fault handler. 2) Make hw_rei a serializing instruction (flushes pipe, basically).
Two fixes to try and get TLB miss cost more in line with real platform:
1) Add fault_handler_delay param to FullCPU to wait N cycles after
committing faulting instruction before fetching fault handler.
2) Make hw_rei a serializing instruction (flushes pipe, basically).

arch/alpha/isa_desc:
    Make hw_rei a serializing instruction (guarantees previous insts
    complete before hw_rei will issue).

haowu4682/gem5,haowu4682/gem5,haowu4682/gem5,LingxiaoJIA/gem5,haowu4682/gem5,haowu4682/gem5,andrewfu0325/gem5-aladdin,LingxiaoJIA/gem5,LingxiaoJIA/gem5,haowu4682/gem5,andrewfu0325/gem5-aladdin,haowu4682/gem5,LingxiaoJIA/gem5,andrewfu0325/gem5-aladdin,andrewfu0325/gem5-aladdin,haowu4682/gem5,andrewfu0325/gem5-aladdin,LingxiaoJIA/gem5,haowu4682/gem5,andrewfu0325/gem5-aladdin,LingxiaoJIA/gem5,andrewfu0325/gem5-aladdin,LingxiaoJIA/gem5