cpu/esp_common: port periph/i2c_sw with calculated delays
cpu/esp_common: port periph/i2c_sw with calculated delays

Fixed delay values are replaced by calculated delays measured in CPU cycles in I2C software implementation. The advantage is that for each ESP SoC only a clock calibration offset has to be specified. The delay measured in CPU cycles are then then derived from current CPU frequency for the given bus speed. The disadvantage is that the calculated delays are not as precise as the predefined fixed delays.

jasonatran/RIOT,kYc0o/RIOT,kaspar030/RIOT,kaspar030/RIOT,miri64/RIOT,kYc0o/RIOT,ant9000/RIOT,RIOT-OS/RIOT,kaspar030/RIOT,RIOT-OS/RIOT,kYc0o/RIOT,jasonatran/RIOT,kaspar030/RIOT,ant9000/RIOT,miri64/RIOT,kYc0o/RIOT,kYc0o/RIOT,ant9000/RIOT,kaspar030/RIOT,jasonatran/RIOT,ant9000/RIOT,RIOT-OS/RIOT,miri64/RIOT,RIOT-OS/RIOT,RIOT-OS/RIOT,jasonatran/RIOT,ant9000/RIOT,jasonatran/RIOT,miri64/RIOT,miri64/RIOT