genxml/hsw: Add L3 cache control registers
genxml/hsw: Add L3 cache control registers

These were added to the i965 driver in
5912da45a69923afa1b7f2eb5bb371d848813c41.

Signed-off-by: Jordan Justen <a79006884ba9cf5f4f7fcbb92a15b208780d8c97@intel.com>
Reviewed-by: Jason Ekstrand <68c46a606457643eab92053c1c05574abb26f861@jlekstrand.net>

metora/MesaGLSLCompiler,metora/MesaGLSLCompiler,metora/MesaGLSLCompiler