strago: Power state transition in case of apshutdown
strago: Power state transition in case of apshutdown

In case of 'apshutdown', during transition to S5 state,
GPIO_PCH_SLP_S4_L signal was not getting deasserted but
required rail went away (GPIO_PCH_SYS_PWROK). So it was
going on a loop S5 -> S3 and S3 -> S5.
In strago GPIO_PCH_SYS_PWROK is the PMIC_EN GPIO and hence
conditinally setting it based on CONFIG_PMIC

BUG=none
TEST=apshutdown on strago
BRANCH=none

Change-Id: I9c581a3dfcb9cc84a22b41505e7df496d72d5f4c
Signed-off-by: Kumar, Gomathi <070fec7cecd76393d5037ded1740fbf718e6a3f6@intel.com>
Signed-off-by: Divagar Mohandass <ff426658e16095e1f3195dd2cccc34b48025db22@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/292024
Reviewed-by: Shawn N <5259333ce42e3ace6a73988cec7115ed9d3a661a@chromium.org>

fourier49/BIZ_EC,fourier49/BIZ_EC,fourier49/BIZ_EC,fourier49/BIZ_EC