PCI: designware: Fix RC BAR to be single 64-bit non-prefetchable memory BAR
PCI: designware: Fix RC BAR to be single 64-bit non-prefetchable memory BAR

The Synopsys PCIe core provides one pair of 32-bit BARs (BAR 0 and BAR 1).
The BARs can be configured as follows:

  - One 64-bit BAR: BARs 0 and 1 are combined to form a single 64-bit BAR
  - Two 32-bit BARs: BARs 0 and 1 are two independent 32-bit BARs

This patch corrects 64-bit, non-prefetchable memory BAR configuration
implemented in dw driver.

Signed-off-by: Mohit Kumar <e81db36ab52392345806c7bc8596be7c3b491eae@st.com>
Signed-off-by: Bjorn Helgaas <f10ec01be0c6b54271af5c550cd257810bdf3268@google.com>
Cc: Pratyush Anand <312638e7d640785762ded1305e88fac68d55a9ab@st.com>
Cc: Jingoo Han <fc379137a64feb86ce38ec5811a14280acc1ccfc@samsung.com>
Cc: Arnd Bergmann <f2c659f01951776204a6c5b902787d9019fbeebd@arndb.de>
Cc: 4fbacc2fa0ffdbb11bf1ad6925b886ebd08dd15f@vger.kernel.org	# v3.12+
KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs