gpio: sifive: fix interrupt handling
gpio: sifive: fix interrupt handling

The primary problem was that the callback was being invoked twice,
which broke the tests.

A secondary issue is that when two level tests occur consecutively the
second will fail.  Instrumentation confirms that the registers are
being configured correctly, and ip indicates that the condition was
detected, but the interrupt does not occur.  Tests pass as long as no
level test precedes the failing test.

It's not clear whether this is an issue with the PLIC, or the GPIO
implementation (hardware or software).  As "normal" GPIO applications
appear to work we'll run with it and keep an issue open.

Signed-off-by: Peter A. Bigot <650538893330be855f76604594b4820eb226769e@pabigot.com>

zephyrproject-rtos/zephyr,zephyrproject-rtos/zephyr,zephyrproject-rtos/zephyr,galak/zephyr,galak/zephyr,nashif/zephyr,nashif/zephyr,finikorg/zephyr,Vudentz/zephyr,finikorg/zephyr,finikorg/zephyr,Vudentz/zephyr,Vudentz/zephyr,nashif/zephyr,finikorg/zephyr,zephyrproject-rtos/zephyr,nashif/zephyr,galak/zephyr,galak/zephyr,zephyrproject-rtos/zephyr,nashif/zephyr,galak/zephyr,Vudentz/zephyr,Vudentz/zephyr,finikorg/zephyr,Vudentz/zephyr