MIPS: JZ4740: define IRQ numbers based on number of intc IRQs
MIPS: JZ4740: define IRQ numbers based on number of intc IRQs

For interrupts numbered after those of the interrupt controller, define
their numbers based upon the number of interrupts provided by the SoC
interrupt controller. This is in preparation for supporting newer
Ingenic SoCs which provide more interrupts.

Signed-off-by: Paul Burton <85f1bffadddedccfafc0ae065a06aa636075387f@imgtec.com>
Cc: Lars-Peter Clausen <3318dc5ce3e4fb7c28a0b841b6801c884e1d0896@metafoo.de>
Cc: Thomas Gleixner <00e4cf8f46a57000a44449bf9dd8cbbcc209fd2a@linutronix.de>
Cc: Jason Cooper <68c46a606457643eab92053c1c05574abb26f861@lakedaemon.net>
Cc: 562397917b9a8bf316569a848858b12fb417723f@linux-mips.org
Cc: 2578944098299abf708b08eff6fcf60565553586@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10143/
Signed-off-by: Ralf Baechle <92f48d309cda194c8eda36aa8f9ae28c488fa208@linux-mips.org>

KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs