[dv,top] Fix chip_sw_aon_timer_irq
[dv,top] Fix chip_sw_aon_timer_irq

The test is requires an ISR to happen at within a certain number of
cycles of the programmed timeout. It provides some slack to account
for the time it takes to service the ISR, but that slack is too tight.
This increases the slack from 500 to 600 CPU cycles.

Fixes #14838

Signed-off-by: Guillermo Maturana <085716c7110d3f31793f7d964c2e5fd26da1c550@google.com>

lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan,lowRISC/opentitan