Config: change how cpu class is set This changes the way in which the cpu class while restoring from a checkpoint is set. Earlier it was assumed if cpu type with which to restore is not same as the cpu type with the which to run the simulation, then the checkpoint should be restored with the atomic cpu. This assumption is being dropped. The checkpoint can now be restored with any cpu type, the default being atomic cpu.
Config: change how cpu class is set
This changes the way in which the cpu class while restoring from a checkpoint
is set. Earlier it was assumed if cpu type with which to restore is not same
as the cpu type with the which to run the simulation, then the checkpoint
should be restored with the atomic cpu. This assumption is being dropped. The
checkpoint can now be restored with any cpu type, the default being atomic cpu.

briancoutinho0905/2dsampling,sobercoder/gem5,briancoutinho0905/2dsampling,aclifton/cpeg853-gem5,yb-kim/gemV,powerjg/gem5-ci-test,samueldotj/TeeRISC-Simulator,HwisooSo/gemV-update,TUD-OS/gem5-dtu,sobercoder/gem5,powerjg/gem5-ci-test,samueldotj/TeeRISC-Simulator,Weil0ng/gem5,aclifton/cpeg853-gem5,samueldotj/TeeRISC-Simulator,gedare/gem5,austinharris/gem5-riscv,gem5/gem5,Weil0ng/gem5,SanchayanMaity/gem5,qizenguf/MLC-STT,TUD-OS/gem5-dtu,sobercoder/gem5,TUD-OS/gem5-dtu,gem5/gem5,briancoutinho0905/2dsampling,rjschof/gem5,Weil0ng/gem5,joerocklin/gem5,qizenguf/MLC-STT,zlfben/gem5,yb-kim/gemV,yb-kim/gemV,qizenguf/MLC-STT,qizenguf/MLC-STT,SanchayanMaity/gem5,joerocklin/gem5,SanchayanMaity/gem5,joerocklin/gem5,powerjg/gem5-ci-test,markoshorro/gem5,TUD-OS/gem5-dtu,rallylee/gem5,KuroeKurose/gem5,sobercoder/gem5,briancoutinho0905/2dsampling,markoshorro/gem5,powerjg/gem5-ci-test,SanchayanMaity/gem5,HwisooSo/gemV-update,gem5/gem5,yb-kim/gemV,gem5/gem5,zlfben/gem5,austinharris/gem5-riscv,joerocklin/gem5,KuroeKurose/gem5,markoshorro/gem5,austinharris/gem5-riscv,sobercoder/gem5,powerjg/gem5-ci-test,austinharris/gem5-riscv,HwisooSo/gemV-update,aclifton/cpeg853-gem5,SanchayanMaity/gem5,SanchayanMaity/gem5,TUD-OS/gem5-dtu,yb-kim/gemV,cancro7/gem5,zlfben/gem5,rjschof/gem5,cancro7/gem5,HwisooSo/gemV-update,gem5/gem5,KuroeKurose/gem5,briancoutinho0905/2dsampling,joerocklin/gem5,samueldotj/TeeRISC-Simulator,gedare/gem5,gedare/gem5,sobercoder/gem5,Weil0ng/gem5,rjschof/gem5,markoshorro/gem5,yb-kim/gemV,kaiyuanl/gem5,austinharris/gem5-riscv,rjschof/gem5,samueldotj/TeeRISC-Simulator,rjschof/gem5,KuroeKurose/gem5,aclifton/cpeg853-gem5,sobercoder/gem5,gedare/gem5,gedare/gem5,rallylee/gem5,HwisooSo/gemV-update,gem5/gem5,samueldotj/TeeRISC-Simulator,gedare/gem5,austinharris/gem5-riscv,samueldotj/TeeRISC-Simulator,cancro7/gem5,cancro7/gem5,kaiyuanl/gem5,Weil0ng/gem5,joerocklin/gem5,HwisooSo/gemV-update,zlfben/gem5,qizenguf/MLC-STT,markoshorro/gem5,SanchayanMaity/gem5,markoshorro/gem5,cancro7/gem5,gedare/gem5,zlfben/gem5,gem5/gem5,KuroeKurose/gem5,austinharris/gem5-riscv,rallylee/gem5,Weil0ng/gem5,rallylee/gem5,zlfben/gem5,kaiyuanl/gem5,TUD-OS/gem5-dtu,yb-kim/gemV,rjschof/gem5,rjschof/gem5,briancoutinho0905/2dsampling,KuroeKurose/gem5,aclifton/cpeg853-gem5,kaiyuanl/gem5,rallylee/gem5,rallylee/gem5,joerocklin/gem5,Weil0ng/gem5,HwisooSo/gemV-update,joerocklin/gem5,aclifton/cpeg853-gem5,powerjg/gem5-ci-test,cancro7/gem5,zlfben/gem5,kaiyuanl/gem5,cancro7/gem5,aclifton/cpeg853-gem5,rallylee/gem5,briancoutinho0905/2dsampling,powerjg/gem5-ci-test,kaiyuanl/gem5,KuroeKurose/gem5,markoshorro/gem5,qizenguf/MLC-STT,kaiyuanl/gem5,TUD-OS/gem5-dtu,qizenguf/MLC-STT,yb-kim/gemV