TCPMv2: PRL: Reorder prl state machines to fix hard reset issue
TCPMv2: PRL: Reorder prl state machines to fix hard reset issue

This CL fixes a race condition issue with the order of the PRL state
machines. If the hard reset state machine is executed last each tick,
then there can be a burst of hard reset messages sent if the phy layer
can act quickly (on chip TCPCs).

The hard reset state machine is executed first. Once
hard reset state machine is active, other state machines are paused,
except to send the hard reset message to the phy layer. When the hard
reset sequence completes, all other PRL state machines will have been
reset.

In addition, this CL enables the hr state machine to signal the phy
without requiring the prl tx state machine to execute. This allows all
other state machines to remain frozen once a hard reset sequence has
begun. This path matches the spec hard reset state flow more closely.

BUG=b:181142612
BRANCH=None
TEST=Triggered reset via 'pd 0 hard' and verified only one hard reset
event occurs.

Signed-off-by: Scott Collyer <7d40b3eb9e17bf55d972074a5e77a7ea4159f9dd@google.com>
Change-Id: I72335cefea9ab3c34cd2c166b07516133e6f523e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2667234
Tested-by: Scott Collyer <7d40b3eb9e17bf55d972074a5e77a7ea4159f9dd@chromium.org>
Reviewed-by: Diana Z <cb2016afc7183e5356c690dc63b4ba817470501a@chromium.org>
Commit-Queue: Scott Collyer <7d40b3eb9e17bf55d972074a5e77a7ea4159f9dd@chromium.org>

coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec