clk: tegra: Properly setup PWM clock on Tegra30
clk: tegra: Properly setup PWM clock on Tegra30

The clock for the PWM controller is slightly different from other
peripheral clocks on Tegra30. The clock source mux field start at
bit position 28 rather than 30.

Signed-off-by: Thierry Reding <3055038c414aef68bf32c33b8118623e7554e0f2@nvidia.com>

KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs