TimingSimpleCPU: fix NO_ACCESS memory op handling
TimingSimpleCPU: fix NO_ACCESS memory op handling

When a request is NO_ACCESS (x86 CDA microinstruction), the memory op
doesn't go to the cache, so TimingSimpleCPU::completeDataAccess needs
to handle the case where the current status of the CPU is Running
and not DcacheWaitResponse or DTBWaitResponse

markoshorro/gem5,gem5/gem5,markoshorro/gem5,briancoutinho0905/2dsampling,kaiyuanl/gem5,gem5/gem5,TUD-OS/gem5-dtu,SanchayanMaity/gem5,cancro7/gem5,cancro7/gem5,cancro7/gem5,gedare/gem5,rallylee/gem5,gedare/gem5,zlfben/gem5,qizenguf/MLC-STT,powerjg/gem5-ci-test,HwisooSo/gemV-update,KuroeKurose/gem5,kaiyuanl/gem5,rjschof/gem5,SanchayanMaity/gem5,yb-kim/gemV,gem5/gem5,Weil0ng/gem5,KuroeKurose/gem5,TUD-OS/gem5-dtu,Weil0ng/gem5,gedare/gem5,rjschof/gem5,briancoutinho0905/2dsampling,yb-kim/gemV,HwisooSo/gemV-update,KuroeKurose/gem5,sobercoder/gem5,joerocklin/gem5,markoshorro/gem5,rallylee/gem5,aclifton/cpeg853-gem5,zlfben/gem5,cancro7/gem5,SanchayanMaity/gem5,powerjg/gem5-ci-test,yb-kim/gemV,rjschof/gem5,Weil0ng/gem5,gem5/gem5,yb-kim/gemV,powerjg/gem5-ci-test,joerocklin/gem5,gedare/gem5,yb-kim/gemV,markoshorro/gem5,Weil0ng/gem5,samueldotj/TeeRISC-Simulator,samueldotj/TeeRISC-Simulator,aclifton/cpeg853-gem5,samueldotj/TeeRISC-Simulator,HwisooSo/gemV-update,qizenguf/MLC-STT,cancro7/gem5,SanchayanMaity/gem5,cancro7/gem5,sobercoder/gem5,kaiyuanl/gem5,austinharris/gem5-riscv,aclifton/cpeg853-gem5,rjschof/gem5,kaiyuanl/gem5,briancoutinho0905/2dsampling,zlfben/gem5,gedare/gem5,yb-kim/gemV,HwisooSo/gemV-update,samueldotj/TeeRISC-Simulator,rjschof/gem5,markoshorro/gem5,aclifton/cpeg853-gem5,aclifton/cpeg853-gem5,rallylee/gem5,zlfben/gem5,samueldotj/TeeRISC-Simulator,austinharris/gem5-riscv,KuroeKurose/gem5,kaiyuanl/gem5,briancoutinho0905/2dsampling,qizenguf/MLC-STT,joerocklin/gem5,gem5/gem5,samueldotj/TeeRISC-Simulator,markoshorro/gem5,cancro7/gem5,briancoutinho0905/2dsampling,powerjg/gem5-ci-test,zlfben/gem5,briancoutinho0905/2dsampling,gedare/gem5,Weil0ng/gem5,austinharris/gem5-riscv,yb-kim/gemV,KuroeKurose/gem5,austinharris/gem5-riscv,austinharris/gem5-riscv,qizenguf/MLC-STT,KuroeKurose/gem5,sobercoder/gem5,kaiyuanl/gem5,qizenguf/MLC-STT,austinharris/gem5-riscv,sobercoder/gem5,joerocklin/gem5,zlfben/gem5,joerocklin/gem5,gem5/gem5,samueldotj/TeeRISC-Simulator,TUD-OS/gem5-dtu,powerjg/gem5-ci-test,sobercoder/gem5,qizenguf/MLC-STT,powerjg/gem5-ci-test,gedare/gem5,rjschof/gem5,Weil0ng/gem5,rjschof/gem5,kaiyuanl/gem5,sobercoder/gem5,TUD-OS/gem5-dtu,KuroeKurose/gem5,powerjg/gem5-ci-test,yb-kim/gemV,joerocklin/gem5,Weil0ng/gem5,briancoutinho0905/2dsampling,rallylee/gem5,SanchayanMaity/gem5,zlfben/gem5,gem5/gem5,HwisooSo/gemV-update,TUD-OS/gem5-dtu,joerocklin/gem5,HwisooSo/gemV-update,sobercoder/gem5,TUD-OS/gem5-dtu,aclifton/cpeg853-gem5,rallylee/gem5,SanchayanMaity/gem5,aclifton/cpeg853-gem5,joerocklin/gem5,SanchayanMaity/gem5,qizenguf/MLC-STT,austinharris/gem5-riscv,rallylee/gem5,rallylee/gem5,HwisooSo/gemV-update,TUD-OS/gem5-dtu,markoshorro/gem5