drm/i915/hsw: Fix workaround for server AUX channel clock divisor
drm/i915/hsw: Fix workaround for server AUX channel clock divisor

According to the HSW b-spec we need to try clock divisors of 63
and 72, each 3 or more times, when attempting DP AUX channel
communication on a server chipset.  This actually wasn't happening
due to a short-circuit that only checked the DP_AUX_CH_CTL_DONE bit
in status rather than checking that the operation was done and
that DP_AUX_CH_CTL_TIME_OUT_ERROR was not set.

[v2] Implemented alternate solution suggested by Jani Nikula.

Cc: 4fbacc2fa0ffdbb11bf1ad6925b886ebd08dd15f@vger.kernel.org
Signed-off-by: Jim Bride <1afae83b95e182fce195feabb2305ca95369497a@linux.intel.com>
Signed-off-by: Jani Nikula <ba783f3beccaedfda693f41a15407d612a629408@intel.com>

KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs,KristFoundation/Programs