Change how to get cacheline size
Change how to get cacheline size

Some architecture does not support getting of LEVEL1_DCACHE_LINESIZE
by getconf. For example, ARM will return 0. Therefore, this can not be
built by architecture that is not supported LEVEL1_DCACHE_LINESIZE.
As far as I checked, 32bit architecture such as ARM, MIPS and other align
with 32.

This changes that set 32 to CACHELINE_SIZE when the LEVEL1_DCACHE_LINESIZE
returns 0.
It is difficult to cope in all architecture, but this can support much
architectures.

Signed-off-by: Nobuhiro Iwamatsu <b91c10c1aec1667e57a5b2aee1063de531249b10@nigauri.org>

mkouhei/yrmcds,cybozu/yrmcds,cybozu/yrmcds