Move \init from source wire to submod if output port
Move \init from source wire to submod if output port

cliffordwolf/yosys,YosysHQ/yosys,YosysHQ/yosys,YosysHQ/yosys,antmicro/yosys,YosysHQ/yosys,YosysHQ/yosys,antmicro/yosys,SymbiFlow/yosys,antmicro/yosys,antmicro/yosys,antmicro/yosys,cliffordwolf/yosys,cliffordwolf/yosys,antmicro/yosys,YosysHQ/yosys,cliffordwolf/yosys,YosysHQ/yosys,SymbiFlow/yosys,SymbiFlow/yosys,cliffordwolf/yosys,antmicro/yosys,YosysHQ/yosys,SymbiFlow/yosys,SymbiFlow/yosys,cliffordwolf/yosys,SymbiFlow/yosys,cliffordwolf/yosys,cliffordwolf/yosys,SymbiFlow/yosys,antmicro/yosys,cliffordwolf/yosys,SymbiFlow/yosys