hatch: Configure EC_INT_L as low before entering S5/G3
hatch: Configure EC_INT_L as low before entering S5/G3

EC_INT_L on hatch is a push-pull line driven by EC and going to SoC
GPIO. Having this driven high in G3 results in leakage on PP3300_A_SOC
rail. This change configures EC_INT_L to drive it low on entering S5
and re-configures it to drive high on exiting S5.

BUG=b:129306003
BRANCH=None
TEST=Verified that SLP_S0_L, EC_INT_L and SYS_RESET_L are pulled low
in G3.

Change-Id: I9b00eef72762b9d16afc42723e8985d752f83c55
Signed-off-by: Furquan Shaikh <6be5c96c464778f89679b1062a2e0a6af93d2aa5@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1553562
Commit-Ready: ChromeOS CL Exonerator Bot <fa429e5907f00867f797423aea74327bb02c91b6@appspot.gserviceaccount.com>
Tested-by: Furquan Shaikh <6be5c96c464778f89679b1062a2e0a6af93d2aa5@chromium.org>
Reviewed-by: Rachel Nancollas <375089e973a88bcaf6019cd9e416663e9022721a@google.com>
Reviewed-by: Philip Chen <3ee404f9ef892bc3fda6e6a76e65843b5fa44db2@chromium.org>
Reviewed-by: Tim Wawrzynczak <86444811eee8c2cb29e29a251d7a069e64ccc665@chromium.org>
Reviewed-by: Paul Fagerburg <d8c44b60afb21c60f56d931aa690ca1cf34910c8@chromium.org>

coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec