regulator: anatop: improve precision of delay time
regulator: anatop: improve precision of delay time

For cpufreq example, it takes 13 steps (25 mV for one step) to increase
vddcore from 0.95 V to 1.275 V, and the time of 64 clock cycles at
24 MHz for one step is ~2.67 uS, so the total delay time would be
~34.71 uS.  But the current calculation in the driver gives 39 uS.
Change the formula to have the addition of 1 be the last step, so that
we can get a more precise delay time.  For example above, the new
formula will give 35 uS.

Signed-off-by: Shawn Guo <912cf7eb7d8018e2943586ae6657d21fd4e38239@linaro.org>
Signed-off-by: Mark Brown <b51b9a92386687a9ac927cebfa0f978adeb8cea5@opensource.wolfsonmicro.com>

KristFoundation/Programs,KristFoundation/Programs,TeamVee-Kanas/android_kernel_samsung_kanas,TeamVee-Kanas/android_kernel_samsung_kanas,KristFoundation/Programs,TeamVee-Kanas/android_kernel_samsung_kanas,KristFoundation/Programs,KristFoundation/Programs,TeamVee-Kanas/android_kernel_samsung_kanas,TeamVee-Kanas/android_kernel_samsung_kanas,KristFoundation/Programs