Finish off most data hazards/stalling for memory.
Finish off most data hazards/stalling for memory.

- Be able to route previous pipeline registers by name.
- Stalls are inserted if hazard is detected, may not work under all cases yet.
- Loads have a delay slot after them, in attempt to follow MIPS I/R2000 as closely as possible.
- Add memtoreg control signal to get correct write_data.
- Human readable instructions for program.

deekshadangwal/PyRTL,UCSBarchlab/PyRTL,nvandervoort/PyRTL,UCSBarchlab/PyRTL,deekshadangwal/PyRTL,nvandervoort/PyRTL