arch-x86: fix CondInst decoding for MOV to Control Registers
arch-x86: fix CondInst decoding for MOV to Control Registers

MOV Rd,Cd is MR encoded but the control register is operand 2
not operand 1 hence this needs to be MODRM_REG not MODRM_RM.
While MOV Cd,Rd is RM encoded registers are also swapped, so
it also needs to be MODRM_REG as well (as it already correctly is).

This fixes incorrect UD2 reportings leading to invalid traps
reported in O3 on X86 FS introduced with 4e939a7 .

Change-Id: Ib33c8ba87b00e0264d33da44fff64ed9e4d2d9d8
Reviewed-on: https://gem5-review.googlesource.com/4861
Reviewed-by: Jason Lowe-Power <68c46a606457643eab92053c1c05574abb26f861@lowepower.com>
Reviewed-by: Gabe Black <5c8aa1266c03186393d9e7b3b4e3b14239af8201@google.com>
Maintainer: Jason Lowe-Power <68c46a606457643eab92053c1c05574abb26f861@lowepower.com>

TUD-OS/gem5-dtu,TUD-OS/gem5-dtu,TUD-OS/gem5-dtu,gem5/gem5,TUD-OS/gem5-dtu,gem5/gem5,gem5/gem5,TUD-OS/gem5-dtu,TUD-OS/gem5-dtu,gem5/gem5,gem5/gem5,TUD-OS/gem5-dtu,gem5/gem5,gem5/gem5