change default headerCycles back to 1
change default headerCycles back to 1

aferr/LatticeMemCtl,aferr/TimingCompartments,xiaoyaozi5566/GEM5_DRAMSim2,aferr/TimingCompartments,aferr/LatticeMemCtl,xiaoyaozi5566/DynamicCache,aferr/LatticeMemCtl,aferr/LatticeMemCtl,xiaoyaozi5566/DynamicCache,xiaoyaozi5566/GEM5_DRAMSim2,aferr/TimingCompartments,aferr/LatticeMemCtl,aferr/TimingCompartments,aferr/LatticeMemCtl,aferr/TimingCompartments,xiaoyaozi5566/DynamicCache,xiaoyaozi5566/GEM5_DRAMSim2,aferr/TimingCompartments,aferr/LatticeMemCtl,xiaoyaozi5566/DynamicCache,xiaoyaozi5566/DynamicCache,xiaoyaozi5566/DynamicCache,xiaoyaozi5566/DynamicCache,xiaoyaozi5566/DynamicCache,xiaoyaozi5566/GEM5_DRAMSim2,aferr/LatticeMemCtl,aferr/TimingCompartments,aferr/LatticeMemCtl,xiaoyaozi5566/GEM5_DRAMSim2,xiaoyaozi5566/GEM5_DRAMSim2,xiaoyaozi5566/DynamicCache,xiaoyaozi5566/GEM5_DRAMSim2,xiaoyaozi5566/GEM5_DRAMSim2,aferr/TimingCompartments,xiaoyaozi5566/GEM5_DRAMSim2,aferr/TimingCompartments,xiaoyaozi5566/DynamicCache