Avoid emitting VHDL Bool_To_Logic calls for common cases
Avoid emitting VHDL Bool_To_Logic calls for common cases

No functional change, just improves the output a bit. E.g.

  x <= Bool_To_Logic(y = z);

Becomes:

  x <= '1' when y = z else '0';

themperek/iverilog,themperek/iverilog,CastMi/iverilog,themperek/iverilog,CastMi/iverilog,CastMi/iverilog