mfd/axp20x: avoid irq numbering collision
mfd/axp20x: avoid irq numbering collision

IRQ numbers in axp20x devices are defined with high-order bit first
in each IRQ enable/status registers. On Intel platforms it is more
common to number IRQs with least significant bit first. Therefore,
sharing IRQ# between the two is very difficult. Since AXP288 is a
customized PMIC for Intel platform and the amount of shared IRQs are
very small, we use separate IRQ numbering. This also fixes collision
and a duplicate in WBTO interrupt.

e.g. For the 16 interrupts controlled in IRQ enabled registers 1 & 2,
on axp20x for ARM, the PMIC local IRQ numbers and register bits are
mapped as:
IRQ#:  0  1  2  3  4  5  6  7      8  9 10 11 12 13 14 15
---------------------------------------------------------
ARM:   7  6  5  4  3  2  1  0      7  6  5  4  3  2  1  0
Intel: 0  1  2  3  4  5  6  7      0  1  2  3  4  5  6  7

Signed-off-by: Todd Brandt <8da30c6e5270f3ec55b7f431aadf4dbb2152d8e9@linux.intel.com>
Signed-off-by: Jacob Pan <148d80f820771051461d15e2fa9640db8055fb59@linux.intel.com>
Acked-by: Jonathan Cameron <09f65b71b7655725897b2fd41a09a0cefe2e1ace@kernel.org>
Signed-off-by: Lee Jones <630e34333487a351a857f6b705e04d30b37c1629@linaro.org>

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