mem: Add HMC Timing Parameters A single HMC-2500 x32 model based on:
mem: Add HMC Timing Parameters
A single HMC-2500 x32 model based on:

[1] DRAMSpec: a high-level DRAM bank modelling tool developed at the University
of Kaiserslautern. This high level tool uses RC (resistance-capacitance) and CV
(capacitance-voltage) models to estimate the DRAM bank latency and power
numbers.

[2] A Logic-base Interconnect for Supporting Near Memory Computation in the
Hybrid Memory Cube (E. Azarkhish et. al) Assumed for the HMC model is a 30 nm
technology node.  The modelled HMC consists of a 4 Gbit part with 4 layers
connected with TSVs.  Each layer has 16 vaults and each vault consists of 2
banks per layer.  In order to be able to use the same controller used for 2D
DRAM generations for HMC, the following analogy is done: Channel (DDR) => Vault
(HMC) device_size (DDR) => size of a single layer in a vault ranks per channel
(DDR) => number of layers banks per rank (DDR) => banks per layer devices per
rank (DDR) => devices per layer ( 1 for HMC).  The parameters for which no
input is available are inherited from the DDR3 configuration.

Weil0ng/gem5,gem5/gem5,austinharris/gem5-riscv,qizenguf/MLC-STT,briancoutinho0905/2dsampling,KuroeKurose/gem5,sobercoder/gem5,briancoutinho0905/2dsampling,briancoutinho0905/2dsampling,gedare/gem5,zlfben/gem5,rallylee/gem5,cancro7/gem5,aclifton/cpeg853-gem5,qizenguf/MLC-STT,aclifton/cpeg853-gem5,austinharris/gem5-riscv,KuroeKurose/gem5,Weil0ng/gem5,sobercoder/gem5,gem5/gem5,TUD-OS/gem5-dtu,gedare/gem5,kaiyuanl/gem5,gem5/gem5,TUD-OS/gem5-dtu,TUD-OS/gem5-dtu,SanchayanMaity/gem5,SanchayanMaity/gem5,rallylee/gem5,kaiyuanl/gem5,kaiyuanl/gem5,rallylee/gem5,qizenguf/MLC-STT,sobercoder/gem5,TUD-OS/gem5-dtu,briancoutinho0905/2dsampling,qizenguf/MLC-STT,rallylee/gem5,aclifton/cpeg853-gem5,Weil0ng/gem5,qizenguf/MLC-STT,cancro7/gem5,rallylee/gem5,rjschof/gem5,KuroeKurose/gem5,Weil0ng/gem5,TUD-OS/gem5-dtu,zlfben/gem5,SanchayanMaity/gem5,cancro7/gem5,rjschof/gem5,HwisooSo/gemV-update,zlfben/gem5,HwisooSo/gemV-update,gedare/gem5,rjschof/gem5,Weil0ng/gem5,austinharris/gem5-riscv,rjschof/gem5,sobercoder/gem5,powerjg/gem5-ci-test,TUD-OS/gem5-dtu,powerjg/gem5-ci-test,TUD-OS/gem5-dtu,powerjg/gem5-ci-test,SanchayanMaity/gem5,aclifton/cpeg853-gem5,zlfben/gem5,rjschof/gem5,briancoutinho0905/2dsampling,Weil0ng/gem5,KuroeKurose/gem5,zlfben/gem5,cancro7/gem5,kaiyuanl/gem5,aclifton/cpeg853-gem5,powerjg/gem5-ci-test,powerjg/gem5-ci-test,aclifton/cpeg853-gem5,powerjg/gem5-ci-test,gedare/gem5,austinharris/gem5-riscv,sobercoder/gem5,KuroeKurose/gem5,SanchayanMaity/gem5,SanchayanMaity/gem5,cancro7/gem5,briancoutinho0905/2dsampling,powerjg/gem5-ci-test,qizenguf/MLC-STT,rjschof/gem5,HwisooSo/gemV-update,Weil0ng/gem5,HwisooSo/gemV-update,KuroeKurose/gem5,kaiyuanl/gem5,gem5/gem5,sobercoder/gem5,zlfben/gem5,HwisooSo/gemV-update,HwisooSo/gemV-update,HwisooSo/gemV-update,kaiyuanl/gem5,rjschof/gem5,gedare/gem5,sobercoder/gem5,kaiyuanl/gem5,austinharris/gem5-riscv,aclifton/cpeg853-gem5,rallylee/gem5,qizenguf/MLC-STT,gem5/gem5,briancoutinho0905/2dsampling,austinharris/gem5-riscv,gedare/gem5,gem5/gem5,austinharris/gem5-riscv,rallylee/gem5,gem5/gem5,gedare/gem5,cancro7/gem5,zlfben/gem5,cancro7/gem5,KuroeKurose/gem5,SanchayanMaity/gem5