Handle DFF with clock-enable in blif code generator
Handle DFF with clock-enable in blif code generator

In the ASIC universe, it is (probably) OK to replace a DFF CE
with a mux of the D input with the Q output. The idea is that
if the CE is true, the DFF latches D, but if CE is false, the DFF
re-latches the current output.

CastMi/iverilog,themperek/iverilog,CastMi/iverilog,themperek/iverilog,CastMi/iverilog,themperek/iverilog