[dv] Add cpuctrlsts writes to riscv_rand_instr_test
[dv] Add cpuctrlsts writes to riscv_rand_instr_test

This will have the effect of randomly enabling/disabling

 - The ICache
 - Dummy instruction insertion
 - Data independent timing

lowRISC/ibex,lowRISC/ibex,lowRISC/ibex,lowRISC/ibex