Fixed a bug in the execution engine where ldm/stm where loading/storing registers in the incorrect order in memory.  The incorrect order was registers 0-15 from the current address in Rn toward higher or lower memory based on the UP/down flag.  It turns out the registers are always supposed to be stored lower number to higher number from low address to higher address regardless of the UP/down flag.  This change fixes that.  However, it does violate the spec in that it stores them in the order from low to high or high to low depending on the UP/down flag.  For this in-memory-only version of the processor, that's completely fine.
Fixed a bug in the execution engine where ldm/stm where loading/storing
registers in the incorrect order in memory.  The incorrect order was
registers 0-15 from the current address in Rn toward higher or lower memory
based on the UP/down flag.  It turns out the registers are always supposed
to be stored lower number to higher number from low address to higher
address regardless of the UP/down flag.  This change fixes that.  However,
it does violate the spec in that it stores them in the order from low to
high or high to low depending on the UP/down flag.  For this in-memory-only
version of the processor, that's completely fine.



git-svn-id: 2a42d4147853adcf1a20d13614e77797555e50d1@49 d0763410-cf01-4c7c-9b55-0f7f3399ec47

rthelen/arm-sim,rthelen/arm-sim,rthelen/arm-sim