arm: set ldr_ret_uop as conditional or unconditional control This patch adds a missing flag to the ldr_ret_uop microop instruction. The flag is added when the instruction is used, not directly in the constructor of the instruction.
arm: set ldr_ret_uop as conditional or unconditional control
This patch adds a missing flag to the ldr_ret_uop microop instruction.
The flag is added when the instruction is used, not directly in the
constructor of the instruction.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>"

rjschof/gem5,qizenguf/MLC-STT,gedare/gem5,sobercoder/gem5,austinharris/gem5-riscv,briancoutinho0905/2dsampling,rjschof/gem5,briancoutinho0905/2dsampling,KuroeKurose/gem5,SanchayanMaity/gem5,aclifton/cpeg853-gem5,briancoutinho0905/2dsampling,KuroeKurose/gem5,aclifton/cpeg853-gem5,SanchayanMaity/gem5,gedare/gem5,kaiyuanl/gem5,TUD-OS/gem5-dtu,qizenguf/MLC-STT,yb-kim/gemV,briancoutinho0905/2dsampling,gem5/gem5,qizenguf/MLC-STT,kaiyuanl/gem5,yb-kim/gemV,kaiyuanl/gem5,gedare/gem5,cancro7/gem5,Weil0ng/gem5,gedare/gem5,Weil0ng/gem5,samueldotj/TeeRISC-Simulator,austinharris/gem5-riscv,qizenguf/MLC-STT,Weil0ng/gem5,qizenguf/MLC-STT,zlfben/gem5,gem5/gem5,powerjg/gem5-ci-test,Weil0ng/gem5,aclifton/cpeg853-gem5,SanchayanMaity/gem5,SanchayanMaity/gem5,powerjg/gem5-ci-test,joerocklin/gem5,cancro7/gem5,austinharris/gem5-riscv,sobercoder/gem5,markoshorro/gem5,rjschof/gem5,kaiyuanl/gem5,yb-kim/gemV,powerjg/gem5-ci-test,rjschof/gem5,gem5/gem5,joerocklin/gem5,HwisooSo/gemV-update,samueldotj/TeeRISC-Simulator,qizenguf/MLC-STT,qizenguf/MLC-STT,aclifton/cpeg853-gem5,KuroeKurose/gem5,powerjg/gem5-ci-test,rallylee/gem5,HwisooSo/gemV-update,joerocklin/gem5,Weil0ng/gem5,Weil0ng/gem5,KuroeKurose/gem5,rallylee/gem5,joerocklin/gem5,rallylee/gem5,kaiyuanl/gem5,gem5/gem5,HwisooSo/gemV-update,markoshorro/gem5,markoshorro/gem5,sobercoder/gem5,TUD-OS/gem5-dtu,TUD-OS/gem5-dtu,sobercoder/gem5,rallylee/gem5,TUD-OS/gem5-dtu,Weil0ng/gem5,briancoutinho0905/2dsampling,zlfben/gem5,zlfben/gem5,cancro7/gem5,zlfben/gem5,sobercoder/gem5,HwisooSo/gemV-update,briancoutinho0905/2dsampling,gedare/gem5,kaiyuanl/gem5,gedare/gem5,austinharris/gem5-riscv,cancro7/gem5,samueldotj/TeeRISC-Simulator,austinharris/gem5-riscv,samueldotj/TeeRISC-Simulator,gem5/gem5,TUD-OS/gem5-dtu,yb-kim/gemV,gedare/gem5,gem5/gem5,briancoutinho0905/2dsampling,samueldotj/TeeRISC-Simulator,samueldotj/TeeRISC-Simulator,zlfben/gem5,SanchayanMaity/gem5,joerocklin/gem5,sobercoder/gem5,austinharris/gem5-riscv,rallylee/gem5,markoshorro/gem5,TUD-OS/gem5-dtu,rallylee/gem5,gem5/gem5,cancro7/gem5,zlfben/gem5,HwisooSo/gemV-update,HwisooSo/gemV-update,markoshorro/gem5,sobercoder/gem5,samueldotj/TeeRISC-Simulator,markoshorro/gem5,KuroeKurose/gem5,joerocklin/gem5,yb-kim/gemV,aclifton/cpeg853-gem5,aclifton/cpeg853-gem5,cancro7/gem5,powerjg/gem5-ci-test,TUD-OS/gem5-dtu,aclifton/cpeg853-gem5,KuroeKurose/gem5,zlfben/gem5,joerocklin/gem5,joerocklin/gem5,rjschof/gem5,rjschof/gem5,cancro7/gem5,yb-kim/gemV,yb-kim/gemV,powerjg/gem5-ci-test,kaiyuanl/gem5,rallylee/gem5,HwisooSo/gemV-update,markoshorro/gem5,yb-kim/gemV,austinharris/gem5-riscv,SanchayanMaity/gem5,rjschof/gem5,SanchayanMaity/gem5,KuroeKurose/gem5,powerjg/gem5-ci-test