verilog: fix wildcard port connections leaking memory
verilog: fix wildcard port connections leaking memory

cliffordwolf/yosys,cliffordwolf/yosys,cliffordwolf/yosys,YosysHQ/yosys,antmicro/yosys,YosysHQ/yosys,cliffordwolf/yosys,cliffordwolf/yosys,antmicro/yosys,YosysHQ/yosys,YosysHQ/yosys,antmicro/yosys,antmicro/yosys,cliffordwolf/yosys,YosysHQ/yosys,antmicro/yosys,cliffordwolf/yosys,antmicro/yosys,YosysHQ/yosys,cliffordwolf/yosys,cliffordwolf/yosys,antmicro/yosys,antmicro/yosys,YosysHQ/yosys,YosysHQ/yosys