mchp: Correct integrated SPI flash pins' configuration
mchp: Correct integrated SPI flash pins' configuration

Corrected MEC1727 integrated SPI flash CS# (GPIO116) and CLK (GPIO117)
alternative function as 1 (Internal SPI functionality) from 2 (General
purpose SPI functionality).

BUG=none
BRANCH=none
TEST=Tested on ADL RVP via EC UART console
> sysjump RW: able to switch to RW from RO
> sysjump RO: able to switch to RO from RW

Signed-off-by: martin yan <409cb29bb9001f9bb84010e71644764e5f7609ce@microchip.corp-partner.google.com>
Change-Id: I870925183e670022dc023812265a7ef496b5f255
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3021101
Reviewed-by: Vijay Hiremath <006c712879a3af08bfdb5c2b8491a8b2d5fd73cd@intel.com>
Reviewed-by: Aseda Aboagye <12c9b286316a940fd31c24070da5ab64cdd4d0e7@chromium.org>
Commit-Queue: Aseda Aboagye <12c9b286316a940fd31c24070da5ab64cdd4d0e7@chromium.org>

coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec,coreboot/chrome-ec