inorder: write-hints bug fix make sure to only read 1 src reg. for write-hint and any other similar 'store' instruction. Reading the source reg when its not necessary can cause the simulator to read from uninitialized values
inorder: write-hints bug fix
make sure to only read 1 src reg. for write-hint and any other similar
'store' instruction. Reading the source reg when its not necessary
can cause the simulator to read from uninitialized values

SanchayanMaity/gem5,gem5/gem5,Weil0ng/gem5,cancro7/gem5,rallylee/gem5,KuroeKurose/gem5,rjschof/gem5,aclifton/cpeg853-gem5,markoshorro/gem5,Weil0ng/gem5,samueldotj/TeeRISC-Simulator,HwisooSo/gemV-update,briancoutinho0905/2dsampling,austinharris/gem5-riscv,markoshorro/gem5,gedare/gem5,sobercoder/gem5,SanchayanMaity/gem5,yb-kim/gemV,zlfben/gem5,samueldotj/TeeRISC-Simulator,austinharris/gem5-riscv,austinharris/gem5-riscv,Weil0ng/gem5,SanchayanMaity/gem5,gem5/gem5,aclifton/cpeg853-gem5,Weil0ng/gem5,joerocklin/gem5,joerocklin/gem5,markoshorro/gem5,cancro7/gem5,gedare/gem5,aclifton/cpeg853-gem5,HwisooSo/gemV-update,rallylee/gem5,cancro7/gem5,cancro7/gem5,rjschof/gem5,qizenguf/MLC-STT,samueldotj/TeeRISC-Simulator,powerjg/gem5-ci-test,HwisooSo/gemV-update,TUD-OS/gem5-dtu,TUD-OS/gem5-dtu,sobercoder/gem5,TUD-OS/gem5-dtu,aclifton/cpeg853-gem5,briancoutinho0905/2dsampling,zlfben/gem5,TUD-OS/gem5-dtu,qizenguf/MLC-STT,qizenguf/MLC-STT,HwisooSo/gemV-update,briancoutinho0905/2dsampling,yb-kim/gemV,qizenguf/MLC-STT,zlfben/gem5,gedare/gem5,briancoutinho0905/2dsampling,gem5/gem5,gedare/gem5,powerjg/gem5-ci-test,Weil0ng/gem5,yb-kim/gemV,austinharris/gem5-riscv,briancoutinho0905/2dsampling,sobercoder/gem5,sobercoder/gem5,briancoutinho0905/2dsampling,kaiyuanl/gem5,zlfben/gem5,powerjg/gem5-ci-test,gem5/gem5,qizenguf/MLC-STT,kaiyuanl/gem5,yb-kim/gemV,rjschof/gem5,qizenguf/MLC-STT,zlfben/gem5,gedare/gem5,yb-kim/gemV,gedare/gem5,joerocklin/gem5,joerocklin/gem5,rallylee/gem5,samueldotj/TeeRISC-Simulator,KuroeKurose/gem5,austinharris/gem5-riscv,kaiyuanl/gem5,samueldotj/TeeRISC-Simulator,rjschof/gem5,SanchayanMaity/gem5,rjschof/gem5,aclifton/cpeg853-gem5,zlfben/gem5,aclifton/cpeg853-gem5,SanchayanMaity/gem5,HwisooSo/gemV-update,briancoutinho0905/2dsampling,gem5/gem5,KuroeKurose/gem5,austinharris/gem5-riscv,samueldotj/TeeRISC-Simulator,HwisooSo/gemV-update,Weil0ng/gem5,TUD-OS/gem5-dtu,aclifton/cpeg853-gem5,joerocklin/gem5,yb-kim/gemV,gem5/gem5,SanchayanMaity/gem5,markoshorro/gem5,SanchayanMaity/gem5,TUD-OS/gem5-dtu,zlfben/gem5,kaiyuanl/gem5,gem5/gem5,cancro7/gem5,KuroeKurose/gem5,sobercoder/gem5,KuroeKurose/gem5,markoshorro/gem5,sobercoder/gem5,KuroeKurose/gem5,powerjg/gem5-ci-test,samueldotj/TeeRISC-Simulator,markoshorro/gem5,rallylee/gem5,joerocklin/gem5,yb-kim/gemV,joerocklin/gem5,yb-kim/gemV,HwisooSo/gemV-update,cancro7/gem5,KuroeKurose/gem5,kaiyuanl/gem5,rjschof/gem5,qizenguf/MLC-STT,rallylee/gem5,kaiyuanl/gem5,powerjg/gem5-ci-test,gedare/gem5,sobercoder/gem5,markoshorro/gem5,rjschof/gem5,powerjg/gem5-ci-test,austinharris/gem5-riscv,cancro7/gem5,rallylee/gem5,Weil0ng/gem5,rallylee/gem5,joerocklin/gem5,TUD-OS/gem5-dtu,powerjg/gem5-ci-test,kaiyuanl/gem5